./Ultimate.py --spec ../../sv-benchmarks/c/Termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.07_true-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 5842f4b8 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_3a6714ee-9413-49e8-b921-8f98627a95b6/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_3a6714ee-9413-49e8-b921-8f98627a95b6/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_3a6714ee-9413-49e8-b921-8f98627a95b6/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_3a6714ee-9413-49e8-b921-8f98627a95b6/bin-2019/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.07_true-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_3a6714ee-9413-49e8-b921-8f98627a95b6/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_3a6714ee-9413-49e8-b921-8f98627a95b6/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 35aa81144c06555695e96f98f1b941f438431e9e ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.1.23-5842f4b [2018-11-18 15:27:51,779 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-18 15:27:51,780 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-18 15:27:51,786 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-18 15:27:51,787 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-18 15:27:51,787 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-18 15:27:51,788 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-18 15:27:51,789 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-18 15:27:51,790 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-18 15:27:51,791 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-18 15:27:51,792 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-18 15:27:51,792 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-18 15:27:51,793 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-18 15:27:51,793 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-18 15:27:51,794 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-18 15:27:51,795 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-18 15:27:51,795 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-18 15:27:51,797 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-18 15:27:51,798 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-18 15:27:51,799 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-18 15:27:51,800 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-18 15:27:51,801 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-18 15:27:51,803 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-18 15:27:51,803 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-18 15:27:51,803 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-18 15:27:51,804 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-18 15:27:51,805 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-18 15:27:51,805 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-18 15:27:51,806 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-18 15:27:51,807 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-18 15:27:51,807 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-18 15:27:51,807 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-18 15:27:51,807 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-18 15:27:51,807 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-18 15:27:51,808 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-18 15:27:51,808 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-18 15:27:51,808 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_3a6714ee-9413-49e8-b921-8f98627a95b6/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2018-11-18 15:27:51,818 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-18 15:27:51,818 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-18 15:27:51,819 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-18 15:27:51,819 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-18 15:27:51,819 INFO L133 SettingsManager]: * Use SBE=true [2018-11-18 15:27:51,819 INFO L131 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2018-11-18 15:27:51,820 INFO L133 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2018-11-18 15:27:51,820 INFO L133 SettingsManager]: * Use old map elimination=false [2018-11-18 15:27:51,820 INFO L133 SettingsManager]: * Use external solver (rank synthesis)=false [2018-11-18 15:27:51,820 INFO L133 SettingsManager]: * Use only trivial implications for array writes=true [2018-11-18 15:27:51,820 INFO L133 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2018-11-18 15:27:51,820 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-18 15:27:51,820 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-18 15:27:51,820 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-11-18 15:27:51,821 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-18 15:27:51,821 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-18 15:27:51,821 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-18 15:27:51,821 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2018-11-18 15:27:51,821 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2018-11-18 15:27:51,821 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2018-11-18 15:27:51,823 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-18 15:27:51,823 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-18 15:27:51,823 INFO L133 SettingsManager]: * Assume nondeterminstic values are in range=false [2018-11-18 15:27:51,823 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-18 15:27:51,824 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2018-11-18 15:27:51,824 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-18 15:27:51,824 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-18 15:27:51,824 INFO L133 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2018-11-18 15:27:51,824 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-18 15:27:51,824 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-18 15:27:51,824 INFO L133 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2018-11-18 15:27:51,825 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-11-18 15:27:51,825 INFO L133 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_3a6714ee-9413-49e8-b921-8f98627a95b6/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 35aa81144c06555695e96f98f1b941f438431e9e [2018-11-18 15:27:51,850 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-18 15:27:51,860 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-18 15:27:51,862 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-18 15:27:51,864 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-18 15:27:51,864 INFO L276 PluginConnector]: CDTParser initialized [2018-11-18 15:27:51,865 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_3a6714ee-9413-49e8-b921-8f98627a95b6/bin-2019/uautomizer/../../sv-benchmarks/c/systemc/token_ring.07_true-unreach-call_false-termination.cil.c [2018-11-18 15:27:51,913 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_3a6714ee-9413-49e8-b921-8f98627a95b6/bin-2019/uautomizer/data/01a2c81ae/c8cca01a95a6422b9c52377d3d64abf3/FLAG5dfb82af6 [2018-11-18 15:27:52,279 INFO L307 CDTParser]: Found 1 translation units. [2018-11-18 15:27:52,279 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_3a6714ee-9413-49e8-b921-8f98627a95b6/sv-benchmarks/c/systemc/token_ring.07_true-unreach-call_false-termination.cil.c [2018-11-18 15:27:52,289 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_3a6714ee-9413-49e8-b921-8f98627a95b6/bin-2019/uautomizer/data/01a2c81ae/c8cca01a95a6422b9c52377d3d64abf3/FLAG5dfb82af6 [2018-11-18 15:27:52,674 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_3a6714ee-9413-49e8-b921-8f98627a95b6/bin-2019/uautomizer/data/01a2c81ae/c8cca01a95a6422b9c52377d3d64abf3 [2018-11-18 15:27:52,677 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-18 15:27:52,678 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-18 15:27:52,679 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-18 15:27:52,679 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-18 15:27:52,683 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-18 15:27:52,683 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 03:27:52" (1/1) ... [2018-11-18 15:27:52,686 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5c51124e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:27:52, skipping insertion in model container [2018-11-18 15:27:52,686 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 03:27:52" (1/1) ... [2018-11-18 15:27:52,694 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-18 15:27:52,727 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-18 15:27:52,889 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 15:27:52,893 INFO L191 MainTranslator]: Completed pre-run [2018-11-18 15:27:52,932 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 15:27:52,950 INFO L195 MainTranslator]: Completed translation [2018-11-18 15:27:52,950 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:27:52 WrapperNode [2018-11-18 15:27:52,950 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-18 15:27:52,951 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-18 15:27:52,951 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-18 15:27:52,951 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-18 15:27:52,958 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:27:52" (1/1) ... [2018-11-18 15:27:52,964 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:27:52" (1/1) ... [2018-11-18 15:27:53,061 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-18 15:27:53,062 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-18 15:27:53,062 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-18 15:27:53,062 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-18 15:27:53,068 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:27:52" (1/1) ... [2018-11-18 15:27:53,068 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:27:52" (1/1) ... [2018-11-18 15:27:53,072 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:27:52" (1/1) ... [2018-11-18 15:27:53,072 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:27:52" (1/1) ... [2018-11-18 15:27:53,088 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:27:52" (1/1) ... [2018-11-18 15:27:53,107 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:27:52" (1/1) ... [2018-11-18 15:27:53,110 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:27:52" (1/1) ... [2018-11-18 15:27:53,117 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-18 15:27:53,118 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-18 15:27:53,118 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-18 15:27:53,118 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-18 15:27:53,119 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:27:52" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3a6714ee-9413-49e8-b921-8f98627a95b6/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 15:27:53,177 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-18 15:27:53,177 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-18 15:27:54,370 INFO L278 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-18 15:27:54,371 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 03:27:54 BoogieIcfgContainer [2018-11-18 15:27:54,373 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-18 15:27:54,374 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2018-11-18 15:27:54,374 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2018-11-18 15:27:54,377 INFO L276 PluginConnector]: BuchiAutomizer initialized [2018-11-18 15:27:54,378 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-18 15:27:54,378 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 18.11 03:27:52" (1/3) ... [2018-11-18 15:27:54,379 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@49c9a077 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 18.11 03:27:54, skipping insertion in model container [2018-11-18 15:27:54,380 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-18 15:27:54,380 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:27:52" (2/3) ... [2018-11-18 15:27:54,380 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@49c9a077 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 18.11 03:27:54, skipping insertion in model container [2018-11-18 15:27:54,380 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-18 15:27:54,380 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 03:27:54" (3/3) ... [2018-11-18 15:27:54,382 INFO L375 chiAutomizerObserver]: Analyzing ICFG token_ring.07_true-unreach-call_false-termination.cil.c [2018-11-18 15:27:54,431 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-18 15:27:54,431 INFO L374 BuchiCegarLoop]: Interprodecural is true [2018-11-18 15:27:54,432 INFO L375 BuchiCegarLoop]: Hoare is false [2018-11-18 15:27:54,432 INFO L376 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2018-11-18 15:27:54,432 INFO L377 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-18 15:27:54,432 INFO L378 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-18 15:27:54,432 INFO L379 BuchiCegarLoop]: Difference is false [2018-11-18 15:27:54,432 INFO L380 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-18 15:27:54,432 INFO L383 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2018-11-18 15:27:54,461 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 846 states. [2018-11-18 15:27:54,498 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 739 [2018-11-18 15:27:54,498 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:27:54,498 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:27:54,508 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:27:54,508 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:27:54,508 INFO L442 BuchiCegarLoop]: ======== Iteration 1============ [2018-11-18 15:27:54,508 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 846 states. [2018-11-18 15:27:54,518 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 739 [2018-11-18 15:27:54,518 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:27:54,518 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:27:54,522 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:27:54,522 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:27:54,529 INFO L794 eck$LassoCheckResult]: Stem: 291#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 229#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 827#L1131true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 557#L519true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 364#L526true assume !(1 == ~m_i~0);~m_st~0 := 2; 365#L526-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 184#L531-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 843#L536-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 558#L541-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 355#L546-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 147#L551-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 62#L556-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 725#L561-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 730#L759true assume !(0 == ~M_E~0); 735#L759-2true assume !(0 == ~T1_E~0); 421#L764-1true assume !(0 == ~T2_E~0); 256#L769-1true assume !(0 == ~T3_E~0); 43#L774-1true assume !(0 == ~T4_E~0); 812#L779-1true assume !(0 == ~T5_E~0); 616#L784-1true assume 0 == ~T6_E~0;~T6_E~0 := 1; 405#L789-1true assume !(0 == ~T7_E~0); 113#L794-1true assume !(0 == ~E_M~0); 776#L799-1true assume !(0 == ~E_1~0); 671#L804-1true assume !(0 == ~E_2~0); 517#L809-1true assume !(0 == ~E_3~0); 323#L814-1true assume !(0 == ~E_4~0); 5#L819-1true assume !(0 == ~E_5~0); 646#L824-1true assume 0 == ~E_6~0;~E_6~0 := 1; 486#L829-1true assume !(0 == ~E_7~0); 372#L834-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 599#L366true assume !(1 == ~m_pc~0); 602#L366-2true is_master_triggered_~__retres1~0 := 0; 167#L377true is_master_triggered_#res := is_master_triggered_~__retres1~0; 35#L378true activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 257#L945true assume !(0 != activate_threads_~tmp~1); 258#L945-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 712#L385true assume 1 == ~t1_pc~0; 572#L386true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 303#L396true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 136#L397true activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 782#L953true assume !(0 != activate_threads_~tmp___0~0); 783#L953-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 829#L404true assume !(1 == ~t2_pc~0); 834#L404-2true is_transmit2_triggered_~__retres1~2 := 0; 403#L415true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 366#L416true activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 586#L961true assume !(0 != activate_threads_~tmp___1~0); 589#L961-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 99#L423true assume 1 == ~t3_pc~0; 51#L424true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 542#L434true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 502#L435true activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 279#L969true assume !(0 != activate_threads_~tmp___2~0); 280#L969-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 112#L442true assume !(1 == ~t4_pc~0); 106#L442-2true is_transmit4_triggered_~__retres1~4 := 0; 560#L453true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 610#L454true activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 817#L977true assume !(0 != activate_threads_~tmp___3~0); 820#L977-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 239#L461true assume 1 == ~t5_pc~0; 300#L462true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 637#L472true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 707#L473true activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 521#L985true assume !(0 != activate_threads_~tmp___4~0); 522#L985-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 356#L480true assume 1 == ~t6_pc~0; 400#L481true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 770#L491true is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 844#L492true activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 210#L993true assume !(0 != activate_threads_~tmp___5~0); 213#L993-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 461#L499true assume !(1 == ~t7_pc~0); 465#L499-2true is_transmit7_triggered_~__retres1~7 := 0; 31#L510true is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 3#L511true activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 737#L1001true assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 738#L1001-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 740#L847true assume !(1 == ~M_E~0); 729#L847-2true assume !(1 == ~T1_E~0); 418#L852-1true assume !(1 == ~T2_E~0); 252#L857-1true assume !(1 == ~T3_E~0); 41#L862-1true assume 1 == ~T4_E~0;~T4_E~0 := 2; 806#L867-1true assume !(1 == ~T5_E~0); 614#L872-1true assume !(1 == ~T6_E~0); 336#L877-1true assume !(1 == ~T7_E~0); 117#L882-1true assume !(1 == ~E_M~0); 784#L887-1true assume !(1 == ~E_1~0); 680#L892-1true assume !(1 == ~E_2~0); 525#L897-1true assume !(1 == ~E_3~0); 334#L902-1true assume 1 == ~E_4~0;~E_4~0 := 2; 11#L907-1true assume !(1 == ~E_5~0); 652#L912-1true assume !(1 == ~E_6~0); 482#L917-1true assume !(1 == ~E_7~0); 370#L922-1true assume { :end_inline_reset_delta_events } true; 122#L1168-3true [2018-11-18 15:27:54,530 INFO L796 eck$LassoCheckResult]: Loop: 122#L1168-3true assume true; 133#L1168-1true assume !false; 216#L1169true start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 847#L734true assume !true; 275#L749true assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 559#L519-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 719#L759-3true assume 0 == ~M_E~0;~M_E~0 := 1; 723#L759-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 412#L764-3true assume !(0 == ~T2_E~0); 247#L769-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 37#L774-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 796#L779-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 612#L784-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 409#L789-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 115#L794-3true assume 0 == ~E_M~0;~E_M~0 := 1; 778#L799-3true assume 0 == ~E_1~0;~E_1~0 := 1; 674#L804-3true assume !(0 == ~E_2~0); 519#L809-3true assume 0 == ~E_3~0;~E_3~0 := 1; 325#L814-3true assume 0 == ~E_4~0;~E_4~0 := 1; 6#L819-3true assume 0 == ~E_5~0;~E_5~0 := 1; 647#L824-3true assume 0 == ~E_6~0;~E_6~0 := 1; 491#L829-3true assume 0 == ~E_7~0;~E_7~0 := 1; 373#L834-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 462#L366-27true assume !(1 == ~m_pc~0); 466#L366-29true is_master_triggered_~__retres1~0 := 0; 164#L377-9true is_master_triggered_#res := is_master_triggered_~__retres1~0; 17#L378-9true activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 226#L945-27true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 327#L945-29true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 581#L385-27true assume 1 == ~t1_pc~0; 562#L386-9true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 285#L396-9true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 119#L397-9true activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 744#L953-27true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 746#L953-29true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 787#L404-27true assume 1 == ~t2_pc~0; 657#L405-9true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 383#L415-9true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 263#L416-9true activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 443#L961-27true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 424#L961-29true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 60#L423-27true assume !(1 == ~t3_pc~0); 64#L423-29true is_transmit3_triggered_~__retres1~3 := 0; 527#L434-9true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 500#L435-9true activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 120#L969-27true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 123#L969-29true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 199#L442-27true assume !(1 == ~t4_pc~0); 183#L442-29true is_transmit4_triggered_~__retres1~4 := 0; 623#L453-9true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 594#L454-9true activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 658#L977-27true assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 648#L977-29true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 313#L461-27true assume 1 == ~t5_pc~0; 299#L462-9true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 635#L472-9true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 703#L473-9true activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 360#L985-27true assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 361#L985-29true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 411#L480-27true assume 1 == ~t6_pc~0; 380#L481-9true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 752#L491-9true is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 823#L492-9true activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 163#L993-27true assume !(0 != activate_threads_~tmp___5~0); 150#L993-29true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 414#L499-27true assume 1 == ~t7_pc~0; 536#L500-9true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 29#L510-9true is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 92#L511-9true activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 684#L1001-27true assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 686#L1001-29true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 731#L847-3true assume 1 == ~M_E~0;~M_E~0 := 2; 736#L847-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 420#L852-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 254#L857-3true assume !(1 == ~T3_E~0); 42#L862-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 811#L867-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 615#L872-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 339#L877-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 118#L882-3true assume 1 == ~E_M~0;~E_M~0 := 2; 775#L887-3true assume 1 == ~E_1~0;~E_1~0 := 2; 670#L892-3true assume 1 == ~E_2~0;~E_2~0 := 2; 515#L897-3true assume !(1 == ~E_3~0); 321#L902-3true assume 1 == ~E_4~0;~E_4~0 := 2; 4#L907-3true assume 1 == ~E_5~0;~E_5~0 := 2; 645#L912-3true assume 1 == ~E_6~0;~E_6~0 := 2; 485#L917-3true assume 1 == ~E_7~0;~E_7~0 := 2; 371#L922-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 110#L574-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 314#L616-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 144#L617-1true start_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 260#L1187true assume !(0 == start_simulation_~tmp~3); 264#L1187-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 111#L574-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 316#L616-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 146#L617-2true stop_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 384#L1142true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 15#L1149true stop_simulation_#res := stop_simulation_~__retres2~0; 81#L1150true start_simulation_#t~ret20 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 704#L1200true assume !(0 != start_simulation_~tmp___0~1); 122#L1168-3true [2018-11-18 15:27:54,536 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:27:54,536 INFO L82 PathProgramCache]: Analyzing trace with hash 1617538625, now seen corresponding path program 1 times [2018-11-18 15:27:54,538 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:27:54,538 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:27:54,570 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:54,570 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:27:54,570 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:54,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:27:54,673 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:27:54,675 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:27:54,676 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:27:54,680 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 15:27:54,680 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:27:54,680 INFO L82 PathProgramCache]: Analyzing trace with hash 1292837848, now seen corresponding path program 1 times [2018-11-18 15:27:54,681 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:27:54,681 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:27:54,682 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:54,682 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:27:54,682 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:54,688 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:27:54,706 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:27:54,706 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:27:54,707 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 15:27:54,708 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:27:54,720 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:27:54,720 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:27:54,721 INFO L87 Difference]: Start difference. First operand 846 states. Second operand 3 states. [2018-11-18 15:27:54,755 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:27:54,756 INFO L93 Difference]: Finished difference Result 845 states and 1255 transitions. [2018-11-18 15:27:54,756 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:27:54,758 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 845 states and 1255 transitions. [2018-11-18 15:27:54,764 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 737 [2018-11-18 15:27:54,772 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 845 states to 840 states and 1250 transitions. [2018-11-18 15:27:54,774 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 840 [2018-11-18 15:27:54,775 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 840 [2018-11-18 15:27:54,776 INFO L73 IsDeterministic]: Start isDeterministic. Operand 840 states and 1250 transitions. [2018-11-18 15:27:54,780 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:27:54,780 INFO L705 BuchiCegarLoop]: Abstraction has 840 states and 1250 transitions. [2018-11-18 15:27:54,796 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 840 states and 1250 transitions. [2018-11-18 15:27:54,823 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 840 to 840. [2018-11-18 15:27:54,824 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 840 states. [2018-11-18 15:27:54,827 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 840 states to 840 states and 1250 transitions. [2018-11-18 15:27:54,828 INFO L728 BuchiCegarLoop]: Abstraction has 840 states and 1250 transitions. [2018-11-18 15:27:54,829 INFO L608 BuchiCegarLoop]: Abstraction has 840 states and 1250 transitions. [2018-11-18 15:27:54,829 INFO L442 BuchiCegarLoop]: ======== Iteration 2============ [2018-11-18 15:27:54,829 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 840 states and 1250 transitions. [2018-11-18 15:27:54,834 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 737 [2018-11-18 15:27:54,834 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:27:54,834 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:27:54,836 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:27:54,836 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:27:54,837 INFO L794 eck$LassoCheckResult]: Stem: 2136#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 2050#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 2051#L1131 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 2373#L519 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2220#L526 assume 1 == ~m_i~0;~m_st~0 := 0; 2221#L526-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2011#L531-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2012#L536-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2374#L541-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2208#L546-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1949#L551-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1831#L556-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1832#L561-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2487#L759 assume !(0 == ~M_E~0); 2491#L759-2 assume !(0 == ~T1_E~0); 2272#L764-1 assume !(0 == ~T2_E~0); 2084#L769-1 assume !(0 == ~T3_E~0); 1786#L774-1 assume !(0 == ~T4_E~0); 1787#L779-1 assume !(0 == ~T5_E~0); 2429#L784-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2258#L789-1 assume !(0 == ~T7_E~0); 1887#L794-1 assume !(0 == ~E_M~0); 1888#L799-1 assume !(0 == ~E_1~0); 2471#L804-1 assume !(0 == ~E_2~0); 2358#L809-1 assume !(0 == ~E_3~0); 2164#L814-1 assume !(0 == ~E_4~0); 1704#L819-1 assume !(0 == ~E_5~0); 1705#L824-1 assume 0 == ~E_6~0;~E_6~0 := 1; 2331#L829-1 assume !(0 == ~E_7~0); 2230#L834-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2231#L366 assume !(1 == ~m_pc~0); 2323#L366-2 is_master_triggered_~__retres1~0 := 0; 1981#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1767#L378 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1768#L945 assume !(0 != activate_threads_~tmp~1); 2085#L945-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2086#L385 assume 1 == ~t1_pc~0; 2392#L386 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2153#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1928#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1929#L953 assume !(0 != activate_threads_~tmp___0~0); 2530#L953-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2531#L404 assume !(1 == ~t2_pc~0); 2535#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 2257#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2222#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2223#L961 assume !(0 != activate_threads_~tmp___1~0); 2404#L961-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1870#L423 assume 1 == ~t3_pc~0; 1809#L424 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1810#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2342#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2120#L969 assume !(0 != activate_threads_~tmp___2~0); 2121#L969-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1885#L442 assume !(1 == ~t4_pc~0); 1876#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 1877#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2376#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2423#L977 assume !(0 != activate_threads_~tmp___3~0); 2539#L977-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2066#L461 assume 1 == ~t5_pc~0; 2067#L462 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 2070#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2439#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2361#L985 assume !(0 != activate_threads_~tmp___4~0); 2362#L985-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2209#L480 assume 1 == ~t6_pc~0; 2210#L481 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 2197#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2523#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2029#L993 assume !(0 != activate_threads_~tmp___5~0); 2030#L993-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 2032#L499 assume !(1 == ~t7_pc~0); 2316#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 1760#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1700#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1701#L1001 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 2493#L1001-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2494#L847 assume !(1 == ~M_E~0); 2490#L847-2 assume !(1 == ~T1_E~0); 2270#L852-1 assume !(1 == ~T2_E~0); 2081#L857-1 assume !(1 == ~T3_E~0); 1782#L862-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1783#L867-1 assume !(1 == ~T5_E~0); 2427#L872-1 assume !(1 == ~T6_E~0); 2176#L877-1 assume !(1 == ~T7_E~0); 1895#L882-1 assume !(1 == ~E_M~0); 1896#L887-1 assume !(1 == ~E_1~0); 2475#L892-1 assume !(1 == ~E_2~0); 2365#L897-1 assume !(1 == ~E_3~0); 2172#L902-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1719#L907-1 assume !(1 == ~E_5~0); 1720#L912-1 assume !(1 == ~E_6~0); 2328#L917-1 assume !(1 == ~E_7~0); 2228#L922-1 assume { :end_inline_reset_delta_events } true; 1905#L1168-3 [2018-11-18 15:27:54,838 INFO L796 eck$LassoCheckResult]: Loop: 1905#L1168-3 assume true; 1906#L1168-1 assume !false; 1924#L1169 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 1986#L734 assume true; 2443#L626-1 assume !false; 2444#L627 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 1882#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 1778#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 1939#L617 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 1940#L631 assume !(0 != eval_~tmp~0); 2115#L749 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 2116#L519-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 2375#L759-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2484#L759-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2262#L764-3 assume !(0 == ~T2_E~0); 2077#L769-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1771#L774-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1772#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2425#L784-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2261#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1891#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1892#L799-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2472#L804-3 assume !(0 == ~E_2~0); 2359#L809-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2165#L814-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1706#L819-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1707#L824-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2332#L829-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2232#L834-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2233#L366-27 assume 1 == ~m_pc~0; 2295#L367-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 1977#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1731#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1732#L945-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2046#L945-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2167#L385-27 assume 1 == ~t1_pc~0; 2377#L386-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2128#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1899#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1900#L953-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2498#L953-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2499#L404-27 assume 1 == ~t2_pc~0; 2452#L405-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2248#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2095#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2096#L961-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2275#L961-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1828#L423-27 assume 1 == ~t3_pc~0; 1803#L424-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1804#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2341#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1901#L969-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1902#L969-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1907#L442-27 assume 1 == ~t4_pc~0; 1968#L443-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1969#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2409#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2410#L977-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 2445#L977-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2158#L461-27 assume 1 == ~t5_pc~0; 2150#L462-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 2151#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2438#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2215#L985-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 2216#L985-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2217#L480-27 assume 1 == ~t6_pc~0; 2241#L481-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 2242#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2504#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1976#L993-27 assume !(0 != activate_threads_~tmp___5~0); 1952#L993-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1953#L499-27 assume 1 == ~t7_pc~0; 2264#L500-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 1755#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1756#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1864#L1001-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 2476#L1001-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2477#L847-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2492#L847-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2271#L852-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2083#L857-3 assume !(1 == ~T3_E~0); 1784#L862-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1785#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2428#L872-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2181#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1897#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1898#L887-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2470#L892-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2355#L897-3 assume !(1 == ~E_3~0); 2162#L902-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1702#L907-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1703#L912-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2330#L917-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2229#L922-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 1883#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 1780#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 1943#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 1944#L1187 assume !(0 == start_simulation_~tmp~3); 2089#L1187-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 1884#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 1758#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 1947#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 1948#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1727#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 1728#L1150 start_simulation_#t~ret20 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 1853#L1200 assume !(0 != start_simulation_~tmp___0~1); 1905#L1168-3 [2018-11-18 15:27:54,838 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:27:54,838 INFO L82 PathProgramCache]: Analyzing trace with hash -736846657, now seen corresponding path program 1 times [2018-11-18 15:27:54,838 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:27:54,838 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:27:54,839 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:54,839 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:27:54,840 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:54,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:27:54,901 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:27:54,902 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:27:54,902 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:27:54,902 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 15:27:54,904 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:27:54,904 INFO L82 PathProgramCache]: Analyzing trace with hash -1063146082, now seen corresponding path program 1 times [2018-11-18 15:27:54,904 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:27:54,905 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:27:54,905 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:54,906 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:27:54,906 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:54,926 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:27:54,983 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:27:54,983 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:27:54,984 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:27:54,984 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:27:54,984 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:27:54,984 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:27:54,985 INFO L87 Difference]: Start difference. First operand 840 states and 1250 transitions. cyclomatic complexity: 411 Second operand 3 states. [2018-11-18 15:27:54,999 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:27:54,999 INFO L93 Difference]: Finished difference Result 840 states and 1249 transitions. [2018-11-18 15:27:55,000 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:27:55,001 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 840 states and 1249 transitions. [2018-11-18 15:27:55,004 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 737 [2018-11-18 15:27:55,007 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 840 states to 840 states and 1249 transitions. [2018-11-18 15:27:55,007 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 840 [2018-11-18 15:27:55,008 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 840 [2018-11-18 15:27:55,008 INFO L73 IsDeterministic]: Start isDeterministic. Operand 840 states and 1249 transitions. [2018-11-18 15:27:55,010 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:27:55,010 INFO L705 BuchiCegarLoop]: Abstraction has 840 states and 1249 transitions. [2018-11-18 15:27:55,010 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 840 states and 1249 transitions. [2018-11-18 15:27:55,020 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 840 to 840. [2018-11-18 15:27:55,020 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 840 states. [2018-11-18 15:27:55,022 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 840 states to 840 states and 1249 transitions. [2018-11-18 15:27:55,022 INFO L728 BuchiCegarLoop]: Abstraction has 840 states and 1249 transitions. [2018-11-18 15:27:55,022 INFO L608 BuchiCegarLoop]: Abstraction has 840 states and 1249 transitions. [2018-11-18 15:27:55,022 INFO L442 BuchiCegarLoop]: ======== Iteration 3============ [2018-11-18 15:27:55,022 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 840 states and 1249 transitions. [2018-11-18 15:27:55,025 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 737 [2018-11-18 15:27:55,025 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:27:55,025 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:27:55,026 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:27:55,026 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:27:55,026 INFO L794 eck$LassoCheckResult]: Stem: 3823#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 3737#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 3738#L1131 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 4060#L519 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3907#L526 assume 1 == ~m_i~0;~m_st~0 := 0; 3908#L526-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3698#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3699#L536-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4061#L541-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3895#L546-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3636#L551-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3518#L556-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3519#L561-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4174#L759 assume !(0 == ~M_E~0); 4178#L759-2 assume !(0 == ~T1_E~0); 3959#L764-1 assume !(0 == ~T2_E~0); 3771#L769-1 assume !(0 == ~T3_E~0); 3473#L774-1 assume !(0 == ~T4_E~0); 3474#L779-1 assume !(0 == ~T5_E~0); 4116#L784-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3945#L789-1 assume !(0 == ~T7_E~0); 3574#L794-1 assume !(0 == ~E_M~0); 3575#L799-1 assume !(0 == ~E_1~0); 4158#L804-1 assume !(0 == ~E_2~0); 4045#L809-1 assume !(0 == ~E_3~0); 3851#L814-1 assume !(0 == ~E_4~0); 3391#L819-1 assume !(0 == ~E_5~0); 3392#L824-1 assume 0 == ~E_6~0;~E_6~0 := 1; 4018#L829-1 assume !(0 == ~E_7~0); 3917#L834-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3918#L366 assume !(1 == ~m_pc~0); 4010#L366-2 is_master_triggered_~__retres1~0 := 0; 3668#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3454#L378 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3455#L945 assume !(0 != activate_threads_~tmp~1); 3772#L945-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3773#L385 assume 1 == ~t1_pc~0; 4079#L386 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 3840#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3615#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3616#L953 assume !(0 != activate_threads_~tmp___0~0); 4217#L953-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4218#L404 assume !(1 == ~t2_pc~0); 4222#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 3944#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3909#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3910#L961 assume !(0 != activate_threads_~tmp___1~0); 4091#L961-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3557#L423 assume 1 == ~t3_pc~0; 3496#L424 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3497#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4029#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3807#L969 assume !(0 != activate_threads_~tmp___2~0); 3808#L969-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3572#L442 assume !(1 == ~t4_pc~0); 3563#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 3564#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4063#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4110#L977 assume !(0 != activate_threads_~tmp___3~0); 4226#L977-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3753#L461 assume 1 == ~t5_pc~0; 3754#L462 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 3757#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4126#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4048#L985 assume !(0 != activate_threads_~tmp___4~0); 4049#L985-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 3896#L480 assume 1 == ~t6_pc~0; 3897#L481 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 3884#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 4210#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3716#L993 assume !(0 != activate_threads_~tmp___5~0); 3717#L993-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 3719#L499 assume !(1 == ~t7_pc~0); 4003#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 3447#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 3387#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3388#L1001 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 4180#L1001-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4181#L847 assume !(1 == ~M_E~0); 4177#L847-2 assume !(1 == ~T1_E~0); 3957#L852-1 assume !(1 == ~T2_E~0); 3768#L857-1 assume !(1 == ~T3_E~0); 3469#L862-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3470#L867-1 assume !(1 == ~T5_E~0); 4114#L872-1 assume !(1 == ~T6_E~0); 3863#L877-1 assume !(1 == ~T7_E~0); 3582#L882-1 assume !(1 == ~E_M~0); 3583#L887-1 assume !(1 == ~E_1~0); 4162#L892-1 assume !(1 == ~E_2~0); 4052#L897-1 assume !(1 == ~E_3~0); 3859#L902-1 assume 1 == ~E_4~0;~E_4~0 := 2; 3406#L907-1 assume !(1 == ~E_5~0); 3407#L912-1 assume !(1 == ~E_6~0); 4015#L917-1 assume !(1 == ~E_7~0); 3915#L922-1 assume { :end_inline_reset_delta_events } true; 3592#L1168-3 [2018-11-18 15:27:55,027 INFO L796 eck$LassoCheckResult]: Loop: 3592#L1168-3 assume true; 3593#L1168-1 assume !false; 3611#L1169 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 3673#L734 assume true; 4130#L626-1 assume !false; 4131#L627 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 3569#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 3465#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 3626#L617 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 3627#L631 assume !(0 != eval_~tmp~0); 3802#L749 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 3803#L519-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 4062#L759-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4171#L759-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3949#L764-3 assume !(0 == ~T2_E~0); 3764#L769-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3458#L774-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3459#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4112#L784-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3948#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3578#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3579#L799-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4159#L804-3 assume !(0 == ~E_2~0); 4046#L809-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3852#L814-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3393#L819-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3394#L824-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4019#L829-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3919#L834-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3920#L366-27 assume 1 == ~m_pc~0; 3982#L367-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 3664#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3418#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3419#L945-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3733#L945-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3854#L385-27 assume 1 == ~t1_pc~0; 4064#L386-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 3815#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3586#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3587#L953-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4185#L953-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4186#L404-27 assume 1 == ~t2_pc~0; 4139#L405-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3935#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3782#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3783#L961-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3962#L961-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3515#L423-27 assume 1 == ~t3_pc~0; 3490#L424-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3491#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4028#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3588#L969-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 3589#L969-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3594#L442-27 assume 1 == ~t4_pc~0; 3655#L443-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3656#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4096#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4097#L977-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 4132#L977-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3845#L461-27 assume 1 == ~t5_pc~0; 3837#L462-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 3838#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4125#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3902#L985-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 3903#L985-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 3904#L480-27 assume 1 == ~t6_pc~0; 3928#L481-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 3929#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 4191#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3663#L993-27 assume !(0 != activate_threads_~tmp___5~0); 3639#L993-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 3640#L499-27 assume !(1 == ~t7_pc~0); 3952#L499-29 is_transmit7_triggered_~__retres1~7 := 0; 3442#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 3443#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3551#L1001-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 4163#L1001-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4164#L847-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4179#L847-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3958#L852-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3770#L857-3 assume !(1 == ~T3_E~0); 3471#L862-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3472#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4115#L872-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3868#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3584#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3585#L887-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4157#L892-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4042#L897-3 assume !(1 == ~E_3~0); 3849#L902-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3389#L907-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3390#L912-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4017#L917-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3916#L922-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 3570#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 3467#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 3630#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 3631#L1187 assume !(0 == start_simulation_~tmp~3); 3776#L1187-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 3571#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 3445#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 3634#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 3635#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 3414#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 3415#L1150 start_simulation_#t~ret20 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 3540#L1200 assume !(0 != start_simulation_~tmp___0~1); 3592#L1168-3 [2018-11-18 15:27:55,027 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:27:55,027 INFO L82 PathProgramCache]: Analyzing trace with hash 33886909, now seen corresponding path program 1 times [2018-11-18 15:27:55,027 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:27:55,027 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:27:55,028 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:55,028 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:27:55,028 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:55,034 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:27:55,062 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:27:55,063 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:27:55,063 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:27:55,063 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 15:27:55,063 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:27:55,063 INFO L82 PathProgramCache]: Analyzing trace with hash -11696993, now seen corresponding path program 1 times [2018-11-18 15:27:55,063 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:27:55,064 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:27:55,064 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:55,064 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:27:55,064 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:55,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:27:55,120 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:27:55,120 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:27:55,121 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:27:55,121 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:27:55,121 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:27:55,121 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:27:55,121 INFO L87 Difference]: Start difference. First operand 840 states and 1249 transitions. cyclomatic complexity: 410 Second operand 3 states. [2018-11-18 15:27:55,130 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:27:55,130 INFO L93 Difference]: Finished difference Result 840 states and 1248 transitions. [2018-11-18 15:27:55,131 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:27:55,131 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 840 states and 1248 transitions. [2018-11-18 15:27:55,134 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 737 [2018-11-18 15:27:55,136 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 840 states to 840 states and 1248 transitions. [2018-11-18 15:27:55,136 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 840 [2018-11-18 15:27:55,137 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 840 [2018-11-18 15:27:55,137 INFO L73 IsDeterministic]: Start isDeterministic. Operand 840 states and 1248 transitions. [2018-11-18 15:27:55,137 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:27:55,138 INFO L705 BuchiCegarLoop]: Abstraction has 840 states and 1248 transitions. [2018-11-18 15:27:55,138 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 840 states and 1248 transitions. [2018-11-18 15:27:55,143 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 840 to 840. [2018-11-18 15:27:55,144 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 840 states. [2018-11-18 15:27:55,145 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 840 states to 840 states and 1248 transitions. [2018-11-18 15:27:55,145 INFO L728 BuchiCegarLoop]: Abstraction has 840 states and 1248 transitions. [2018-11-18 15:27:55,145 INFO L608 BuchiCegarLoop]: Abstraction has 840 states and 1248 transitions. [2018-11-18 15:27:55,145 INFO L442 BuchiCegarLoop]: ======== Iteration 4============ [2018-11-18 15:27:55,145 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 840 states and 1248 transitions. [2018-11-18 15:27:55,148 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 737 [2018-11-18 15:27:55,148 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:27:55,148 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:27:55,149 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:27:55,149 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:27:55,150 INFO L794 eck$LassoCheckResult]: Stem: 5510#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 5424#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 5425#L1131 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 5747#L519 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5594#L526 assume 1 == ~m_i~0;~m_st~0 := 0; 5595#L526-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5385#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5386#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5748#L541-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5582#L546-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5323#L551-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5205#L556-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5206#L561-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5861#L759 assume !(0 == ~M_E~0); 5865#L759-2 assume !(0 == ~T1_E~0); 5646#L764-1 assume !(0 == ~T2_E~0); 5458#L769-1 assume !(0 == ~T3_E~0); 5160#L774-1 assume !(0 == ~T4_E~0); 5161#L779-1 assume !(0 == ~T5_E~0); 5803#L784-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5632#L789-1 assume !(0 == ~T7_E~0); 5261#L794-1 assume !(0 == ~E_M~0); 5262#L799-1 assume !(0 == ~E_1~0); 5845#L804-1 assume !(0 == ~E_2~0); 5732#L809-1 assume !(0 == ~E_3~0); 5538#L814-1 assume !(0 == ~E_4~0); 5078#L819-1 assume !(0 == ~E_5~0); 5079#L824-1 assume 0 == ~E_6~0;~E_6~0 := 1; 5705#L829-1 assume !(0 == ~E_7~0); 5604#L834-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5605#L366 assume !(1 == ~m_pc~0); 5697#L366-2 is_master_triggered_~__retres1~0 := 0; 5355#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5141#L378 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 5142#L945 assume !(0 != activate_threads_~tmp~1); 5459#L945-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5460#L385 assume 1 == ~t1_pc~0; 5766#L386 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 5527#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5302#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 5303#L953 assume !(0 != activate_threads_~tmp___0~0); 5904#L953-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5905#L404 assume !(1 == ~t2_pc~0); 5909#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 5631#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5596#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 5597#L961 assume !(0 != activate_threads_~tmp___1~0); 5778#L961-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5244#L423 assume 1 == ~t3_pc~0; 5183#L424 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 5184#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5716#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 5494#L969 assume !(0 != activate_threads_~tmp___2~0); 5495#L969-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5259#L442 assume !(1 == ~t4_pc~0); 5250#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 5251#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5750#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5797#L977 assume !(0 != activate_threads_~tmp___3~0); 5913#L977-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5440#L461 assume 1 == ~t5_pc~0; 5441#L462 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 5444#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5813#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 5735#L985 assume !(0 != activate_threads_~tmp___4~0); 5736#L985-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 5583#L480 assume 1 == ~t6_pc~0; 5584#L481 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 5571#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 5897#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 5403#L993 assume !(0 != activate_threads_~tmp___5~0); 5404#L993-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 5406#L499 assume !(1 == ~t7_pc~0); 5690#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 5134#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 5074#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5075#L1001 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 5867#L1001-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5868#L847 assume !(1 == ~M_E~0); 5864#L847-2 assume !(1 == ~T1_E~0); 5644#L852-1 assume !(1 == ~T2_E~0); 5455#L857-1 assume !(1 == ~T3_E~0); 5156#L862-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5157#L867-1 assume !(1 == ~T5_E~0); 5801#L872-1 assume !(1 == ~T6_E~0); 5550#L877-1 assume !(1 == ~T7_E~0); 5269#L882-1 assume !(1 == ~E_M~0); 5270#L887-1 assume !(1 == ~E_1~0); 5849#L892-1 assume !(1 == ~E_2~0); 5739#L897-1 assume !(1 == ~E_3~0); 5546#L902-1 assume 1 == ~E_4~0;~E_4~0 := 2; 5093#L907-1 assume !(1 == ~E_5~0); 5094#L912-1 assume !(1 == ~E_6~0); 5702#L917-1 assume !(1 == ~E_7~0); 5602#L922-1 assume { :end_inline_reset_delta_events } true; 5279#L1168-3 [2018-11-18 15:27:55,150 INFO L796 eck$LassoCheckResult]: Loop: 5279#L1168-3 assume true; 5280#L1168-1 assume !false; 5298#L1169 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 5360#L734 assume true; 5817#L626-1 assume !false; 5818#L627 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 5256#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 5152#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 5313#L617 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 5314#L631 assume !(0 != eval_~tmp~0); 5489#L749 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 5490#L519-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 5749#L759-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5858#L759-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5636#L764-3 assume !(0 == ~T2_E~0); 5451#L769-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5145#L774-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5146#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5799#L784-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5635#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5265#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5266#L799-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5846#L804-3 assume !(0 == ~E_2~0); 5733#L809-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5539#L814-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5080#L819-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5081#L824-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5706#L829-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5606#L834-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5607#L366-27 assume 1 == ~m_pc~0; 5669#L367-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 5351#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5105#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 5106#L945-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 5420#L945-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5541#L385-27 assume 1 == ~t1_pc~0; 5751#L386-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 5502#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5273#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 5274#L953-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5872#L953-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5873#L404-27 assume 1 == ~t2_pc~0; 5826#L405-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5622#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5469#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 5470#L961-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 5649#L961-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5202#L423-27 assume 1 == ~t3_pc~0; 5177#L424-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 5178#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5715#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 5275#L969-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 5276#L969-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5281#L442-27 assume !(1 == ~t4_pc~0); 5344#L442-29 is_transmit4_triggered_~__retres1~4 := 0; 5343#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5783#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5784#L977-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 5819#L977-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5532#L461-27 assume 1 == ~t5_pc~0; 5524#L462-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 5525#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5812#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 5589#L985-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 5590#L985-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 5591#L480-27 assume !(1 == ~t6_pc~0); 5617#L480-29 is_transmit6_triggered_~__retres1~6 := 0; 5616#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 5878#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 5350#L993-27 assume !(0 != activate_threads_~tmp___5~0); 5326#L993-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 5327#L499-27 assume 1 == ~t7_pc~0; 5638#L500-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 5129#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 5130#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5238#L1001-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 5850#L1001-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5851#L847-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5866#L847-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5645#L852-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5457#L857-3 assume !(1 == ~T3_E~0); 5158#L862-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5159#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5802#L872-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5555#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5271#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5272#L887-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5844#L892-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5729#L897-3 assume !(1 == ~E_3~0); 5536#L902-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5076#L907-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5077#L912-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5704#L917-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5603#L922-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 5257#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 5154#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 5317#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 5318#L1187 assume !(0 == start_simulation_~tmp~3); 5463#L1187-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 5258#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 5132#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 5321#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 5322#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5101#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 5102#L1150 start_simulation_#t~ret20 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 5227#L1200 assume !(0 != start_simulation_~tmp___0~1); 5279#L1168-3 [2018-11-18 15:27:55,150 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:27:55,150 INFO L82 PathProgramCache]: Analyzing trace with hash 1028580607, now seen corresponding path program 1 times [2018-11-18 15:27:55,150 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:27:55,151 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:27:55,159 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:55,159 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:27:55,159 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:55,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:27:55,182 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:27:55,182 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:27:55,182 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:27:55,182 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 15:27:55,182 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:27:55,182 INFO L82 PathProgramCache]: Analyzing trace with hash -1822099296, now seen corresponding path program 1 times [2018-11-18 15:27:55,183 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:27:55,183 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:27:55,183 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:55,183 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:27:55,184 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:55,190 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:27:55,227 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:27:55,227 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:27:55,228 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:27:55,228 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:27:55,228 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:27:55,228 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:27:55,228 INFO L87 Difference]: Start difference. First operand 840 states and 1248 transitions. cyclomatic complexity: 409 Second operand 3 states. [2018-11-18 15:27:55,241 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:27:55,241 INFO L93 Difference]: Finished difference Result 840 states and 1247 transitions. [2018-11-18 15:27:55,242 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:27:55,242 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 840 states and 1247 transitions. [2018-11-18 15:27:55,244 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 737 [2018-11-18 15:27:55,246 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 840 states to 840 states and 1247 transitions. [2018-11-18 15:27:55,246 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 840 [2018-11-18 15:27:55,247 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 840 [2018-11-18 15:27:55,247 INFO L73 IsDeterministic]: Start isDeterministic. Operand 840 states and 1247 transitions. [2018-11-18 15:27:55,248 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:27:55,248 INFO L705 BuchiCegarLoop]: Abstraction has 840 states and 1247 transitions. [2018-11-18 15:27:55,249 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 840 states and 1247 transitions. [2018-11-18 15:27:55,254 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 840 to 840. [2018-11-18 15:27:55,254 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 840 states. [2018-11-18 15:27:55,256 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 840 states to 840 states and 1247 transitions. [2018-11-18 15:27:55,256 INFO L728 BuchiCegarLoop]: Abstraction has 840 states and 1247 transitions. [2018-11-18 15:27:55,256 INFO L608 BuchiCegarLoop]: Abstraction has 840 states and 1247 transitions. [2018-11-18 15:27:55,256 INFO L442 BuchiCegarLoop]: ======== Iteration 5============ [2018-11-18 15:27:55,256 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 840 states and 1247 transitions. [2018-11-18 15:27:55,258 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 737 [2018-11-18 15:27:55,258 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:27:55,258 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:27:55,260 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:27:55,260 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:27:55,260 INFO L794 eck$LassoCheckResult]: Stem: 7197#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 7111#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 7112#L1131 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 7434#L519 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7281#L526 assume 1 == ~m_i~0;~m_st~0 := 0; 7282#L526-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7074#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7075#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7435#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7269#L546-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 7010#L551-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6892#L556-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6893#L561-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7548#L759 assume !(0 == ~M_E~0); 7552#L759-2 assume !(0 == ~T1_E~0); 7334#L764-1 assume !(0 == ~T2_E~0); 7145#L769-1 assume !(0 == ~T3_E~0); 6847#L774-1 assume !(0 == ~T4_E~0); 6848#L779-1 assume !(0 == ~T5_E~0); 7490#L784-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7319#L789-1 assume !(0 == ~T7_E~0); 6948#L794-1 assume !(0 == ~E_M~0); 6949#L799-1 assume !(0 == ~E_1~0); 7532#L804-1 assume !(0 == ~E_2~0); 7419#L809-1 assume !(0 == ~E_3~0); 7225#L814-1 assume !(0 == ~E_4~0); 6765#L819-1 assume !(0 == ~E_5~0); 6766#L824-1 assume 0 == ~E_6~0;~E_6~0 := 1; 7392#L829-1 assume !(0 == ~E_7~0); 7291#L834-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7292#L366 assume !(1 == ~m_pc~0); 7384#L366-2 is_master_triggered_~__retres1~0 := 0; 7045#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6830#L378 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 6831#L945 assume !(0 != activate_threads_~tmp~1); 7146#L945-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7147#L385 assume 1 == ~t1_pc~0; 7453#L386 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 7214#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6989#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 6990#L953 assume !(0 != activate_threads_~tmp___0~0); 7591#L953-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7592#L404 assume !(1 == ~t2_pc~0); 7596#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 7318#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7283#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 7284#L961 assume !(0 != activate_threads_~tmp___1~0); 7465#L961-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6931#L423 assume 1 == ~t3_pc~0; 6870#L424 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 6871#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7403#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 7181#L969 assume !(0 != activate_threads_~tmp___2~0); 7182#L969-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6946#L442 assume !(1 == ~t4_pc~0); 6937#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 6938#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7437#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 7484#L977 assume !(0 != activate_threads_~tmp___3~0); 7600#L977-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7127#L461 assume 1 == ~t5_pc~0; 7128#L462 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 7131#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7500#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 7422#L985 assume !(0 != activate_threads_~tmp___4~0); 7423#L985-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 7270#L480 assume 1 == ~t6_pc~0; 7271#L481 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 7258#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 7585#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 7090#L993 assume !(0 != activate_threads_~tmp___5~0); 7091#L993-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 7093#L499 assume !(1 == ~t7_pc~0); 7378#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 6821#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 6761#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 6762#L1001 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 7554#L1001-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7555#L847 assume !(1 == ~M_E~0); 7551#L847-2 assume !(1 == ~T1_E~0); 7331#L852-1 assume !(1 == ~T2_E~0); 7142#L857-1 assume !(1 == ~T3_E~0); 6843#L862-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6844#L867-1 assume !(1 == ~T5_E~0); 7488#L872-1 assume !(1 == ~T6_E~0); 7238#L877-1 assume !(1 == ~T7_E~0); 6956#L882-1 assume !(1 == ~E_M~0); 6957#L887-1 assume !(1 == ~E_1~0); 7536#L892-1 assume !(1 == ~E_2~0); 7426#L897-1 assume !(1 == ~E_3~0); 7233#L902-1 assume 1 == ~E_4~0;~E_4~0 := 2; 6780#L907-1 assume !(1 == ~E_5~0); 6781#L912-1 assume !(1 == ~E_6~0); 7389#L917-1 assume !(1 == ~E_7~0); 7289#L922-1 assume { :end_inline_reset_delta_events } true; 6966#L1168-3 [2018-11-18 15:27:55,261 INFO L796 eck$LassoCheckResult]: Loop: 6966#L1168-3 assume true; 6967#L1168-1 assume !false; 6985#L1169 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 7047#L734 assume true; 7504#L626-1 assume !false; 7505#L627 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 6943#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 6839#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 7000#L617 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 7001#L631 assume !(0 != eval_~tmp~0); 7176#L749 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 7177#L519-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 7436#L759-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7545#L759-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7324#L764-3 assume !(0 == ~T2_E~0); 7138#L769-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6832#L774-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6833#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7486#L784-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7322#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6952#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 6953#L799-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7533#L804-3 assume !(0 == ~E_2~0); 7420#L809-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7226#L814-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6767#L819-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6768#L824-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7393#L829-3 assume 0 == ~E_7~0;~E_7~0 := 1; 7293#L834-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7294#L366-27 assume 1 == ~m_pc~0; 7356#L367-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 7038#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6792#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 6793#L945-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 7107#L945-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7228#L385-27 assume 1 == ~t1_pc~0; 7438#L386-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 7189#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6960#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 6961#L953-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 7559#L953-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7560#L404-27 assume 1 == ~t2_pc~0; 7513#L405-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 7309#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7156#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 7157#L961-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 7336#L961-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6889#L423-27 assume 1 == ~t3_pc~0; 6864#L424-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 6865#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7402#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 6962#L969-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 6963#L969-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6968#L442-27 assume 1 == ~t4_pc~0; 7029#L443-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 7030#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7470#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 7471#L977-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 7506#L977-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7218#L461-27 assume 1 == ~t5_pc~0; 7211#L462-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 7212#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 7499#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 7276#L985-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 7277#L985-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 7278#L480-27 assume 1 == ~t6_pc~0; 7302#L481-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 7303#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 7565#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 7037#L993-27 assume !(0 != activate_threads_~tmp___5~0); 7013#L993-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 7014#L499-27 assume 1 == ~t7_pc~0; 7325#L500-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 6816#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 6817#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 6925#L1001-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 7537#L1001-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7538#L847-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7553#L847-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7332#L852-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7144#L857-3 assume !(1 == ~T3_E~0); 6845#L862-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6846#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7489#L872-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7242#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6958#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 6959#L887-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7531#L892-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7416#L897-3 assume !(1 == ~E_3~0); 7223#L902-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6763#L907-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6764#L912-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7391#L917-3 assume 1 == ~E_7~0;~E_7~0 := 2; 7290#L922-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 6944#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 6841#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 7004#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 7005#L1187 assume !(0 == start_simulation_~tmp~3); 7150#L1187-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 6945#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 6819#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 7008#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 7009#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 6788#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 6789#L1150 start_simulation_#t~ret20 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 6914#L1200 assume !(0 != start_simulation_~tmp___0~1); 6966#L1168-3 [2018-11-18 15:27:55,261 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:27:55,261 INFO L82 PathProgramCache]: Analyzing trace with hash 1614856829, now seen corresponding path program 1 times [2018-11-18 15:27:55,261 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:27:55,261 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:27:55,262 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:55,262 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:27:55,262 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:55,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:27:55,290 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:27:55,290 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:27:55,290 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:27:55,290 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 15:27:55,290 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:27:55,291 INFO L82 PathProgramCache]: Analyzing trace with hash -1063146082, now seen corresponding path program 2 times [2018-11-18 15:27:55,291 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:27:55,291 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:27:55,291 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:55,291 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:27:55,292 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:55,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:27:55,327 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:27:55,328 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:27:55,328 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:27:55,328 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:27:55,328 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:27:55,328 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:27:55,329 INFO L87 Difference]: Start difference. First operand 840 states and 1247 transitions. cyclomatic complexity: 408 Second operand 3 states. [2018-11-18 15:27:55,353 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:27:55,353 INFO L93 Difference]: Finished difference Result 840 states and 1246 transitions. [2018-11-18 15:27:55,354 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:27:55,354 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 840 states and 1246 transitions. [2018-11-18 15:27:55,358 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 737 [2018-11-18 15:27:55,362 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 840 states to 840 states and 1246 transitions. [2018-11-18 15:27:55,362 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 840 [2018-11-18 15:27:55,363 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 840 [2018-11-18 15:27:55,363 INFO L73 IsDeterministic]: Start isDeterministic. Operand 840 states and 1246 transitions. [2018-11-18 15:27:55,364 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:27:55,364 INFO L705 BuchiCegarLoop]: Abstraction has 840 states and 1246 transitions. [2018-11-18 15:27:55,365 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 840 states and 1246 transitions. [2018-11-18 15:27:55,373 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 840 to 840. [2018-11-18 15:27:55,374 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 840 states. [2018-11-18 15:27:55,375 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 840 states to 840 states and 1246 transitions. [2018-11-18 15:27:55,376 INFO L728 BuchiCegarLoop]: Abstraction has 840 states and 1246 transitions. [2018-11-18 15:27:55,376 INFO L608 BuchiCegarLoop]: Abstraction has 840 states and 1246 transitions. [2018-11-18 15:27:55,376 INFO L442 BuchiCegarLoop]: ======== Iteration 6============ [2018-11-18 15:27:55,376 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 840 states and 1246 transitions. [2018-11-18 15:27:55,379 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 737 [2018-11-18 15:27:55,379 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:27:55,379 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:27:55,380 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:27:55,380 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:27:55,381 INFO L794 eck$LassoCheckResult]: Stem: 8884#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 8798#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 8799#L1131 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 9121#L519 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8968#L526 assume 1 == ~m_i~0;~m_st~0 := 0; 8969#L526-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8761#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8762#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9122#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8956#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8697#L551-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8579#L556-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8580#L561-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9235#L759 assume !(0 == ~M_E~0); 9239#L759-2 assume !(0 == ~T1_E~0); 9021#L764-1 assume !(0 == ~T2_E~0); 8832#L769-1 assume !(0 == ~T3_E~0); 8534#L774-1 assume !(0 == ~T4_E~0); 8535#L779-1 assume !(0 == ~T5_E~0); 9177#L784-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9006#L789-1 assume !(0 == ~T7_E~0); 8635#L794-1 assume !(0 == ~E_M~0); 8636#L799-1 assume !(0 == ~E_1~0); 9219#L804-1 assume !(0 == ~E_2~0); 9106#L809-1 assume !(0 == ~E_3~0); 8912#L814-1 assume !(0 == ~E_4~0); 8452#L819-1 assume !(0 == ~E_5~0); 8453#L824-1 assume 0 == ~E_6~0;~E_6~0 := 1; 9079#L829-1 assume !(0 == ~E_7~0); 8978#L834-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8979#L366 assume !(1 == ~m_pc~0); 9071#L366-2 is_master_triggered_~__retres1~0 := 0; 8729#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8517#L378 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 8518#L945 assume !(0 != activate_threads_~tmp~1); 8833#L945-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8834#L385 assume 1 == ~t1_pc~0; 9140#L386 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 8901#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8676#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 8677#L953 assume !(0 != activate_threads_~tmp___0~0); 9278#L953-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9279#L404 assume !(1 == ~t2_pc~0); 9283#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 9005#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8970#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 8971#L961 assume !(0 != activate_threads_~tmp___1~0); 9152#L961-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8618#L423 assume 1 == ~t3_pc~0; 8557#L424 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 8558#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9090#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 8868#L969 assume !(0 != activate_threads_~tmp___2~0); 8869#L969-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 8633#L442 assume !(1 == ~t4_pc~0); 8624#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 8625#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9124#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 9171#L977 assume !(0 != activate_threads_~tmp___3~0); 9287#L977-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 8814#L461 assume 1 == ~t5_pc~0; 8815#L462 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 8818#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 9187#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 9109#L985 assume !(0 != activate_threads_~tmp___4~0); 9110#L985-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 8957#L480 assume 1 == ~t6_pc~0; 8958#L481 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 8945#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 9271#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 8777#L993 assume !(0 != activate_threads_~tmp___5~0); 8778#L993-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 8780#L499 assume !(1 == ~t7_pc~0); 9064#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 8508#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 8448#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 8449#L1001 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 9241#L1001-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9242#L847 assume !(1 == ~M_E~0); 9238#L847-2 assume !(1 == ~T1_E~0); 9018#L852-1 assume !(1 == ~T2_E~0); 8829#L857-1 assume !(1 == ~T3_E~0); 8530#L862-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8531#L867-1 assume !(1 == ~T5_E~0); 9175#L872-1 assume !(1 == ~T6_E~0); 8925#L877-1 assume !(1 == ~T7_E~0); 8643#L882-1 assume !(1 == ~E_M~0); 8644#L887-1 assume !(1 == ~E_1~0); 9223#L892-1 assume !(1 == ~E_2~0); 9113#L897-1 assume !(1 == ~E_3~0); 8920#L902-1 assume 1 == ~E_4~0;~E_4~0 := 2; 8467#L907-1 assume !(1 == ~E_5~0); 8468#L912-1 assume !(1 == ~E_6~0); 9076#L917-1 assume !(1 == ~E_7~0); 8976#L922-1 assume { :end_inline_reset_delta_events } true; 8653#L1168-3 [2018-11-18 15:27:55,381 INFO L796 eck$LassoCheckResult]: Loop: 8653#L1168-3 assume true; 8654#L1168-1 assume !false; 8672#L1169 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 8734#L734 assume true; 9191#L626-1 assume !false; 9192#L627 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 8630#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 8526#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 8687#L617 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 8688#L631 assume !(0 != eval_~tmp~0); 8863#L749 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 8864#L519-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 9123#L759-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9232#L759-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9011#L764-3 assume !(0 == ~T2_E~0); 8825#L769-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8519#L774-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8520#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9173#L784-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9009#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8639#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8640#L799-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9220#L804-3 assume !(0 == ~E_2~0); 9107#L809-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8913#L814-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8454#L819-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8455#L824-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9080#L829-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8980#L834-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8981#L366-27 assume 1 == ~m_pc~0; 9043#L367-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 8725#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8479#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 8480#L945-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 8794#L945-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8915#L385-27 assume 1 == ~t1_pc~0; 9125#L386-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 8876#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8647#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 8648#L953-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 9246#L953-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9247#L404-27 assume 1 == ~t2_pc~0; 9200#L405-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 8996#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8843#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 8844#L961-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 9025#L961-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8576#L423-27 assume 1 == ~t3_pc~0; 8551#L424-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 8552#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9089#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 8649#L969-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 8650#L969-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 8655#L442-27 assume 1 == ~t4_pc~0; 8716#L443-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 8717#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9157#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 9158#L977-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 9193#L977-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 8905#L461-27 assume 1 == ~t5_pc~0; 8897#L462-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 8898#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 9186#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 8963#L985-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 8964#L985-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 8965#L480-27 assume 1 == ~t6_pc~0; 8988#L481-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 8989#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 9251#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 8724#L993-27 assume !(0 != activate_threads_~tmp___5~0); 8700#L993-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 8701#L499-27 assume 1 == ~t7_pc~0; 9012#L500-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 8501#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 8502#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 8612#L1001-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 9224#L1001-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9225#L847-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9240#L847-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9019#L852-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8831#L857-3 assume !(1 == ~T3_E~0); 8532#L862-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8533#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9176#L872-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8929#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8645#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8646#L887-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9218#L892-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9103#L897-3 assume !(1 == ~E_3~0); 8910#L902-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8450#L907-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8451#L912-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9078#L917-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8977#L922-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 8631#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 8528#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 8691#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 8692#L1187 assume !(0 == start_simulation_~tmp~3); 8837#L1187-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 8632#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 8506#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 8695#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 8696#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 8475#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 8476#L1150 start_simulation_#t~ret20 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 8601#L1200 assume !(0 != start_simulation_~tmp___0~1); 8653#L1168-3 [2018-11-18 15:27:55,381 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:27:55,381 INFO L82 PathProgramCache]: Analyzing trace with hash -721535681, now seen corresponding path program 1 times [2018-11-18 15:27:55,381 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:27:55,381 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:27:55,382 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:55,382 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:27:55,382 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:55,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:27:55,414 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:27:55,415 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:27:55,415 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:27:55,415 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 15:27:55,415 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:27:55,415 INFO L82 PathProgramCache]: Analyzing trace with hash -1063146082, now seen corresponding path program 3 times [2018-11-18 15:27:55,416 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:27:55,416 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:27:55,416 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:55,416 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:27:55,416 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:55,423 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:27:55,467 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:27:55,467 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:27:55,467 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:27:55,468 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:27:55,468 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:27:55,468 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:27:55,468 INFO L87 Difference]: Start difference. First operand 840 states and 1246 transitions. cyclomatic complexity: 407 Second operand 3 states. [2018-11-18 15:27:55,481 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:27:55,481 INFO L93 Difference]: Finished difference Result 840 states and 1245 transitions. [2018-11-18 15:27:55,482 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:27:55,482 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 840 states and 1245 transitions. [2018-11-18 15:27:55,486 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 737 [2018-11-18 15:27:55,490 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 840 states to 840 states and 1245 transitions. [2018-11-18 15:27:55,490 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 840 [2018-11-18 15:27:55,490 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 840 [2018-11-18 15:27:55,491 INFO L73 IsDeterministic]: Start isDeterministic. Operand 840 states and 1245 transitions. [2018-11-18 15:27:55,493 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:27:55,493 INFO L705 BuchiCegarLoop]: Abstraction has 840 states and 1245 transitions. [2018-11-18 15:27:55,494 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 840 states and 1245 transitions. [2018-11-18 15:27:55,502 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 840 to 840. [2018-11-18 15:27:55,503 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 840 states. [2018-11-18 15:27:55,504 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 840 states to 840 states and 1245 transitions. [2018-11-18 15:27:55,505 INFO L728 BuchiCegarLoop]: Abstraction has 840 states and 1245 transitions. [2018-11-18 15:27:55,505 INFO L608 BuchiCegarLoop]: Abstraction has 840 states and 1245 transitions. [2018-11-18 15:27:55,505 INFO L442 BuchiCegarLoop]: ======== Iteration 7============ [2018-11-18 15:27:55,505 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 840 states and 1245 transitions. [2018-11-18 15:27:55,508 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 737 [2018-11-18 15:27:55,508 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:27:55,508 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:27:55,509 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:27:55,509 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:27:55,510 INFO L794 eck$LassoCheckResult]: Stem: 10571#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 10485#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 10486#L1131 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 10808#L519 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10655#L526 assume 1 == ~m_i~0;~m_st~0 := 0; 10656#L526-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10446#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10447#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10809#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10643#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10384#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 10266#L556-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10267#L561-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10922#L759 assume !(0 == ~M_E~0); 10926#L759-2 assume !(0 == ~T1_E~0); 10707#L764-1 assume !(0 == ~T2_E~0); 10519#L769-1 assume !(0 == ~T3_E~0); 10221#L774-1 assume !(0 == ~T4_E~0); 10222#L779-1 assume !(0 == ~T5_E~0); 10864#L784-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10693#L789-1 assume !(0 == ~T7_E~0); 10322#L794-1 assume !(0 == ~E_M~0); 10323#L799-1 assume !(0 == ~E_1~0); 10906#L804-1 assume !(0 == ~E_2~0); 10793#L809-1 assume !(0 == ~E_3~0); 10599#L814-1 assume !(0 == ~E_4~0); 10139#L819-1 assume !(0 == ~E_5~0); 10140#L824-1 assume 0 == ~E_6~0;~E_6~0 := 1; 10766#L829-1 assume !(0 == ~E_7~0); 10665#L834-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10666#L366 assume !(1 == ~m_pc~0); 10758#L366-2 is_master_triggered_~__retres1~0 := 0; 10416#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10202#L378 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 10203#L945 assume !(0 != activate_threads_~tmp~1); 10520#L945-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10521#L385 assume 1 == ~t1_pc~0; 10827#L386 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 10588#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10363#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 10364#L953 assume !(0 != activate_threads_~tmp___0~0); 10965#L953-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10966#L404 assume !(1 == ~t2_pc~0); 10970#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 10692#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10657#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 10658#L961 assume !(0 != activate_threads_~tmp___1~0); 10839#L961-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 10305#L423 assume 1 == ~t3_pc~0; 10244#L424 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 10245#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 10777#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 10555#L969 assume !(0 != activate_threads_~tmp___2~0); 10556#L969-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 10320#L442 assume !(1 == ~t4_pc~0); 10311#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 10312#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 10811#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 10858#L977 assume !(0 != activate_threads_~tmp___3~0); 10974#L977-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 10501#L461 assume 1 == ~t5_pc~0; 10502#L462 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 10505#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 10874#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 10796#L985 assume !(0 != activate_threads_~tmp___4~0); 10797#L985-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 10644#L480 assume 1 == ~t6_pc~0; 10645#L481 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 10632#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 10958#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 10464#L993 assume !(0 != activate_threads_~tmp___5~0); 10465#L993-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 10467#L499 assume !(1 == ~t7_pc~0); 10751#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 10195#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 10135#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 10136#L1001 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 10928#L1001-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10929#L847 assume !(1 == ~M_E~0); 10925#L847-2 assume !(1 == ~T1_E~0); 10705#L852-1 assume !(1 == ~T2_E~0); 10516#L857-1 assume !(1 == ~T3_E~0); 10217#L862-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10218#L867-1 assume !(1 == ~T5_E~0); 10862#L872-1 assume !(1 == ~T6_E~0); 10611#L877-1 assume !(1 == ~T7_E~0); 10330#L882-1 assume !(1 == ~E_M~0); 10331#L887-1 assume !(1 == ~E_1~0); 10910#L892-1 assume !(1 == ~E_2~0); 10800#L897-1 assume !(1 == ~E_3~0); 10607#L902-1 assume 1 == ~E_4~0;~E_4~0 := 2; 10154#L907-1 assume !(1 == ~E_5~0); 10155#L912-1 assume !(1 == ~E_6~0); 10763#L917-1 assume !(1 == ~E_7~0); 10663#L922-1 assume { :end_inline_reset_delta_events } true; 10340#L1168-3 [2018-11-18 15:27:55,510 INFO L796 eck$LassoCheckResult]: Loop: 10340#L1168-3 assume true; 10341#L1168-1 assume !false; 10359#L1169 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 10421#L734 assume true; 10878#L626-1 assume !false; 10879#L627 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 10317#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 10213#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 10374#L617 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 10375#L631 assume !(0 != eval_~tmp~0); 10550#L749 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 10551#L519-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 10810#L759-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10919#L759-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10697#L764-3 assume !(0 == ~T2_E~0); 10512#L769-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10206#L774-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10207#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10860#L784-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10696#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10326#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 10327#L799-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10907#L804-3 assume !(0 == ~E_2~0); 10794#L809-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10600#L814-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10141#L819-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10142#L824-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10767#L829-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10667#L834-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10668#L366-27 assume 1 == ~m_pc~0; 10730#L367-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 10412#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10166#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 10167#L945-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 10481#L945-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10602#L385-27 assume 1 == ~t1_pc~0; 10812#L386-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 10563#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10334#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 10335#L953-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 10933#L953-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10934#L404-27 assume 1 == ~t2_pc~0; 10887#L405-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 10683#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10530#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 10531#L961-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 10710#L961-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 10263#L423-27 assume !(1 == ~t3_pc~0); 10240#L423-29 is_transmit3_triggered_~__retres1~3 := 0; 10239#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 10776#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 10336#L969-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 10337#L969-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 10342#L442-27 assume 1 == ~t4_pc~0; 10403#L443-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 10404#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 10844#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 10845#L977-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 10880#L977-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 10593#L461-27 assume 1 == ~t5_pc~0; 10585#L462-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 10586#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 10873#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 10650#L985-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 10651#L985-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 10652#L480-27 assume 1 == ~t6_pc~0; 10676#L481-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 10677#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 10939#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 10411#L993-27 assume !(0 != activate_threads_~tmp___5~0); 10387#L993-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 10388#L499-27 assume 1 == ~t7_pc~0; 10699#L500-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 10190#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 10191#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 10299#L1001-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 10911#L1001-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10912#L847-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10927#L847-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10706#L852-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10518#L857-3 assume !(1 == ~T3_E~0); 10219#L862-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10220#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10863#L872-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10616#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10332#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 10333#L887-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10905#L892-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10790#L897-3 assume !(1 == ~E_3~0); 10597#L902-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10137#L907-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10138#L912-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10765#L917-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10664#L922-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 10318#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 10215#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 10378#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 10379#L1187 assume !(0 == start_simulation_~tmp~3); 10524#L1187-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 10319#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 10193#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 10382#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 10383#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 10162#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 10163#L1150 start_simulation_#t~ret20 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 10288#L1200 assume !(0 != start_simulation_~tmp___0~1); 10340#L1168-3 [2018-11-18 15:27:55,510 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:27:55,510 INFO L82 PathProgramCache]: Analyzing trace with hash 1696948797, now seen corresponding path program 1 times [2018-11-18 15:27:55,510 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:27:55,510 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:27:55,511 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:55,511 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:27:55,511 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:55,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:27:55,544 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:27:55,544 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:27:55,544 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:27:55,544 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 15:27:55,544 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:27:55,544 INFO L82 PathProgramCache]: Analyzing trace with hash -2094476897, now seen corresponding path program 1 times [2018-11-18 15:27:55,545 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:27:55,545 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:27:55,545 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:55,545 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:27:55,545 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:55,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:27:55,590 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:27:55,590 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:27:55,590 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:27:55,590 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:27:55,591 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:27:55,591 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:27:55,591 INFO L87 Difference]: Start difference. First operand 840 states and 1245 transitions. cyclomatic complexity: 406 Second operand 3 states. [2018-11-18 15:27:55,620 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:27:55,620 INFO L93 Difference]: Finished difference Result 840 states and 1244 transitions. [2018-11-18 15:27:55,620 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:27:55,620 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 840 states and 1244 transitions. [2018-11-18 15:27:55,624 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 737 [2018-11-18 15:27:55,627 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 840 states to 840 states and 1244 transitions. [2018-11-18 15:27:55,627 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 840 [2018-11-18 15:27:55,628 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 840 [2018-11-18 15:27:55,628 INFO L73 IsDeterministic]: Start isDeterministic. Operand 840 states and 1244 transitions. [2018-11-18 15:27:55,629 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:27:55,629 INFO L705 BuchiCegarLoop]: Abstraction has 840 states and 1244 transitions. [2018-11-18 15:27:55,631 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 840 states and 1244 transitions. [2018-11-18 15:27:55,640 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 840 to 840. [2018-11-18 15:27:55,640 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 840 states. [2018-11-18 15:27:55,642 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 840 states to 840 states and 1244 transitions. [2018-11-18 15:27:55,642 INFO L728 BuchiCegarLoop]: Abstraction has 840 states and 1244 transitions. [2018-11-18 15:27:55,643 INFO L608 BuchiCegarLoop]: Abstraction has 840 states and 1244 transitions. [2018-11-18 15:27:55,643 INFO L442 BuchiCegarLoop]: ======== Iteration 8============ [2018-11-18 15:27:55,643 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 840 states and 1244 transitions. [2018-11-18 15:27:55,646 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 737 [2018-11-18 15:27:55,646 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:27:55,646 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:27:55,647 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:27:55,647 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:27:55,647 INFO L794 eck$LassoCheckResult]: Stem: 12258#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 12172#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 12173#L1131 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 12495#L519 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12342#L526 assume 1 == ~m_i~0;~m_st~0 := 0; 12343#L526-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12133#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12134#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12496#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12330#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12071#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 11953#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 11954#L561-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12609#L759 assume !(0 == ~M_E~0); 12613#L759-2 assume !(0 == ~T1_E~0); 12394#L764-1 assume !(0 == ~T2_E~0); 12206#L769-1 assume !(0 == ~T3_E~0); 11908#L774-1 assume !(0 == ~T4_E~0); 11909#L779-1 assume !(0 == ~T5_E~0); 12551#L784-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12380#L789-1 assume !(0 == ~T7_E~0); 12009#L794-1 assume !(0 == ~E_M~0); 12010#L799-1 assume !(0 == ~E_1~0); 12593#L804-1 assume !(0 == ~E_2~0); 12480#L809-1 assume !(0 == ~E_3~0); 12286#L814-1 assume !(0 == ~E_4~0); 11826#L819-1 assume !(0 == ~E_5~0); 11827#L824-1 assume 0 == ~E_6~0;~E_6~0 := 1; 12453#L829-1 assume !(0 == ~E_7~0); 12352#L834-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12353#L366 assume !(1 == ~m_pc~0); 12445#L366-2 is_master_triggered_~__retres1~0 := 0; 12103#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 11889#L378 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 11890#L945 assume !(0 != activate_threads_~tmp~1); 12207#L945-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12208#L385 assume 1 == ~t1_pc~0; 12514#L386 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 12275#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12050#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 12051#L953 assume !(0 != activate_threads_~tmp___0~0); 12652#L953-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12653#L404 assume !(1 == ~t2_pc~0); 12657#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 12379#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12344#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 12345#L961 assume !(0 != activate_threads_~tmp___1~0); 12526#L961-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 11992#L423 assume 1 == ~t3_pc~0; 11931#L424 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 11932#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 12464#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 12242#L969 assume !(0 != activate_threads_~tmp___2~0); 12243#L969-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 12007#L442 assume !(1 == ~t4_pc~0); 11998#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 11999#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 12498#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 12545#L977 assume !(0 != activate_threads_~tmp___3~0); 12661#L977-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 12188#L461 assume 1 == ~t5_pc~0; 12189#L462 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 12192#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 12561#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 12483#L985 assume !(0 != activate_threads_~tmp___4~0); 12484#L985-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 12331#L480 assume 1 == ~t6_pc~0; 12332#L481 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 12319#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 12645#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 12151#L993 assume !(0 != activate_threads_~tmp___5~0); 12152#L993-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 12154#L499 assume !(1 == ~t7_pc~0); 12438#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 11882#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 11822#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 11823#L1001 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 12615#L1001-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12616#L847 assume !(1 == ~M_E~0); 12612#L847-2 assume !(1 == ~T1_E~0); 12392#L852-1 assume !(1 == ~T2_E~0); 12203#L857-1 assume !(1 == ~T3_E~0); 11904#L862-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11905#L867-1 assume !(1 == ~T5_E~0); 12549#L872-1 assume !(1 == ~T6_E~0); 12298#L877-1 assume !(1 == ~T7_E~0); 12017#L882-1 assume !(1 == ~E_M~0); 12018#L887-1 assume !(1 == ~E_1~0); 12597#L892-1 assume !(1 == ~E_2~0); 12487#L897-1 assume !(1 == ~E_3~0); 12294#L902-1 assume 1 == ~E_4~0;~E_4~0 := 2; 11841#L907-1 assume !(1 == ~E_5~0); 11842#L912-1 assume !(1 == ~E_6~0); 12450#L917-1 assume !(1 == ~E_7~0); 12350#L922-1 assume { :end_inline_reset_delta_events } true; 12027#L1168-3 [2018-11-18 15:27:55,648 INFO L796 eck$LassoCheckResult]: Loop: 12027#L1168-3 assume true; 12028#L1168-1 assume !false; 12046#L1169 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 12108#L734 assume true; 12565#L626-1 assume !false; 12566#L627 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 12004#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 11900#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 12061#L617 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 12062#L631 assume !(0 != eval_~tmp~0); 12237#L749 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 12238#L519-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 12497#L759-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12606#L759-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12384#L764-3 assume !(0 == ~T2_E~0); 12199#L769-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11893#L774-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11894#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12547#L784-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 12383#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12013#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 12014#L799-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12594#L804-3 assume !(0 == ~E_2~0); 12481#L809-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12287#L814-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11828#L819-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11829#L824-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12454#L829-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12354#L834-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12355#L366-27 assume 1 == ~m_pc~0; 12417#L367-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 12099#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 11853#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 11854#L945-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 12168#L945-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12289#L385-27 assume 1 == ~t1_pc~0; 12499#L386-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 12250#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12021#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 12022#L953-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 12620#L953-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12621#L404-27 assume 1 == ~t2_pc~0; 12574#L405-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 12370#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12217#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 12218#L961-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 12397#L961-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 11950#L423-27 assume 1 == ~t3_pc~0; 11925#L424-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 11926#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 12463#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 12023#L969-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 12024#L969-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 12029#L442-27 assume 1 == ~t4_pc~0; 12090#L443-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 12091#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 12531#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 12532#L977-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 12567#L977-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 12280#L461-27 assume 1 == ~t5_pc~0; 12272#L462-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 12273#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 12560#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 12337#L985-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 12338#L985-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 12339#L480-27 assume 1 == ~t6_pc~0; 12363#L481-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 12364#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 12626#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 12098#L993-27 assume !(0 != activate_threads_~tmp___5~0); 12074#L993-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 12075#L499-27 assume 1 == ~t7_pc~0; 12386#L500-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 11877#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 11878#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 11986#L1001-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 12598#L1001-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12599#L847-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12614#L847-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12393#L852-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12205#L857-3 assume !(1 == ~T3_E~0); 11906#L862-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11907#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12550#L872-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12303#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12019#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12020#L887-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12592#L892-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12477#L897-3 assume !(1 == ~E_3~0); 12284#L902-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11824#L907-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11825#L912-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12452#L917-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12351#L922-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 12005#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 11902#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 12065#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 12066#L1187 assume !(0 == start_simulation_~tmp~3); 12211#L1187-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 12006#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 11880#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 12069#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 12070#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 11849#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 11850#L1150 start_simulation_#t~ret20 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 11975#L1200 assume !(0 != start_simulation_~tmp___0~1); 12027#L1168-3 [2018-11-18 15:27:55,648 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:27:55,648 INFO L82 PathProgramCache]: Analyzing trace with hash -718887553, now seen corresponding path program 1 times [2018-11-18 15:27:55,648 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:27:55,648 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:27:55,649 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:55,649 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:27:55,649 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:55,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:27:55,680 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:27:55,680 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:27:55,681 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 15:27:55,681 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 15:27:55,681 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:27:55,681 INFO L82 PathProgramCache]: Analyzing trace with hash -1063146082, now seen corresponding path program 4 times [2018-11-18 15:27:55,681 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:27:55,681 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:27:55,682 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:55,682 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:27:55,682 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:55,687 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:27:55,715 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:27:55,716 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:27:55,716 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:27:55,716 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:27:55,716 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:27:55,716 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:27:55,716 INFO L87 Difference]: Start difference. First operand 840 states and 1244 transitions. cyclomatic complexity: 405 Second operand 3 states. [2018-11-18 15:27:55,741 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:27:55,742 INFO L93 Difference]: Finished difference Result 840 states and 1239 transitions. [2018-11-18 15:27:55,743 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:27:55,743 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 840 states and 1239 transitions. [2018-11-18 15:27:55,746 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 737 [2018-11-18 15:27:55,750 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 840 states to 840 states and 1239 transitions. [2018-11-18 15:27:55,751 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 840 [2018-11-18 15:27:55,752 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 840 [2018-11-18 15:27:55,752 INFO L73 IsDeterministic]: Start isDeterministic. Operand 840 states and 1239 transitions. [2018-11-18 15:27:55,753 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:27:55,753 INFO L705 BuchiCegarLoop]: Abstraction has 840 states and 1239 transitions. [2018-11-18 15:27:55,754 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 840 states and 1239 transitions. [2018-11-18 15:27:55,765 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 840 to 840. [2018-11-18 15:27:55,765 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 840 states. [2018-11-18 15:27:55,767 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 840 states to 840 states and 1239 transitions. [2018-11-18 15:27:55,767 INFO L728 BuchiCegarLoop]: Abstraction has 840 states and 1239 transitions. [2018-11-18 15:27:55,767 INFO L608 BuchiCegarLoop]: Abstraction has 840 states and 1239 transitions. [2018-11-18 15:27:55,769 INFO L442 BuchiCegarLoop]: ======== Iteration 9============ [2018-11-18 15:27:55,769 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 840 states and 1239 transitions. [2018-11-18 15:27:55,771 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 737 [2018-11-18 15:27:55,772 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:27:55,772 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:27:55,773 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:27:55,773 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:27:55,773 INFO L794 eck$LassoCheckResult]: Stem: 13945#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 13859#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 13860#L1131 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 14182#L519 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14029#L526 assume 1 == ~m_i~0;~m_st~0 := 0; 14030#L526-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13820#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13821#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14183#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14017#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 13758#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 13640#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 13641#L561-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14296#L759 assume !(0 == ~M_E~0); 14300#L759-2 assume !(0 == ~T1_E~0); 14081#L764-1 assume !(0 == ~T2_E~0); 13893#L769-1 assume !(0 == ~T3_E~0); 13595#L774-1 assume !(0 == ~T4_E~0); 13596#L779-1 assume !(0 == ~T5_E~0); 14238#L784-1 assume !(0 == ~T6_E~0); 14067#L789-1 assume !(0 == ~T7_E~0); 13696#L794-1 assume !(0 == ~E_M~0); 13697#L799-1 assume !(0 == ~E_1~0); 14280#L804-1 assume !(0 == ~E_2~0); 14167#L809-1 assume !(0 == ~E_3~0); 13973#L814-1 assume !(0 == ~E_4~0); 13513#L819-1 assume !(0 == ~E_5~0); 13514#L824-1 assume 0 == ~E_6~0;~E_6~0 := 1; 14140#L829-1 assume !(0 == ~E_7~0); 14039#L834-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 14040#L366 assume !(1 == ~m_pc~0); 14132#L366-2 is_master_triggered_~__retres1~0 := 0; 13790#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 13576#L378 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 13577#L945 assume !(0 != activate_threads_~tmp~1); 13894#L945-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 13895#L385 assume 1 == ~t1_pc~0; 14201#L386 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 13962#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 13737#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 13738#L953 assume !(0 != activate_threads_~tmp___0~0); 14339#L953-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 14340#L404 assume !(1 == ~t2_pc~0); 14344#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 14066#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 14031#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 14032#L961 assume !(0 != activate_threads_~tmp___1~0); 14213#L961-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 13679#L423 assume 1 == ~t3_pc~0; 13618#L424 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 13619#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 14151#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 13929#L969 assume !(0 != activate_threads_~tmp___2~0); 13930#L969-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 13694#L442 assume !(1 == ~t4_pc~0); 13685#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 13686#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 14185#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 14232#L977 assume !(0 != activate_threads_~tmp___3~0); 14348#L977-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 13875#L461 assume 1 == ~t5_pc~0; 13876#L462 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 13879#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 14248#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 14170#L985 assume !(0 != activate_threads_~tmp___4~0); 14171#L985-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 14018#L480 assume 1 == ~t6_pc~0; 14019#L481 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 14006#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 14332#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 13838#L993 assume !(0 != activate_threads_~tmp___5~0); 13839#L993-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 13841#L499 assume !(1 == ~t7_pc~0); 14125#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 13569#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 13509#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 13510#L1001 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 14302#L1001-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14303#L847 assume !(1 == ~M_E~0); 14299#L847-2 assume !(1 == ~T1_E~0); 14079#L852-1 assume !(1 == ~T2_E~0); 13890#L857-1 assume !(1 == ~T3_E~0); 13591#L862-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13592#L867-1 assume !(1 == ~T5_E~0); 14236#L872-1 assume !(1 == ~T6_E~0); 13985#L877-1 assume !(1 == ~T7_E~0); 13704#L882-1 assume !(1 == ~E_M~0); 13705#L887-1 assume !(1 == ~E_1~0); 14284#L892-1 assume !(1 == ~E_2~0); 14174#L897-1 assume !(1 == ~E_3~0); 13981#L902-1 assume 1 == ~E_4~0;~E_4~0 := 2; 13528#L907-1 assume !(1 == ~E_5~0); 13529#L912-1 assume !(1 == ~E_6~0); 14137#L917-1 assume !(1 == ~E_7~0); 14037#L922-1 assume { :end_inline_reset_delta_events } true; 13714#L1168-3 [2018-11-18 15:27:55,773 INFO L796 eck$LassoCheckResult]: Loop: 13714#L1168-3 assume true; 13715#L1168-1 assume !false; 13733#L1169 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 13795#L734 assume true; 14252#L626-1 assume !false; 14253#L627 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 13691#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 13587#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 13748#L617 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 13749#L631 assume !(0 != eval_~tmp~0); 13924#L749 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 13925#L519-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 14184#L759-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14293#L759-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14071#L764-3 assume !(0 == ~T2_E~0); 13886#L769-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13580#L774-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13581#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14234#L784-3 assume !(0 == ~T6_E~0); 14070#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 13700#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 13701#L799-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14281#L804-3 assume !(0 == ~E_2~0); 14168#L809-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13974#L814-3 assume 0 == ~E_4~0;~E_4~0 := 1; 13515#L819-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13516#L824-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14141#L829-3 assume 0 == ~E_7~0;~E_7~0 := 1; 14041#L834-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 14042#L366-27 assume 1 == ~m_pc~0; 14104#L367-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 13786#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 13540#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 13541#L945-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 13855#L945-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 13976#L385-27 assume 1 == ~t1_pc~0; 14186#L386-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 13937#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 13708#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 13709#L953-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 14307#L953-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 14308#L404-27 assume 1 == ~t2_pc~0; 14261#L405-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 14057#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 13904#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 13905#L961-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 14084#L961-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 13637#L423-27 assume 1 == ~t3_pc~0; 13612#L424-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 13613#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 14150#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 13710#L969-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 13711#L969-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 13716#L442-27 assume 1 == ~t4_pc~0; 13777#L443-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 13778#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 14218#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 14219#L977-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 14254#L977-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 13967#L461-27 assume 1 == ~t5_pc~0; 13959#L462-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 13960#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 14247#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 14024#L985-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 14025#L985-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 14026#L480-27 assume 1 == ~t6_pc~0; 14050#L481-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 14051#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 14313#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 13785#L993-27 assume !(0 != activate_threads_~tmp___5~0); 13761#L993-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 13762#L499-27 assume 1 == ~t7_pc~0; 14073#L500-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 13564#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 13565#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 13673#L1001-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 14285#L1001-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14286#L847-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14301#L847-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14080#L852-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13892#L857-3 assume !(1 == ~T3_E~0); 13593#L862-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13594#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14237#L872-3 assume !(1 == ~T6_E~0); 13990#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13706#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 13707#L887-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14279#L892-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14164#L897-3 assume !(1 == ~E_3~0); 13971#L902-3 assume 1 == ~E_4~0;~E_4~0 := 2; 13511#L907-3 assume 1 == ~E_5~0;~E_5~0 := 2; 13512#L912-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14139#L917-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14038#L922-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 13692#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 13589#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 13752#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 13753#L1187 assume !(0 == start_simulation_~tmp~3); 13898#L1187-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 13693#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 13567#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 13756#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 13757#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 13536#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 13537#L1150 start_simulation_#t~ret20 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 13662#L1200 assume !(0 != start_simulation_~tmp___0~1); 13714#L1168-3 [2018-11-18 15:27:55,774 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:27:55,774 INFO L82 PathProgramCache]: Analyzing trace with hash 1498742845, now seen corresponding path program 1 times [2018-11-18 15:27:55,774 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:27:55,774 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:27:55,775 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:55,775 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:27:55,775 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:55,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:27:55,797 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:27:55,797 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:27:55,797 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 15:27:55,798 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 15:27:55,798 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:27:55,798 INFO L82 PathProgramCache]: Analyzing trace with hash 431689182, now seen corresponding path program 1 times [2018-11-18 15:27:55,798 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:27:55,798 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:27:55,799 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:55,799 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:27:55,799 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:55,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:27:55,831 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:27:55,831 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:27:55,831 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:27:55,831 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:27:55,832 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:27:55,832 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:27:55,832 INFO L87 Difference]: Start difference. First operand 840 states and 1239 transitions. cyclomatic complexity: 400 Second operand 3 states. [2018-11-18 15:27:55,886 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:27:55,886 INFO L93 Difference]: Finished difference Result 840 states and 1224 transitions. [2018-11-18 15:27:55,887 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:27:55,887 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 840 states and 1224 transitions. [2018-11-18 15:27:55,890 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 737 [2018-11-18 15:27:55,893 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 840 states to 840 states and 1224 transitions. [2018-11-18 15:27:55,894 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 840 [2018-11-18 15:27:55,894 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 840 [2018-11-18 15:27:55,894 INFO L73 IsDeterministic]: Start isDeterministic. Operand 840 states and 1224 transitions. [2018-11-18 15:27:55,895 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:27:55,895 INFO L705 BuchiCegarLoop]: Abstraction has 840 states and 1224 transitions. [2018-11-18 15:27:55,897 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 840 states and 1224 transitions. [2018-11-18 15:27:55,904 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 840 to 840. [2018-11-18 15:27:55,904 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 840 states. [2018-11-18 15:27:55,906 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 840 states to 840 states and 1224 transitions. [2018-11-18 15:27:55,906 INFO L728 BuchiCegarLoop]: Abstraction has 840 states and 1224 transitions. [2018-11-18 15:27:55,906 INFO L608 BuchiCegarLoop]: Abstraction has 840 states and 1224 transitions. [2018-11-18 15:27:55,906 INFO L442 BuchiCegarLoop]: ======== Iteration 10============ [2018-11-18 15:27:55,906 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 840 states and 1224 transitions. [2018-11-18 15:27:55,909 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 737 [2018-11-18 15:27:55,909 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:27:55,909 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:27:55,910 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:27:55,910 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:27:55,911 INFO L794 eck$LassoCheckResult]: Stem: 15632#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 15546#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 15547#L1131 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 15869#L519 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15716#L526 assume 1 == ~m_i~0;~m_st~0 := 0; 15717#L526-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15507#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15508#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15870#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15704#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 15445#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 15327#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 15328#L561-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15983#L759 assume !(0 == ~M_E~0); 15987#L759-2 assume !(0 == ~T1_E~0); 15768#L764-1 assume !(0 == ~T2_E~0); 15580#L769-1 assume !(0 == ~T3_E~0); 15282#L774-1 assume !(0 == ~T4_E~0); 15283#L779-1 assume !(0 == ~T5_E~0); 15925#L784-1 assume !(0 == ~T6_E~0); 15752#L789-1 assume !(0 == ~T7_E~0); 15383#L794-1 assume !(0 == ~E_M~0); 15384#L799-1 assume !(0 == ~E_1~0); 15967#L804-1 assume !(0 == ~E_2~0); 15854#L809-1 assume !(0 == ~E_3~0); 15660#L814-1 assume !(0 == ~E_4~0); 15200#L819-1 assume !(0 == ~E_5~0); 15201#L824-1 assume !(0 == ~E_6~0); 15827#L829-1 assume !(0 == ~E_7~0); 15726#L834-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15727#L366 assume !(1 == ~m_pc~0); 15819#L366-2 is_master_triggered_~__retres1~0 := 0; 15477#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15263#L378 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 15264#L945 assume !(0 != activate_threads_~tmp~1); 15581#L945-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15582#L385 assume 1 == ~t1_pc~0; 15888#L386 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 15649#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 15424#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 15425#L953 assume !(0 != activate_threads_~tmp___0~0); 16026#L953-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 16027#L404 assume !(1 == ~t2_pc~0); 16031#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 15751#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 15718#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 15719#L961 assume !(0 != activate_threads_~tmp___1~0); 15900#L961-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 15366#L423 assume 1 == ~t3_pc~0; 15305#L424 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 15306#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 15838#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 15616#L969 assume !(0 != activate_threads_~tmp___2~0); 15617#L969-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 15381#L442 assume !(1 == ~t4_pc~0); 15372#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 15373#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 15872#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 15919#L977 assume !(0 != activate_threads_~tmp___3~0); 16035#L977-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 15562#L461 assume 1 == ~t5_pc~0; 15563#L462 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 15566#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 15935#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 15857#L985 assume !(0 != activate_threads_~tmp___4~0); 15858#L985-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 15705#L480 assume !(1 == ~t6_pc~0); 15692#L480-2 is_transmit6_triggered_~__retres1~6 := 0; 15693#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 16019#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 15525#L993 assume !(0 != activate_threads_~tmp___5~0); 15526#L993-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 15528#L499 assume !(1 == ~t7_pc~0); 15812#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 15256#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 15196#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 15197#L1001 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 15989#L1001-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15990#L847 assume !(1 == ~M_E~0); 15986#L847-2 assume !(1 == ~T1_E~0); 15766#L852-1 assume !(1 == ~T2_E~0); 15577#L857-1 assume !(1 == ~T3_E~0); 15278#L862-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15279#L867-1 assume !(1 == ~T5_E~0); 15923#L872-1 assume !(1 == ~T6_E~0); 15672#L877-1 assume !(1 == ~T7_E~0); 15391#L882-1 assume !(1 == ~E_M~0); 15392#L887-1 assume !(1 == ~E_1~0); 15971#L892-1 assume !(1 == ~E_2~0); 15861#L897-1 assume !(1 == ~E_3~0); 15668#L902-1 assume 1 == ~E_4~0;~E_4~0 := 2; 15215#L907-1 assume !(1 == ~E_5~0); 15216#L912-1 assume !(1 == ~E_6~0); 15824#L917-1 assume !(1 == ~E_7~0); 15724#L922-1 assume { :end_inline_reset_delta_events } true; 15401#L1168-3 [2018-11-18 15:27:55,911 INFO L796 eck$LassoCheckResult]: Loop: 15401#L1168-3 assume true; 15402#L1168-1 assume !false; 15420#L1169 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 15482#L734 assume true; 15939#L626-1 assume !false; 15940#L627 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 15378#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 15274#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 15435#L617 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 15436#L631 assume !(0 != eval_~tmp~0); 15611#L749 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 15612#L519-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 15871#L759-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15980#L759-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15758#L764-3 assume !(0 == ~T2_E~0); 15573#L769-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15267#L774-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15268#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15921#L784-3 assume !(0 == ~T6_E~0); 15756#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15387#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 15388#L799-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15968#L804-3 assume !(0 == ~E_2~0); 15855#L809-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15661#L814-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15202#L819-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15203#L824-3 assume !(0 == ~E_6~0); 15828#L829-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15728#L834-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15729#L366-27 assume !(1 == ~m_pc~0); 15792#L366-29 is_master_triggered_~__retres1~0 := 0; 15473#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15227#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 15228#L945-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 15542#L945-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15663#L385-27 assume 1 == ~t1_pc~0; 15873#L386-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 15624#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 15395#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 15396#L953-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 15994#L953-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15995#L404-27 assume 1 == ~t2_pc~0; 15948#L405-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 15741#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 15591#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 15592#L961-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 15771#L961-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 15324#L423-27 assume 1 == ~t3_pc~0; 15299#L424-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 15300#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 15837#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 15397#L969-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 15398#L969-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 15403#L442-27 assume 1 == ~t4_pc~0; 15464#L443-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 15465#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 15905#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 15906#L977-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 15941#L977-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 15654#L461-27 assume !(1 == ~t5_pc~0); 15648#L461-29 is_transmit5_triggered_~__retres1~5 := 0; 15647#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 15934#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 15711#L985-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 15712#L985-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 15713#L480-27 assume !(1 == ~t6_pc~0); 15737#L480-29 is_transmit6_triggered_~__retres1~6 := 0; 15749#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 16000#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 15472#L993-27 assume !(0 != activate_threads_~tmp___5~0); 15448#L993-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 15449#L499-27 assume 1 == ~t7_pc~0; 15760#L500-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 15251#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 15252#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 15360#L1001-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 15972#L1001-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15973#L847-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15988#L847-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15767#L852-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15579#L857-3 assume !(1 == ~T3_E~0); 15280#L862-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15281#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15924#L872-3 assume !(1 == ~T6_E~0); 15677#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15393#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 15394#L887-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15966#L892-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15851#L897-3 assume !(1 == ~E_3~0); 15658#L902-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15198#L907-3 assume 1 == ~E_5~0;~E_5~0 := 2; 15199#L912-3 assume !(1 == ~E_6~0); 15826#L917-3 assume 1 == ~E_7~0;~E_7~0 := 2; 15725#L922-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 15379#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 15276#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 15439#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 15440#L1187 assume !(0 == start_simulation_~tmp~3); 15585#L1187-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 15380#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 15254#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 15443#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 15444#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 15223#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 15224#L1150 start_simulation_#t~ret20 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 15349#L1200 assume !(0 != start_simulation_~tmp___0~1); 15401#L1168-3 [2018-11-18 15:27:55,911 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:27:55,911 INFO L82 PathProgramCache]: Analyzing trace with hash 1481008316, now seen corresponding path program 1 times [2018-11-18 15:27:55,911 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:27:55,911 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:27:55,912 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:55,912 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:27:55,912 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:55,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:27:55,945 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:27:55,945 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:27:55,946 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 15:27:55,946 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 15:27:55,946 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:27:55,946 INFO L82 PathProgramCache]: Analyzing trace with hash -1916640351, now seen corresponding path program 1 times [2018-11-18 15:27:55,946 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:27:55,946 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:27:55,947 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:55,947 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:27:55,947 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:55,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:27:55,982 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:27:55,982 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:27:55,982 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:27:55,983 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:27:55,983 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:27:55,983 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:27:55,983 INFO L87 Difference]: Start difference. First operand 840 states and 1224 transitions. cyclomatic complexity: 385 Second operand 3 states. [2018-11-18 15:27:56,081 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:27:56,081 INFO L93 Difference]: Finished difference Result 1508 states and 2180 transitions. [2018-11-18 15:27:56,082 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:27:56,082 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1508 states and 2180 transitions. [2018-11-18 15:27:56,088 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1404 [2018-11-18 15:27:56,093 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1508 states to 1508 states and 2180 transitions. [2018-11-18 15:27:56,093 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1508 [2018-11-18 15:27:56,094 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1508 [2018-11-18 15:27:56,094 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1508 states and 2180 transitions. [2018-11-18 15:27:56,096 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:27:56,096 INFO L705 BuchiCegarLoop]: Abstraction has 1508 states and 2180 transitions. [2018-11-18 15:27:56,097 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1508 states and 2180 transitions. [2018-11-18 15:27:56,111 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1508 to 1505. [2018-11-18 15:27:56,111 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1505 states. [2018-11-18 15:27:56,114 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1505 states to 1505 states and 2177 transitions. [2018-11-18 15:27:56,114 INFO L728 BuchiCegarLoop]: Abstraction has 1505 states and 2177 transitions. [2018-11-18 15:27:56,114 INFO L608 BuchiCegarLoop]: Abstraction has 1505 states and 2177 transitions. [2018-11-18 15:27:56,114 INFO L442 BuchiCegarLoop]: ======== Iteration 11============ [2018-11-18 15:27:56,114 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1505 states and 2177 transitions. [2018-11-18 15:27:56,118 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1401 [2018-11-18 15:27:56,118 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:27:56,118 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:27:56,119 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:27:56,119 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:27:56,120 INFO L794 eck$LassoCheckResult]: Stem: 17988#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 17902#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 17903#L1131 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 18228#L519 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18073#L526 assume 1 == ~m_i~0;~m_st~0 := 0; 18074#L526-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17865#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17866#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18229#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18061#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 17800#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 17682#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 17683#L561-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18362#L759 assume !(0 == ~M_E~0); 18366#L759-2 assume !(0 == ~T1_E~0); 18126#L764-1 assume !(0 == ~T2_E~0); 17936#L769-1 assume !(0 == ~T3_E~0); 17637#L774-1 assume !(0 == ~T4_E~0); 17638#L779-1 assume !(0 == ~T5_E~0); 18293#L784-1 assume !(0 == ~T6_E~0); 18109#L789-1 assume !(0 == ~T7_E~0); 17738#L794-1 assume !(0 == ~E_M~0); 17739#L799-1 assume !(0 == ~E_1~0); 18337#L804-1 assume !(0 == ~E_2~0); 18212#L809-1 assume !(0 == ~E_3~0); 18016#L814-1 assume !(0 == ~E_4~0); 17555#L819-1 assume !(0 == ~E_5~0); 17556#L824-1 assume !(0 == ~E_6~0); 18185#L829-1 assume !(0 == ~E_7~0); 18083#L834-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 18084#L366 assume !(1 == ~m_pc~0); 18176#L366-2 is_master_triggered_~__retres1~0 := 0; 17836#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 17620#L378 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 17621#L945 assume !(0 != activate_threads_~tmp~1); 17937#L945-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 17938#L385 assume !(1 == ~t1_pc~0); 18357#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 18005#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 17779#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 17780#L953 assume !(0 != activate_threads_~tmp___0~0); 18405#L953-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 18406#L404 assume !(1 == ~t2_pc~0); 18411#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 18108#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 18075#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 18076#L961 assume !(0 != activate_threads_~tmp___1~0); 18268#L961-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 17721#L423 assume 1 == ~t3_pc~0; 17660#L424 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 17661#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 18196#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 17972#L969 assume !(0 != activate_threads_~tmp___2~0); 17973#L969-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 17736#L442 assume !(1 == ~t4_pc~0); 17727#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 17728#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 18231#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 18287#L977 assume !(0 != activate_threads_~tmp___3~0); 18415#L977-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 17918#L461 assume 1 == ~t5_pc~0; 17919#L462 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 17922#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 18305#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 18215#L985 assume !(0 != activate_threads_~tmp___4~0); 18216#L985-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 18062#L480 assume !(1 == ~t6_pc~0); 18049#L480-2 is_transmit6_triggered_~__retres1~6 := 0; 18050#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 18399#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 17881#L993 assume !(0 != activate_threads_~tmp___5~0); 17882#L993-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 17884#L499 assume !(1 == ~t7_pc~0); 18170#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 17611#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 17551#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 17552#L1001 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 18368#L1001-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18369#L847 assume !(1 == ~M_E~0); 18365#L847-2 assume !(1 == ~T1_E~0); 18123#L852-1 assume !(1 == ~T2_E~0); 17933#L857-1 assume !(1 == ~T3_E~0); 17633#L862-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17634#L867-1 assume !(1 == ~T5_E~0); 18291#L872-1 assume !(1 == ~T6_E~0); 18030#L877-1 assume !(1 == ~T7_E~0); 17746#L882-1 assume !(1 == ~E_M~0); 17747#L887-1 assume !(1 == ~E_1~0); 18344#L892-1 assume !(1 == ~E_2~0); 18219#L897-1 assume !(1 == ~E_3~0); 18025#L902-1 assume 1 == ~E_4~0;~E_4~0 := 2; 17570#L907-1 assume !(1 == ~E_5~0); 17571#L912-1 assume !(1 == ~E_6~0); 18182#L917-1 assume !(1 == ~E_7~0); 18081#L922-1 assume { :end_inline_reset_delta_events } true; 17756#L1168-3 [2018-11-18 15:27:56,120 INFO L796 eck$LassoCheckResult]: Loop: 17756#L1168-3 assume true; 17757#L1168-1 assume !false; 17775#L1169 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 17838#L734 assume true; 18309#L626-1 assume !false; 18310#L627 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 17733#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 17629#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 17790#L617 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 17791#L631 assume !(0 != eval_~tmp~0); 18181#L749 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 19054#L519-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 19053#L759-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19052#L759-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19051#L764-3 assume !(0 == ~T2_E~0); 19050#L769-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19049#L774-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 19048#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 19047#L784-3 assume !(0 == ~T6_E~0); 19046#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19045#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 19044#L799-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19043#L804-3 assume !(0 == ~E_2~0); 19042#L809-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19041#L814-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19040#L819-3 assume 0 == ~E_5~0;~E_5~0 := 1; 19039#L824-3 assume !(0 == ~E_6~0); 19038#L829-3 assume 0 == ~E_7~0;~E_7~0 := 1; 19037#L834-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 19036#L366-27 assume 1 == ~m_pc~0; 19034#L367-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 19033#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 17582#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 17583#L945-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 17898#L945-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 18265#L385-27 assume !(1 == ~t1_pc~0); 18252#L385-29 is_transmit1_triggered_~__retres1~1 := 0; 17980#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 17750#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 17751#L953-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 18373#L953-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 18374#L404-27 assume 1 == ~t2_pc~0; 18318#L405-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 18098#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 17947#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 17948#L961-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 18128#L961-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 17679#L423-27 assume 1 == ~t3_pc~0; 17654#L424-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 17655#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 18195#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 17752#L969-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 17753#L969-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 17758#L442-27 assume 1 == ~t4_pc~0; 17819#L443-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 17820#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 18273#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 18274#L977-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 18311#L977-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 18010#L461-27 assume 1 == ~t5_pc~0; 18002#L462-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 18003#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 18304#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 18068#L985-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 18069#L985-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 18070#L480-27 assume !(1 == ~t6_pc~0); 18094#L480-29 is_transmit6_triggered_~__retres1~6 := 0; 18106#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 18379#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 17827#L993-27 assume !(0 != activate_threads_~tmp___5~0); 17803#L993-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 17804#L499-27 assume 1 == ~t7_pc~0; 18117#L500-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 17606#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 17607#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 17715#L1001-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 18345#L1001-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18347#L847-3 assume 1 == ~M_E~0;~M_E~0 := 2; 18367#L847-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18124#L852-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17935#L857-3 assume !(1 == ~T3_E~0); 17635#L862-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17636#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 18292#L872-3 assume !(1 == ~T6_E~0); 18034#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17748#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 17749#L887-3 assume 1 == ~E_1~0;~E_1~0 := 2; 18336#L892-3 assume 1 == ~E_2~0;~E_2~0 := 2; 18209#L897-3 assume !(1 == ~E_3~0); 18014#L902-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17553#L907-3 assume 1 == ~E_5~0;~E_5~0 := 2; 17554#L912-3 assume !(1 == ~E_6~0); 18184#L917-3 assume 1 == ~E_7~0;~E_7~0 := 2; 18082#L922-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 17734#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 17631#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 17794#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 17795#L1187 assume !(0 == start_simulation_~tmp~3); 17941#L1187-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 17735#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 17609#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 17798#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 17799#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 17578#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 17579#L1150 start_simulation_#t~ret20 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 17704#L1200 assume !(0 != start_simulation_~tmp___0~1); 17756#L1168-3 [2018-11-18 15:27:56,120 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:27:56,120 INFO L82 PathProgramCache]: Analyzing trace with hash 449677501, now seen corresponding path program 1 times [2018-11-18 15:27:56,120 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:27:56,120 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:27:56,121 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:56,121 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:27:56,121 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:56,125 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:27:56,147 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:27:56,147 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:27:56,147 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 15:27:56,147 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 15:27:56,148 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:27:56,148 INFO L82 PathProgramCache]: Analyzing trace with hash -136205600, now seen corresponding path program 1 times [2018-11-18 15:27:56,148 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:27:56,148 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:27:56,148 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:56,148 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:27:56,149 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:56,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:27:56,182 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:27:56,182 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:27:56,182 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:27:56,183 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:27:56,183 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:27:56,183 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:27:56,183 INFO L87 Difference]: Start difference. First operand 1505 states and 2177 transitions. cyclomatic complexity: 674 Second operand 3 states. [2018-11-18 15:27:56,264 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:27:56,264 INFO L93 Difference]: Finished difference Result 2773 states and 3985 transitions. [2018-11-18 15:27:56,265 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:27:56,266 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2773 states and 3985 transitions. [2018-11-18 15:27:56,275 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2664 [2018-11-18 15:27:56,285 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2773 states to 2773 states and 3985 transitions. [2018-11-18 15:27:56,285 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2773 [2018-11-18 15:27:56,287 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2773 [2018-11-18 15:27:56,288 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2773 states and 3985 transitions. [2018-11-18 15:27:56,291 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:27:56,291 INFO L705 BuchiCegarLoop]: Abstraction has 2773 states and 3985 transitions. [2018-11-18 15:27:56,293 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2773 states and 3985 transitions. [2018-11-18 15:27:56,321 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2773 to 2767. [2018-11-18 15:27:56,322 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2767 states. [2018-11-18 15:27:56,327 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2767 states to 2767 states and 3979 transitions. [2018-11-18 15:27:56,327 INFO L728 BuchiCegarLoop]: Abstraction has 2767 states and 3979 transitions. [2018-11-18 15:27:56,327 INFO L608 BuchiCegarLoop]: Abstraction has 2767 states and 3979 transitions. [2018-11-18 15:27:56,327 INFO L442 BuchiCegarLoop]: ======== Iteration 12============ [2018-11-18 15:27:56,328 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2767 states and 3979 transitions. [2018-11-18 15:27:56,334 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2658 [2018-11-18 15:27:56,334 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:27:56,334 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:27:56,335 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:27:56,336 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:27:56,336 INFO L794 eck$LassoCheckResult]: Stem: 22291#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 22198#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 22199#L1131 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 22537#L519 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22378#L526 assume 1 == ~m_i~0;~m_st~0 := 0; 22379#L526-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22161#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22162#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 22538#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22365#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22096#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 21964#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 21965#L561-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22677#L759 assume !(0 == ~M_E~0); 22681#L759-2 assume !(0 == ~T1_E~0); 22434#L764-1 assume !(0 == ~T2_E~0); 22237#L769-1 assume !(0 == ~T3_E~0); 21922#L774-1 assume !(0 == ~T4_E~0); 21923#L779-1 assume !(0 == ~T5_E~0); 22605#L784-1 assume !(0 == ~T6_E~0); 22416#L789-1 assume !(0 == ~T7_E~0); 22034#L794-1 assume !(0 == ~E_M~0); 22035#L799-1 assume !(0 == ~E_1~0); 22649#L804-1 assume !(0 == ~E_2~0); 22521#L809-1 assume !(0 == ~E_3~0); 22320#L814-1 assume !(0 == ~E_4~0); 21840#L819-1 assume !(0 == ~E_5~0); 21841#L824-1 assume !(0 == ~E_6~0); 22493#L829-1 assume !(0 == ~E_7~0); 22388#L834-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 22389#L366 assume !(1 == ~m_pc~0); 22484#L366-2 is_master_triggered_~__retres1~0 := 0; 22131#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 21905#L378 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 21906#L945 assume !(0 != activate_threads_~tmp~1); 22238#L945-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 22239#L385 assume !(1 == ~t1_pc~0); 22672#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 22308#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 22075#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 22076#L953 assume !(0 != activate_threads_~tmp___0~0); 22722#L953-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 22723#L404 assume !(1 == ~t2_pc~0); 22730#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 22415#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 22380#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 22381#L961 assume !(0 != activate_threads_~tmp___1~0); 22578#L961-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 22015#L423 assume !(1 == ~t3_pc~0); 22016#L423-2 is_transmit3_triggered_~__retres1~3 := 0; 22021#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 22505#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 22273#L969 assume !(0 != activate_threads_~tmp___2~0); 22274#L969-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 22032#L442 assume !(1 == ~t4_pc~0); 22023#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 22024#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 22540#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 22599#L977 assume !(0 != activate_threads_~tmp___3~0); 22737#L977-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 22215#L461 assume 1 == ~t5_pc~0; 22216#L462 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 22219#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 22617#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 22524#L985 assume !(0 != activate_threads_~tmp___4~0); 22525#L985-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 22366#L480 assume !(1 == ~t6_pc~0); 22352#L480-2 is_transmit6_triggered_~__retres1~6 := 0; 22353#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 22715#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 22177#L993 assume !(0 != activate_threads_~tmp___5~0); 22178#L993-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 22180#L499 assume !(1 == ~t7_pc~0); 22478#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 21896#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 21836#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 21837#L1001 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 22684#L1001-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22685#L847 assume !(1 == ~M_E~0); 22680#L847-2 assume !(1 == ~T1_E~0); 22431#L852-1 assume !(1 == ~T2_E~0); 22232#L857-1 assume !(1 == ~T3_E~0); 21918#L862-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21919#L867-1 assume !(1 == ~T5_E~0); 22603#L872-1 assume !(1 == ~T6_E~0); 22333#L877-1 assume !(1 == ~T7_E~0); 22042#L882-1 assume !(1 == ~E_M~0); 22043#L887-1 assume !(1 == ~E_1~0); 22656#L892-1 assume !(1 == ~E_2~0); 22528#L897-1 assume !(1 == ~E_3~0); 22328#L902-1 assume 1 == ~E_4~0;~E_4~0 := 2; 21855#L907-1 assume !(1 == ~E_5~0); 21856#L912-1 assume !(1 == ~E_6~0); 22490#L917-1 assume !(1 == ~E_7~0); 22386#L922-1 assume { :end_inline_reset_delta_events } true; 22052#L1168-3 [2018-11-18 15:27:56,336 INFO L796 eck$LassoCheckResult]: Loop: 22052#L1168-3 assume true; 22053#L1168-1 assume !false; 22071#L1169 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 22133#L734 assume true; 22621#L626-1 assume !false; 22622#L627 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 22029#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 21914#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 22086#L617 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 22087#L631 assume !(0 != eval_~tmp~0); 22489#L749 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 24602#L519-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 24601#L759-3 assume 0 == ~M_E~0;~M_E~0 := 1; 24600#L759-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 24599#L764-3 assume !(0 == ~T2_E~0); 24598#L769-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 24597#L774-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 24596#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 24595#L784-3 assume !(0 == ~T6_E~0); 24594#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 24593#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 24592#L799-3 assume 0 == ~E_1~0;~E_1~0 := 1; 24591#L804-3 assume !(0 == ~E_2~0); 24590#L809-3 assume 0 == ~E_3~0;~E_3~0 := 1; 24589#L814-3 assume 0 == ~E_4~0;~E_4~0 := 1; 24562#L819-3 assume 0 == ~E_5~0;~E_5~0 := 1; 24561#L824-3 assume !(0 == ~E_6~0); 24560#L829-3 assume 0 == ~E_7~0;~E_7~0 := 1; 24559#L834-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 24558#L366-27 assume 1 == ~m_pc~0; 24556#L367-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 24555#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 24290#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 24289#L945-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 24240#L945-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 22575#L385-27 assume !(1 == ~t1_pc~0); 22561#L385-29 is_transmit1_triggered_~__retres1~1 := 0; 22281#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 22046#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 22047#L953-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 22689#L953-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 22690#L404-27 assume 1 == ~t2_pc~0; 22630#L405-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 22404#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 22248#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 22249#L961-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 22438#L961-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 21960#L423-27 assume !(1 == ~t3_pc~0); 21961#L423-29 is_transmit3_triggered_~__retres1~3 := 0; 21968#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 22503#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 22048#L969-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 22049#L969-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 22054#L442-27 assume 1 == ~t4_pc~0; 22114#L443-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 22115#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 22584#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 22585#L977-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 22623#L977-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 22313#L461-27 assume 1 == ~t5_pc~0; 22304#L462-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 22305#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 22616#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 22373#L985-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 22374#L985-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 22375#L480-27 assume !(1 == ~t6_pc~0); 22398#L480-29 is_transmit6_triggered_~__retres1~6 := 0; 22413#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 22694#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 22123#L993-27 assume !(0 != activate_threads_~tmp___5~0); 22099#L993-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 22100#L499-27 assume 1 == ~t7_pc~0; 24174#L500-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 24173#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 24172#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 24171#L1001-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 24161#L1001-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24158#L847-3 assume 1 == ~M_E~0;~M_E~0 := 2; 24155#L847-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 24153#L852-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 24152#L857-3 assume !(1 == ~T3_E~0); 21920#L862-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21921#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22604#L872-3 assume !(1 == ~T6_E~0); 22337#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22044#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 22045#L887-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22648#L892-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22518#L897-3 assume !(1 == ~E_3~0); 22318#L902-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21838#L907-3 assume 1 == ~E_5~0;~E_5~0 := 2; 21839#L912-3 assume !(1 == ~E_6~0); 22492#L917-3 assume 1 == ~E_7~0;~E_7~0 := 2; 22387#L922-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 22030#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 21916#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 22090#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 22091#L1187 assume !(0 == start_simulation_~tmp~3); 22242#L1187-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 22031#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 21894#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 22094#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 22095#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 21863#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 21864#L1150 start_simulation_#t~ret20 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 21994#L1200 assume !(0 != start_simulation_~tmp___0~1); 22052#L1168-3 [2018-11-18 15:27:56,336 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:27:56,336 INFO L82 PathProgramCache]: Analyzing trace with hash -1443764674, now seen corresponding path program 1 times [2018-11-18 15:27:56,336 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:27:56,336 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:27:56,337 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:56,337 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:27:56,337 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:56,341 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:27:56,372 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:27:56,372 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:27:56,373 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 15:27:56,373 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 15:27:56,373 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:27:56,373 INFO L82 PathProgramCache]: Analyzing trace with hash -1167536415, now seen corresponding path program 1 times [2018-11-18 15:27:56,373 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:27:56,373 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:27:56,374 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:56,374 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:27:56,374 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:56,380 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:27:56,403 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:27:56,403 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:27:56,403 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:27:56,403 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:27:56,404 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:27:56,404 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:27:56,404 INFO L87 Difference]: Start difference. First operand 2767 states and 3979 transitions. cyclomatic complexity: 1216 Second operand 3 states. [2018-11-18 15:27:56,503 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:27:56,503 INFO L93 Difference]: Finished difference Result 5168 states and 7386 transitions. [2018-11-18 15:27:56,505 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:27:56,505 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5168 states and 7386 transitions. [2018-11-18 15:27:56,520 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5044 [2018-11-18 15:27:56,538 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5168 states to 5168 states and 7386 transitions. [2018-11-18 15:27:56,538 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5168 [2018-11-18 15:27:56,541 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5168 [2018-11-18 15:27:56,541 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5168 states and 7386 transitions. [2018-11-18 15:27:56,548 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:27:56,548 INFO L705 BuchiCegarLoop]: Abstraction has 5168 states and 7386 transitions. [2018-11-18 15:27:56,551 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5168 states and 7386 transitions. [2018-11-18 15:27:56,601 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5168 to 5156. [2018-11-18 15:27:56,601 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5156 states. [2018-11-18 15:27:56,609 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5156 states to 5156 states and 7374 transitions. [2018-11-18 15:27:56,609 INFO L728 BuchiCegarLoop]: Abstraction has 5156 states and 7374 transitions. [2018-11-18 15:27:56,610 INFO L608 BuchiCegarLoop]: Abstraction has 5156 states and 7374 transitions. [2018-11-18 15:27:56,610 INFO L442 BuchiCegarLoop]: ======== Iteration 13============ [2018-11-18 15:27:56,610 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5156 states and 7374 transitions. [2018-11-18 15:27:56,622 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5032 [2018-11-18 15:27:56,622 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:27:56,622 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:27:56,623 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:27:56,623 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:27:56,623 INFO L794 eck$LassoCheckResult]: Stem: 30226#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 30138#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 30139#L1131 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 30498#L519 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30321#L526 assume 1 == ~m_i~0;~m_st~0 := 0; 30322#L526-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 30100#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 30101#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30499#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 30308#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 30037#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29906#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 29907#L561-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30646#L759 assume !(0 == ~M_E~0); 30651#L759-2 assume !(0 == ~T1_E~0); 30379#L764-1 assume !(0 == ~T2_E~0); 30172#L769-1 assume !(0 == ~T3_E~0); 29864#L774-1 assume !(0 == ~T4_E~0); 29865#L779-1 assume !(0 == ~T5_E~0); 30565#L784-1 assume !(0 == ~T6_E~0); 30361#L789-1 assume !(0 == ~T7_E~0); 29974#L794-1 assume !(0 == ~E_M~0); 29975#L799-1 assume !(0 == ~E_1~0); 30613#L804-1 assume !(0 == ~E_2~0); 30477#L809-1 assume !(0 == ~E_3~0); 30262#L814-1 assume !(0 == ~E_4~0); 29782#L819-1 assume !(0 == ~E_5~0); 29783#L824-1 assume !(0 == ~E_6~0); 30449#L829-1 assume !(0 == ~E_7~0); 30333#L834-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 30334#L366 assume !(1 == ~m_pc~0); 30437#L366-2 is_master_triggered_~__retres1~0 := 0; 30069#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 29845#L378 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 29846#L945 assume !(0 != activate_threads_~tmp~1); 30173#L945-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 30174#L385 assume !(1 == ~t1_pc~0); 30636#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 30243#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 30016#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 30017#L953 assume !(0 != activate_threads_~tmp___0~0); 30694#L953-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 30695#L404 assume !(1 == ~t2_pc~0); 30701#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 30360#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 30323#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 30324#L961 assume !(0 != activate_threads_~tmp___1~0); 30540#L961-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 29954#L423 assume !(1 == ~t3_pc~0); 29955#L423-2 is_transmit3_triggered_~__retres1~3 := 0; 29961#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 30461#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 30209#L969 assume !(0 != activate_threads_~tmp___2~0); 30210#L969-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 29972#L442 assume !(1 == ~t4_pc~0); 29963#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 29964#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 30501#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 30559#L977 assume !(0 != activate_threads_~tmp___3~0); 30710#L977-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 30154#L461 assume !(1 == ~t5_pc~0); 30155#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 30158#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 30577#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 30480#L985 assume !(0 != activate_threads_~tmp___4~0); 30481#L985-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 30309#L480 assume !(1 == ~t6_pc~0); 30296#L480-2 is_transmit6_triggered_~__retres1~6 := 0; 30297#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 30685#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 30118#L993 assume !(0 != activate_threads_~tmp___5~0); 30119#L993-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 30121#L499 assume !(1 == ~t7_pc~0); 30427#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 29838#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 29778#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 29779#L1001 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 30654#L1001-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30655#L847 assume !(1 == ~M_E~0); 30650#L847-2 assume !(1 == ~T1_E~0); 30375#L852-1 assume !(1 == ~T2_E~0); 30169#L857-1 assume !(1 == ~T3_E~0); 29860#L862-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29861#L867-1 assume !(1 == ~T5_E~0); 30563#L872-1 assume !(1 == ~T6_E~0); 30276#L877-1 assume !(1 == ~T7_E~0); 29983#L882-1 assume !(1 == ~E_M~0); 29984#L887-1 assume !(1 == ~E_1~0); 30620#L892-1 assume !(1 == ~E_2~0); 30484#L897-1 assume !(1 == ~E_3~0); 30272#L902-1 assume 1 == ~E_4~0;~E_4~0 := 2; 29797#L907-1 assume !(1 == ~E_5~0); 29798#L912-1 assume !(1 == ~E_6~0); 30446#L917-1 assume !(1 == ~E_7~0); 30330#L922-1 assume { :end_inline_reset_delta_events } true; 30331#L1168-3 [2018-11-18 15:27:56,623 INFO L796 eck$LassoCheckResult]: Loop: 30331#L1168-3 assume true; 32134#L1168-1 assume !false; 32070#L1169 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 32068#L734 assume true; 32066#L626-1 assume !false; 32063#L627 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 29969#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 29856#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 30027#L617 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 30028#L631 assume !(0 != eval_~tmp~0); 30444#L749 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 32508#L519-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 32506#L759-3 assume 0 == ~M_E~0;~M_E~0 := 1; 32504#L759-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 32502#L764-3 assume !(0 == ~T2_E~0); 32500#L769-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 32498#L774-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 32496#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 32494#L784-3 assume !(0 == ~T6_E~0); 32492#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 32490#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 32488#L799-3 assume 0 == ~E_1~0;~E_1~0 := 1; 32486#L804-3 assume !(0 == ~E_2~0); 32484#L809-3 assume 0 == ~E_3~0;~E_3~0 := 1; 32482#L814-3 assume 0 == ~E_4~0;~E_4~0 := 1; 32480#L819-3 assume 0 == ~E_5~0;~E_5~0 := 1; 32478#L824-3 assume !(0 == ~E_6~0); 32476#L829-3 assume 0 == ~E_7~0;~E_7~0 := 1; 32474#L834-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 32472#L366-27 assume 1 == ~m_pc~0; 32469#L367-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 32466#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 32464#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 32462#L945-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 32460#L945-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 32457#L385-27 assume !(1 == ~t1_pc~0); 32458#L385-29 is_transmit1_triggered_~__retres1~1 := 0; 32906#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 32905#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 32904#L953-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 32903#L953-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 32902#L404-27 assume 1 == ~t2_pc~0; 32440#L405-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 32438#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 32436#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 32435#L961-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 32434#L961-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 32430#L423-27 assume !(1 == ~t3_pc~0); 32427#L423-29 is_transmit3_triggered_~__retres1~3 := 0; 32425#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 32423#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 32421#L969-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 32419#L969-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 32417#L442-27 assume 1 == ~t4_pc~0; 32414#L443-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 32411#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 32410#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 32409#L977-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 32408#L977-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 32407#L461-27 assume !(1 == ~t5_pc~0); 32406#L461-29 is_transmit5_triggered_~__retres1~5 := 0; 32405#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 32404#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 32403#L985-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 32402#L985-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 32401#L480-27 assume !(1 == ~t6_pc~0); 32399#L480-29 is_transmit6_triggered_~__retres1~6 := 0; 32398#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 32397#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 32396#L993-27 assume !(0 != activate_threads_~tmp___5~0); 32395#L993-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 32394#L499-27 assume 1 == ~t7_pc~0; 32392#L500-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 32391#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 32390#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 32389#L1001-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 32388#L1001-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32386#L847-3 assume 1 == ~M_E~0;~M_E~0 := 2; 32383#L847-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 32381#L852-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 32379#L857-3 assume !(1 == ~T3_E~0); 32377#L862-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 32375#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 32373#L872-3 assume !(1 == ~T6_E~0); 32372#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 32371#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 32370#L887-3 assume 1 == ~E_1~0;~E_1~0 := 2; 32368#L892-3 assume 1 == ~E_2~0;~E_2~0 := 2; 32365#L897-3 assume !(1 == ~E_3~0); 32363#L902-3 assume 1 == ~E_4~0;~E_4~0 := 2; 32361#L907-3 assume 1 == ~E_5~0;~E_5~0 := 2; 32359#L912-3 assume !(1 == ~E_6~0); 32357#L917-3 assume 1 == ~E_7~0;~E_7~0 := 2; 32354#L922-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 32183#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 32173#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 32170#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 32165#L1187 assume !(0 == start_simulation_~tmp~3); 32160#L1187-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 32158#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 32149#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 32147#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 32144#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 32140#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 32138#L1150 start_simulation_#t~ret20 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 32136#L1200 assume !(0 != start_simulation_~tmp___0~1); 30331#L1168-3 [2018-11-18 15:27:56,624 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:27:56,624 INFO L82 PathProgramCache]: Analyzing trace with hash -392315585, now seen corresponding path program 1 times [2018-11-18 15:27:56,624 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:27:56,624 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:27:56,624 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:56,625 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:27:56,625 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:56,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:27:56,666 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:27:56,666 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:27:56,666 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 15:27:56,667 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 15:27:56,667 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:27:56,667 INFO L82 PathProgramCache]: Analyzing trace with hash 1233988706, now seen corresponding path program 1 times [2018-11-18 15:27:56,667 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:27:56,667 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:27:56,668 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:56,668 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:27:56,668 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:56,673 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:27:56,702 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:27:56,702 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:27:56,702 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:27:56,703 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:27:56,703 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:27:56,703 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:27:56,703 INFO L87 Difference]: Start difference. First operand 5156 states and 7374 transitions. cyclomatic complexity: 2226 Second operand 3 states. [2018-11-18 15:27:56,735 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:27:56,735 INFO L93 Difference]: Finished difference Result 5156 states and 7348 transitions. [2018-11-18 15:27:56,737 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:27:56,737 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5156 states and 7348 transitions. [2018-11-18 15:27:56,752 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5032 [2018-11-18 15:27:56,771 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5156 states to 5156 states and 7348 transitions. [2018-11-18 15:27:56,771 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5156 [2018-11-18 15:27:56,775 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5156 [2018-11-18 15:27:56,775 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5156 states and 7348 transitions. [2018-11-18 15:27:56,779 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:27:56,779 INFO L705 BuchiCegarLoop]: Abstraction has 5156 states and 7348 transitions. [2018-11-18 15:27:56,783 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5156 states and 7348 transitions. [2018-11-18 15:27:56,831 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5156 to 5156. [2018-11-18 15:27:56,832 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5156 states. [2018-11-18 15:27:56,841 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5156 states to 5156 states and 7348 transitions. [2018-11-18 15:27:56,841 INFO L728 BuchiCegarLoop]: Abstraction has 5156 states and 7348 transitions. [2018-11-18 15:27:56,841 INFO L608 BuchiCegarLoop]: Abstraction has 5156 states and 7348 transitions. [2018-11-18 15:27:56,841 INFO L442 BuchiCegarLoop]: ======== Iteration 14============ [2018-11-18 15:27:56,841 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5156 states and 7348 transitions. [2018-11-18 15:27:56,854 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5032 [2018-11-18 15:27:56,854 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:27:56,854 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:27:56,855 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:27:56,855 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:27:56,855 INFO L794 eck$LassoCheckResult]: Stem: 40545#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 40461#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 40462#L1131 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 40805#L519 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 40649#L526 assume 1 == ~m_i~0;~m_st~0 := 0; 40650#L526-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 40422#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 40423#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 40806#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 40637#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 40359#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 40227#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 40228#L561-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 40946#L759 assume !(0 == ~M_E~0); 40950#L759-2 assume !(0 == ~T1_E~0); 40702#L764-1 assume !(0 == ~T2_E~0); 40493#L769-1 assume !(0 == ~T3_E~0); 40183#L774-1 assume !(0 == ~T4_E~0); 40184#L779-1 assume !(0 == ~T5_E~0); 40872#L784-1 assume !(0 == ~T6_E~0); 40686#L789-1 assume !(0 == ~T7_E~0); 40297#L794-1 assume !(0 == ~E_M~0); 40298#L799-1 assume !(0 == ~E_1~0); 40917#L804-1 assume !(0 == ~E_2~0); 40790#L809-1 assume !(0 == ~E_3~0); 40590#L814-1 assume !(0 == ~E_4~0); 40101#L819-1 assume !(0 == ~E_5~0); 40102#L824-1 assume !(0 == ~E_6~0); 40763#L829-1 assume !(0 == ~E_7~0); 40659#L834-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 40660#L366 assume !(1 == ~m_pc~0); 40754#L366-2 is_master_triggered_~__retres1~0 := 0; 40391#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 40164#L378 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 40165#L945 assume !(0 != activate_threads_~tmp~1); 40494#L945-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 40495#L385 assume !(1 == ~t1_pc~0); 40940#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 40567#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 40338#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 40339#L953 assume !(0 != activate_threads_~tmp___0~0); 40990#L953-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 40991#L404 assume !(1 == ~t2_pc~0); 40998#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 40685#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 40651#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 40652#L961 assume !(0 != activate_threads_~tmp___1~0); 40847#L961-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 40278#L423 assume !(1 == ~t3_pc~0); 40279#L423-2 is_transmit3_triggered_~__retres1~3 := 0; 40284#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 40774#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 40529#L969 assume !(0 != activate_threads_~tmp___2~0); 40530#L969-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 40295#L442 assume !(1 == ~t4_pc~0); 40286#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 40287#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 40808#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 40866#L977 assume !(0 != activate_threads_~tmp___3~0); 41004#L977-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 40477#L461 assume !(1 == ~t5_pc~0); 40478#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 40480#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 40884#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 40793#L985 assume !(0 != activate_threads_~tmp___4~0); 40794#L985-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 40638#L480 assume !(1 == ~t6_pc~0); 40625#L480-2 is_transmit6_triggered_~__retres1~6 := 0; 40626#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 40983#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 40441#L993 assume !(0 != activate_threads_~tmp___5~0); 40442#L993-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 40444#L499 assume !(1 == ~t7_pc~0); 40747#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 40157#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 40097#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 40098#L1001 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 40952#L1001-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40953#L847 assume !(1 == ~M_E~0); 40949#L847-2 assume !(1 == ~T1_E~0); 40700#L852-1 assume !(1 == ~T2_E~0); 40490#L857-1 assume !(1 == ~T3_E~0); 40179#L862-1 assume !(1 == ~T4_E~0); 40180#L867-1 assume !(1 == ~T5_E~0); 40870#L872-1 assume !(1 == ~T6_E~0); 40605#L877-1 assume !(1 == ~T7_E~0); 40305#L882-1 assume !(1 == ~E_M~0); 40306#L887-1 assume !(1 == ~E_1~0); 40927#L892-1 assume !(1 == ~E_2~0); 40797#L897-1 assume !(1 == ~E_3~0); 40601#L902-1 assume 1 == ~E_4~0;~E_4~0 := 2; 40116#L907-1 assume !(1 == ~E_5~0); 40117#L912-1 assume !(1 == ~E_6~0); 40760#L917-1 assume !(1 == ~E_7~0); 40657#L922-1 assume { :end_inline_reset_delta_events } true; 40315#L1168-3 [2018-11-18 15:27:56,856 INFO L796 eck$LassoCheckResult]: Loop: 40315#L1168-3 assume true; 40316#L1168-1 assume !false; 40334#L1169 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 40396#L734 assume true; 40889#L626-1 assume !false; 40890#L627 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 40292#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 40175#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 40349#L617 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 40350#L631 assume !(0 != eval_~tmp~0); 40759#L749 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 45164#L519-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 45163#L759-3 assume 0 == ~M_E~0;~M_E~0 := 1; 45162#L759-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 45160#L764-3 assume !(0 == ~T2_E~0); 45158#L769-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 45156#L774-3 assume !(0 == ~T4_E~0); 45155#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 45154#L784-3 assume !(0 == ~T6_E~0); 45153#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 45152#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 45151#L799-3 assume 0 == ~E_1~0;~E_1~0 := 1; 45150#L804-3 assume !(0 == ~E_2~0); 45149#L809-3 assume 0 == ~E_3~0;~E_3~0 := 1; 45148#L814-3 assume 0 == ~E_4~0;~E_4~0 := 1; 45147#L819-3 assume 0 == ~E_5~0;~E_5~0 := 1; 45146#L824-3 assume !(0 == ~E_6~0); 45144#L829-3 assume 0 == ~E_7~0;~E_7~0 := 1; 45142#L834-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 45140#L366-27 assume 1 == ~m_pc~0; 45137#L367-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 45135#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 45132#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 45130#L945-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 45128#L945-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 45126#L385-27 assume !(1 == ~t1_pc~0); 45124#L385-29 is_transmit1_triggered_~__retres1~1 := 0; 45122#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 45120#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 45118#L953-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 40958#L953-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 40959#L404-27 assume 1 == ~t2_pc~0; 40898#L405-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 40675#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 40504#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 40505#L961-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 40705#L961-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 40223#L423-27 assume !(1 == ~t3_pc~0); 40224#L423-29 is_transmit3_triggered_~__retres1~3 := 0; 40231#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 40773#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 40311#L969-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 40312#L969-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 40317#L442-27 assume 1 == ~t4_pc~0; 40378#L443-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 40379#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 40852#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 40853#L977-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 40891#L977-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 40581#L461-27 assume !(1 == ~t5_pc~0); 40582#L461-29 is_transmit5_triggered_~__retres1~5 := 0; 40584#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 40883#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 40644#L985-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 40645#L985-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 40646#L480-27 assume !(1 == ~t6_pc~0); 40671#L480-29 is_transmit6_triggered_~__retres1~6 := 0; 40683#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 40964#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 40386#L993-27 assume !(0 != activate_threads_~tmp___5~0); 40362#L993-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 40363#L499-27 assume 1 == ~t7_pc~0; 40694#L500-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 40152#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 40153#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 40272#L1001-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 40928#L1001-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40930#L847-3 assume 1 == ~M_E~0;~M_E~0 := 2; 40951#L847-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 40701#L852-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 40492#L857-3 assume !(1 == ~T3_E~0); 40181#L862-3 assume !(1 == ~T4_E~0); 40182#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 40871#L872-3 assume !(1 == ~T6_E~0); 40610#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 40307#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 40308#L887-3 assume 1 == ~E_1~0;~E_1~0 := 2; 40916#L892-3 assume 1 == ~E_2~0;~E_2~0 := 2; 40787#L897-3 assume !(1 == ~E_3~0); 40587#L902-3 assume 1 == ~E_4~0;~E_4~0 := 2; 40099#L907-3 assume 1 == ~E_5~0;~E_5~0 := 2; 40100#L912-3 assume !(1 == ~E_6~0); 40762#L917-3 assume 1 == ~E_7~0;~E_7~0 := 2; 40658#L922-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 40293#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 40177#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 40353#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 40354#L1187 assume !(0 == start_simulation_~tmp~3); 40498#L1187-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 40294#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 40155#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 40357#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 40358#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 40124#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 40125#L1150 start_simulation_#t~ret20 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 40257#L1200 assume !(0 != start_simulation_~tmp___0~1); 40315#L1168-3 [2018-11-18 15:27:56,856 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:27:56,856 INFO L82 PathProgramCache]: Analyzing trace with hash -979121599, now seen corresponding path program 1 times [2018-11-18 15:27:56,856 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:27:56,856 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:27:56,857 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:56,857 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:27:56,857 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:56,861 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:27:56,894 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:27:56,895 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:27:56,895 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 15:27:56,895 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 15:27:56,895 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:27:56,895 INFO L82 PathProgramCache]: Analyzing trace with hash -1043366750, now seen corresponding path program 1 times [2018-11-18 15:27:56,895 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:27:56,895 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:27:56,896 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:56,896 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:27:56,896 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:56,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:27:56,930 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:27:56,931 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:27:56,931 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:27:56,931 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:27:56,931 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:27:56,931 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:27:56,931 INFO L87 Difference]: Start difference. First operand 5156 states and 7348 transitions. cyclomatic complexity: 2200 Second operand 3 states. [2018-11-18 15:27:56,991 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:27:56,991 INFO L93 Difference]: Finished difference Result 5156 states and 7257 transitions. [2018-11-18 15:27:56,992 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:27:56,993 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5156 states and 7257 transitions. [2018-11-18 15:27:57,009 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5032 [2018-11-18 15:27:57,029 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5156 states to 5156 states and 7257 transitions. [2018-11-18 15:27:57,029 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5156 [2018-11-18 15:27:57,032 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5156 [2018-11-18 15:27:57,032 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5156 states and 7257 transitions. [2018-11-18 15:27:57,037 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:27:57,037 INFO L705 BuchiCegarLoop]: Abstraction has 5156 states and 7257 transitions. [2018-11-18 15:27:57,041 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5156 states and 7257 transitions. [2018-11-18 15:27:57,090 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5156 to 5156. [2018-11-18 15:27:57,090 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5156 states. [2018-11-18 15:27:57,098 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5156 states to 5156 states and 7257 transitions. [2018-11-18 15:27:57,099 INFO L728 BuchiCegarLoop]: Abstraction has 5156 states and 7257 transitions. [2018-11-18 15:27:57,099 INFO L608 BuchiCegarLoop]: Abstraction has 5156 states and 7257 transitions. [2018-11-18 15:27:57,099 INFO L442 BuchiCegarLoop]: ======== Iteration 15============ [2018-11-18 15:27:57,099 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5156 states and 7257 transitions. [2018-11-18 15:27:57,111 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5032 [2018-11-18 15:27:57,111 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:27:57,111 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:27:57,112 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:27:57,113 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:27:57,113 INFO L794 eck$LassoCheckResult]: Stem: 50862#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 50775#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 50776#L1131 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 51131#L519 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 50965#L526 assume 1 == ~m_i~0;~m_st~0 := 0; 50966#L526-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 50731#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 50732#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 51132#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 50953#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 50672#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 50546#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 50547#L561-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 51266#L759 assume !(0 == ~M_E~0); 51270#L759-2 assume !(0 == ~T1_E~0); 51022#L764-1 assume !(0 == ~T2_E~0); 50808#L769-1 assume !(0 == ~T3_E~0); 50502#L774-1 assume !(0 == ~T4_E~0); 50503#L779-1 assume !(0 == ~T5_E~0); 51195#L784-1 assume !(0 == ~T6_E~0); 51004#L789-1 assume !(0 == ~T7_E~0); 50610#L794-1 assume !(0 == ~E_M~0); 50611#L799-1 assume !(0 == ~E_1~0); 51241#L804-1 assume !(0 == ~E_2~0); 51114#L809-1 assume !(0 == ~E_3~0); 50906#L814-1 assume !(0 == ~E_4~0); 50420#L819-1 assume !(0 == ~E_5~0); 50421#L824-1 assume !(0 == ~E_6~0); 51086#L829-1 assume !(0 == ~E_7~0); 50976#L834-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 50977#L366 assume !(1 == ~m_pc~0); 51074#L366-2 is_master_triggered_~__retres1~0 := 0; 50701#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 50485#L378 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 50486#L945 assume !(0 != activate_threads_~tmp~1); 50809#L945-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 50810#L385 assume !(1 == ~t1_pc~0); 51262#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 50882#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 50651#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 50652#L953 assume !(0 != activate_threads_~tmp___0~0); 51310#L953-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 51311#L404 assume !(1 == ~t2_pc~0); 51318#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 51003#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 50967#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 50968#L961 assume !(0 != activate_threads_~tmp___1~0); 51169#L961-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 50591#L423 assume !(1 == ~t3_pc~0); 50592#L423-2 is_transmit3_triggered_~__retres1~3 := 0; 50597#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 51097#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 50845#L969 assume !(0 != activate_threads_~tmp___2~0); 50846#L969-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 50608#L442 assume !(1 == ~t4_pc~0); 50599#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 50600#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 51134#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 51188#L977 assume !(0 != activate_threads_~tmp___3~0); 51322#L977-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 50791#L461 assume !(1 == ~t5_pc~0); 50792#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 50794#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 51206#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 51117#L985 assume !(0 != activate_threads_~tmp___4~0); 51118#L985-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 50954#L480 assume !(1 == ~t6_pc~0); 50941#L480-2 is_transmit6_triggered_~__retres1~6 := 0; 50942#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 51303#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 50752#L993 assume !(0 != activate_threads_~tmp___5~0); 50753#L993-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 50755#L499 assume !(1 == ~t7_pc~0); 51067#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 50476#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 50416#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 50417#L1001 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 51272#L1001-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 51273#L847 assume !(1 == ~M_E~0); 51269#L847-2 assume !(1 == ~T1_E~0); 51019#L852-1 assume !(1 == ~T2_E~0); 50805#L857-1 assume !(1 == ~T3_E~0); 50498#L862-1 assume !(1 == ~T4_E~0); 50499#L867-1 assume !(1 == ~T5_E~0); 51193#L872-1 assume !(1 == ~T6_E~0); 50922#L877-1 assume !(1 == ~T7_E~0); 50618#L882-1 assume !(1 == ~E_M~0); 50619#L887-1 assume !(1 == ~E_1~0); 51247#L892-1 assume !(1 == ~E_2~0); 51121#L897-1 assume !(1 == ~E_3~0); 50917#L902-1 assume !(1 == ~E_4~0); 50435#L907-1 assume !(1 == ~E_5~0); 50436#L912-1 assume !(1 == ~E_6~0); 51083#L917-1 assume !(1 == ~E_7~0); 50973#L922-1 assume { :end_inline_reset_delta_events } true; 50974#L1168-3 [2018-11-18 15:27:57,113 INFO L796 eck$LassoCheckResult]: Loop: 50974#L1168-3 assume true; 55197#L1168-1 assume !false; 50758#L1169 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 50705#L734 assume true; 51211#L626-1 assume !false; 51212#L627 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 50605#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 50494#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 50662#L617 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 50663#L631 assume !(0 != eval_~tmp~0); 55091#L749 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 55359#L519-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 55358#L759-3 assume 0 == ~M_E~0;~M_E~0 := 1; 55357#L759-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 55356#L764-3 assume !(0 == ~T2_E~0); 55355#L769-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 55354#L774-3 assume !(0 == ~T4_E~0); 55353#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 55352#L784-3 assume !(0 == ~T6_E~0); 55351#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 55350#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 55349#L799-3 assume 0 == ~E_1~0;~E_1~0 := 1; 55348#L804-3 assume !(0 == ~E_2~0); 55347#L809-3 assume 0 == ~E_3~0;~E_3~0 := 1; 55346#L814-3 assume !(0 == ~E_4~0); 55345#L819-3 assume 0 == ~E_5~0;~E_5~0 := 1; 55344#L824-3 assume !(0 == ~E_6~0); 55343#L829-3 assume 0 == ~E_7~0;~E_7~0 := 1; 55341#L834-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 55339#L366-27 assume 1 == ~m_pc~0; 55336#L367-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 55334#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 55331#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 55329#L945-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 55327#L945-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 55325#L385-27 assume !(1 == ~t1_pc~0); 55323#L385-29 is_transmit1_triggered_~__retres1~1 := 0; 55321#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 55319#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 55317#L953-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 55315#L953-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 55313#L404-27 assume 1 == ~t2_pc~0; 55310#L405-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 55308#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 55307#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 55304#L961-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 55302#L961-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 55300#L423-27 assume !(1 == ~t3_pc~0); 55298#L423-29 is_transmit3_triggered_~__retres1~3 := 0; 55296#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 55294#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 55292#L969-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 55289#L969-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 55287#L442-27 assume !(1 == ~t4_pc~0); 55284#L442-29 is_transmit4_triggered_~__retres1~4 := 0; 55282#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 55280#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 55278#L977-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 55276#L977-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 55274#L461-27 assume !(1 == ~t5_pc~0); 55272#L461-29 is_transmit5_triggered_~__retres1~5 := 0; 55270#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 55268#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 55266#L985-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 55264#L985-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 55262#L480-27 assume !(1 == ~t6_pc~0); 55259#L480-29 is_transmit6_triggered_~__retres1~6 := 0; 55257#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 55255#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 55253#L993-27 assume !(0 != activate_threads_~tmp___5~0); 55251#L993-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 55249#L499-27 assume 1 == ~t7_pc~0; 55246#L500-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 55245#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 55244#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 55243#L1001-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 55242#L1001-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 55241#L847-3 assume 1 == ~M_E~0;~M_E~0 := 2; 55240#L847-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 55239#L852-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 55238#L857-3 assume !(1 == ~T3_E~0); 55237#L862-3 assume !(1 == ~T4_E~0); 55236#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 55235#L872-3 assume !(1 == ~T6_E~0); 55234#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 55233#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 55232#L887-3 assume 1 == ~E_1~0;~E_1~0 := 2; 55231#L892-3 assume 1 == ~E_2~0;~E_2~0 := 2; 55230#L897-3 assume !(1 == ~E_3~0); 55229#L902-3 assume !(1 == ~E_4~0); 55228#L907-3 assume 1 == ~E_5~0;~E_5~0 := 2; 55227#L912-3 assume !(1 == ~E_6~0); 55226#L917-3 assume 1 == ~E_7~0;~E_7~0 := 2; 55225#L922-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 55224#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 55216#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 55215#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 55214#L1187 assume !(0 == start_simulation_~tmp~3); 55212#L1187-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 55211#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 55203#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 55202#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 55201#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 55200#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 55199#L1150 start_simulation_#t~ret20 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 55198#L1200 assume !(0 != start_simulation_~tmp___0~1); 50974#L1168-3 [2018-11-18 15:27:57,113 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:27:57,113 INFO L82 PathProgramCache]: Analyzing trace with hash -977274557, now seen corresponding path program 1 times [2018-11-18 15:27:57,114 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:27:57,114 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:27:57,114 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:57,114 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:27:57,114 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:57,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:27:57,180 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:27:57,181 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:27:57,181 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 15:27:57,181 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 15:27:57,181 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:27:57,181 INFO L82 PathProgramCache]: Analyzing trace with hash -1338735197, now seen corresponding path program 1 times [2018-11-18 15:27:57,181 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:27:57,182 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:27:57,182 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:57,182 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:27:57,182 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:57,188 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:27:57,217 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:27:57,217 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:27:57,218 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:27:57,218 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:27:57,218 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 15:27:57,218 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:27:57,218 INFO L87 Difference]: Start difference. First operand 5156 states and 7257 transitions. cyclomatic complexity: 2109 Second operand 5 states. [2018-11-18 15:27:57,488 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:27:57,488 INFO L93 Difference]: Finished difference Result 11459 states and 16188 transitions. [2018-11-18 15:27:57,489 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 15:27:57,490 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11459 states and 16188 transitions. [2018-11-18 15:27:57,523 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11248 [2018-11-18 15:27:57,551 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11459 states to 11459 states and 16188 transitions. [2018-11-18 15:27:57,552 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11459 [2018-11-18 15:27:57,557 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11459 [2018-11-18 15:27:57,558 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11459 states and 16188 transitions. [2018-11-18 15:27:57,564 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:27:57,564 INFO L705 BuchiCegarLoop]: Abstraction has 11459 states and 16188 transitions. [2018-11-18 15:27:57,572 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11459 states and 16188 transitions. [2018-11-18 15:27:57,631 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11459 to 5363. [2018-11-18 15:27:57,631 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5363 states. [2018-11-18 15:27:57,639 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5363 states to 5363 states and 7464 transitions. [2018-11-18 15:27:57,639 INFO L728 BuchiCegarLoop]: Abstraction has 5363 states and 7464 transitions. [2018-11-18 15:27:57,640 INFO L608 BuchiCegarLoop]: Abstraction has 5363 states and 7464 transitions. [2018-11-18 15:27:57,640 INFO L442 BuchiCegarLoop]: ======== Iteration 16============ [2018-11-18 15:27:57,640 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5363 states and 7464 transitions. [2018-11-18 15:27:57,652 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5236 [2018-11-18 15:27:57,652 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:27:57,652 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:27:57,653 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:27:57,653 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:27:57,653 INFO L794 eck$LassoCheckResult]: Stem: 67501#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 67416#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 67417#L1131 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 67807#L519 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 67606#L526 assume 1 == ~m_i~0;~m_st~0 := 0; 67607#L526-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 67372#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 67373#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 67808#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 67594#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 67316#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 67175#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 67176#L561-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 67961#L759 assume !(0 == ~M_E~0); 67967#L759-2 assume !(0 == ~T1_E~0); 67669#L764-1 assume !(0 == ~T2_E~0); 67448#L769-1 assume !(0 == ~T3_E~0); 67131#L774-1 assume !(0 == ~T4_E~0); 67132#L779-1 assume !(0 == ~T5_E~0); 67875#L784-1 assume !(0 == ~T6_E~0); 67648#L789-1 assume !(0 == ~T7_E~0); 67254#L794-1 assume !(0 == ~E_M~0); 67255#L799-1 assume !(0 == ~E_1~0); 67928#L804-1 assume !(0 == ~E_2~0); 67775#L809-1 assume !(0 == ~E_3~0); 67546#L814-1 assume !(0 == ~E_4~0); 67048#L819-1 assume !(0 == ~E_5~0); 67049#L824-1 assume !(0 == ~E_6~0); 67746#L829-1 assume !(0 == ~E_7~0); 67616#L834-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 67617#L366 assume !(1 == ~m_pc~0); 67734#L366-2 is_master_triggered_~__retres1~0 := 0; 67345#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 67112#L378 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 67113#L945 assume !(0 != activate_threads_~tmp~1); 67449#L945-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 67450#L385 assume !(1 == ~t1_pc~0); 67955#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 67523#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 67295#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 67296#L953 assume !(0 != activate_threads_~tmp___0~0); 68008#L953-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 68009#L404 assume !(1 == ~t2_pc~0); 68016#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 67647#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 67608#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 67609#L961 assume !(0 != activate_threads_~tmp___1~0); 67850#L961-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 67232#L423 assume !(1 == ~t3_pc~0); 67233#L423-2 is_transmit3_triggered_~__retres1~3 := 0; 67240#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 67759#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 67484#L969 assume !(0 != activate_threads_~tmp___2~0); 67485#L969-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 67252#L442 assume !(1 == ~t4_pc~0); 67243#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 67244#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 67810#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 67869#L977 assume !(0 != activate_threads_~tmp___3~0); 68023#L977-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 67431#L461 assume !(1 == ~t5_pc~0); 67432#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 67434#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 67887#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 67778#L985 assume !(0 != activate_threads_~tmp___4~0); 67779#L985-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 67595#L480 assume !(1 == ~t6_pc~0); 67582#L480-2 is_transmit6_triggered_~__retres1~6 := 0; 67583#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 68001#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 67395#L993 assume !(0 != activate_threads_~tmp___5~0); 67396#L993-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 67398#L499 assume !(1 == ~t7_pc~0); 67727#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 67104#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 67105#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 67969#L1001 assume !(0 != activate_threads_~tmp___6~0); 67970#L1001-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 67971#L847 assume !(1 == ~M_E~0); 67966#L847-2 assume !(1 == ~T1_E~0); 67666#L852-1 assume !(1 == ~T2_E~0); 67445#L857-1 assume !(1 == ~T3_E~0); 67127#L862-1 assume !(1 == ~T4_E~0); 67128#L867-1 assume !(1 == ~T5_E~0); 67873#L872-1 assume !(1 == ~T6_E~0); 67562#L877-1 assume !(1 == ~T7_E~0); 67262#L882-1 assume !(1 == ~E_M~0); 67263#L887-1 assume !(1 == ~E_1~0); 67936#L892-1 assume !(1 == ~E_2~0); 67782#L897-1 assume !(1 == ~E_3~0); 67558#L902-1 assume !(1 == ~E_4~0); 67063#L907-1 assume !(1 == ~E_5~0); 67064#L912-1 assume !(1 == ~E_6~0); 67743#L917-1 assume !(1 == ~E_7~0); 67614#L922-1 assume { :end_inline_reset_delta_events } true; 67272#L1168-3 [2018-11-18 15:27:57,654 INFO L796 eck$LassoCheckResult]: Loop: 67272#L1168-3 assume true; 67273#L1168-1 assume !false; 67291#L1169 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 67349#L734 assume true; 67891#L626-1 assume !false; 67892#L627 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 67249#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 67123#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 67306#L617 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 67307#L631 assume !(0 != eval_~tmp~0); 67741#L749 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 72406#L519-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 72405#L759-3 assume 0 == ~M_E~0;~M_E~0 := 1; 67959#L759-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 67655#L764-3 assume !(0 == ~T2_E~0); 67440#L769-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 67116#L774-3 assume !(0 == ~T4_E~0); 67117#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 67871#L784-3 assume !(0 == ~T6_E~0); 67652#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 67258#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 67259#L799-3 assume 0 == ~E_1~0;~E_1~0 := 1; 67931#L804-3 assume !(0 == ~E_2~0); 67776#L809-3 assume 0 == ~E_3~0;~E_3~0 := 1; 67548#L814-3 assume !(0 == ~E_4~0); 67050#L819-3 assume 0 == ~E_5~0;~E_5~0 := 1; 67051#L824-3 assume !(0 == ~E_6~0); 72377#L829-3 assume 0 == ~E_7~0;~E_7~0 := 1; 67618#L834-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 67619#L366-27 assume 1 == ~m_pc~0; 67699#L367-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 67341#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 67075#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 67076#L945-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 67412#L945-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 67551#L385-27 assume !(1 == ~t1_pc~0); 72284#L385-29 is_transmit1_triggered_~__retres1~1 := 0; 72283#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 72282#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 72281#L953-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 72280#L953-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 72279#L404-27 assume 1 == ~t2_pc~0; 72277#L405-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 72276#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 72275#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 72274#L961-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 72273#L961-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 72272#L423-27 assume !(1 == ~t3_pc~0); 72271#L423-29 is_transmit3_triggered_~__retres1~3 := 0; 72270#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 72269#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 72268#L969-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 72267#L969-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 72266#L442-27 assume !(1 == ~t4_pc~0); 72264#L442-29 is_transmit4_triggered_~__retres1~4 := 0; 72263#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 72262#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 72261#L977-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 72260#L977-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 67537#L461-27 assume !(1 == ~t5_pc~0); 67538#L461-29 is_transmit5_triggered_~__retres1~5 := 0; 72256#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 72255#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 72254#L985-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 72253#L985-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 72252#L480-27 assume !(1 == ~t6_pc~0); 72248#L480-29 is_transmit6_triggered_~__retres1~6 := 0; 72246#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 72244#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 72242#L993-27 assume !(0 != activate_threads_~tmp___5~0); 72235#L993-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 72234#L499-27 assume !(1 == ~t7_pc~0); 72233#L499-29 is_transmit7_triggered_~__retres1~7 := 0; 72231#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 72229#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 72223#L1001-27 assume !(0 != activate_threads_~tmp___6~0); 72218#L1001-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 72215#L847-3 assume 1 == ~M_E~0;~M_E~0 := 2; 72212#L847-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 72208#L852-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 72184#L857-3 assume !(1 == ~T3_E~0); 72183#L862-3 assume !(1 == ~T4_E~0); 72181#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 72179#L872-3 assume !(1 == ~T6_E~0); 72177#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 72175#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 72173#L887-3 assume 1 == ~E_1~0;~E_1~0 := 2; 72067#L892-3 assume 1 == ~E_2~0;~E_2~0 := 2; 72066#L897-3 assume !(1 == ~E_3~0); 72065#L902-3 assume !(1 == ~E_4~0); 72064#L907-3 assume 1 == ~E_5~0;~E_5~0 := 2; 72063#L912-3 assume !(1 == ~E_6~0); 72038#L917-3 assume 1 == ~E_7~0;~E_7~0 := 2; 71847#L922-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 71648#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 71639#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 71637#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 71635#L1187 assume !(0 == start_simulation_~tmp~3); 71633#L1187-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 71632#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 71624#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 71623#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 67634#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 67071#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 67072#L1150 start_simulation_#t~ret20 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 67204#L1200 assume !(0 != start_simulation_~tmp___0~1); 67272#L1168-3 [2018-11-18 15:27:57,654 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:27:57,654 INFO L82 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 1 times [2018-11-18 15:27:57,654 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:27:57,654 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:27:57,655 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:57,655 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:27:57,655 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:57,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:27:57,666 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:27:57,702 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:27:57,702 INFO L82 PathProgramCache]: Analyzing trace with hash 414313766, now seen corresponding path program 1 times [2018-11-18 15:27:57,703 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:27:57,703 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:27:57,703 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:57,703 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:27:57,703 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:57,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:27:57,739 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:27:57,739 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:27:57,739 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:27:57,739 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:27:57,740 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:27:57,740 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:27:57,740 INFO L87 Difference]: Start difference. First operand 5363 states and 7464 transitions. cyclomatic complexity: 2109 Second operand 3 states. [2018-11-18 15:27:57,776 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:27:57,776 INFO L93 Difference]: Finished difference Result 6032 states and 8400 transitions. [2018-11-18 15:27:57,777 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:27:57,778 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6032 states and 8400 transitions. [2018-11-18 15:27:57,795 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5832 [2018-11-18 15:27:57,810 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6032 states to 6032 states and 8400 transitions. [2018-11-18 15:27:57,810 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6032 [2018-11-18 15:27:57,814 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6032 [2018-11-18 15:27:57,814 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6032 states and 8400 transitions. [2018-11-18 15:27:57,818 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:27:57,818 INFO L705 BuchiCegarLoop]: Abstraction has 6032 states and 8400 transitions. [2018-11-18 15:27:57,823 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6032 states and 8400 transitions. [2018-11-18 15:27:57,866 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6032 to 6032. [2018-11-18 15:27:57,866 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6032 states. [2018-11-18 15:27:57,875 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6032 states to 6032 states and 8400 transitions. [2018-11-18 15:27:57,876 INFO L728 BuchiCegarLoop]: Abstraction has 6032 states and 8400 transitions. [2018-11-18 15:27:57,876 INFO L608 BuchiCegarLoop]: Abstraction has 6032 states and 8400 transitions. [2018-11-18 15:27:57,876 INFO L442 BuchiCegarLoop]: ======== Iteration 17============ [2018-11-18 15:27:57,876 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6032 states and 8400 transitions. [2018-11-18 15:27:57,890 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5832 [2018-11-18 15:27:57,890 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:27:57,890 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:27:57,891 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:27:57,891 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:27:57,891 INFO L794 eck$LassoCheckResult]: Stem: 78898#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 78808#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 78809#L1131 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 79181#L519 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 78998#L526 assume 1 == ~m_i~0;~m_st~0 := 0; 78999#L526-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 78764#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 78765#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 79182#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 78985#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 78706#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 78575#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 78576#L561-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 79328#L759 assume !(0 == ~M_E~0); 79334#L759-2 assume !(0 == ~T1_E~0); 79057#L764-1 assume !(0 == ~T2_E~0); 78841#L769-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 78531#L774-1 assume !(0 == ~T4_E~0); 78532#L779-1 assume !(0 == ~T5_E~0); 79248#L784-1 assume !(0 == ~T6_E~0); 79037#L789-1 assume !(0 == ~T7_E~0); 78644#L794-1 assume !(0 == ~E_M~0); 78645#L799-1 assume !(0 == ~E_1~0); 79299#L804-1 assume !(0 == ~E_2~0); 79150#L809-1 assume !(0 == ~E_3~0); 79151#L814-1 assume !(0 == ~E_4~0); 79612#L819-1 assume !(0 == ~E_5~0); 79611#L824-1 assume !(0 == ~E_6~0); 79609#L829-1 assume !(0 == ~E_7~0); 79009#L834-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 79010#L366 assume !(1 == ~m_pc~0); 79112#L366-2 is_master_triggered_~__retres1~0 := 0; 78736#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 78514#L378 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 78515#L945 assume !(0 != activate_threads_~tmp~1); 78843#L945-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 78844#L385 assume !(1 == ~t1_pc~0); 79323#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 78921#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 78685#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 78686#L953 assume !(0 != activate_threads_~tmp___0~0); 79375#L953-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 79376#L404 assume !(1 == ~t2_pc~0); 79381#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 79035#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 79036#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 79561#L961 assume !(0 != activate_threads_~tmp___1~0); 79558#L961-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 79556#L423 assume !(1 == ~t3_pc~0); 79555#L423-2 is_transmit3_triggered_~__retres1~3 := 0; 79554#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 79500#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 79499#L969 assume !(0 != activate_threads_~tmp___2~0); 79498#L969-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 79489#L442 assume !(1 == ~t4_pc~0); 79480#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 79184#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 79185#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 79465#L977 assume !(0 != activate_threads_~tmp___3~0); 79461#L977-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 79458#L461 assume !(1 == ~t5_pc~0); 79454#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 79260#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 79261#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 79154#L985 assume !(0 != activate_threads_~tmp___4~0); 79155#L985-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 78986#L480 assume !(1 == ~t6_pc~0); 78973#L480-2 is_transmit6_triggered_~__retres1~6 := 0; 78974#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 79369#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 78785#L993 assume !(0 != activate_threads_~tmp___5~0); 78786#L993-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 78788#L499 assume !(1 == ~t7_pc~0); 79105#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 79416#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 79417#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 79336#L1001 assume !(0 != activate_threads_~tmp___6~0); 79337#L1001-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 79338#L847 assume !(1 == ~M_E~0); 79333#L847-2 assume !(1 == ~T1_E~0); 79052#L852-1 assume !(1 == ~T2_E~0); 78838#L857-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 78527#L862-1 assume !(1 == ~T4_E~0); 78528#L867-1 assume !(1 == ~T5_E~0); 79246#L872-1 assume !(1 == ~T6_E~0); 78954#L877-1 assume !(1 == ~T7_E~0); 78652#L882-1 assume !(1 == ~E_M~0); 78653#L887-1 assume !(1 == ~E_1~0); 79307#L892-1 assume !(1 == ~E_2~0); 79160#L897-1 assume !(1 == ~E_3~0); 78949#L902-1 assume !(1 == ~E_4~0); 78464#L907-1 assume !(1 == ~E_5~0); 78465#L912-1 assume !(1 == ~E_6~0); 79119#L917-1 assume !(1 == ~E_7~0); 79006#L922-1 assume { :end_inline_reset_delta_events } true; 79007#L1168-3 [2018-11-18 15:27:57,891 INFO L796 eck$LassoCheckResult]: Loop: 79007#L1168-3 assume true; 83635#L1168-1 assume !false; 83423#L1169 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 83422#L734 assume true; 83421#L626-1 assume !false; 83420#L627 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 83412#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 83411#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 83410#L617 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 83408#L631 assume !(0 != eval_~tmp~0); 83407#L749 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 83406#L519-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 83405#L759-3 assume 0 == ~M_E~0;~M_E~0 := 1; 83404#L759-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 83403#L764-3 assume !(0 == ~T2_E~0); 83401#L769-3 assume !(0 == ~T3_E~0); 83400#L774-3 assume !(0 == ~T4_E~0); 83399#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 83398#L784-3 assume !(0 == ~T6_E~0); 83397#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 83396#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 83395#L799-3 assume 0 == ~E_1~0;~E_1~0 := 1; 83394#L804-3 assume !(0 == ~E_2~0); 83393#L809-3 assume 0 == ~E_3~0;~E_3~0 := 1; 83392#L814-3 assume !(0 == ~E_4~0); 83391#L819-3 assume 0 == ~E_5~0;~E_5~0 := 1; 83390#L824-3 assume !(0 == ~E_6~0); 83389#L829-3 assume 0 == ~E_7~0;~E_7~0 := 1; 83388#L834-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 83387#L366-27 assume 1 == ~m_pc~0; 83385#L367-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 83384#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 83383#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 83382#L945-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 83381#L945-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 83380#L385-27 assume !(1 == ~t1_pc~0); 83379#L385-29 is_transmit1_triggered_~__retres1~1 := 0; 83378#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 83377#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 83376#L953-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 83375#L953-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 83374#L404-27 assume 1 == ~t2_pc~0; 83371#L405-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 83369#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 83367#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 83364#L961-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 83362#L961-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 83360#L423-27 assume !(1 == ~t3_pc~0); 83358#L423-29 is_transmit3_triggered_~__retres1~3 := 0; 83356#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 83354#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 83352#L969-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 83350#L969-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 83348#L442-27 assume !(1 == ~t4_pc~0); 83345#L442-29 is_transmit4_triggered_~__retres1~4 := 0; 83343#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 83340#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 83338#L977-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 83336#L977-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 83334#L461-27 assume !(1 == ~t5_pc~0); 83326#L461-29 is_transmit5_triggered_~__retres1~5 := 0; 83321#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 83318#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 83319#L985-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 83764#L985-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 83762#L480-27 assume !(1 == ~t6_pc~0); 83759#L480-29 is_transmit6_triggered_~__retres1~6 := 0; 83757#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 83755#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 83300#L993-27 assume !(0 != activate_threads_~tmp___5~0); 83298#L993-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 83295#L499-27 assume !(1 == ~t7_pc~0); 83289#L499-29 is_transmit7_triggered_~__retres1~7 := 0; 83287#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 83284#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 83285#L1001-27 assume !(0 != activate_threads_~tmp___6~0); 83734#L1001-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 83732#L847-3 assume 1 == ~M_E~0;~M_E~0 := 2; 83730#L847-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 83727#L852-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 83696#L857-3 assume !(1 == ~T3_E~0); 83695#L862-3 assume !(1 == ~T4_E~0); 83694#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 83693#L872-3 assume !(1 == ~T6_E~0); 83692#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 83691#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 83690#L887-3 assume 1 == ~E_1~0;~E_1~0 := 2; 83689#L892-3 assume 1 == ~E_2~0;~E_2~0 := 2; 83688#L897-3 assume !(1 == ~E_3~0); 83687#L902-3 assume !(1 == ~E_4~0); 83686#L907-3 assume 1 == ~E_5~0;~E_5~0 := 2; 83683#L912-3 assume !(1 == ~E_6~0); 83681#L917-3 assume 1 == ~E_7~0;~E_7~0 := 2; 83679#L922-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 83677#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 83668#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 83666#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 83663#L1187 assume !(0 == start_simulation_~tmp~3); 83660#L1187-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 83658#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 83649#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 83647#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 83644#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 83642#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 83640#L1150 start_simulation_#t~ret20 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 83638#L1200 assume !(0 != start_simulation_~tmp___0~1); 79007#L1168-3 [2018-11-18 15:27:57,892 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:27:57,892 INFO L82 PathProgramCache]: Analyzing trace with hash -1895340795, now seen corresponding path program 1 times [2018-11-18 15:27:57,892 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:27:57,892 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:27:57,892 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:57,893 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:27:57,893 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:57,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:27:57,920 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:27:57,920 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:27:57,920 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 15:27:57,921 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 15:27:57,921 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:27:57,921 INFO L82 PathProgramCache]: Analyzing trace with hash -1526268248, now seen corresponding path program 1 times [2018-11-18 15:27:57,921 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:27:57,921 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:27:57,922 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:57,922 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:27:57,922 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:57,926 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:27:57,956 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:27:57,957 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:27:57,957 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:27:57,957 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:27:57,957 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:27:57,957 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:27:57,957 INFO L87 Difference]: Start difference. First operand 6032 states and 8400 transitions. cyclomatic complexity: 2376 Second operand 3 states. [2018-11-18 15:27:57,990 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:27:57,990 INFO L93 Difference]: Finished difference Result 5363 states and 7438 transitions. [2018-11-18 15:27:57,992 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:27:57,992 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5363 states and 7438 transitions. [2018-11-18 15:27:58,008 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5236 [2018-11-18 15:27:58,021 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5363 states to 5363 states and 7438 transitions. [2018-11-18 15:27:58,022 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5363 [2018-11-18 15:27:58,025 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5363 [2018-11-18 15:27:58,025 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5363 states and 7438 transitions. [2018-11-18 15:27:58,028 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:27:58,028 INFO L705 BuchiCegarLoop]: Abstraction has 5363 states and 7438 transitions. [2018-11-18 15:27:58,033 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5363 states and 7438 transitions. [2018-11-18 15:27:58,069 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5363 to 5363. [2018-11-18 15:27:58,070 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5363 states. [2018-11-18 15:27:58,078 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5363 states to 5363 states and 7438 transitions. [2018-11-18 15:27:58,078 INFO L728 BuchiCegarLoop]: Abstraction has 5363 states and 7438 transitions. [2018-11-18 15:27:58,078 INFO L608 BuchiCegarLoop]: Abstraction has 5363 states and 7438 transitions. [2018-11-18 15:27:58,078 INFO L442 BuchiCegarLoop]: ======== Iteration 18============ [2018-11-18 15:27:58,078 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5363 states and 7438 transitions. [2018-11-18 15:27:58,090 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5236 [2018-11-18 15:27:58,090 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:27:58,090 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:27:58,091 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:27:58,091 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:27:58,091 INFO L794 eck$LassoCheckResult]: Stem: 90296#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 90211#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 90212#L1131 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 90583#L519 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 90403#L526 assume 1 == ~m_i~0;~m_st~0 := 0; 90404#L526-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 90164#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 90165#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 90584#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 90390#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 90108#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 89976#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 89977#L561-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 90724#L759 assume !(0 == ~M_E~0); 90728#L759-2 assume !(0 == ~T1_E~0); 90462#L764-1 assume !(0 == ~T2_E~0); 90243#L769-1 assume !(0 == ~T3_E~0); 89933#L774-1 assume !(0 == ~T4_E~0); 89934#L779-1 assume !(0 == ~T5_E~0); 90645#L784-1 assume !(0 == ~T6_E~0); 90444#L789-1 assume !(0 == ~T7_E~0); 90045#L794-1 assume !(0 == ~E_M~0); 90046#L799-1 assume !(0 == ~E_1~0); 90694#L804-1 assume !(0 == ~E_2~0); 90557#L809-1 assume !(0 == ~E_3~0); 90344#L814-1 assume !(0 == ~E_4~0); 89851#L819-1 assume !(0 == ~E_5~0); 89852#L824-1 assume !(0 == ~E_6~0); 90528#L829-1 assume !(0 == ~E_7~0); 90415#L834-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 90416#L366 assume !(1 == ~m_pc~0); 90518#L366-2 is_master_triggered_~__retres1~0 := 0; 90136#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 89914#L378 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 89915#L945 assume !(0 != activate_threads_~tmp~1); 90244#L945-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 90245#L385 assume !(1 == ~t1_pc~0); 90717#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 90319#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 90087#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 90088#L953 assume !(0 != activate_threads_~tmp___0~0); 90772#L953-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 90773#L404 assume !(1 == ~t2_pc~0); 90780#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 90443#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 90405#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 90406#L961 assume !(0 != activate_threads_~tmp___1~0); 90619#L961-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 90026#L423 assume !(1 == ~t3_pc~0); 90027#L423-2 is_transmit3_triggered_~__retres1~3 := 0; 90032#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 90540#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 90280#L969 assume !(0 != activate_threads_~tmp___2~0); 90281#L969-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 90043#L442 assume !(1 == ~t4_pc~0); 90034#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 90035#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 90586#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 90638#L977 assume !(0 != activate_threads_~tmp___3~0); 90785#L977-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 90227#L461 assume !(1 == ~t5_pc~0); 90228#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 90230#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 90659#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 90560#L985 assume !(0 != activate_threads_~tmp___4~0); 90561#L985-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 90391#L480 assume !(1 == ~t6_pc~0); 90378#L480-2 is_transmit6_triggered_~__retres1~6 := 0; 90379#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 90764#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 90188#L993 assume !(0 != activate_threads_~tmp___5~0); 90189#L993-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 90191#L499 assume !(1 == ~t7_pc~0); 90511#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 89907#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 89847#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 89848#L1001 assume !(0 != activate_threads_~tmp___6~0); 90732#L1001-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 90733#L847 assume !(1 == ~M_E~0); 90727#L847-2 assume !(1 == ~T1_E~0); 90460#L852-1 assume !(1 == ~T2_E~0); 90240#L857-1 assume !(1 == ~T3_E~0); 89929#L862-1 assume !(1 == ~T4_E~0); 89930#L867-1 assume !(1 == ~T5_E~0); 90643#L872-1 assume !(1 == ~T6_E~0); 90358#L877-1 assume !(1 == ~T7_E~0); 90053#L882-1 assume !(1 == ~E_M~0); 90054#L887-1 assume !(1 == ~E_1~0); 90702#L892-1 assume !(1 == ~E_2~0); 90564#L897-1 assume !(1 == ~E_3~0); 90354#L902-1 assume !(1 == ~E_4~0); 89866#L907-1 assume !(1 == ~E_5~0); 89867#L912-1 assume !(1 == ~E_6~0); 90525#L917-1 assume !(1 == ~E_7~0); 90411#L922-1 assume { :end_inline_reset_delta_events } true; 90412#L1168-3 [2018-11-18 15:27:58,092 INFO L796 eck$LassoCheckResult]: Loop: 90412#L1168-3 assume true; 91693#L1168-1 assume !false; 91560#L1169 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 91558#L734 assume true; 91557#L626-1 assume !false; 91556#L627 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 91548#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 91546#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 91544#L617 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 91540#L631 assume !(0 != eval_~tmp~0); 91541#L749 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 94481#L519-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 94480#L759-3 assume 0 == ~M_E~0;~M_E~0 := 1; 94479#L759-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 94478#L764-3 assume !(0 == ~T2_E~0); 94477#L769-3 assume !(0 == ~T3_E~0); 94476#L774-3 assume !(0 == ~T4_E~0); 94475#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 94474#L784-3 assume !(0 == ~T6_E~0); 94473#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 94472#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 94470#L799-3 assume 0 == ~E_1~0;~E_1~0 := 1; 94467#L804-3 assume !(0 == ~E_2~0); 94465#L809-3 assume 0 == ~E_3~0;~E_3~0 := 1; 94463#L814-3 assume !(0 == ~E_4~0); 94461#L819-3 assume 0 == ~E_5~0;~E_5~0 := 1; 94459#L824-3 assume !(0 == ~E_6~0); 94457#L829-3 assume 0 == ~E_7~0;~E_7~0 := 1; 94454#L834-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 94452#L366-27 assume 1 == ~m_pc~0; 94449#L367-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 94447#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 94445#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 94443#L945-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 94440#L945-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 94438#L385-27 assume !(1 == ~t1_pc~0); 94436#L385-29 is_transmit1_triggered_~__retres1~1 := 0; 94434#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 94432#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 94430#L953-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 94427#L953-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 94425#L404-27 assume !(1 == ~t2_pc~0); 94423#L404-29 is_transmit2_triggered_~__retres1~2 := 0; 94420#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 94418#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 94415#L961-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 94413#L961-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 94392#L423-27 assume !(1 == ~t3_pc~0); 94389#L423-29 is_transmit3_triggered_~__retres1~3 := 0; 94388#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 94387#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 94386#L969-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 94385#L969-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 94384#L442-27 assume !(1 == ~t4_pc~0); 94382#L442-29 is_transmit4_triggered_~__retres1~4 := 0; 94381#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 94380#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 94379#L977-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 94378#L977-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 94377#L461-27 assume !(1 == ~t5_pc~0); 94375#L461-29 is_transmit5_triggered_~__retres1~5 := 0; 94374#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 94373#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 94372#L985-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 94371#L985-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 94370#L480-27 assume !(1 == ~t6_pc~0); 94368#L480-29 is_transmit6_triggered_~__retres1~6 := 0; 94366#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 94363#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 94361#L993-27 assume !(0 != activate_threads_~tmp___5~0); 94359#L993-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 94357#L499-27 assume !(1 == ~t7_pc~0); 94355#L499-29 is_transmit7_triggered_~__retres1~7 := 0; 94861#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 94859#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 94337#L1001-27 assume !(0 != activate_threads_~tmp___6~0); 94334#L1001-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 94332#L847-3 assume 1 == ~M_E~0;~M_E~0 := 2; 94330#L847-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 94328#L852-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 94326#L857-3 assume !(1 == ~T3_E~0); 94323#L862-3 assume !(1 == ~T4_E~0); 94321#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 94319#L872-3 assume !(1 == ~T6_E~0); 94317#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 94158#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 91752#L887-3 assume 1 == ~E_1~0;~E_1~0 := 2; 91748#L892-3 assume 1 == ~E_2~0;~E_2~0 := 2; 91746#L897-3 assume !(1 == ~E_3~0); 91744#L902-3 assume !(1 == ~E_4~0); 91742#L907-3 assume 1 == ~E_5~0;~E_5~0 := 2; 91739#L912-3 assume !(1 == ~E_6~0); 91737#L917-3 assume 1 == ~E_7~0;~E_7~0 := 2; 91736#L922-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 91735#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 91726#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 91723#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 91720#L1187 assume !(0 == start_simulation_~tmp~3); 91717#L1187-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 91715#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 91706#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 91704#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 91702#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 91700#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 91698#L1150 start_simulation_#t~ret20 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 91696#L1200 assume !(0 != start_simulation_~tmp___0~1); 90412#L1168-3 [2018-11-18 15:27:58,092 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:27:58,092 INFO L82 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 2 times [2018-11-18 15:27:58,092 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:27:58,092 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:27:58,093 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:58,093 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:27:58,093 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:58,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:27:58,102 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:27:58,124 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:27:58,124 INFO L82 PathProgramCache]: Analyzing trace with hash -1148625431, now seen corresponding path program 1 times [2018-11-18 15:27:58,125 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:27:58,125 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:27:58,125 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:58,125 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:27:58,125 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:58,130 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:27:58,174 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:27:58,174 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:27:58,174 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:27:58,175 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:27:58,175 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:27:58,175 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:27:58,175 INFO L87 Difference]: Start difference. First operand 5363 states and 7438 transitions. cyclomatic complexity: 2083 Second operand 3 states. [2018-11-18 15:27:58,258 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:27:58,258 INFO L93 Difference]: Finished difference Result 8016 states and 11071 transitions. [2018-11-18 15:27:58,260 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:27:58,260 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8016 states and 11071 transitions. [2018-11-18 15:27:58,290 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7808 [2018-11-18 15:27:58,312 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8016 states to 8016 states and 11071 transitions. [2018-11-18 15:27:58,312 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8016 [2018-11-18 15:27:58,317 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8016 [2018-11-18 15:27:58,317 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8016 states and 11071 transitions. [2018-11-18 15:27:58,322 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:27:58,322 INFO L705 BuchiCegarLoop]: Abstraction has 8016 states and 11071 transitions. [2018-11-18 15:27:58,327 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8016 states and 11071 transitions. [2018-11-18 15:27:58,395 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8016 to 8012. [2018-11-18 15:27:58,396 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8012 states. [2018-11-18 15:27:58,410 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8012 states to 8012 states and 11067 transitions. [2018-11-18 15:27:58,411 INFO L728 BuchiCegarLoop]: Abstraction has 8012 states and 11067 transitions. [2018-11-18 15:27:58,411 INFO L608 BuchiCegarLoop]: Abstraction has 8012 states and 11067 transitions. [2018-11-18 15:27:58,411 INFO L442 BuchiCegarLoop]: ======== Iteration 19============ [2018-11-18 15:27:58,411 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8012 states and 11067 transitions. [2018-11-18 15:27:58,432 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7804 [2018-11-18 15:27:58,433 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:27:58,433 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:27:58,434 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:27:58,434 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:27:58,434 INFO L794 eck$LassoCheckResult]: Stem: 103693#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 103601#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 103602#L1131 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 103995#L519 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 103801#L526 assume 1 == ~m_i~0;~m_st~0 := 0; 103802#L526-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 103554#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 103555#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 103996#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 103787#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 103492#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 103354#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 103355#L561-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 104169#L759 assume !(0 == ~M_E~0); 104174#L759-2 assume !(0 == ~T1_E~0); 103861#L764-1 assume !(0 == ~T2_E~0); 103636#L769-1 assume !(0 == ~T3_E~0); 103318#L774-1 assume !(0 == ~T4_E~0); 103319#L779-1 assume !(0 == ~T5_E~0); 104073#L784-1 assume !(0 == ~T6_E~0); 103840#L789-1 assume !(0 == ~T7_E~0); 103430#L794-1 assume !(0 == ~E_M~0); 103431#L799-1 assume !(0 == ~E_1~0); 104129#L804-1 assume !(0 == ~E_2~0); 103961#L809-1 assume 0 == ~E_3~0;~E_3~0 := 1; 103962#L814-1 assume !(0 == ~E_4~0); 103236#L819-1 assume !(0 == ~E_5~0); 103237#L824-1 assume !(0 == ~E_6~0); 103930#L829-1 assume !(0 == ~E_7~0); 103931#L834-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 104052#L366 assume !(1 == ~m_pc~0); 104053#L366-2 is_master_triggered_~__retres1~0 := 0; 103525#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 103526#L378 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 103637#L945 assume !(0 != activate_threads_~tmp~1); 103638#L945-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 104161#L385 assume !(1 == ~t1_pc~0); 104162#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 103716#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 103717#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 104222#L953 assume !(0 != activate_threads_~tmp___0~0); 104223#L953-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 104251#L404 assume !(1 == ~t2_pc~0); 104252#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 103838#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 103839#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 104038#L961 assume !(0 != activate_threads_~tmp___1~0); 104039#L961-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 103408#L423 assume !(1 == ~t3_pc~0); 103409#L423-2 is_transmit3_triggered_~__retres1~3 := 0; 103980#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 103981#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 103674#L969 assume !(0 != activate_threads_~tmp___2~0); 103675#L969-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 103427#L442 assume !(1 == ~t4_pc~0); 103428#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 103998#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 103999#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 104245#L977 assume !(0 != activate_threads_~tmp___3~0); 104246#L977-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 103618#L461 assume !(1 == ~t5_pc~0); 103619#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 104090#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 104091#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 103965#L985 assume !(0 != activate_threads_~tmp___4~0); 103966#L985-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 103788#L480 assume !(1 == ~t6_pc~0); 103790#L480-2 is_transmit6_triggered_~__retres1~6 := 0; 104213#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 104214#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 103575#L993 assume !(0 != activate_threads_~tmp___5~0); 103576#L993-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 104277#L499 assume !(1 == ~t7_pc~0); 104275#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 104273#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 104271#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 104270#L1001 assume !(0 != activate_threads_~tmp___6~0); 104178#L1001-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 104179#L847 assume !(1 == ~M_E~0); 104173#L847-2 assume !(1 == ~T1_E~0); 103857#L852-1 assume !(1 == ~T2_E~0); 103632#L857-1 assume !(1 == ~T3_E~0); 103633#L862-1 assume !(1 == ~T4_E~0); 104238#L867-1 assume !(1 == ~T5_E~0); 104239#L872-1 assume !(1 == ~T6_E~0); 103756#L877-1 assume !(1 == ~T7_E~0); 103438#L882-1 assume !(1 == ~E_M~0); 103439#L887-1 assume !(1 == ~E_1~0); 104140#L892-1 assume !(1 == ~E_2~0); 103971#L897-1 assume 1 == ~E_3~0;~E_3~0 := 2; 103751#L902-1 assume !(1 == ~E_4~0); 103251#L907-1 assume !(1 == ~E_5~0); 103252#L912-1 assume !(1 == ~E_6~0); 103926#L917-1 assume !(1 == ~E_7~0); 103809#L922-1 assume { :end_inline_reset_delta_events } true; 103810#L1168-3 [2018-11-18 15:27:58,435 INFO L796 eck$LassoCheckResult]: Loop: 103810#L1168-3 assume true; 107135#L1168-1 assume !false; 106898#L1169 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 106896#L734 assume true; 106894#L626-1 assume !false; 106892#L627 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 106872#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 106870#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 106867#L617 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 106864#L631 assume !(0 != eval_~tmp~0); 106865#L749 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 107342#L519-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 107340#L759-3 assume 0 == ~M_E~0;~M_E~0 := 1; 107338#L759-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 107336#L764-3 assume !(0 == ~T2_E~0); 107334#L769-3 assume !(0 == ~T3_E~0); 107332#L774-3 assume !(0 == ~T4_E~0); 107328#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 107326#L784-3 assume !(0 == ~T6_E~0); 107324#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 107322#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 107319#L799-3 assume 0 == ~E_1~0;~E_1~0 := 1; 107317#L804-3 assume !(0 == ~E_2~0); 107314#L809-3 assume 0 == ~E_3~0;~E_3~0 := 1; 107312#L814-3 assume !(0 == ~E_4~0); 107310#L819-3 assume 0 == ~E_5~0;~E_5~0 := 1; 107308#L824-3 assume !(0 == ~E_6~0); 107306#L829-3 assume 0 == ~E_7~0;~E_7~0 := 1; 107304#L834-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 107302#L366-27 assume 1 == ~m_pc~0; 107299#L367-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 107297#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 107295#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 107293#L945-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 107292#L945-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 107291#L385-27 assume !(1 == ~t1_pc~0); 107290#L385-29 is_transmit1_triggered_~__retres1~1 := 0; 107289#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 107288#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 107287#L953-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 107286#L953-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 107285#L404-27 assume 1 == ~t2_pc~0; 107283#L405-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 107280#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 107278#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 107276#L961-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 107274#L961-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 107272#L423-27 assume !(1 == ~t3_pc~0); 107269#L423-29 is_transmit3_triggered_~__retres1~3 := 0; 107267#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 107265#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 107263#L969-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 107261#L969-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 107259#L442-27 assume !(1 == ~t4_pc~0); 107256#L442-29 is_transmit4_triggered_~__retres1~4 := 0; 107254#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 107252#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 107250#L977-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 107248#L977-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 107246#L461-27 assume !(1 == ~t5_pc~0); 107243#L461-29 is_transmit5_triggered_~__retres1~5 := 0; 107241#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 107239#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 107237#L985-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 107235#L985-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 107233#L480-27 assume !(1 == ~t6_pc~0); 107230#L480-29 is_transmit6_triggered_~__retres1~6 := 0; 107228#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 107226#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 107224#L993-27 assume !(0 != activate_threads_~tmp___5~0); 107222#L993-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 107221#L499-27 assume !(1 == ~t7_pc~0); 107219#L499-29 is_transmit7_triggered_~__retres1~7 := 0; 107217#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 107215#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 107214#L1001-27 assume !(0 != activate_threads_~tmp___6~0); 107210#L1001-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 107208#L847-3 assume 1 == ~M_E~0;~M_E~0 := 2; 107206#L847-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 107204#L852-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 107202#L857-3 assume !(1 == ~T3_E~0); 107200#L862-3 assume !(1 == ~T4_E~0); 107198#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 107196#L872-3 assume !(1 == ~T6_E~0); 107194#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 107192#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 107190#L887-3 assume 1 == ~E_1~0;~E_1~0 := 2; 107188#L892-3 assume 1 == ~E_2~0;~E_2~0 := 2; 107185#L897-3 assume 1 == ~E_3~0;~E_3~0 := 2; 107182#L902-3 assume !(1 == ~E_4~0); 107180#L907-3 assume 1 == ~E_5~0;~E_5~0 := 2; 107178#L912-3 assume !(1 == ~E_6~0); 107176#L917-3 assume 1 == ~E_7~0;~E_7~0 := 2; 107174#L922-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 107172#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 107162#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 107160#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 107157#L1187 assume !(0 == start_simulation_~tmp~3); 107153#L1187-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 107151#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 107142#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 107141#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 107140#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 107139#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 107138#L1150 start_simulation_#t~ret20 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 107137#L1200 assume !(0 != start_simulation_~tmp___0~1); 103810#L1168-3 [2018-11-18 15:27:58,435 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:27:58,435 INFO L82 PathProgramCache]: Analyzing trace with hash -1756125947, now seen corresponding path program 1 times [2018-11-18 15:27:58,435 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:27:58,435 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:27:58,436 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:58,436 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:27:58,436 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:58,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:27:58,499 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:27:58,500 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:27:58,500 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 15:27:58,500 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 15:27:58,500 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:27:58,500 INFO L82 PathProgramCache]: Analyzing trace with hash 467876458, now seen corresponding path program 1 times [2018-11-18 15:27:58,500 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:27:58,500 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:27:58,501 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:58,501 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:27:58,501 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:58,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:27:58,554 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:27:58,554 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:27:58,554 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 15:27:58,555 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:27:58,555 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:27:58,555 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:27:58,555 INFO L87 Difference]: Start difference. First operand 8012 states and 11067 transitions. cyclomatic complexity: 3063 Second operand 3 states. [2018-11-18 15:27:58,599 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:27:58,599 INFO L93 Difference]: Finished difference Result 5363 states and 7376 transitions. [2018-11-18 15:27:58,601 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:27:58,602 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5363 states and 7376 transitions. [2018-11-18 15:27:58,619 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5236 [2018-11-18 15:27:58,632 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5363 states to 5363 states and 7376 transitions. [2018-11-18 15:27:58,632 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5363 [2018-11-18 15:27:58,638 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5363 [2018-11-18 15:27:58,638 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5363 states and 7376 transitions. [2018-11-18 15:27:58,641 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:27:58,642 INFO L705 BuchiCegarLoop]: Abstraction has 5363 states and 7376 transitions. [2018-11-18 15:27:58,648 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5363 states and 7376 transitions. [2018-11-18 15:27:58,682 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5363 to 5363. [2018-11-18 15:27:58,682 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5363 states. [2018-11-18 15:27:58,690 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5363 states to 5363 states and 7376 transitions. [2018-11-18 15:27:58,690 INFO L728 BuchiCegarLoop]: Abstraction has 5363 states and 7376 transitions. [2018-11-18 15:27:58,690 INFO L608 BuchiCegarLoop]: Abstraction has 5363 states and 7376 transitions. [2018-11-18 15:27:58,690 INFO L442 BuchiCegarLoop]: ======== Iteration 20============ [2018-11-18 15:27:58,690 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5363 states and 7376 transitions. [2018-11-18 15:27:58,703 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5236 [2018-11-18 15:27:58,703 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:27:58,703 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:27:58,704 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:27:58,704 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:27:58,705 INFO L794 eck$LassoCheckResult]: Stem: 117059#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 116975#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 116976#L1131 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 117334#L519 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 117163#L526 assume 1 == ~m_i~0;~m_st~0 := 0; 117164#L526-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 116931#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 116932#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 117335#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 117149#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 116873#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 116737#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 116738#L561-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 117470#L759 assume !(0 == ~M_E~0); 117474#L759-2 assume !(0 == ~T1_E~0); 117221#L764-1 assume !(0 == ~T2_E~0); 117007#L769-1 assume !(0 == ~T3_E~0); 116702#L774-1 assume !(0 == ~T4_E~0); 116703#L779-1 assume !(0 == ~T5_E~0); 117399#L784-1 assume !(0 == ~T6_E~0); 117202#L789-1 assume !(0 == ~T7_E~0); 116810#L794-1 assume !(0 == ~E_M~0); 116811#L799-1 assume !(0 == ~E_1~0); 117447#L804-1 assume !(0 == ~E_2~0); 117308#L809-1 assume !(0 == ~E_3~0); 117102#L814-1 assume !(0 == ~E_4~0); 116620#L819-1 assume !(0 == ~E_5~0); 116621#L824-1 assume !(0 == ~E_6~0); 117281#L829-1 assume !(0 == ~E_7~0); 117175#L834-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 117176#L366 assume !(1 == ~m_pc~0); 117272#L366-2 is_master_triggered_~__retres1~0 := 0; 116901#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 116685#L378 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 116686#L945 assume !(0 != activate_threads_~tmp~1); 117008#L945-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 117009#L385 assume !(1 == ~t1_pc~0); 117465#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 117080#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 116852#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 116853#L953 assume !(0 != activate_threads_~tmp___0~0); 117517#L953-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 117518#L404 assume !(1 == ~t2_pc~0); 117525#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 117201#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 117165#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 117166#L961 assume !(0 != activate_threads_~tmp___1~0); 117373#L961-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 116790#L423 assume !(1 == ~t3_pc~0); 116791#L423-2 is_transmit3_triggered_~__retres1~3 := 0; 116797#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 117292#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 117043#L969 assume !(0 != activate_threads_~tmp___2~0); 117044#L969-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 116808#L442 assume !(1 == ~t4_pc~0); 116799#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 116800#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 117337#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 117392#L977 assume !(0 != activate_threads_~tmp___3~0); 117531#L977-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 116990#L461 assume !(1 == ~t5_pc~0); 116991#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 116993#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 117411#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 117311#L985 assume !(0 != activate_threads_~tmp___4~0); 117312#L985-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 117150#L480 assume !(1 == ~t6_pc~0); 117137#L480-2 is_transmit6_triggered_~__retres1~6 := 0; 117138#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 117509#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 116954#L993 assume !(0 != activate_threads_~tmp___5~0); 116955#L993-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 116957#L499 assume !(1 == ~t7_pc~0); 117265#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 116676#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 116616#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 116617#L1001 assume !(0 != activate_threads_~tmp___6~0); 117477#L1001-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 117478#L847 assume !(1 == ~M_E~0); 117473#L847-2 assume !(1 == ~T1_E~0); 117217#L852-1 assume !(1 == ~T2_E~0); 117004#L857-1 assume !(1 == ~T3_E~0); 116698#L862-1 assume !(1 == ~T4_E~0); 116699#L867-1 assume !(1 == ~T5_E~0); 117396#L872-1 assume !(1 == ~T6_E~0); 117118#L877-1 assume !(1 == ~T7_E~0); 116819#L882-1 assume !(1 == ~E_M~0); 116820#L887-1 assume !(1 == ~E_1~0); 117454#L892-1 assume !(1 == ~E_2~0); 117315#L897-1 assume !(1 == ~E_3~0); 117113#L902-1 assume !(1 == ~E_4~0); 116635#L907-1 assume !(1 == ~E_5~0); 116636#L912-1 assume !(1 == ~E_6~0); 117278#L917-1 assume !(1 == ~E_7~0); 117172#L922-1 assume { :end_inline_reset_delta_events } true; 117173#L1168-3 [2018-11-18 15:27:58,705 INFO L796 eck$LassoCheckResult]: Loop: 117173#L1168-3 assume true; 118997#L1168-1 assume !false; 118741#L1169 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 118739#L734 assume true; 118738#L626-1 assume !false; 118737#L627 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 118724#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 118722#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 118720#L617 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 118718#L631 assume !(0 != eval_~tmp~0); 117038#L749 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 117039#L519-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 117336#L759-3 assume 0 == ~M_E~0;~M_E~0 := 1; 117466#L759-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 117210#L764-3 assume !(0 == ~T2_E~0); 117000#L769-3 assume !(0 == ~T3_E~0); 116687#L774-3 assume !(0 == ~T4_E~0); 116688#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 121736#L784-3 assume !(0 == ~T6_E~0); 121735#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 121734#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 121733#L799-3 assume 0 == ~E_1~0;~E_1~0 := 1; 121732#L804-3 assume !(0 == ~E_2~0); 121731#L809-3 assume !(0 == ~E_3~0); 121730#L814-3 assume !(0 == ~E_4~0); 121729#L819-3 assume 0 == ~E_5~0;~E_5~0 := 1; 121728#L824-3 assume !(0 == ~E_6~0); 121727#L829-3 assume 0 == ~E_7~0;~E_7~0 := 1; 121726#L834-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 121725#L366-27 assume 1 == ~m_pc~0; 121723#L367-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 121722#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 121721#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 121720#L945-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 121719#L945-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 117368#L385-27 assume !(1 == ~t1_pc~0); 117369#L385-29 is_transmit1_triggered_~__retres1~1 := 0; 121972#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 121971#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 121970#L953-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 121969#L953-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 121968#L404-27 assume !(1 == ~t2_pc~0); 121967#L404-29 is_transmit2_triggered_~__retres1~2 := 0; 121965#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 121964#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 121958#L961-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 121957#L961-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 121956#L423-27 assume !(1 == ~t3_pc~0); 121955#L423-29 is_transmit3_triggered_~__retres1~3 := 0; 121954#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 121953#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 121952#L969-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 121951#L969-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 121859#L442-27 assume !(1 == ~t4_pc~0); 121857#L442-29 is_transmit4_triggered_~__retres1~4 := 0; 117402#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 117378#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 117379#L977-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 117420#L977-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 117092#L461-27 assume !(1 == ~t5_pc~0); 117093#L461-29 is_transmit5_triggered_~__retres1~5 := 0; 117096#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 117410#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 117158#L985-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 117159#L985-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 117160#L480-27 assume !(1 == ~t6_pc~0); 117185#L480-29 is_transmit6_triggered_~__retres1~6 := 0; 117199#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 117488#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 116896#L993-27 assume !(0 != activate_threads_~tmp___5~0); 116876#L993-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 116877#L499-27 assume 1 == ~t7_pc~0; 117211#L500-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 117319#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 121960#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 121959#L1001-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 117455#L1001-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 117457#L847-3 assume 1 == ~M_E~0;~M_E~0 := 2; 117475#L847-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 117219#L852-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 117006#L857-3 assume !(1 == ~T3_E~0); 116700#L862-3 assume !(1 == ~T4_E~0); 116701#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 117397#L872-3 assume !(1 == ~T6_E~0); 117398#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 121745#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 117512#L887-3 assume 1 == ~E_1~0;~E_1~0 := 2; 117446#L892-3 assume 1 == ~E_2~0;~E_2~0 := 2; 117305#L897-3 assume !(1 == ~E_3~0); 117099#L902-3 assume !(1 == ~E_4~0); 116618#L907-3 assume 1 == ~E_5~0;~E_5~0 := 2; 116619#L912-3 assume !(1 == ~E_6~0); 117419#L917-3 assume 1 == ~E_7~0;~E_7~0 := 2; 121718#L922-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 119042#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 119033#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 119031#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 119028#L1187 assume !(0 == start_simulation_~tmp~3); 119025#L1187-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 119021#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 119012#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 119010#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 119008#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 119005#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 119003#L1150 start_simulation_#t~ret20 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 119000#L1200 assume !(0 != start_simulation_~tmp___0~1); 117173#L1168-3 [2018-11-18 15:27:58,705 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:27:58,705 INFO L82 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 3 times [2018-11-18 15:27:58,705 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:27:58,705 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:27:58,706 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:58,706 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:27:58,706 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:58,712 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:27:58,718 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:27:58,743 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:27:58,743 INFO L82 PathProgramCache]: Analyzing trace with hash -1576818200, now seen corresponding path program 1 times [2018-11-18 15:27:58,743 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:27:58,743 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:27:58,744 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:58,744 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:27:58,744 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:58,749 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:27:58,789 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:27:58,790 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:27:58,790 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 15:27:58,790 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:27:58,790 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 15:27:58,790 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:27:58,790 INFO L87 Difference]: Start difference. First operand 5363 states and 7376 transitions. cyclomatic complexity: 2021 Second operand 5 states. [2018-11-18 15:27:58,883 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:27:58,883 INFO L93 Difference]: Finished difference Result 9803 states and 13348 transitions. [2018-11-18 15:27:58,884 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-18 15:27:58,885 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9803 states and 13348 transitions. [2018-11-18 15:27:58,909 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 9652 [2018-11-18 15:27:58,928 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9803 states to 9803 states and 13348 transitions. [2018-11-18 15:27:58,928 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9803 [2018-11-18 15:27:58,933 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9803 [2018-11-18 15:27:58,933 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9803 states and 13348 transitions. [2018-11-18 15:27:58,939 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:27:58,939 INFO L705 BuchiCegarLoop]: Abstraction has 9803 states and 13348 transitions. [2018-11-18 15:27:58,944 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9803 states and 13348 transitions. [2018-11-18 15:27:58,981 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9803 to 5387. [2018-11-18 15:27:58,981 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5387 states. [2018-11-18 15:27:58,988 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5387 states to 5387 states and 7400 transitions. [2018-11-18 15:27:58,988 INFO L728 BuchiCegarLoop]: Abstraction has 5387 states and 7400 transitions. [2018-11-18 15:27:58,988 INFO L608 BuchiCegarLoop]: Abstraction has 5387 states and 7400 transitions. [2018-11-18 15:27:58,988 INFO L442 BuchiCegarLoop]: ======== Iteration 21============ [2018-11-18 15:27:58,988 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5387 states and 7400 transitions. [2018-11-18 15:27:59,000 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5260 [2018-11-18 15:27:59,000 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:27:59,000 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:27:59,002 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:27:59,002 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:27:59,002 INFO L794 eck$LassoCheckResult]: Stem: 132254#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 132164#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 132165#L1131 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 132522#L519 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 132349#L526 assume 1 == ~m_i~0;~m_st~0 := 0; 132350#L526-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 132116#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 132117#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 132523#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 132337#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 132059#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 131919#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 131920#L561-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 132653#L759 assume !(0 == ~M_E~0); 132657#L759-2 assume !(0 == ~T1_E~0); 132404#L764-1 assume !(0 == ~T2_E~0); 132199#L769-1 assume !(0 == ~T3_E~0); 131884#L774-1 assume !(0 == ~T4_E~0); 131885#L779-1 assume !(0 == ~T5_E~0); 132584#L784-1 assume !(0 == ~T6_E~0); 132386#L789-1 assume !(0 == ~T7_E~0); 131996#L794-1 assume !(0 == ~E_M~0); 131997#L799-1 assume !(0 == ~E_1~0); 132631#L804-1 assume !(0 == ~E_2~0); 132495#L809-1 assume !(0 == ~E_3~0); 132289#L814-1 assume !(0 == ~E_4~0); 131802#L819-1 assume !(0 == ~E_5~0); 131803#L824-1 assume !(0 == ~E_6~0); 132467#L829-1 assume !(0 == ~E_7~0); 132360#L834-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 132361#L366 assume !(1 == ~m_pc~0); 132458#L366-2 is_master_triggered_~__retres1~0 := 0; 132087#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 131865#L378 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 131866#L945 assume !(0 != activate_threads_~tmp~1); 132200#L945-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 132201#L385 assume !(1 == ~t1_pc~0); 132649#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 132274#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 132038#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 132039#L953 assume !(0 != activate_threads_~tmp___0~0); 132699#L953-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 132700#L404 assume !(1 == ~t2_pc~0); 132706#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 132385#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 132351#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 132352#L961 assume !(0 != activate_threads_~tmp___1~0); 132558#L961-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 131977#L423 assume !(1 == ~t3_pc~0); 131978#L423-2 is_transmit3_triggered_~__retres1~3 := 0; 131983#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 132479#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 132237#L969 assume !(0 != activate_threads_~tmp___2~0); 132238#L969-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 131994#L442 assume !(1 == ~t4_pc~0); 131985#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 131986#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 132525#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 132577#L977 assume !(0 != activate_threads_~tmp___3~0); 132712#L977-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 132180#L461 assume !(1 == ~t5_pc~0); 132181#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 132183#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 132596#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 132498#L985 assume !(0 != activate_threads_~tmp___4~0); 132499#L985-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 132338#L480 assume !(1 == ~t6_pc~0); 132325#L480-2 is_transmit6_triggered_~__retres1~6 := 0; 132326#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 132690#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 132140#L993 assume !(0 != activate_threads_~tmp___5~0); 132141#L993-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 132143#L499 assume !(1 == ~t7_pc~0); 132450#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 132454#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 132717#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 132660#L1001 assume !(0 != activate_threads_~tmp___6~0); 132661#L1001-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 132662#L847 assume !(1 == ~M_E~0); 132656#L847-2 assume !(1 == ~T1_E~0); 132401#L852-1 assume !(1 == ~T2_E~0); 132195#L857-1 assume !(1 == ~T3_E~0); 131880#L862-1 assume !(1 == ~T4_E~0); 131881#L867-1 assume !(1 == ~T5_E~0); 132581#L872-1 assume !(1 == ~T6_E~0); 132305#L877-1 assume !(1 == ~T7_E~0); 132005#L882-1 assume !(1 == ~E_M~0); 132006#L887-1 assume !(1 == ~E_1~0); 132635#L892-1 assume !(1 == ~E_2~0); 132502#L897-1 assume !(1 == ~E_3~0); 132301#L902-1 assume !(1 == ~E_4~0); 131817#L907-1 assume !(1 == ~E_5~0); 131818#L912-1 assume !(1 == ~E_6~0); 132464#L917-1 assume !(1 == ~E_7~0); 132357#L922-1 assume { :end_inline_reset_delta_events } true; 132358#L1168-3 [2018-11-18 15:27:59,002 INFO L796 eck$LassoCheckResult]: Loop: 132358#L1168-3 assume true; 134588#L1168-1 assume !false; 134343#L1169 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 134341#L734 assume true; 134339#L626-1 assume !false; 134172#L627 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 134154#L574 assume !(0 == ~m_st~0); 134156#L578 assume !(0 == ~t1_st~0); 134160#L582 assume !(0 == ~t2_st~0); 134162#L586 assume !(0 == ~t3_st~0); 134158#L590 assume !(0 == ~t4_st~0); 134159#L594 assume !(0 == ~t5_st~0); 134161#L598 assume !(0 == ~t6_st~0); 134157#L602 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8 := 0; 134151#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 134148#L617 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 134149#L631 assume !(0 != eval_~tmp~0); 132231#L749 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 132232#L519-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 132524#L759-3 assume 0 == ~M_E~0;~M_E~0 := 1; 132650#L759-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 132392#L764-3 assume !(0 == ~T2_E~0); 132190#L769-3 assume !(0 == ~T3_E~0); 131869#L774-3 assume !(0 == ~T4_E~0); 131870#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 132579#L784-3 assume !(0 == ~T6_E~0); 132390#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 132001#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 132002#L799-3 assume 0 == ~E_1~0;~E_1~0 := 1; 132632#L804-3 assume !(0 == ~E_2~0); 132496#L809-3 assume !(0 == ~E_3~0); 132290#L814-3 assume !(0 == ~E_4~0); 132291#L819-3 assume 0 == ~E_5~0;~E_5~0 := 1; 134700#L824-3 assume !(0 == ~E_6~0); 134699#L829-3 assume 0 == ~E_7~0;~E_7~0 := 1; 134698#L834-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 134697#L366-27 assume 1 == ~m_pc~0; 134695#L367-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 134694#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 134693#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 134692#L945-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 134691#L945-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 134690#L385-27 assume !(1 == ~t1_pc~0); 134689#L385-29 is_transmit1_triggered_~__retres1~1 := 0; 134688#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 134687#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 134686#L953-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 134685#L953-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 134684#L404-27 assume 1 == ~t2_pc~0; 134682#L405-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 134681#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 134680#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 134679#L961-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 134678#L961-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 134677#L423-27 assume !(1 == ~t3_pc~0); 134676#L423-29 is_transmit3_triggered_~__retres1~3 := 0; 134675#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 134674#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 134673#L969-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 134672#L969-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 134671#L442-27 assume !(1 == ~t4_pc~0); 134669#L442-29 is_transmit4_triggered_~__retres1~4 := 0; 134668#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 134667#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 134666#L977-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 134665#L977-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 134664#L461-27 assume !(1 == ~t5_pc~0); 134663#L461-29 is_transmit5_triggered_~__retres1~5 := 0; 134662#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 134661#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 134660#L985-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 134659#L985-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 134658#L480-27 assume !(1 == ~t6_pc~0); 134656#L480-29 is_transmit6_triggered_~__retres1~6 := 0; 134655#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 134654#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 134653#L993-27 assume !(0 != activate_threads_~tmp___5~0); 134652#L993-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 134651#L499-27 assume !(1 == ~t7_pc~0); 134650#L499-29 is_transmit7_triggered_~__retres1~7 := 0; 134648#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 134646#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 134644#L1001-27 assume !(0 != activate_threads_~tmp___6~0); 134642#L1001-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 134641#L847-3 assume 1 == ~M_E~0;~M_E~0 := 2; 134640#L847-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 134639#L852-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 134638#L857-3 assume !(1 == ~T3_E~0); 134637#L862-3 assume !(1 == ~T4_E~0); 134636#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 134635#L872-3 assume !(1 == ~T6_E~0); 134634#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 134633#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 134632#L887-3 assume 1 == ~E_1~0;~E_1~0 := 2; 134631#L892-3 assume 1 == ~E_2~0;~E_2~0 := 2; 134630#L897-3 assume !(1 == ~E_3~0); 134629#L902-3 assume !(1 == ~E_4~0); 134628#L907-3 assume 1 == ~E_5~0;~E_5~0 := 2; 134627#L912-3 assume !(1 == ~E_6~0); 134626#L917-3 assume 1 == ~E_7~0;~E_7~0 := 2; 134625#L922-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 134624#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 134615#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 134613#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 134609#L1187 assume !(0 == start_simulation_~tmp~3); 134606#L1187-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 134605#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 134596#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 134595#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 134594#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 134593#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 134592#L1150 start_simulation_#t~ret20 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 134591#L1200 assume !(0 != start_simulation_~tmp___0~1); 132358#L1168-3 [2018-11-18 15:27:59,002 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:27:59,003 INFO L82 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 4 times [2018-11-18 15:27:59,003 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:27:59,003 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:27:59,004 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:59,004 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:27:59,004 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:59,009 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:27:59,015 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:27:59,036 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:27:59,036 INFO L82 PathProgramCache]: Analyzing trace with hash -2060497684, now seen corresponding path program 1 times [2018-11-18 15:27:59,036 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:27:59,036 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:27:59,037 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:59,037 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:27:59,037 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:59,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:27:59,101 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:27:59,101 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:27:59,102 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 15:27:59,102 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:27:59,102 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 15:27:59,102 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:27:59,102 INFO L87 Difference]: Start difference. First operand 5387 states and 7400 transitions. cyclomatic complexity: 2021 Second operand 5 states. [2018-11-18 15:27:59,249 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:27:59,249 INFO L93 Difference]: Finished difference Result 10383 states and 14161 transitions. [2018-11-18 15:27:59,249 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 15:27:59,249 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10383 states and 14161 transitions. [2018-11-18 15:27:59,274 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10240 [2018-11-18 15:27:59,292 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10383 states to 10383 states and 14161 transitions. [2018-11-18 15:27:59,292 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10383 [2018-11-18 15:27:59,297 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10383 [2018-11-18 15:27:59,297 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10383 states and 14161 transitions. [2018-11-18 15:27:59,303 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:27:59,303 INFO L705 BuchiCegarLoop]: Abstraction has 10383 states and 14161 transitions. [2018-11-18 15:27:59,309 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10383 states and 14161 transitions. [2018-11-18 15:27:59,344 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10383 to 5495. [2018-11-18 15:27:59,344 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5495 states. [2018-11-18 15:27:59,350 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5495 states to 5495 states and 7475 transitions. [2018-11-18 15:27:59,350 INFO L728 BuchiCegarLoop]: Abstraction has 5495 states and 7475 transitions. [2018-11-18 15:27:59,350 INFO L608 BuchiCegarLoop]: Abstraction has 5495 states and 7475 transitions. [2018-11-18 15:27:59,351 INFO L442 BuchiCegarLoop]: ======== Iteration 22============ [2018-11-18 15:27:59,351 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5495 states and 7475 transitions. [2018-11-18 15:27:59,362 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5368 [2018-11-18 15:27:59,362 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:27:59,362 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:27:59,363 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:27:59,364 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:27:59,364 INFO L794 eck$LassoCheckResult]: Stem: 148034#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 147944#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 147945#L1131 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 148320#L519 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 148140#L526 assume 1 == ~m_i~0;~m_st~0 := 0; 148141#L526-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 147897#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 147898#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 148321#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 148128#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 147838#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 147703#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 147704#L561-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 148479#L759 assume !(0 == ~M_E~0); 148483#L759-2 assume !(0 == ~T1_E~0); 148195#L764-1 assume !(0 == ~T2_E~0); 147977#L769-1 assume !(0 == ~T3_E~0); 147668#L774-1 assume !(0 == ~T4_E~0); 147669#L779-1 assume !(0 == ~T5_E~0); 148388#L784-1 assume !(0 == ~T6_E~0); 148179#L789-1 assume !(0 == ~T7_E~0); 147776#L794-1 assume !(0 == ~E_M~0); 147777#L799-1 assume !(0 == ~E_1~0); 148441#L804-1 assume !(0 == ~E_2~0); 148294#L809-1 assume !(0 == ~E_3~0); 148075#L814-1 assume !(0 == ~E_4~0); 147586#L819-1 assume !(0 == ~E_5~0); 147587#L824-1 assume !(0 == ~E_6~0); 148265#L829-1 assume !(0 == ~E_7~0); 148152#L834-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 148153#L366 assume !(1 == ~m_pc~0); 148255#L366-2 is_master_triggered_~__retres1~0 := 0; 147867#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 147649#L378 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 147650#L945 assume !(0 != activate_threads_~tmp~1); 147978#L945-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 147979#L385 assume !(1 == ~t1_pc~0); 148473#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 148054#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 147817#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 147818#L953 assume !(0 != activate_threads_~tmp___0~0); 148527#L953-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 148528#L404 assume !(1 == ~t2_pc~0); 148534#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 148178#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 148142#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 148143#L961 assume !(0 != activate_threads_~tmp___1~0); 148362#L961-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 147757#L423 assume !(1 == ~t3_pc~0); 147758#L423-2 is_transmit3_triggered_~__retres1~3 := 0; 147763#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 148276#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 148016#L969 assume !(0 != activate_threads_~tmp___2~0); 148017#L969-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 147774#L442 assume !(1 == ~t4_pc~0); 147765#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 147766#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 148323#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 148382#L977 assume !(0 != activate_threads_~tmp___3~0); 148538#L977-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 147960#L461 assume !(1 == ~t5_pc~0); 147961#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 147963#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 148401#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 148297#L985 assume !(0 != activate_threads_~tmp___4~0); 148298#L985-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 148129#L480 assume !(1 == ~t6_pc~0); 148114#L480-2 is_transmit6_triggered_~__retres1~6 := 0; 148115#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 148520#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 147921#L993 assume !(0 != activate_threads_~tmp___5~0); 147922#L993-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 147924#L499 assume !(1 == ~t7_pc~0); 148246#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 148250#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 148540#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 148485#L1001 assume !(0 != activate_threads_~tmp___6~0); 148486#L1001-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 148487#L847 assume !(1 == ~M_E~0); 148482#L847-2 assume !(1 == ~T1_E~0); 148193#L852-1 assume !(1 == ~T2_E~0); 147974#L857-1 assume !(1 == ~T3_E~0); 147664#L862-1 assume !(1 == ~T4_E~0); 147665#L867-1 assume !(1 == ~T5_E~0); 148386#L872-1 assume !(1 == ~T6_E~0); 148094#L877-1 assume !(1 == ~T7_E~0); 147784#L882-1 assume !(1 == ~E_M~0); 147785#L887-1 assume !(1 == ~E_1~0); 148447#L892-1 assume !(1 == ~E_2~0); 148301#L897-1 assume !(1 == ~E_3~0); 148090#L902-1 assume !(1 == ~E_4~0); 147601#L907-1 assume !(1 == ~E_5~0); 147602#L912-1 assume !(1 == ~E_6~0); 148262#L917-1 assume !(1 == ~E_7~0); 148149#L922-1 assume { :end_inline_reset_delta_events } true; 148150#L1168-3 [2018-11-18 15:27:59,364 INFO L796 eck$LassoCheckResult]: Loop: 148150#L1168-3 assume true; 150261#L1168-1 assume !false; 150256#L1169 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 150255#L734 assume true; 150254#L626-1 assume !false; 150253#L627 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 150244#L574 assume !(0 == ~m_st~0); 150245#L578 assume !(0 == ~t1_st~0); 150250#L582 assume !(0 == ~t2_st~0); 150252#L586 assume !(0 == ~t3_st~0); 150248#L590 assume !(0 == ~t4_st~0); 150249#L594 assume !(0 == ~t5_st~0); 150251#L598 assume !(0 == ~t6_st~0); 150246#L602 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8 := 0; 150247#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 150108#L617 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 150109#L631 assume !(0 != eval_~tmp~0); 150640#L749 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 150639#L519-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 150638#L759-3 assume 0 == ~M_E~0;~M_E~0 := 1; 150637#L759-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 150636#L764-3 assume !(0 == ~T2_E~0); 150635#L769-3 assume !(0 == ~T3_E~0); 150634#L774-3 assume !(0 == ~T4_E~0); 150633#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 150632#L784-3 assume !(0 == ~T6_E~0); 150631#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 150630#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 150629#L799-3 assume 0 == ~E_1~0;~E_1~0 := 1; 150628#L804-3 assume !(0 == ~E_2~0); 150627#L809-3 assume !(0 == ~E_3~0); 150626#L814-3 assume !(0 == ~E_4~0); 150625#L819-3 assume 0 == ~E_5~0;~E_5~0 := 1; 150624#L824-3 assume !(0 == ~E_6~0); 150623#L829-3 assume 0 == ~E_7~0;~E_7~0 := 1; 150622#L834-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 150621#L366-27 assume 1 == ~m_pc~0; 150619#L367-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 150618#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 150617#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 150616#L945-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 150615#L945-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 150614#L385-27 assume !(1 == ~t1_pc~0); 150613#L385-29 is_transmit1_triggered_~__retres1~1 := 0; 150611#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 150608#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 150606#L953-27 assume !(0 != activate_threads_~tmp___0~0); 150604#L953-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 150602#L404-27 assume 1 == ~t2_pc~0; 150599#L405-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 150597#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 150595#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 150593#L961-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 150591#L961-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 150589#L423-27 assume !(1 == ~t3_pc~0); 150587#L423-29 is_transmit3_triggered_~__retres1~3 := 0; 150585#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 150582#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 150580#L969-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 150578#L969-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 150576#L442-27 assume !(1 == ~t4_pc~0); 150573#L442-29 is_transmit4_triggered_~__retres1~4 := 0; 150571#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 150569#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 150567#L977-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 150565#L977-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 150563#L461-27 assume !(1 == ~t5_pc~0); 150561#L461-29 is_transmit5_triggered_~__retres1~5 := 0; 150558#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 150556#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 150553#L985-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 150549#L985-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 150546#L480-27 assume !(1 == ~t6_pc~0); 150542#L480-29 is_transmit6_triggered_~__retres1~6 := 0; 150539#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 150536#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 150533#L993-27 assume !(0 != activate_threads_~tmp___5~0); 150530#L993-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 150527#L499-27 assume 1 == ~t7_pc~0; 150523#L500-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 150518#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 150514#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 150510#L1001-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 150506#L1001-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 150503#L847-3 assume 1 == ~M_E~0;~M_E~0 := 2; 150500#L847-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 150497#L852-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 150493#L857-3 assume !(1 == ~T3_E~0); 150489#L862-3 assume !(1 == ~T4_E~0); 150485#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 150481#L872-3 assume !(1 == ~T6_E~0); 150478#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 150475#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 150472#L887-3 assume 1 == ~E_1~0;~E_1~0 := 2; 150468#L892-3 assume 1 == ~E_2~0;~E_2~0 := 2; 150465#L897-3 assume !(1 == ~E_3~0); 150462#L902-3 assume !(1 == ~E_4~0); 150459#L907-3 assume 1 == ~E_5~0;~E_5~0 := 2; 150456#L912-3 assume !(1 == ~E_6~0); 150453#L917-3 assume 1 == ~E_7~0;~E_7~0 := 2; 150449#L922-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 150442#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 150431#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 150427#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 150422#L1187 assume !(0 == start_simulation_~tmp~3); 150416#L1187-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 150316#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 150303#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 150295#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 150290#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 150284#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 150278#L1150 start_simulation_#t~ret20 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 150272#L1200 assume !(0 != start_simulation_~tmp___0~1); 148150#L1168-3 [2018-11-18 15:27:59,364 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:27:59,365 INFO L82 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 5 times [2018-11-18 15:27:59,365 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:27:59,365 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:27:59,365 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:59,365 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:27:59,365 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:59,371 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:27:59,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:27:59,395 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:27:59,395 INFO L82 PathProgramCache]: Analyzing trace with hash -734733077, now seen corresponding path program 1 times [2018-11-18 15:27:59,395 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:27:59,395 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:27:59,396 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:59,396 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:27:59,396 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:59,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:27:59,470 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:27:59,470 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:27:59,470 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 15:27:59,470 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:27:59,470 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 15:27:59,470 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:27:59,471 INFO L87 Difference]: Start difference. First operand 5495 states and 7475 transitions. cyclomatic complexity: 1988 Second operand 5 states. [2018-11-18 15:27:59,625 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:27:59,625 INFO L93 Difference]: Finished difference Result 7291 states and 9921 transitions. [2018-11-18 15:27:59,627 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 15:27:59,627 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7291 states and 9921 transitions. [2018-11-18 15:27:59,642 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7148 [2018-11-18 15:27:59,652 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7291 states to 7291 states and 9921 transitions. [2018-11-18 15:27:59,652 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7291 [2018-11-18 15:27:59,655 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7291 [2018-11-18 15:27:59,655 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7291 states and 9921 transitions. [2018-11-18 15:27:59,658 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:27:59,659 INFO L705 BuchiCegarLoop]: Abstraction has 7291 states and 9921 transitions. [2018-11-18 15:27:59,662 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7291 states and 9921 transitions. [2018-11-18 15:27:59,689 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7291 to 5507. [2018-11-18 15:27:59,689 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5507 states. [2018-11-18 15:27:59,695 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5507 states to 5507 states and 7422 transitions. [2018-11-18 15:27:59,695 INFO L728 BuchiCegarLoop]: Abstraction has 5507 states and 7422 transitions. [2018-11-18 15:27:59,695 INFO L608 BuchiCegarLoop]: Abstraction has 5507 states and 7422 transitions. [2018-11-18 15:27:59,696 INFO L442 BuchiCegarLoop]: ======== Iteration 23============ [2018-11-18 15:27:59,696 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5507 states and 7422 transitions. [2018-11-18 15:27:59,707 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5380 [2018-11-18 15:27:59,707 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:27:59,707 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:27:59,708 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:27:59,708 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:27:59,709 INFO L794 eck$LassoCheckResult]: Stem: 160845#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 160755#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 160756#L1131 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 161152#L519 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 160951#L526 assume 1 == ~m_i~0;~m_st~0 := 0; 160952#L526-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 160703#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 160704#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 161153#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 160937#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 160645#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 160503#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 160504#L561-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 161338#L759 assume !(0 == ~M_E~0); 161343#L759-2 assume !(0 == ~T1_E~0); 161010#L764-1 assume !(0 == ~T2_E~0); 160789#L769-1 assume !(0 == ~T3_E~0); 160468#L774-1 assume !(0 == ~T4_E~0); 160469#L779-1 assume !(0 == ~T5_E~0); 161230#L784-1 assume !(0 == ~T6_E~0); 160992#L789-1 assume !(0 == ~T7_E~0); 160582#L794-1 assume !(0 == ~E_M~0); 160583#L799-1 assume !(0 == ~E_1~0); 161297#L804-1 assume !(0 == ~E_2~0); 161118#L809-1 assume !(0 == ~E_3~0); 160885#L814-1 assume !(0 == ~E_4~0); 160386#L819-1 assume !(0 == ~E_5~0); 160387#L824-1 assume !(0 == ~E_6~0); 161082#L829-1 assume !(0 == ~E_7~0); 160963#L834-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 160964#L366 assume !(1 == ~m_pc~0); 161071#L366-2 is_master_triggered_~__retres1~0 := 0; 160673#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 160449#L378 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 160450#L945 assume !(0 != activate_threads_~tmp~1); 160790#L945-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 160791#L385 assume !(1 == ~t1_pc~0); 161328#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 160866#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 160624#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 160625#L953 assume !(0 != activate_threads_~tmp___0~0); 161389#L953-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 161390#L404 assume !(1 == ~t2_pc~0); 161402#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 160991#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 160953#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 160954#L961 assume !(0 != activate_threads_~tmp___1~0); 161199#L961-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 160562#L423 assume !(1 == ~t3_pc~0); 160563#L423-2 is_transmit3_triggered_~__retres1~3 := 0; 160569#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 161097#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 160827#L969 assume !(0 != activate_threads_~tmp___2~0); 160828#L969-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 160580#L442 assume !(1 == ~t4_pc~0); 160571#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 160572#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 161155#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 161224#L977 assume !(0 != activate_threads_~tmp___3~0); 161411#L977-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 160773#L461 assume !(1 == ~t5_pc~0); 160774#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 160776#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 161252#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 161121#L985 assume !(0 != activate_threads_~tmp___4~0); 161122#L985-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 160938#L480 assume !(1 == ~t6_pc~0); 160925#L480-2 is_transmit6_triggered_~__retres1~6 := 0; 160926#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 161381#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 160732#L993 assume !(0 != activate_threads_~tmp___5~0); 160733#L993-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 160736#L499 assume !(1 == ~t7_pc~0); 161062#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 160442#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 160382#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 160383#L1001 assume !(0 != activate_threads_~tmp___6~0); 161346#L1001-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 161347#L847 assume !(1 == ~M_E~0); 161342#L847-2 assume !(1 == ~T1_E~0); 161007#L852-1 assume !(1 == ~T2_E~0); 160786#L857-1 assume !(1 == ~T3_E~0); 160464#L862-1 assume !(1 == ~T4_E~0); 160465#L867-1 assume !(1 == ~T5_E~0); 161228#L872-1 assume !(1 == ~T6_E~0); 160904#L877-1 assume !(1 == ~T7_E~0); 160591#L882-1 assume !(1 == ~E_M~0); 160592#L887-1 assume !(1 == ~E_1~0); 161307#L892-1 assume !(1 == ~E_2~0); 161126#L897-1 assume !(1 == ~E_3~0); 160900#L902-1 assume !(1 == ~E_4~0); 160401#L907-1 assume !(1 == ~E_5~0); 160402#L912-1 assume !(1 == ~E_6~0); 161079#L917-1 assume !(1 == ~E_7~0); 160959#L922-1 assume { :end_inline_reset_delta_events } true; 160960#L1168-3 [2018-11-18 15:27:59,709 INFO L796 eck$LassoCheckResult]: Loop: 160960#L1168-3 assume true; 163909#L1168-1 assume !false; 163904#L1169 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 163903#L734 assume true; 163902#L626-1 assume !false; 163901#L627 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 163892#L574 assume !(0 == ~m_st~0); 163893#L578 assume !(0 == ~t1_st~0); 163898#L582 assume !(0 == ~t2_st~0); 163900#L586 assume !(0 == ~t3_st~0); 163896#L590 assume !(0 == ~t4_st~0); 163897#L594 assume !(0 == ~t5_st~0); 163899#L598 assume !(0 == ~t6_st~0); 163894#L602 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8 := 0; 163895#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 163872#L617 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 163873#L631 assume !(0 != eval_~tmp~0); 165869#L749 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 165867#L519-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 165866#L759-3 assume 0 == ~M_E~0;~M_E~0 := 1; 165865#L759-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 165864#L764-3 assume !(0 == ~T2_E~0); 165861#L769-3 assume !(0 == ~T3_E~0); 165860#L774-3 assume !(0 == ~T4_E~0); 165859#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 165858#L784-3 assume !(0 == ~T6_E~0); 165857#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 165856#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 165854#L799-3 assume 0 == ~E_1~0;~E_1~0 := 1; 161299#L804-3 assume !(0 == ~E_2~0); 161119#L809-3 assume !(0 == ~E_3~0); 160886#L814-3 assume !(0 == ~E_4~0); 160388#L819-3 assume 0 == ~E_5~0;~E_5~0 := 1; 160389#L824-3 assume !(0 == ~E_6~0); 165352#L829-3 assume 0 == ~E_7~0;~E_7~0 := 1; 160965#L834-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 160966#L366-27 assume 1 == ~m_pc~0; 161036#L367-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 160669#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 160413#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 160414#L945-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 160751#L945-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 160889#L385-27 assume !(1 == ~t1_pc~0); 164729#L385-29 is_transmit1_triggered_~__retres1~1 := 0; 165284#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 165283#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 165282#L953-27 assume !(0 != activate_threads_~tmp___0~0); 165281#L953-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 165280#L404-27 assume !(1 == ~t2_pc~0); 161274#L404-29 is_transmit2_triggered_~__retres1~2 := 0; 160980#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 160800#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 160801#L961-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 161013#L961-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 160499#L423-27 assume !(1 == ~t3_pc~0); 160500#L423-29 is_transmit3_triggered_~__retres1~3 := 0; 160507#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 161096#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 160597#L969-27 assume !(0 != activate_threads_~tmp___2~0); 160598#L969-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 160603#L442-27 assume !(1 == ~t4_pc~0); 160663#L442-29 is_transmit4_triggered_~__retres1~4 := 0; 161237#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 161238#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 161275#L977-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 161276#L977-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 160875#L461-27 assume !(1 == ~t5_pc~0); 160876#L461-29 is_transmit5_triggered_~__retres1~5 := 0; 160878#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 161322#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 161323#L985-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 160947#L985-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 160948#L480-27 assume !(1 == ~t6_pc~0); 160975#L480-29 is_transmit6_triggered_~__retres1~6 := 0; 160989#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 161360#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 160668#L993-27 assume !(0 != activate_threads_~tmp___5~0); 160648#L993-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 160649#L499-27 assume 1 == ~t7_pc~0; 161000#L500-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 161133#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 165607#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 165606#L1001-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 161309#L1001-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 161311#L847-3 assume 1 == ~M_E~0;~M_E~0 := 2; 161344#L847-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 161009#L852-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 160788#L857-3 assume !(1 == ~T3_E~0); 160466#L862-3 assume !(1 == ~T4_E~0); 160467#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 161410#L872-3 assume !(1 == ~T6_E~0); 164984#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 164982#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 164980#L887-3 assume 1 == ~E_1~0;~E_1~0 := 2; 164978#L892-3 assume 1 == ~E_2~0;~E_2~0 := 2; 164976#L897-3 assume !(1 == ~E_3~0); 164974#L902-3 assume !(1 == ~E_4~0); 164972#L907-3 assume 1 == ~E_5~0;~E_5~0 := 2; 161258#L912-3 assume !(1 == ~E_6~0); 161081#L917-3 assume 1 == ~E_7~0;~E_7~0 := 2; 160961#L922-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 160962#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 163968#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 163964#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 163956#L1187 assume !(0 == start_simulation_~tmp~3); 163953#L1187-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 163950#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 163938#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 163933#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 163929#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 163924#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 163919#L1150 start_simulation_#t~ret20 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 163916#L1200 assume !(0 != start_simulation_~tmp___0~1); 160960#L1168-3 [2018-11-18 15:27:59,709 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:27:59,709 INFO L82 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 6 times [2018-11-18 15:27:59,709 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:27:59,709 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:27:59,710 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:59,710 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:27:59,710 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:59,715 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:27:59,721 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:27:59,739 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:27:59,739 INFO L82 PathProgramCache]: Analyzing trace with hash 1029695150, now seen corresponding path program 1 times [2018-11-18 15:27:59,739 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:27:59,740 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:27:59,740 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:59,740 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:27:59,740 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:27:59,746 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:27:59,802 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:27:59,803 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:27:59,803 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 15:27:59,803 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:27:59,803 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 15:27:59,803 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:27:59,804 INFO L87 Difference]: Start difference. First operand 5507 states and 7422 transitions. cyclomatic complexity: 1923 Second operand 5 states. [2018-11-18 15:27:59,954 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:27:59,954 INFO L93 Difference]: Finished difference Result 14786 states and 19777 transitions. [2018-11-18 15:27:59,956 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 15:27:59,956 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14786 states and 19777 transitions. [2018-11-18 15:27:59,991 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 14500 [2018-11-18 15:28:00,018 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14786 states to 14786 states and 19777 transitions. [2018-11-18 15:28:00,018 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14786 [2018-11-18 15:28:00,025 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14786 [2018-11-18 15:28:00,025 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14786 states and 19777 transitions. [2018-11-18 15:28:00,033 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:28:00,033 INFO L705 BuchiCegarLoop]: Abstraction has 14786 states and 19777 transitions. [2018-11-18 15:28:00,040 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14786 states and 19777 transitions. [2018-11-18 15:28:00,082 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14786 to 5714. [2018-11-18 15:28:00,082 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5714 states. [2018-11-18 15:28:00,088 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5714 states to 5714 states and 7629 transitions. [2018-11-18 15:28:00,088 INFO L728 BuchiCegarLoop]: Abstraction has 5714 states and 7629 transitions. [2018-11-18 15:28:00,088 INFO L608 BuchiCegarLoop]: Abstraction has 5714 states and 7629 transitions. [2018-11-18 15:28:00,089 INFO L442 BuchiCegarLoop]: ======== Iteration 24============ [2018-11-18 15:28:00,089 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5714 states and 7629 transitions. [2018-11-18 15:28:00,100 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5584 [2018-11-18 15:28:00,100 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:28:00,100 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:28:00,101 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:00,101 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:00,101 INFO L794 eck$LassoCheckResult]: Stem: 181135#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 181047#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 181048#L1131 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 181439#L519 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 181245#L526 assume 1 == ~m_i~0;~m_st~0 := 0; 181246#L526-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 181003#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 181004#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 181440#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 181233#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 180944#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 180808#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 180809#L561-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 181594#L759 assume !(0 == ~M_E~0); 181598#L759-2 assume !(0 == ~T1_E~0); 181305#L764-1 assume !(0 == ~T2_E~0); 181082#L769-1 assume !(0 == ~T3_E~0); 180775#L774-1 assume !(0 == ~T4_E~0); 180776#L779-1 assume !(0 == ~T5_E~0); 181510#L784-1 assume !(0 == ~T6_E~0); 181289#L789-1 assume !(0 == ~T7_E~0); 180881#L794-1 assume !(0 == ~E_M~0); 180882#L799-1 assume !(0 == ~E_1~0); 181564#L804-1 assume !(0 == ~E_2~0); 181410#L809-1 assume !(0 == ~E_3~0); 181184#L814-1 assume !(0 == ~E_4~0); 180693#L819-1 assume !(0 == ~E_5~0); 180694#L824-1 assume !(0 == ~E_6~0); 181377#L829-1 assume !(0 == ~E_7~0); 181256#L834-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 181257#L366 assume !(1 == ~m_pc~0); 181363#L366-2 is_master_triggered_~__retres1~0 := 0; 180974#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 180756#L378 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 180757#L945 assume !(0 != activate_threads_~tmp~1); 181083#L945-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 181084#L385 assume !(1 == ~t1_pc~0); 181588#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 181158#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 180922#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 180923#L953 assume !(0 != activate_threads_~tmp___0~0); 181643#L953-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 181644#L404 assume !(1 == ~t2_pc~0); 181652#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 181287#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 181288#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 181483#L961 assume !(0 != activate_threads_~tmp___1~0); 181484#L961-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 180862#L423 assume !(1 == ~t3_pc~0); 180863#L423-2 is_transmit3_triggered_~__retres1~3 := 0; 180868#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 181393#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 181119#L969 assume !(0 != activate_threads_~tmp___2~0); 181120#L969-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 180879#L442 assume !(1 == ~t4_pc~0); 180870#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 180871#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 181442#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 181503#L977 assume !(0 != activate_threads_~tmp___3~0); 181672#L977-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 181063#L461 assume !(1 == ~t5_pc~0); 181064#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 181066#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 181523#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 181413#L985 assume !(0 != activate_threads_~tmp___4~0); 181414#L985-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 181234#L480 assume !(1 == ~t6_pc~0); 181220#L480-2 is_transmit6_triggered_~__retres1~6 := 0; 181221#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 181633#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 181026#L993 assume !(0 != activate_threads_~tmp___5~0); 181027#L993-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 181029#L499 assume !(1 == ~t7_pc~0); 181356#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 180749#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 180689#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 180690#L1001 assume !(0 != activate_threads_~tmp___6~0); 181600#L1001-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 181601#L847 assume !(1 == ~M_E~0); 181597#L847-2 assume !(1 == ~T1_E~0); 181303#L852-1 assume !(1 == ~T2_E~0); 181079#L857-1 assume !(1 == ~T3_E~0); 180771#L862-1 assume !(1 == ~T4_E~0); 180772#L867-1 assume !(1 == ~T5_E~0); 181507#L872-1 assume !(1 == ~T6_E~0); 181200#L877-1 assume !(1 == ~T7_E~0); 180889#L882-1 assume !(1 == ~E_M~0); 180890#L887-1 assume !(1 == ~E_1~0); 181572#L892-1 assume !(1 == ~E_2~0); 181417#L897-1 assume !(1 == ~E_3~0); 181196#L902-1 assume !(1 == ~E_4~0); 180708#L907-1 assume !(1 == ~E_5~0); 180709#L912-1 assume !(1 == ~E_6~0); 181374#L917-1 assume !(1 == ~E_7~0); 181253#L922-1 assume { :end_inline_reset_delta_events } true; 181254#L1168-3 [2018-11-18 15:28:00,102 INFO L796 eck$LassoCheckResult]: Loop: 181254#L1168-3 assume true; 184305#L1168-1 assume !false; 184300#L1169 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 184299#L734 assume true; 184298#L626-1 assume !false; 184297#L627 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 184288#L574 assume !(0 == ~m_st~0); 184289#L578 assume !(0 == ~t1_st~0); 184294#L582 assume !(0 == ~t2_st~0); 184296#L586 assume !(0 == ~t3_st~0); 184292#L590 assume !(0 == ~t4_st~0); 184293#L594 assume !(0 == ~t5_st~0); 184295#L598 assume !(0 == ~t6_st~0); 184290#L602 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8 := 0; 184291#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 185003#L617 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 184992#L631 assume !(0 != eval_~tmp~0); 184990#L749 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 184989#L519-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 184986#L759-3 assume 0 == ~M_E~0;~M_E~0 := 1; 184984#L759-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 184983#L764-3 assume !(0 == ~T2_E~0); 184982#L769-3 assume !(0 == ~T3_E~0); 184979#L774-3 assume !(0 == ~T4_E~0); 184977#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 184975#L784-3 assume !(0 == ~T6_E~0); 184973#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 184971#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 184969#L799-3 assume 0 == ~E_1~0;~E_1~0 := 1; 184967#L804-3 assume !(0 == ~E_2~0); 184964#L809-3 assume !(0 == ~E_3~0); 184940#L814-3 assume !(0 == ~E_4~0); 184934#L819-3 assume 0 == ~E_5~0;~E_5~0 := 1; 184927#L824-3 assume !(0 == ~E_6~0); 184922#L829-3 assume 0 == ~E_7~0;~E_7~0 := 1; 184916#L834-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 184915#L366-27 assume !(1 == ~m_pc~0); 184914#L366-29 is_master_triggered_~__retres1~0 := 0; 184912#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 184911#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 184910#L945-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 184909#L945-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 184908#L385-27 assume !(1 == ~t1_pc~0); 184907#L385-29 is_transmit1_triggered_~__retres1~1 := 0; 184906#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 184905#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 184904#L953-27 assume !(0 != activate_threads_~tmp___0~0); 184903#L953-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 184902#L404-27 assume 1 == ~t2_pc~0; 184900#L405-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 184898#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 184896#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 184894#L961-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 184889#L961-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 184884#L423-27 assume !(1 == ~t3_pc~0); 184859#L423-29 is_transmit3_triggered_~__retres1~3 := 0; 184857#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 184855#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 184830#L969-27 assume !(0 != activate_threads_~tmp___2~0); 184824#L969-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 184783#L442-27 assume !(1 == ~t4_pc~0); 184780#L442-29 is_transmit4_triggered_~__retres1~4 := 0; 184778#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 184776#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 184774#L977-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 184772#L977-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 184770#L461-27 assume !(1 == ~t5_pc~0); 184768#L461-29 is_transmit5_triggered_~__retres1~5 := 0; 184766#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 184764#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 184762#L985-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 184754#L985-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 184557#L480-27 assume !(1 == ~t6_pc~0); 184554#L480-29 is_transmit6_triggered_~__retres1~6 := 0; 184551#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 184549#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 184547#L993-27 assume !(0 != activate_threads_~tmp___5~0); 184545#L993-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 184543#L499-27 assume !(1 == ~t7_pc~0); 184539#L499-29 is_transmit7_triggered_~__retres1~7 := 0; 184536#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 184534#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 184532#L1001-27 assume !(0 != activate_threads_~tmp___6~0); 184528#L1001-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 184526#L847-3 assume 1 == ~M_E~0;~M_E~0 := 2; 184525#L847-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 184522#L852-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 184521#L857-3 assume !(1 == ~T3_E~0); 184519#L862-3 assume !(1 == ~T4_E~0); 184517#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 184515#L872-3 assume !(1 == ~T6_E~0); 184514#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 184513#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 184512#L887-3 assume 1 == ~E_1~0;~E_1~0 := 2; 184511#L892-3 assume 1 == ~E_2~0;~E_2~0 := 2; 184485#L897-3 assume !(1 == ~E_3~0); 184472#L902-3 assume !(1 == ~E_4~0); 184468#L907-3 assume 1 == ~E_5~0;~E_5~0 := 2; 184466#L912-3 assume !(1 == ~E_6~0); 184464#L917-3 assume 1 == ~E_7~0;~E_7~0 := 2; 184463#L922-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 184362#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 184353#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 184351#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 184349#L1187 assume !(0 == start_simulation_~tmp~3); 184347#L1187-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 184346#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 184332#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 184325#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 184320#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 184316#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 184314#L1150 start_simulation_#t~ret20 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 184312#L1200 assume !(0 != start_simulation_~tmp___0~1); 181254#L1168-3 [2018-11-18 15:28:00,102 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:00,102 INFO L82 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 7 times [2018-11-18 15:28:00,102 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:00,102 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:00,103 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:00,103 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:28:00,103 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:00,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:28:00,114 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:28:00,133 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:00,133 INFO L82 PathProgramCache]: Analyzing trace with hash 562787505, now seen corresponding path program 1 times [2018-11-18 15:28:00,133 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:00,134 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:00,134 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:00,134 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:28:00,134 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:00,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:00,196 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:28:00,196 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:28:00,196 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 15:28:00,196 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:28:00,196 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 15:28:00,197 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:28:00,197 INFO L87 Difference]: Start difference. First operand 5714 states and 7629 transitions. cyclomatic complexity: 1923 Second operand 5 states. [2018-11-18 15:28:00,352 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:00,352 INFO L93 Difference]: Finished difference Result 16461 states and 21770 transitions. [2018-11-18 15:28:00,353 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 15:28:00,354 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16461 states and 21770 transitions. [2018-11-18 15:28:00,390 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 16140 [2018-11-18 15:28:00,415 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16461 states to 16461 states and 21770 transitions. [2018-11-18 15:28:00,415 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16461 [2018-11-18 15:28:00,423 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16461 [2018-11-18 15:28:00,423 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16461 states and 21770 transitions. [2018-11-18 15:28:00,434 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:28:00,434 INFO L705 BuchiCegarLoop]: Abstraction has 16461 states and 21770 transitions. [2018-11-18 15:28:00,441 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16461 states and 21770 transitions. [2018-11-18 15:28:00,488 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16461 to 5921. [2018-11-18 15:28:00,488 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5921 states. [2018-11-18 15:28:00,494 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5921 states to 5921 states and 7836 transitions. [2018-11-18 15:28:00,494 INFO L728 BuchiCegarLoop]: Abstraction has 5921 states and 7836 transitions. [2018-11-18 15:28:00,494 INFO L608 BuchiCegarLoop]: Abstraction has 5921 states and 7836 transitions. [2018-11-18 15:28:00,494 INFO L442 BuchiCegarLoop]: ======== Iteration 25============ [2018-11-18 15:28:00,494 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5921 states and 7836 transitions. [2018-11-18 15:28:00,506 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5788 [2018-11-18 15:28:00,506 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:28:00,506 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:28:00,507 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:00,507 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:00,507 INFO L794 eck$LassoCheckResult]: Stem: 203341#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 203251#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 203252#L1131 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 203660#L519 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 203451#L526 assume 1 == ~m_i~0;~m_st~0 := 0; 203452#L526-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 203202#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 203203#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 203661#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 203436#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 203135#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 202997#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 202998#L561-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 203830#L759 assume !(0 == ~M_E~0); 203834#L759-2 assume !(0 == ~T1_E~0); 203511#L764-1 assume !(0 == ~T2_E~0); 203287#L769-1 assume !(0 == ~T3_E~0); 202963#L774-1 assume !(0 == ~T4_E~0); 202964#L779-1 assume !(0 == ~T5_E~0); 203739#L784-1 assume !(0 == ~T6_E~0); 203493#L789-1 assume !(0 == ~T7_E~0); 203073#L794-1 assume !(0 == ~E_M~0); 203074#L799-1 assume !(0 == ~E_1~0); 203797#L804-1 assume !(0 == ~E_2~0); 203631#L809-1 assume !(0 == ~E_3~0); 203387#L814-1 assume !(0 == ~E_4~0); 202881#L819-1 assume !(0 == ~E_5~0); 202882#L824-1 assume !(0 == ~E_6~0); 203597#L829-1 assume !(0 == ~E_7~0); 203461#L834-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 203462#L366 assume !(1 == ~m_pc~0); 203580#L366-2 is_master_triggered_~__retres1~0 := 0; 203168#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 203169#L378 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 203288#L945 assume !(0 != activate_threads_~tmp~1); 203289#L945-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 203290#L385 assume !(1 == ~t1_pc~0); 203824#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 203366#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 203114#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 203115#L953 assume !(0 != activate_threads_~tmp___0~0); 203877#L953-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 203878#L404 assume !(1 == ~t2_pc~0); 203885#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 203899#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 203453#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 203454#L961 assume !(0 != activate_threads_~tmp___1~0); 203705#L961-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 203054#L423 assume !(1 == ~t3_pc~0); 203055#L423-2 is_transmit3_triggered_~__retres1~3 := 0; 203060#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 203611#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 203324#L969 assume !(0 != activate_threads_~tmp___2~0); 203325#L969-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 203071#L442 assume !(1 == ~t4_pc~0); 203062#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 203063#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 203663#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 203733#L977 assume !(0 != activate_threads_~tmp___3~0); 203891#L977-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 203267#L461 assume !(1 == ~t5_pc~0); 203268#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 203270#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 203751#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 203634#L985 assume !(0 != activate_threads_~tmp___4~0); 203635#L985-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 203437#L480 assume !(1 == ~t6_pc~0); 203424#L480-2 is_transmit6_triggered_~__retres1~6 := 0; 203425#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 203869#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 203227#L993 assume !(0 != activate_threads_~tmp___5~0); 203228#L993-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 203232#L499 assume !(1 == ~t7_pc~0); 203568#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 202937#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 202877#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 202878#L1001 assume !(0 != activate_threads_~tmp___6~0); 203836#L1001-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 203837#L847 assume !(1 == ~M_E~0); 203833#L847-2 assume !(1 == ~T1_E~0); 203508#L852-1 assume !(1 == ~T2_E~0); 203283#L857-1 assume !(1 == ~T3_E~0); 202959#L862-1 assume !(1 == ~T4_E~0); 202960#L867-1 assume !(1 == ~T5_E~0); 203737#L872-1 assume !(1 == ~T6_E~0); 203404#L877-1 assume !(1 == ~T7_E~0); 203081#L882-1 assume !(1 == ~E_M~0); 203082#L887-1 assume !(1 == ~E_1~0); 203807#L892-1 assume !(1 == ~E_2~0); 203638#L897-1 assume !(1 == ~E_3~0); 203399#L902-1 assume !(1 == ~E_4~0); 202896#L907-1 assume !(1 == ~E_5~0); 202897#L912-1 assume !(1 == ~E_6~0); 203593#L917-1 assume !(1 == ~E_7~0); 203459#L922-1 assume { :end_inline_reset_delta_events } true; 203091#L1168-3 [2018-11-18 15:28:00,508 INFO L796 eck$LassoCheckResult]: Loop: 203091#L1168-3 assume true; 203092#L1168-1 assume !false; 203110#L1169 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 203173#L734 assume true; 203902#L626-1 assume !false; 207199#L627 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 207195#L574 assume !(0 == ~m_st~0); 207194#L578 assume !(0 == ~t1_st~0); 207193#L582 assume !(0 == ~t2_st~0); 207180#L586 assume !(0 == ~t3_st~0); 207177#L590 assume !(0 == ~t4_st~0); 207166#L594 assume !(0 == ~t5_st~0); 207164#L598 assume !(0 == ~t6_st~0); 203903#L602 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8 := 0; 203904#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 208576#L617 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 208574#L631 assume !(0 != eval_~tmp~0); 208573#L749 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 208572#L519-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 208564#L759-3 assume 0 == ~M_E~0;~M_E~0 := 1; 208562#L759-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 208560#L764-3 assume !(0 == ~T2_E~0); 208558#L769-3 assume !(0 == ~T3_E~0); 208556#L774-3 assume !(0 == ~T4_E~0); 208554#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 208552#L784-3 assume !(0 == ~T6_E~0); 208550#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 208546#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 208544#L799-3 assume 0 == ~E_1~0;~E_1~0 := 1; 208542#L804-3 assume !(0 == ~E_2~0); 208540#L809-3 assume !(0 == ~E_3~0); 208537#L814-3 assume !(0 == ~E_4~0); 208535#L819-3 assume 0 == ~E_5~0;~E_5~0 := 1; 208533#L824-3 assume !(0 == ~E_6~0); 208518#L829-3 assume 0 == ~E_7~0;~E_7~0 := 1; 208512#L834-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 203570#L366-27 assume 1 == ~m_pc~0; 203571#L367-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 208510#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 208508#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 208506#L945-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 208505#L945-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 203700#L385-27 assume !(1 == ~t1_pc~0); 203685#L385-29 is_transmit1_triggered_~__retres1~1 := 0; 203332#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 203085#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 203086#L953-27 assume !(0 != activate_threads_~tmp___0~0); 203841#L953-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 203842#L404-27 assume !(1 == ~t2_pc~0); 203771#L404-29 is_transmit2_triggered_~__retres1~2 := 0; 203883#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 208262#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 203537#L961-27 assume !(0 != activate_threads_~tmp___1~0); 203513#L961-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 202993#L423-27 assume !(1 == ~t3_pc~0); 202994#L423-29 is_transmit3_triggered_~__retres1~3 := 0; 203001#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 203610#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 203087#L969-27 assume !(0 != activate_threads_~tmp___2~0); 203088#L969-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 203093#L442-27 assume !(1 == ~t4_pc~0); 203154#L442-29 is_transmit4_triggered_~__retres1~4 := 0; 203199#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 203716#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 203717#L977-27 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 203759#L977-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 203377#L461-27 assume !(1 == ~t5_pc~0); 203378#L461-29 is_transmit5_triggered_~__retres1~5 := 0; 203381#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 203750#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 203446#L985-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 203447#L985-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 203448#L480-27 assume !(1 == ~t6_pc~0); 203473#L480-29 is_transmit6_triggered_~__retres1~6 := 0; 203488#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 203846#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 203161#L993-27 assume !(0 != activate_threads_~tmp___5~0); 203139#L993-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 203140#L499-27 assume 1 == ~t7_pc~0; 208326#L500-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 208327#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 208499#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 208316#L1001-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 208314#L1001-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 208312#L847-3 assume 1 == ~M_E~0;~M_E~0 := 2; 208310#L847-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 208308#L852-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 208306#L857-3 assume !(1 == ~T3_E~0); 208303#L862-3 assume !(1 == ~T4_E~0); 208301#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 208299#L872-3 assume !(1 == ~T6_E~0); 208298#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 208295#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 203872#L887-3 assume 1 == ~E_1~0;~E_1~0 := 2; 203796#L892-3 assume 1 == ~E_2~0;~E_2~0 := 2; 203628#L897-3 assume !(1 == ~E_3~0); 203384#L902-3 assume !(1 == ~E_4~0); 202879#L907-3 assume 1 == ~E_5~0;~E_5~0 := 2; 202880#L912-3 assume !(1 == ~E_6~0); 203596#L917-3 assume 1 == ~E_7~0;~E_7~0 := 2; 203460#L922-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 203069#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 202957#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 203129#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 203130#L1187 assume !(0 == start_simulation_~tmp~3); 203293#L1187-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 203070#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 202935#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 203133#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 203134#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 202904#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 202905#L1150 start_simulation_#t~ret20 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 203030#L1200 assume !(0 != start_simulation_~tmp___0~1); 203091#L1168-3 [2018-11-18 15:28:00,508 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:00,508 INFO L82 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 8 times [2018-11-18 15:28:00,508 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:00,508 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:00,509 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:00,509 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:28:00,509 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:00,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:28:00,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:28:00,540 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:00,540 INFO L82 PathProgramCache]: Analyzing trace with hash -1303697488, now seen corresponding path program 1 times [2018-11-18 15:28:00,540 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:00,540 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:00,541 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:00,541 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:28:00,541 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:00,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:00,601 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:28:00,601 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:28:00,601 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 15:28:00,602 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:28:00,602 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 15:28:00,602 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:28:00,602 INFO L87 Difference]: Start difference. First operand 5921 states and 7836 transitions. cyclomatic complexity: 1923 Second operand 5 states. [2018-11-18 15:28:00,708 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:00,708 INFO L93 Difference]: Finished difference Result 8089 states and 10674 transitions. [2018-11-18 15:28:00,710 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 15:28:00,710 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8089 states and 10674 transitions. [2018-11-18 15:28:00,732 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7940 [2018-11-18 15:28:00,746 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8089 states to 8089 states and 10674 transitions. [2018-11-18 15:28:00,746 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8089 [2018-11-18 15:28:00,750 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8089 [2018-11-18 15:28:00,751 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8089 states and 10674 transitions. [2018-11-18 15:28:00,755 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:28:00,755 INFO L705 BuchiCegarLoop]: Abstraction has 8089 states and 10674 transitions. [2018-11-18 15:28:00,760 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8089 states and 10674 transitions. [2018-11-18 15:28:00,800 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8089 to 5933. [2018-11-18 15:28:00,800 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5933 states. [2018-11-18 15:28:00,808 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5933 states to 5933 states and 7783 transitions. [2018-11-18 15:28:00,808 INFO L728 BuchiCegarLoop]: Abstraction has 5933 states and 7783 transitions. [2018-11-18 15:28:00,808 INFO L608 BuchiCegarLoop]: Abstraction has 5933 states and 7783 transitions. [2018-11-18 15:28:00,808 INFO L442 BuchiCegarLoop]: ======== Iteration 26============ [2018-11-18 15:28:00,808 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5933 states and 7783 transitions. [2018-11-18 15:28:00,822 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5800 [2018-11-18 15:28:00,822 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:28:00,822 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:28:00,823 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:00,823 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:00,824 INFO L794 eck$LassoCheckResult]: Stem: 217382#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 217286#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 217287#L1131 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 217731#L519 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 217499#L526 assume 1 == ~m_i~0;~m_st~0 := 0; 217500#L526-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 217229#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 217230#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 217732#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 217485#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 217165#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 217021#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 217022#L561-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 217929#L759 assume !(0 == ~M_E~0); 217936#L759-2 assume !(0 == ~T1_E~0); 217565#L764-1 assume !(0 == ~T2_E~0); 217321#L769-1 assume !(0 == ~T3_E~0); 216987#L774-1 assume !(0 == ~T4_E~0); 216988#L779-1 assume !(0 == ~T5_E~0); 217811#L784-1 assume !(0 == ~T6_E~0); 217541#L789-1 assume !(0 == ~T7_E~0); 217098#L794-1 assume !(0 == ~E_M~0); 217099#L799-1 assume !(0 == ~E_1~0); 217885#L804-1 assume !(0 == ~E_2~0); 217685#L809-1 assume !(0 == ~E_3~0); 217427#L814-1 assume !(0 == ~E_4~0); 216905#L819-1 assume !(0 == ~E_5~0); 216906#L824-1 assume !(0 == ~E_6~0); 217648#L829-1 assume !(0 == ~E_7~0); 217510#L834-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 217511#L366 assume !(1 == ~m_pc~0); 217638#L366-2 is_master_triggered_~__retres1~0 := 0; 217196#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 217197#L378 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 217322#L945 assume !(0 != activate_threads_~tmp~1); 217323#L945-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 217324#L385 assume !(1 == ~t1_pc~0); 217919#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 217402#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 217143#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 217144#L953 assume !(0 != activate_threads_~tmp___0~0); 217990#L953-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 217991#L404 assume !(1 == ~t2_pc~0); 217998#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 217540#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 217501#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 217502#L961 assume !(0 != activate_threads_~tmp___1~0); 217781#L961-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 217076#L423 assume !(1 == ~t3_pc~0); 217077#L423-2 is_transmit3_triggered_~__retres1~3 := 0; 217083#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 217663#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 217364#L969 assume !(0 != activate_threads_~tmp___2~0); 217365#L969-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 217096#L442 assume !(1 == ~t4_pc~0); 217085#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 217086#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 217734#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 217805#L977 assume !(0 != activate_threads_~tmp___3~0); 218016#L977-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 217302#L461 assume !(1 == ~t5_pc~0); 217303#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 217305#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 217831#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 217691#L985 assume !(0 != activate_threads_~tmp___4~0); 217692#L985-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 217486#L480 assume !(1 == ~t6_pc~0); 217472#L480-2 is_transmit6_triggered_~__retres1~6 := 0; 217473#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 217983#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 217262#L993 assume !(0 != activate_threads_~tmp___5~0); 217263#L993-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 217266#L499 assume !(1 == ~t7_pc~0); 217630#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 216961#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 216901#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 216902#L1001 assume !(0 != activate_threads_~tmp___6~0); 217942#L1001-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 217943#L847 assume !(1 == ~M_E~0); 217935#L847-2 assume !(1 == ~T1_E~0); 217560#L852-1 assume !(1 == ~T2_E~0); 217317#L857-1 assume !(1 == ~T3_E~0); 216983#L862-1 assume !(1 == ~T4_E~0); 216984#L867-1 assume !(1 == ~T5_E~0); 217809#L872-1 assume !(1 == ~T6_E~0); 217450#L877-1 assume !(1 == ~T7_E~0); 217107#L882-1 assume !(1 == ~E_M~0); 217108#L887-1 assume !(1 == ~E_1~0); 217893#L892-1 assume !(1 == ~E_2~0); 217695#L897-1 assume !(1 == ~E_3~0); 217444#L902-1 assume !(1 == ~E_4~0); 216920#L907-1 assume !(1 == ~E_5~0); 216921#L912-1 assume !(1 == ~E_6~0); 217644#L917-1 assume !(1 == ~E_7~0); 217507#L922-1 assume { :end_inline_reset_delta_events } true; 217508#L1168-3 [2018-11-18 15:28:00,824 INFO L796 eck$LassoCheckResult]: Loop: 217508#L1168-3 assume true; 220578#L1168-1 assume !false; 220573#L1169 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 220572#L734 assume true; 220571#L626-1 assume !false; 220570#L627 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 220561#L574 assume !(0 == ~m_st~0); 220562#L578 assume !(0 == ~t1_st~0); 220567#L582 assume !(0 == ~t2_st~0); 220569#L586 assume !(0 == ~t3_st~0); 220565#L590 assume !(0 == ~t4_st~0); 220566#L594 assume !(0 == ~t5_st~0); 220568#L598 assume !(0 == ~t6_st~0); 220563#L602 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8 := 0; 220564#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 219338#L617 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 219339#L631 assume !(0 != eval_~tmp~0); 220928#L749 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 220927#L519-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 220926#L759-3 assume 0 == ~M_E~0;~M_E~0 := 1; 220925#L759-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 220924#L764-3 assume !(0 == ~T2_E~0); 220923#L769-3 assume !(0 == ~T3_E~0); 220922#L774-3 assume !(0 == ~T4_E~0); 220921#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 220920#L784-3 assume !(0 == ~T6_E~0); 220919#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 220918#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 220917#L799-3 assume 0 == ~E_1~0;~E_1~0 := 1; 220916#L804-3 assume !(0 == ~E_2~0); 220915#L809-3 assume !(0 == ~E_3~0); 220914#L814-3 assume !(0 == ~E_4~0); 220913#L819-3 assume 0 == ~E_5~0;~E_5~0 := 1; 220912#L824-3 assume !(0 == ~E_6~0); 220911#L829-3 assume 0 == ~E_7~0;~E_7~0 := 1; 220910#L834-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 220909#L366-27 assume 1 == ~m_pc~0; 220907#L367-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 220905#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 220903#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 220901#L945-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 220900#L945-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 220899#L385-27 assume !(1 == ~t1_pc~0); 220898#L385-29 is_transmit1_triggered_~__retres1~1 := 0; 220897#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 220896#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 220895#L953-27 assume !(0 != activate_threads_~tmp___0~0); 220894#L953-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 220893#L404-27 assume 1 == ~t2_pc~0; 220891#L405-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 220889#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 220887#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 220885#L961-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 220884#L961-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 220883#L423-27 assume !(1 == ~t3_pc~0); 220882#L423-29 is_transmit3_triggered_~__retres1~3 := 0; 220880#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 220877#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 220874#L969-27 assume !(0 != activate_threads_~tmp___2~0); 220871#L969-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 220868#L442-27 assume !(1 == ~t4_pc~0); 220865#L442-29 is_transmit4_triggered_~__retres1~4 := 0; 220863#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 220861#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 220859#L977-27 assume !(0 != activate_threads_~tmp___3~0); 220857#L977-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 220855#L461-27 assume !(1 == ~t5_pc~0); 220853#L461-29 is_transmit5_triggered_~__retres1~5 := 0; 220851#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 220848#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 220845#L985-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 220835#L985-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 220832#L480-27 assume !(1 == ~t6_pc~0); 220829#L480-29 is_transmit6_triggered_~__retres1~6 := 0; 220827#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 220825#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 220823#L993-27 assume !(0 != activate_threads_~tmp___5~0); 220821#L993-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 220819#L499-27 assume !(1 == ~t7_pc~0); 220817#L499-29 is_transmit7_triggered_~__retres1~7 := 0; 220813#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 220810#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 220807#L1001-27 assume !(0 != activate_threads_~tmp___6~0); 220804#L1001-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 220802#L847-3 assume 1 == ~M_E~0;~M_E~0 := 2; 220799#L847-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 220795#L852-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 220791#L857-3 assume !(1 == ~T3_E~0); 220787#L862-3 assume !(1 == ~T4_E~0); 220783#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 220780#L872-3 assume !(1 == ~T6_E~0); 220777#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 220773#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 220769#L887-3 assume 1 == ~E_1~0;~E_1~0 := 2; 220764#L892-3 assume 1 == ~E_2~0;~E_2~0 := 2; 220759#L897-3 assume !(1 == ~E_3~0); 220754#L902-3 assume !(1 == ~E_4~0); 220751#L907-3 assume 1 == ~E_5~0;~E_5~0 := 2; 220747#L912-3 assume !(1 == ~E_6~0); 220740#L917-3 assume 1 == ~E_7~0;~E_7~0 := 2; 220734#L922-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 220689#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 220678#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 220673#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 220668#L1187 assume !(0 == start_simulation_~tmp~3); 220664#L1187-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 220619#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 220607#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 220602#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 220598#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 220593#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 220588#L1150 start_simulation_#t~ret20 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 220585#L1200 assume !(0 != start_simulation_~tmp___0~1); 217508#L1168-3 [2018-11-18 15:28:00,825 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:00,825 INFO L82 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 9 times [2018-11-18 15:28:00,825 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:00,825 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:00,826 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:00,826 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:28:00,826 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:00,832 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:28:00,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:28:00,859 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:00,860 INFO L82 PathProgramCache]: Analyzing trace with hash -1905384718, now seen corresponding path program 1 times [2018-11-18 15:28:00,860 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:00,860 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:00,861 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:00,861 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:28:00,861 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:00,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:00,927 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:28:00,927 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:28:00,928 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 15:28:00,928 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:28:00,928 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 15:28:00,928 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:28:00,928 INFO L87 Difference]: Start difference. First operand 5933 states and 7783 transitions. cyclomatic complexity: 1858 Second operand 5 states. [2018-11-18 15:28:01,104 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:01,104 INFO L93 Difference]: Finished difference Result 10240 states and 13463 transitions. [2018-11-18 15:28:01,105 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 15:28:01,105 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10240 states and 13463 transitions. [2018-11-18 15:28:01,124 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10091 [2018-11-18 15:28:01,137 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10240 states to 10240 states and 13463 transitions. [2018-11-18 15:28:01,137 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10240 [2018-11-18 15:28:01,142 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10240 [2018-11-18 15:28:01,142 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10240 states and 13463 transitions. [2018-11-18 15:28:01,147 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:28:01,147 INFO L705 BuchiCegarLoop]: Abstraction has 10240 states and 13463 transitions. [2018-11-18 15:28:01,152 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10240 states and 13463 transitions. [2018-11-18 15:28:01,185 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10240 to 6041. [2018-11-18 15:28:01,185 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6041 states. [2018-11-18 15:28:01,191 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6041 states to 6041 states and 7858 transitions. [2018-11-18 15:28:01,191 INFO L728 BuchiCegarLoop]: Abstraction has 6041 states and 7858 transitions. [2018-11-18 15:28:01,191 INFO L608 BuchiCegarLoop]: Abstraction has 6041 states and 7858 transitions. [2018-11-18 15:28:01,191 INFO L442 BuchiCegarLoop]: ======== Iteration 27============ [2018-11-18 15:28:01,191 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6041 states and 7858 transitions. [2018-11-18 15:28:01,203 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5908 [2018-11-18 15:28:01,203 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:28:01,203 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:28:01,204 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:01,204 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:01,204 INFO L794 eck$LassoCheckResult]: Stem: 233542#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 233453#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 233454#L1131 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 233837#L519 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 233650#L526 assume 1 == ~m_i~0;~m_st~0 := 0; 233651#L526-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 233406#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 233407#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 233838#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 233637#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 233347#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 233208#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 233209#L561-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 234005#L759 assume !(0 == ~M_E~0); 234009#L759-2 assume !(0 == ~T1_E~0); 233704#L764-1 assume !(0 == ~T2_E~0); 233489#L769-1 assume !(0 == ~T3_E~0); 233174#L774-1 assume !(0 == ~T4_E~0); 233175#L779-1 assume !(0 == ~T5_E~0); 233907#L784-1 assume !(0 == ~T6_E~0); 233688#L789-1 assume !(0 == ~T7_E~0); 233285#L794-1 assume !(0 == ~E_M~0); 233286#L799-1 assume !(0 == ~E_1~0); 233966#L804-1 assume !(0 == ~E_2~0); 233811#L809-1 assume !(0 == ~E_3~0); 233585#L814-1 assume !(0 == ~E_4~0); 233092#L819-1 assume !(0 == ~E_5~0); 233093#L824-1 assume !(0 == ~E_6~0); 233782#L829-1 assume !(0 == ~E_7~0); 233661#L834-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 233662#L366 assume !(1 == ~m_pc~0); 233771#L366-2 is_master_triggered_~__retres1~0 := 0; 233378#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 233379#L378 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 233490#L945 assume !(0 != activate_threads_~tmp~1); 233491#L945-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 233492#L385 assume !(1 == ~t1_pc~0); 233999#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 233562#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 233326#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 233327#L953 assume !(0 != activate_threads_~tmp___0~0); 234051#L953-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 234052#L404 assume !(1 == ~t2_pc~0); 234059#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 233687#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 233652#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 233653#L961 assume !(0 != activate_threads_~tmp___1~0); 233880#L961-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 233265#L423 assume !(1 == ~t3_pc~0); 233266#L423-2 is_transmit3_triggered_~__retres1~3 := 0; 233272#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 233795#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 233526#L969 assume !(0 != activate_threads_~tmp___2~0); 233527#L969-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 233283#L442 assume !(1 == ~t4_pc~0); 233274#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 233275#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 233840#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 233901#L977 assume !(0 != activate_threads_~tmp___3~0); 234070#L977-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 233470#L461 assume !(1 == ~t5_pc~0); 233471#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 233473#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 233920#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 233814#L985 assume !(0 != activate_threads_~tmp___4~0); 233815#L985-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 233638#L480 assume !(1 == ~t6_pc~0); 233625#L480-2 is_transmit6_triggered_~__retres1~6 := 0; 233626#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 234045#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 233430#L993 assume !(0 != activate_threads_~tmp___5~0); 233431#L993-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 233433#L499 assume !(1 == ~t7_pc~0); 233762#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 233148#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 233088#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 233089#L1001 assume !(0 != activate_threads_~tmp___6~0); 234011#L1001-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 234012#L847 assume !(1 == ~M_E~0); 234008#L847-2 assume !(1 == ~T1_E~0); 233702#L852-1 assume !(1 == ~T2_E~0); 233486#L857-1 assume !(1 == ~T3_E~0); 233170#L862-1 assume !(1 == ~T4_E~0); 233171#L867-1 assume !(1 == ~T5_E~0); 233905#L872-1 assume !(1 == ~T6_E~0); 233605#L877-1 assume !(1 == ~T7_E~0); 233293#L882-1 assume !(1 == ~E_M~0); 233294#L887-1 assume !(1 == ~E_1~0); 233974#L892-1 assume !(1 == ~E_2~0); 233818#L897-1 assume !(1 == ~E_3~0); 233601#L902-1 assume !(1 == ~E_4~0); 233107#L907-1 assume !(1 == ~E_5~0); 233108#L912-1 assume !(1 == ~E_6~0); 233777#L917-1 assume !(1 == ~E_7~0); 233658#L922-1 assume { :end_inline_reset_delta_events } true; 233659#L1168-3 [2018-11-18 15:28:01,204 INFO L796 eck$LassoCheckResult]: Loop: 233659#L1168-3 assume true; 236248#L1168-1 assume !false; 236239#L1169 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 236237#L734 assume true; 236233#L626-1 assume !false; 236231#L627 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 236172#L574 assume !(0 == ~m_st~0); 236173#L578 assume !(0 == ~t1_st~0); 236178#L582 assume !(0 == ~t2_st~0); 236180#L586 assume !(0 == ~t3_st~0); 236176#L590 assume !(0 == ~t4_st~0); 236177#L594 assume !(0 == ~t5_st~0); 236179#L598 assume !(0 == ~t6_st~0); 236174#L602 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8 := 0; 236175#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 235160#L617 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 235161#L631 assume !(0 != eval_~tmp~0); 237372#L749 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 237371#L519-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 237370#L759-3 assume 0 == ~M_E~0;~M_E~0 := 1; 237369#L759-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 237368#L764-3 assume !(0 == ~T2_E~0); 237367#L769-3 assume !(0 == ~T3_E~0); 237366#L774-3 assume !(0 == ~T4_E~0); 237365#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 237364#L784-3 assume !(0 == ~T6_E~0); 237363#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 237362#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 237361#L799-3 assume 0 == ~E_1~0;~E_1~0 := 1; 237360#L804-3 assume !(0 == ~E_2~0); 237359#L809-3 assume !(0 == ~E_3~0); 237358#L814-3 assume !(0 == ~E_4~0); 237357#L819-3 assume 0 == ~E_5~0;~E_5~0 := 1; 237356#L824-3 assume !(0 == ~E_6~0); 237355#L829-3 assume 0 == ~E_7~0;~E_7~0 := 1; 237354#L834-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 237353#L366-27 assume 1 == ~m_pc~0; 237351#L367-9 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 237349#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 237347#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 237345#L945-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 237344#L945-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 237343#L385-27 assume !(1 == ~t1_pc~0); 237342#L385-29 is_transmit1_triggered_~__retres1~1 := 0; 237341#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 237340#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 237339#L953-27 assume !(0 != activate_threads_~tmp___0~0); 237338#L953-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 237337#L404-27 assume 1 == ~t2_pc~0; 237335#L405-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 237333#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 237331#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 237329#L961-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 237328#L961-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 237327#L423-27 assume !(1 == ~t3_pc~0); 237326#L423-29 is_transmit3_triggered_~__retres1~3 := 0; 237325#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 237324#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 237323#L969-27 assume !(0 != activate_threads_~tmp___2~0); 237322#L969-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 237321#L442-27 assume !(1 == ~t4_pc~0); 237319#L442-29 is_transmit4_triggered_~__retres1~4 := 0; 237318#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 237317#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 237316#L977-27 assume !(0 != activate_threads_~tmp___3~0); 233926#L977-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 233573#L461-27 assume !(1 == ~t5_pc~0); 233574#L461-29 is_transmit5_triggered_~__retres1~5 := 0; 236567#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 236565#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 236563#L985-27 assume !(0 != activate_threads_~tmp___4~0); 236561#L985-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 236559#L480-27 assume !(1 == ~t6_pc~0); 236556#L480-29 is_transmit6_triggered_~__retres1~6 := 0; 236553#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 236550#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 236547#L993-27 assume !(0 != activate_threads_~tmp___5~0); 236544#L993-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 236540#L499-27 assume !(1 == ~t7_pc~0); 236537#L499-29 is_transmit7_triggered_~__retres1~7 := 0; 236533#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 236529#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 236525#L1001-27 assume !(0 != activate_threads_~tmp___6~0); 236520#L1001-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 236516#L847-3 assume 1 == ~M_E~0;~M_E~0 := 2; 236511#L847-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 236506#L852-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 236502#L857-3 assume !(1 == ~T3_E~0); 236498#L862-3 assume !(1 == ~T4_E~0); 236494#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 236490#L872-3 assume !(1 == ~T6_E~0); 236486#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 236482#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 236479#L887-3 assume 1 == ~E_1~0;~E_1~0 := 2; 236476#L892-3 assume 1 == ~E_2~0;~E_2~0 := 2; 236472#L897-3 assume !(1 == ~E_3~0); 236467#L902-3 assume !(1 == ~E_4~0); 236462#L907-3 assume 1 == ~E_5~0;~E_5~0 := 2; 236457#L912-3 assume !(1 == ~E_6~0); 236452#L917-3 assume 1 == ~E_7~0;~E_7~0 := 2; 236446#L922-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 236436#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 236422#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 236415#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 236408#L1187 assume !(0 == start_simulation_~tmp~3); 236402#L1187-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 236271#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 236262#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 236259#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 236257#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 236255#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 236252#L1150 start_simulation_#t~ret20 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 236250#L1200 assume !(0 != start_simulation_~tmp___0~1); 233659#L1168-3 [2018-11-18 15:28:01,205 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:01,205 INFO L82 PathProgramCache]: Analyzing trace with hash 1628748997, now seen corresponding path program 10 times [2018-11-18 15:28:01,205 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:01,205 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:01,206 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:01,206 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:28:01,206 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:01,211 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:28:01,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:28:01,235 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:01,236 INFO L82 PathProgramCache]: Analyzing trace with hash 1492189300, now seen corresponding path program 1 times [2018-11-18 15:28:01,236 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:01,236 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:01,236 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:01,236 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:28:01,237 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:01,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:28:01,247 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:28:01,260 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:01,260 INFO L82 PathProgramCache]: Analyzing trace with hash -1648159696, now seen corresponding path program 1 times [2018-11-18 15:28:01,260 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:01,261 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:01,261 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:01,261 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:28:01,261 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:01,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:01,305 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:28:01,305 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:28:01,305 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:28:01,932 WARN L180 SmtUtils]: Spent 617.00 ms on a formula simplification. DAG size of input: 239 DAG size of output: 219 [2018-11-18 15:28:02,187 WARN L180 SmtUtils]: Spent 248.00 ms on a formula simplification that was a NOOP. DAG size: 191 [2018-11-18 15:28:02,200 INFO L216 LassoAnalysis]: Preferences: [2018-11-18 15:28:02,201 INFO L124 ssoRankerPreferences]: Compute integeral hull: false [2018-11-18 15:28:02,201 INFO L125 ssoRankerPreferences]: Enable LassoPartitioneer: true [2018-11-18 15:28:02,201 INFO L126 ssoRankerPreferences]: Term annotations enabled: false [2018-11-18 15:28:02,201 INFO L127 ssoRankerPreferences]: Use exernal solver: true [2018-11-18 15:28:02,201 INFO L128 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 15:28:02,201 INFO L129 ssoRankerPreferences]: Dump SMT script to file: false [2018-11-18 15:28:02,201 INFO L130 ssoRankerPreferences]: Path of dumped script: [2018-11-18 15:28:02,201 INFO L131 ssoRankerPreferences]: Filename of dumped script: token_ring.07_true-unreach-call_false-termination.cil.c_Iteration27_Loop [2018-11-18 15:28:02,201 INFO L132 ssoRankerPreferences]: MapElimAlgo: Frank [2018-11-18 15:28:02,202 INFO L282 LassoAnalysis]: Starting lasso preprocessing... [2018-11-18 15:28:02,226 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,230 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,234 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,235 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,240 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,246 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,252 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,262 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,264 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,267 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,269 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,271 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,276 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,277 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,279 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,282 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,284 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,287 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,288 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,291 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,292 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,296 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,311 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,336 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,350 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,357 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,370 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,376 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,378 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,380 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,386 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,391 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,397 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,402 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,405 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,407 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,414 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,417 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,422 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,426 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,429 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,435 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,440 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,448 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,453 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,471 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,479 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,482 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,485 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,493 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,494 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,496 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,498 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,499 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,502 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,503 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,505 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,507 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,508 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,512 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,516 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,517 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,518 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,520 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,524 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,527 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,529 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,531 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,532 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,536 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,554 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,558 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,565 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:02,568 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,005 INFO L300 LassoAnalysis]: Preprocessing complete. [2018-11-18 15:28:03,006 INFO L412 LassoAnalysis]: Checking for nontermination... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3a6714ee-9413-49e8-b921-8f98627a95b6/bin-2019/uautomizer/z3 Starting monitored process 2 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 15:28:03,016 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-18 15:28:03,016 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-18 15:28:03,022 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-18 15:28:03,022 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~ret1=0} Honda state: {ULTIMATE.start_eval_#t~ret1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3a6714ee-9413-49e8-b921-8f98627a95b6/bin-2019/uautomizer/z3 Starting monitored process 3 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 15:28:03,040 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-18 15:28:03,040 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-18 15:28:03,046 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-18 15:28:03,047 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_stop_simulation_~tmp~2=1, ULTIMATE.start_exists_runnable_thread_#res=1, ULTIMATE.start_exists_runnable_thread_~__retres1~8=1} Honda state: {ULTIMATE.start_stop_simulation_~tmp~2=1, ULTIMATE.start_exists_runnable_thread_#res=1, ULTIMATE.start_exists_runnable_thread_~__retres1~8=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3a6714ee-9413-49e8-b921-8f98627a95b6/bin-2019/uautomizer/z3 Starting monitored process 4 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 15:28:03,081 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-18 15:28:03,081 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-18 15:28:03,087 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-18 15:28:03,087 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_7~0=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_7~0=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3a6714ee-9413-49e8-b921-8f98627a95b6/bin-2019/uautomizer/z3 Starting monitored process 5 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 15:28:03,108 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-18 15:28:03,108 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-18 15:28:03,112 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-18 15:28:03,112 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t4_st~0=-1} Honda state: {~t4_st~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3a6714ee-9413-49e8-b921-8f98627a95b6/bin-2019/uautomizer/z3 Starting monitored process 6 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 15:28:03,130 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-18 15:28:03,131 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-18 15:28:03,135 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-18 15:28:03,136 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_stop_simulation_~__retres2~0=0, ULTIMATE.start_start_simulation_~tmp___0~1=0, ULTIMATE.start_stop_simulation_#res=0} Honda state: {ULTIMATE.start_stop_simulation_~__retres2~0=0, ULTIMATE.start_start_simulation_~tmp___0~1=0, ULTIMATE.start_stop_simulation_#res=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3a6714ee-9413-49e8-b921-8f98627a95b6/bin-2019/uautomizer/z3 Starting monitored process 7 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 15:28:03,170 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-18 15:28:03,170 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-18 15:28:03,176 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-18 15:28:03,176 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~m_pc~0=1} Honda state: {~m_pc~0=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3a6714ee-9413-49e8-b921-8f98627a95b6/bin-2019/uautomizer/z3 Starting monitored process 8 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 15:28:03,196 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-18 15:28:03,196 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-18 15:28:03,199 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-18 15:28:03,200 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~E_3~0=-5} Honda state: {~E_3~0=-5} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3a6714ee-9413-49e8-b921-8f98627a95b6/bin-2019/uautomizer/z3 Starting monitored process 9 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 15:28:03,219 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-18 15:28:03,219 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-18 15:28:03,222 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-18 15:28:03,222 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret14=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret14=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3a6714ee-9413-49e8-b921-8f98627a95b6/bin-2019/uautomizer/z3 Starting monitored process 10 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 15:28:03,241 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-18 15:28:03,241 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-18 15:28:03,243 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-18 15:28:03,243 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret10=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret10=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3a6714ee-9413-49e8-b921-8f98627a95b6/bin-2019/uautomizer/z3 Starting monitored process 11 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 15:28:03,262 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-18 15:28:03,262 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-18 15:28:03,265 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-18 15:28:03,265 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t7_pc~0=4} Honda state: {~t7_pc~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3a6714ee-9413-49e8-b921-8f98627a95b6/bin-2019/uautomizer/z3 Starting monitored process 12 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 15:28:03,285 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-18 15:28:03,285 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-18 15:28:03,291 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-18 15:28:03,291 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_8~0=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_8~0=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3a6714ee-9413-49e8-b921-8f98627a95b6/bin-2019/uautomizer/z3 Starting monitored process 13 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 15:28:03,311 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-18 15:28:03,311 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-18 15:28:03,314 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-18 15:28:03,315 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_~tmp___0~0=0, ULTIMATE.start_is_transmit1_triggered_~__retres1~1=0, ULTIMATE.start_is_transmit1_triggered_#res=0} Honda state: {ULTIMATE.start_activate_threads_~tmp___0~0=0, ULTIMATE.start_is_transmit1_triggered_~__retres1~1=0, ULTIMATE.start_is_transmit1_triggered_#res=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3a6714ee-9413-49e8-b921-8f98627a95b6/bin-2019/uautomizer/z3 Starting monitored process 14 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 15:28:03,335 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-18 15:28:03,335 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-18 15:28:03,338 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-18 15:28:03,338 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet9=0} Honda state: {ULTIMATE.start_eval_#t~nondet9=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3a6714ee-9413-49e8-b921-8f98627a95b6/bin-2019/uautomizer/z3 Starting monitored process 15 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 15:28:03,358 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-18 15:28:03,358 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-18 15:28:03,361 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-18 15:28:03,361 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t3_pc~0=4} Honda state: {~t3_pc~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3a6714ee-9413-49e8-b921-8f98627a95b6/bin-2019/uautomizer/z3 Starting monitored process 16 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 15:28:03,391 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-18 15:28:03,391 INFO L163 nArgumentSynthesizer]: Using integer mode. No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3a6714ee-9413-49e8-b921-8f98627a95b6/bin-2019/uautomizer/z3 Starting monitored process 17 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 15:28:03,414 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2018-11-18 15:28:03,414 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-18 15:28:03,418 INFO L452 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2018-11-18 15:28:03,436 INFO L216 LassoAnalysis]: Preferences: [2018-11-18 15:28:03,436 INFO L124 ssoRankerPreferences]: Compute integeral hull: false [2018-11-18 15:28:03,436 INFO L125 ssoRankerPreferences]: Enable LassoPartitioneer: true [2018-11-18 15:28:03,436 INFO L126 ssoRankerPreferences]: Term annotations enabled: false [2018-11-18 15:28:03,436 INFO L127 ssoRankerPreferences]: Use exernal solver: false [2018-11-18 15:28:03,436 INFO L128 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 15:28:03,437 INFO L129 ssoRankerPreferences]: Dump SMT script to file: false [2018-11-18 15:28:03,437 INFO L130 ssoRankerPreferences]: Path of dumped script: [2018-11-18 15:28:03,437 INFO L131 ssoRankerPreferences]: Filename of dumped script: token_ring.07_true-unreach-call_false-termination.cil.c_Iteration27_Loop [2018-11-18 15:28:03,437 INFO L132 ssoRankerPreferences]: MapElimAlgo: Frank [2018-11-18 15:28:03,437 INFO L282 LassoAnalysis]: Starting lasso preprocessing... [2018-11-18 15:28:03,440 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,456 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,474 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,477 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,483 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,487 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,493 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,501 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,503 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,505 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,508 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,511 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,517 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,539 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,541 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,545 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,551 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,556 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,558 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,560 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,562 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,563 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,569 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,573 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,577 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,585 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,587 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,590 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,594 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,599 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,603 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,609 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,616 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,619 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,623 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,627 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,630 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,633 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,634 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,637 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,639 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,642 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,644 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,647 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,651 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,656 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,657 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,660 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,669 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,670 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,673 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,675 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,677 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,681 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,688 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,695 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,696 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,697 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,701 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,702 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,706 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,707 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,708 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,709 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,712 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,717 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,720 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,721 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,732 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,747 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,780 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,812 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,816 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:03,833 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 15:28:04,249 INFO L300 LassoAnalysis]: Preprocessing complete. [2018-11-18 15:28:04,253 INFO L497 LassoAnalysis]: Using template 'affine'. [2018-11-18 15:28:04,254 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-18 15:28:04,255 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-18 15:28:04,255 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-18 15:28:04,256 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-18 15:28:04,256 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-18 15:28:04,256 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-18 15:28:04,258 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-18 15:28:04,258 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-18 15:28:04,259 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-18 15:28:04,259 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-18 15:28:04,260 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-18 15:28:04,260 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-18 15:28:04,260 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-18 15:28:04,260 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-18 15:28:04,260 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-18 15:28:04,260 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-18 15:28:04,260 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-18 15:28:04,262 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-18 15:28:04,262 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-18 15:28:04,263 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-18 15:28:04,263 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-18 15:28:04,263 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-18 15:28:04,263 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-18 15:28:04,263 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-18 15:28:04,264 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-18 15:28:04,264 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-18 15:28:04,264 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-18 15:28:04,264 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-18 15:28:04,265 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-18 15:28:04,265 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-18 15:28:04,265 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-18 15:28:04,265 INFO L206 nArgumentSynthesizer]: 2 loop disjuncts [2018-11-18 15:28:04,265 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-18 15:28:04,266 INFO L402 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2018-11-18 15:28:04,266 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-18 15:28:04,266 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-18 15:28:04,267 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-18 15:28:04,267 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-18 15:28:04,267 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-18 15:28:04,267 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-18 15:28:04,267 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-18 15:28:04,267 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-18 15:28:04,268 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-18 15:28:04,268 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-18 15:28:04,269 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-18 15:28:04,269 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-18 15:28:04,269 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-18 15:28:04,269 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-18 15:28:04,269 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-18 15:28:04,270 INFO L206 nArgumentSynthesizer]: 2 loop disjuncts [2018-11-18 15:28:04,270 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-18 15:28:04,270 INFO L402 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2018-11-18 15:28:04,270 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-18 15:28:04,271 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-18 15:28:04,272 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-18 15:28:04,272 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-18 15:28:04,272 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-18 15:28:04,272 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-18 15:28:04,272 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-18 15:28:04,272 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-18 15:28:04,273 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-18 15:28:04,273 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-18 15:28:04,274 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-18 15:28:04,275 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-18 15:28:04,275 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-18 15:28:04,275 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-18 15:28:04,275 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-18 15:28:04,275 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-18 15:28:04,275 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-18 15:28:04,276 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-18 15:28:04,276 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-18 15:28:04,276 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-18 15:28:04,277 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-18 15:28:04,277 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-18 15:28:04,277 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-18 15:28:04,277 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-18 15:28:04,277 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-18 15:28:04,277 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-18 15:28:04,278 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-18 15:28:04,278 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-18 15:28:04,278 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-18 15:28:04,279 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-18 15:28:04,279 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-18 15:28:04,279 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-18 15:28:04,279 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-18 15:28:04,280 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-18 15:28:04,280 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-18 15:28:04,280 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-18 15:28:04,280 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-18 15:28:04,281 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-18 15:28:04,281 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-18 15:28:04,281 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-18 15:28:04,281 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-18 15:28:04,281 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-18 15:28:04,281 INFO L206 nArgumentSynthesizer]: 2 loop disjuncts [2018-11-18 15:28:04,282 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-18 15:28:04,282 INFO L402 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2018-11-18 15:28:04,282 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-18 15:28:04,282 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-18 15:28:04,283 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-18 15:28:04,283 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-18 15:28:04,283 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-18 15:28:04,283 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-18 15:28:04,284 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-18 15:28:04,284 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-18 15:28:04,284 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-18 15:28:04,284 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-18 15:28:04,285 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-18 15:28:04,286 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-18 15:28:04,286 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-18 15:28:04,286 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-18 15:28:04,286 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-18 15:28:04,286 INFO L206 nArgumentSynthesizer]: 2 loop disjuncts [2018-11-18 15:28:04,286 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-18 15:28:04,287 INFO L402 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2018-11-18 15:28:04,287 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-18 15:28:04,287 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-18 15:28:04,287 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-18 15:28:04,288 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-18 15:28:04,288 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-18 15:28:04,288 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-18 15:28:04,288 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-18 15:28:04,288 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-18 15:28:04,289 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-18 15:28:04,289 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-18 15:28:04,289 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-18 15:28:04,290 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-18 15:28:04,290 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-18 15:28:04,290 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-18 15:28:04,290 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-18 15:28:04,290 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-18 15:28:04,290 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-18 15:28:04,291 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-18 15:28:04,291 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-18 15:28:04,292 INFO L421 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2018-11-18 15:28:04,295 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2018-11-18 15:28:04,295 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2018-11-18 15:28:04,297 INFO L437 nArgumentSynthesizer]: Simplifying supporting invariants... [2018-11-18 15:28:04,297 INFO L440 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2018-11-18 15:28:04,297 INFO L518 LassoAnalysis]: Proved termination. [2018-11-18 15:28:04,298 INFO L520 LassoAnalysis]: Termination argument consisting of: Ranking function f(~E_5~0) = -1*~E_5~0 + 1 Supporting invariants [] [2018-11-18 15:28:04,299 INFO L297 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2018-11-18 15:28:04,429 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:04,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:04,512 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:28:04,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:04,583 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 15:28:04,659 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:28:04,663 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2018-11-18 15:28:04,664 INFO L72 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 6041 states and 7858 transitions. cyclomatic complexity: 1825 Second operand 5 states. [2018-11-18 15:28:04,939 INFO L76 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 6041 states and 7858 transitions. cyclomatic complexity: 1825. Second operand 5 states. Result 16875 states and 22029 transitions. Complement of second has 5 states. [2018-11-18 15:28:04,939 INFO L142 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2018-11-18 15:28:04,939 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5 states. [2018-11-18 15:28:04,941 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 1080 transitions. [2018-11-18 15:28:04,942 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1080 transitions. Stem has 95 letters. Loop has 113 letters. [2018-11-18 15:28:04,945 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2018-11-18 15:28:04,946 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1080 transitions. Stem has 208 letters. Loop has 113 letters. [2018-11-18 15:28:04,947 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2018-11-18 15:28:04,947 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1080 transitions. Stem has 95 letters. Loop has 226 letters. [2018-11-18 15:28:04,950 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2018-11-18 15:28:04,951 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16875 states and 22029 transitions. [2018-11-18 15:28:05,014 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 11268 [2018-11-18 15:28:05,072 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16875 states to 16867 states and 22021 transitions. [2018-11-18 15:28:05,072 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11434 [2018-11-18 15:28:05,082 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11459 [2018-11-18 15:28:05,082 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16867 states and 22021 transitions. [2018-11-18 15:28:05,082 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-18 15:28:05,082 INFO L705 BuchiCegarLoop]: Abstraction has 16867 states and 22021 transitions. [2018-11-18 15:28:05,092 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16867 states and 22021 transitions. [2018-11-18 15:28:05,361 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16867 to 16834. [2018-11-18 15:28:05,361 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16834 states. [2018-11-18 15:28:05,382 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16834 states to 16834 states and 21964 transitions. [2018-11-18 15:28:05,382 INFO L728 BuchiCegarLoop]: Abstraction has 16834 states and 21964 transitions. [2018-11-18 15:28:05,382 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:28:05,383 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:28:05,383 INFO L87 Difference]: Start difference. First operand 16834 states and 21964 transitions. Second operand 3 states. [2018-11-18 15:28:05,607 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:05,607 INFO L93 Difference]: Finished difference Result 31894 states and 41040 transitions. [2018-11-18 15:28:05,607 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:28:05,608 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 31894 states and 41040 transitions. [2018-11-18 15:28:05,712 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21432 [2018-11-18 15:28:05,783 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 31894 states to 31894 states and 41040 transitions. [2018-11-18 15:28:05,783 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21638 [2018-11-18 15:28:05,799 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21638 [2018-11-18 15:28:05,799 INFO L73 IsDeterministic]: Start isDeterministic. Operand 31894 states and 41040 transitions. [2018-11-18 15:28:05,799 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-18 15:28:05,799 INFO L705 BuchiCegarLoop]: Abstraction has 31894 states and 41040 transitions. [2018-11-18 15:28:05,817 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31894 states and 41040 transitions. [2018-11-18 15:28:06,073 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31894 to 30490. [2018-11-18 15:28:06,074 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 30490 states. [2018-11-18 15:28:06,116 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30490 states to 30490 states and 39336 transitions. [2018-11-18 15:28:06,116 INFO L728 BuchiCegarLoop]: Abstraction has 30490 states and 39336 transitions. [2018-11-18 15:28:06,117 INFO L608 BuchiCegarLoop]: Abstraction has 30490 states and 39336 transitions. [2018-11-18 15:28:06,117 INFO L442 BuchiCegarLoop]: ======== Iteration 28============ [2018-11-18 15:28:06,117 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 30490 states and 39336 transitions. [2018-11-18 15:28:06,187 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 20496 [2018-11-18 15:28:06,187 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:28:06,188 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:28:06,189 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:06,189 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:06,190 INFO L794 eck$LassoCheckResult]: Stem: 306240#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 306073#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 306074#L1131 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 306823#L519 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 306440#L526 assume 1 == ~m_i~0;~m_st~0 := 0; 306441#L526-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 305979#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 305980#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 306824#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 306415#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 305864#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 305604#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 305605#L561-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 307143#L759 assume !(0 == ~M_E~0); 307150#L759-2 assume !(0 == ~T1_E~0); 306549#L764-1 assume !(0 == ~T2_E~0); 306141#L769-1 assume !(0 == ~T3_E~0); 305538#L774-1 assume !(0 == ~T4_E~0); 305539#L779-1 assume !(0 == ~T5_E~0); 306957#L784-1 assume !(0 == ~T6_E~0); 306514#L789-1 assume !(0 == ~T7_E~0); 305749#L794-1 assume !(0 == ~E_M~0); 305750#L799-1 assume !(0 == ~E_1~0); 307077#L804-1 assume !(0 == ~E_2~0); 306771#L809-1 assume !(0 == ~E_3~0); 306327#L814-1 assume !(0 == ~E_4~0); 305386#L819-1 assume !(0 == ~E_5~0); 305387#L824-1 assume !(0 == ~E_6~0); 306713#L829-1 assume !(0 == ~E_7~0); 306458#L834-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 306459#L366 assume !(1 == ~m_pc~0); 306686#L366-2 is_master_triggered_~__retres1~0 := 0; 305924#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 305504#L378 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 305505#L945 assume !(0 != activate_threads_~tmp~1); 306142#L945-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 306143#L385 assume !(1 == ~t1_pc~0); 307129#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 306276#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 305824#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 305825#L953 assume !(0 != activate_threads_~tmp___0~0); 307240#L953-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 307241#L404 assume !(1 == ~t2_pc~0); 307252#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 306512#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 306513#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 306903#L961 assume !(0 != activate_threads_~tmp___1~0); 306904#L961-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 305710#L423 assume !(1 == ~t3_pc~0); 305711#L423-2 is_transmit3_triggered_~__retres1~3 := 0; 305723#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 306740#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 306211#L969 assume !(0 != activate_threads_~tmp___2~0); 306212#L969-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 305747#L442 assume !(1 == ~t4_pc~0); 305725#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 305726#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 306827#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 306945#L977 assume !(0 != activate_threads_~tmp___3~0); 307275#L977-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 306105#L461 assume !(1 == ~t5_pc~0); 306106#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 306108#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 306986#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 306779#L985 assume !(0 != activate_threads_~tmp___4~0); 306780#L985-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 306416#L480 assume !(1 == ~t6_pc~0); 306392#L480-2 is_transmit6_triggered_~__retres1~6 := 0; 306393#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 307222#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 306027#L993 assume !(0 != activate_threads_~tmp___5~0); 306028#L993-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 306032#L499 assume !(1 == ~t7_pc~0); 306670#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 306675#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 307290#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 307156#L1001 assume !(0 != activate_threads_~tmp___6~0); 307157#L1001-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 307158#L847 assume !(1 == ~M_E~0); 307149#L847-2 assume !(1 == ~T1_E~0); 306545#L852-1 assume !(1 == ~T2_E~0); 306134#L857-1 assume !(1 == ~T3_E~0); 305532#L862-1 assume !(1 == ~T4_E~0); 305533#L867-1 assume !(1 == ~T5_E~0); 306954#L872-1 assume !(1 == ~T6_E~0); 306356#L877-1 assume !(1 == ~T7_E~0); 305763#L882-1 assume !(1 == ~E_M~0); 305764#L887-1 assume !(1 == ~E_1~0); 307094#L892-1 assume !(1 == ~E_2~0); 306787#L897-1 assume !(1 == ~E_3~0); 306349#L902-1 assume !(1 == ~E_4~0); 305415#L907-1 assume !(1 == ~E_5~0); 305416#L912-1 assume !(1 == ~E_6~0); 306706#L917-1 assume !(1 == ~E_7~0); 306453#L922-1 assume { :end_inline_reset_delta_events } true; 306454#L1168-3 assume true; 314971#L1168-1 [2018-11-18 15:28:06,190 INFO L796 eck$LassoCheckResult]: Loop: 314971#L1168-1 assume !false; 323943#L1169 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 323941#L734 assume true; 323939#L626-1 assume !false; 323937#L627 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 323934#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 323634#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 323931#L617 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 323929#L631 assume 0 != eval_~tmp~0; 323927#L631-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 323610#L639 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1;assume { :begin_inline_master } true;havoc master_#t~nondet0; 323921#L70 assume 0 == ~m_pc~0; 323918#L95-1 assume true; 323916#L81 assume !false; 323914#L82 ~token~0 := master_#t~nondet0;havoc master_#t~nondet0;~local~0 := ~token~0;~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 323912#L366-3 assume 1 == ~m_pc~0; 323908#L367-1 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0 := 1; 323906#L377-1 is_master_triggered_#res := is_master_triggered_~__retres1~0; 323904#L378-1 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 323902#L945-3 assume !(0 != activate_threads_~tmp~1); 323899#L945-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 323897#L385-3 assume !(1 == ~t1_pc~0); 323893#L385-5 is_transmit1_triggered_~__retres1~1 := 0; 323891#L396-1 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 323889#L397-1 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 323887#L953-3 assume !(0 != activate_threads_~tmp___0~0); 323884#L953-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 323882#L404-3 assume !(1 == ~t2_pc~0); 323878#L404-5 is_transmit2_triggered_~__retres1~2 := 0; 323876#L415-1 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 323874#L416-1 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 323872#L961-3 assume !(0 != activate_threads_~tmp___1~0); 323869#L961-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 323867#L423-3 assume !(1 == ~t3_pc~0); 323865#L423-5 is_transmit3_triggered_~__retres1~3 := 0; 323863#L434-1 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 323861#L435-1 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 323859#L969-3 assume !(0 != activate_threads_~tmp___2~0); 323857#L969-5 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 323851#L442-3 assume !(1 == ~t4_pc~0); 323849#L442-5 is_transmit4_triggered_~__retres1~4 := 0; 323847#L453-1 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 323844#L454-1 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 323843#L977-3 assume !(0 != activate_threads_~tmp___3~0); 323842#L977-5 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 323841#L461-3 assume !(1 == ~t5_pc~0); 323840#L461-5 is_transmit5_triggered_~__retres1~5 := 0; 323832#L472-1 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 323830#L473-1 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 323828#L985-3 assume !(0 != activate_threads_~tmp___4~0); 323824#L985-5 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 323822#L480-3 assume !(1 == ~t6_pc~0); 323818#L480-5 is_transmit6_triggered_~__retres1~6 := 0; 323817#L491-1 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 323816#L492-1 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 323815#L993-3 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 323814#L993-5 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 323806#L499-3 assume !(1 == ~t7_pc~0); 323804#L499-5 is_transmit7_triggered_~__retres1~7 := 0; 327950#L510-1 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 327948#L511-1 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 323796#L1001-3 assume !(0 != activate_threads_~tmp___6~0); 323794#L1001-5 assume { :end_inline_activate_threads } true; 323792#L1018 assume { :end_inline_immediate_notify } true;~E_1~0 := 2;~m_pc~0 := 1;~m_st~0 := 2; 323608#L103 assume { :end_inline_master } true; 323606#L636 assume !(0 == ~t1_st~0); 323521#L650 assume !(0 == ~t2_st~0); 323517#L664 assume !(0 == ~t3_st~0); 323515#L678 assume !(0 == ~t4_st~0); 323651#L692 assume !(0 == ~t5_st~0); 323646#L706 assume !(0 == ~t6_st~0); 323643#L720 assume !(0 == ~t7_st~0); 323638#L734 assume true; 323637#L626-1 assume !false; 323636#L627 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 323633#L574 assume !(0 == ~m_st~0); 323622#L578 assume !(0 == ~t1_st~0); 323623#L582 assume !(0 == ~t2_st~0); 323625#L586 assume !(0 == ~t3_st~0); 323620#L590 assume !(0 == ~t4_st~0); 323621#L594 assume !(0 == ~t5_st~0); 323624#L598 assume !(0 == ~t6_st~0); 323618#L602 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8 := 0; 323619#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 324045#L617 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 324043#L631 assume !(0 != eval_~tmp~0); 324041#L749 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 324039#L519-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 324038#L759-3 assume 0 == ~M_E~0;~M_E~0 := 1; 324035#L759-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 324033#L764-3 assume !(0 == ~T2_E~0); 324031#L769-3 assume !(0 == ~T3_E~0); 324029#L774-3 assume !(0 == ~T4_E~0); 324027#L779-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 324025#L784-3 assume !(0 == ~T6_E~0); 324023#L789-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 324021#L794-3 assume 0 == ~E_M~0;~E_M~0 := 1; 324018#L799-3 assume 0 == ~E_1~0;~E_1~0 := 1; 324016#L804-3 assume !(0 == ~E_2~0); 324014#L809-3 assume !(0 == ~E_3~0); 324012#L814-3 assume !(0 == ~E_4~0); 324010#L819-3 assume !(0 == ~E_5~0); 324008#L824-3 assume !(0 == ~E_6~0); 324006#L829-3 assume 0 == ~E_7~0;~E_7~0 := 1; 324004#L834-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 324002#L366-27 assume !(1 == ~m_pc~0); 324000#L366-29 is_master_triggered_~__retres1~0 := 0; 323996#L377-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 323994#L378-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 323991#L945-27 assume !(0 != activate_threads_~tmp~1); 323989#L945-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 323987#L385-27 assume !(1 == ~t1_pc~0); 323985#L385-29 is_transmit1_triggered_~__retres1~1 := 0; 323983#L396-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 323981#L397-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 323977#L953-27 assume !(0 != activate_threads_~tmp___0~0); 323975#L953-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 323973#L404-27 assume !(1 == ~t2_pc~0); 323969#L404-29 is_transmit2_triggered_~__retres1~2 := 0; 323966#L415-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 323964#L416-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 323960#L961-27 assume !(0 != activate_threads_~tmp___1~0); 323957#L961-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 323955#L423-27 assume !(1 == ~t3_pc~0); 323953#L423-29 is_transmit3_triggered_~__retres1~3 := 0; 323948#L434-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 323942#L435-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 323940#L969-27 assume !(0 != activate_threads_~tmp___2~0); 323938#L969-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 323936#L442-27 assume !(1 == ~t4_pc~0); 323933#L442-29 is_transmit4_triggered_~__retres1~4 := 0; 323932#L453-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 323930#L454-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 323928#L977-27 assume !(0 != activate_threads_~tmp___3~0); 323926#L977-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 323924#L461-27 assume !(1 == ~t5_pc~0); 323923#L461-29 is_transmit5_triggered_~__retres1~5 := 0; 323919#L472-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 323917#L473-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 323915#L985-27 assume !(0 != activate_threads_~tmp___4~0); 323913#L985-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 323911#L480-27 assume !(1 == ~t6_pc~0); 323907#L480-29 is_transmit6_triggered_~__retres1~6 := 0; 323905#L491-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 323903#L492-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 323900#L993-27 assume !(0 != activate_threads_~tmp___5~0); 323898#L993-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 323896#L499-27 assume !(1 == ~t7_pc~0); 323892#L499-29 is_transmit7_triggered_~__retres1~7 := 0; 323890#L510-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 323888#L511-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 323886#L1001-27 assume !(0 != activate_threads_~tmp___6~0); 323883#L1001-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 323879#L847-3 assume 1 == ~M_E~0;~M_E~0 := 2; 323877#L847-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 323875#L852-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 323873#L857-3 assume !(1 == ~T3_E~0); 323870#L862-3 assume !(1 == ~T4_E~0); 323868#L867-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 323866#L872-3 assume !(1 == ~T6_E~0); 323864#L877-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 323862#L882-3 assume 1 == ~E_M~0;~E_M~0 := 2; 323860#L887-3 assume 1 == ~E_1~0;~E_1~0 := 2; 323858#L892-3 assume 1 == ~E_2~0;~E_2~0 := 2; 323856#L897-3 assume !(1 == ~E_3~0); 323855#L902-3 assume !(1 == ~E_4~0); 323854#L907-3 assume !(1 == ~E_5~0); 323853#L912-3 assume !(1 == ~E_6~0); 323850#L917-3 assume 1 == ~E_7~0;~E_7~0 := 2; 323848#L922-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 323845#L574-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 323846#L616-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 324590#L617-1 start_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 324586#L1187 assume !(0 == start_simulation_~tmp~3); 324583#L1187-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret18, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 324581#L574-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 323820#L616-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 324578#L617-2 stop_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret18;havoc stop_simulation_#t~ret18; 324576#L1142 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 324573#L1149 stop_simulation_#res := stop_simulation_~__retres2~0; 324571#L1150 start_simulation_#t~ret20 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 324569#L1200 assume !(0 != start_simulation_~tmp___0~1); 324567#L1168-3 assume true; 314971#L1168-1 [2018-11-18 15:28:06,190 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:06,191 INFO L82 PathProgramCache]: Analyzing trace with hash -1048388204, now seen corresponding path program 1 times [2018-11-18 15:28:06,191 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:06,191 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:06,191 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:06,191 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:28:06,192 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:06,197 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:28:06,203 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:28:06,225 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:06,225 INFO L82 PathProgramCache]: Analyzing trace with hash -826056512, now seen corresponding path program 1 times [2018-11-18 15:28:06,226 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:06,226 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:06,226 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:06,226 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:28:06,226 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:06,231 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:06,280 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:28:06,281 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:28:06,281 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:28:06,281 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:28:06,281 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:28:06,281 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:28:06,281 INFO L87 Difference]: Start difference. First operand 30490 states and 39336 transitions. cyclomatic complexity: 8870 Second operand 3 states. [2018-11-18 15:28:06,444 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:06,447 INFO L93 Difference]: Finished difference Result 41134 states and 52469 transitions. [2018-11-18 15:28:06,449 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:28:06,449 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 41134 states and 52469 transitions. [2018-11-18 15:28:06,576 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 27700 [2018-11-18 15:28:06,663 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 41134 states to 41134 states and 52469 transitions. [2018-11-18 15:28:06,663 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27968 [2018-11-18 15:28:06,679 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27968 [2018-11-18 15:28:06,679 INFO L73 IsDeterministic]: Start isDeterministic. Operand 41134 states and 52469 transitions. [2018-11-18 15:28:06,679 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-18 15:28:06,679 INFO L705 BuchiCegarLoop]: Abstraction has 41134 states and 52469 transitions. [2018-11-18 15:28:06,701 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41134 states and 52469 transitions. [2018-11-18 15:28:06,969 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41134 to 39634. [2018-11-18 15:28:06,969 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 39634 states. [2018-11-18 15:28:07,021 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39634 states to 39634 states and 50669 transitions. [2018-11-18 15:28:07,021 INFO L728 BuchiCegarLoop]: Abstraction has 39634 states and 50669 transitions. [2018-11-18 15:28:07,021 INFO L608 BuchiCegarLoop]: Abstraction has 39634 states and 50669 transitions. [2018-11-18 15:28:07,021 INFO L442 BuchiCegarLoop]: ======== Iteration 29============ [2018-11-18 15:28:07,021 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 39634 states and 50669 transitions. [2018-11-18 15:28:07,200 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 26700 [2018-11-18 15:28:07,200 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:28:07,200 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:28:07,201 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:07,201 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:07,202 INFO L794 eck$LassoCheckResult]: Stem: 377860#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 377699#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 377700#L1131 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 378429#L519 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 378060#L526 assume 1 == ~m_i~0;~m_st~0 := 0; 378061#L526-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 377606#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 377607#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 378430#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 378037#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 377495#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 377231#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 377232#L561-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 378744#L759 assume !(0 == ~M_E~0); 378750#L759-2 assume !(0 == ~T1_E~0); 378164#L764-1 assume !(0 == ~T2_E~0); 377762#L769-1 assume !(0 == ~T3_E~0); 377167#L774-1 assume !(0 == ~T4_E~0); 377168#L779-1 assume !(0 == ~T5_E~0); 378568#L784-1 assume !(0 == ~T6_E~0); 378132#L789-1 assume !(0 == ~T7_E~0); 377379#L794-1 assume !(0 == ~E_M~0); 377380#L799-1 assume !(0 == ~E_1~0); 378676#L804-1 assume !(0 == ~E_2~0); 378379#L809-1 assume !(0 == ~E_3~0); 377947#L814-1 assume !(0 == ~E_4~0); 377016#L819-1 assume !(0 == ~E_5~0); 377017#L824-1 assume !(0 == ~E_6~0); 378322#L829-1 assume !(0 == ~E_7~0); 378077#L834-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 378078#L366 assume !(1 == ~m_pc~0); 378540#L366-2 is_master_triggered_~__retres1~0 := 0; 377552#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 377133#L378 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 377134#L945 assume !(0 != activate_threads_~tmp~1); 377763#L945-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 377764#L385 assume !(1 == ~t1_pc~0); 378730#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 377900#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 377455#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 377456#L953 assume !(0 != activate_threads_~tmp___0~0); 378838#L953-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 378839#L404 assume !(1 == ~t2_pc~0); 378854#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 378130#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 378131#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 378515#L961 assume !(0 != activate_threads_~tmp___1~0); 378516#L961-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 377338#L423 assume !(1 == ~t3_pc~0); 377339#L423-2 is_transmit3_triggered_~__retres1~3 := 0; 377353#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 378348#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 377831#L969 assume !(0 != activate_threads_~tmp___2~0); 377832#L969-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 377377#L442 assume !(1 == ~t4_pc~0); 377355#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 377356#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 378433#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 378558#L977 assume !(0 != activate_threads_~tmp___3~0); 378874#L977-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 377728#L461 assume !(1 == ~t5_pc~0); 377729#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 377732#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 378592#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 378386#L985 assume !(0 != activate_threads_~tmp___4~0); 378387#L985-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 378038#L480 assume !(1 == ~t6_pc~0); 378015#L480-2 is_transmit6_triggered_~__retres1~6 := 0; 378016#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 378820#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 377653#L993 assume !(0 != activate_threads_~tmp___5~0); 377654#L993-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 377657#L499 assume !(1 == ~t7_pc~0); 378282#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 377119#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 377120#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 378755#L1001 assume !(0 != activate_threads_~tmp___6~0); 378756#L1001-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 378757#L847 assume !(1 == ~M_E~0); 378749#L847-2 assume !(1 == ~T1_E~0); 378160#L852-1 assume !(1 == ~T2_E~0); 377756#L857-1 assume !(1 == ~T3_E~0); 377161#L862-1 assume !(1 == ~T4_E~0); 377162#L867-1 assume !(1 == ~T5_E~0); 378565#L872-1 assume !(1 == ~T6_E~0); 377979#L877-1 assume !(1 == ~T7_E~0); 377393#L882-1 assume !(1 == ~E_M~0); 377394#L887-1 assume !(1 == ~E_1~0); 378693#L892-1 assume !(1 == ~E_2~0); 378393#L897-1 assume !(1 == ~E_3~0); 377972#L902-1 assume !(1 == ~E_4~0); 377043#L907-1 assume !(1 == ~E_5~0); 377044#L912-1 assume !(1 == ~E_6~0); 378314#L917-1 assume !(1 == ~E_7~0); 378072#L922-1 assume { :end_inline_reset_delta_events } true; 378073#L1168-3 assume true; 385301#L1168-1 assume !false; 411501#L1169 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 411499#L734 [2018-11-18 15:28:07,202 INFO L796 eck$LassoCheckResult]: Loop: 411499#L734 assume true; 411496#L626-1 assume !false; 397837#L627 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 397832#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 397826#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 397824#L617 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 397822#L631 assume 0 != eval_~tmp~0; 397820#L631-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 397817#L639 assume !(0 != eval_~tmp_ndt_1~0); 397818#L636 assume !(0 == ~t1_st~0); 398602#L650 assume !(0 == ~t2_st~0); 399525#L664 assume !(0 == ~t3_st~0); 399524#L678 assume !(0 == ~t4_st~0); 403233#L692 assume !(0 == ~t5_st~0); 411509#L706 assume !(0 == ~t6_st~0); 411505#L720 assume !(0 == ~t7_st~0); 411499#L734 [2018-11-18 15:28:07,202 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:07,202 INFO L82 PathProgramCache]: Analyzing trace with hash 1816264822, now seen corresponding path program 1 times [2018-11-18 15:28:07,202 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:07,202 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:07,203 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:07,203 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:28:07,203 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:07,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:28:07,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:28:07,235 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:07,235 INFO L82 PathProgramCache]: Analyzing trace with hash -1672281691, now seen corresponding path program 1 times [2018-11-18 15:28:07,235 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:07,235 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:07,235 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:07,235 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:28:07,236 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:07,237 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:28:07,238 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:28:07,240 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:07,240 INFO L82 PathProgramCache]: Analyzing trace with hash 574060570, now seen corresponding path program 1 times [2018-11-18 15:28:07,240 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:07,240 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:07,241 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:07,241 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:28:07,241 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:07,246 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:07,280 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:28:07,280 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:28:07,281 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:28:07,344 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:28:07,345 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:28:07,345 INFO L87 Difference]: Start difference. First operand 39634 states and 50669 transitions. cyclomatic complexity: 11083 Second operand 3 states. [2018-11-18 15:28:07,554 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:07,554 INFO L93 Difference]: Finished difference Result 74974 states and 95135 transitions. [2018-11-18 15:28:07,559 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:28:07,559 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 74974 states and 95135 transitions. [2018-11-18 15:28:07,753 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 49152 [2018-11-18 15:28:07,866 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 74974 states to 74974 states and 95135 transitions. [2018-11-18 15:28:07,866 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 51082 [2018-11-18 15:28:07,890 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 51082 [2018-11-18 15:28:07,890 INFO L73 IsDeterministic]: Start isDeterministic. Operand 74974 states and 95135 transitions. [2018-11-18 15:28:07,890 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-18 15:28:07,890 INFO L705 BuchiCegarLoop]: Abstraction has 74974 states and 95135 transitions. [2018-11-18 15:28:07,922 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74974 states and 95135 transitions. [2018-11-18 15:28:08,269 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74974 to 73048. [2018-11-18 15:28:08,269 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 73048 states. [2018-11-18 15:28:08,344 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73048 states to 73048 states and 92813 transitions. [2018-11-18 15:28:08,344 INFO L728 BuchiCegarLoop]: Abstraction has 73048 states and 92813 transitions. [2018-11-18 15:28:08,344 INFO L608 BuchiCegarLoop]: Abstraction has 73048 states and 92813 transitions. [2018-11-18 15:28:08,344 INFO L442 BuchiCegarLoop]: ======== Iteration 30============ [2018-11-18 15:28:08,344 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 73048 states and 92813 transitions. [2018-11-18 15:28:08,465 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 47868 [2018-11-18 15:28:08,465 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:28:08,465 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:28:08,466 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:08,466 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:08,466 INFO L794 eck$LassoCheckResult]: Stem: 492464#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 492299#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 492300#L1131 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 493036#L519 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 492655#L526 assume 1 == ~m_i~0;~m_st~0 := 0; 492656#L526-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 492206#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 492207#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 493037#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 492633#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 492093#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 491846#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 491847#L561-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 493374#L759 assume !(0 == ~M_E~0); 493381#L759-2 assume !(0 == ~T1_E~0); 492766#L764-1 assume !(0 == ~T2_E~0); 492364#L769-1 assume !(0 == ~T3_E~0); 491783#L774-1 assume !(0 == ~T4_E~0); 491784#L779-1 assume !(0 == ~T5_E~0); 493175#L784-1 assume !(0 == ~T6_E~0); 492728#L789-1 assume !(0 == ~T7_E~0); 491978#L794-1 assume !(0 == ~E_M~0); 491979#L799-1 assume !(0 == ~E_1~0); 493296#L804-1 assume !(0 == ~E_2~0); 492982#L809-1 assume !(0 == ~E_3~0); 492544#L814-1 assume !(0 == ~E_4~0); 491632#L819-1 assume !(0 == ~E_5~0); 491633#L824-1 assume !(0 == ~E_6~0); 492923#L829-1 assume !(0 == ~E_7~0); 492670#L834-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 492671#L366 assume !(1 == ~m_pc~0); 493142#L366-2 is_master_triggered_~__retres1~0 := 0; 492150#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 491749#L378 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 491750#L945 assume !(0 != activate_threads_~tmp~1); 492365#L945-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 492366#L385 assume !(1 == ~t1_pc~0); 493362#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 492503#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 492053#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 492054#L953 assume !(0 != activate_threads_~tmp___0~0); 493485#L953-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 493486#L404 assume !(1 == ~t2_pc~0); 493496#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 492726#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 492727#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 493120#L961 assume !(0 != activate_threads_~tmp___1~0); 493121#L961-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 491942#L423 assume !(1 == ~t3_pc~0); 491943#L423-2 is_transmit3_triggered_~__retres1~3 := 0; 491952#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 492951#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 492433#L969 assume !(0 != activate_threads_~tmp___2~0); 492434#L969-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 491976#L442 assume !(1 == ~t4_pc~0); 491954#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 491955#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 493040#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 498988#L977 assume !(0 != activate_threads_~tmp___3~0); 498982#L977-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 498980#L461 assume !(1 == ~t5_pc~0); 492334#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 492335#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 493205#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 492989#L985 assume !(0 != activate_threads_~tmp___4~0); 492990#L985-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 492634#L480 assume !(1 == ~t6_pc~0); 492610#L480-2 is_transmit6_triggered_~__retres1~6 := 0; 492611#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 493463#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 492251#L993 assume !(0 != activate_threads_~tmp___5~0); 492252#L993-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 492255#L499 assume !(1 == ~t7_pc~0); 492888#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 491735#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 491736#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 493389#L1001 assume !(0 != activate_threads_~tmp___6~0); 493390#L1001-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 493391#L847 assume !(1 == ~M_E~0); 493380#L847-2 assume !(1 == ~T1_E~0); 492761#L852-1 assume !(1 == ~T2_E~0); 492357#L857-1 assume !(1 == ~T3_E~0); 491777#L862-1 assume !(1 == ~T4_E~0); 491778#L867-1 assume !(1 == ~T5_E~0); 493171#L872-1 assume !(1 == ~T6_E~0); 492574#L877-1 assume !(1 == ~T7_E~0); 491992#L882-1 assume !(1 == ~E_M~0); 491993#L887-1 assume !(1 == ~E_1~0); 493313#L892-1 assume !(1 == ~E_2~0); 492995#L897-1 assume !(1 == ~E_3~0); 492566#L902-1 assume !(1 == ~E_4~0); 492567#L907-1 assume !(1 == ~E_5~0); 493228#L912-1 assume !(1 == ~E_6~0); 492916#L917-1 assume !(1 == ~E_7~0); 492666#L922-1 assume { :end_inline_reset_delta_events } true; 492667#L1168-3 assume true; 499709#L1168-1 assume !false; 525980#L1169 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 525971#L734 [2018-11-18 15:28:08,467 INFO L796 eck$LassoCheckResult]: Loop: 525971#L734 assume true; 525962#L626-1 assume !false; 525953#L627 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 525944#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 525937#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 525932#L617 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 525925#L631 assume 0 != eval_~tmp~0; 525919#L631-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 525912#L639 assume !(0 != eval_~tmp_ndt_1~0); 525904#L636 assume !(0 == ~t1_st~0); 525878#L650 assume !(0 == ~t2_st~0); 525874#L664 assume !(0 == ~t3_st~0); 525870#L678 assume !(0 == ~t4_st~0); 525867#L692 assume !(0 == ~t5_st~0); 526024#L706 assume !(0 == ~t6_st~0); 525984#L720 assume !(0 == ~t7_st~0); 525971#L734 [2018-11-18 15:28:08,467 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:08,467 INFO L82 PathProgramCache]: Analyzing trace with hash 932755832, now seen corresponding path program 1 times [2018-11-18 15:28:08,467 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:08,467 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:08,468 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:08,468 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:28:08,468 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:08,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:08,518 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:28:08,518 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:28:08,518 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:28:08,519 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 15:28:08,519 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:08,519 INFO L82 PathProgramCache]: Analyzing trace with hash -1672281691, now seen corresponding path program 2 times [2018-11-18 15:28:08,519 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:08,519 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:08,520 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:08,520 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:28:08,520 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:08,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:28:08,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:28:08,585 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:28:08,585 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:28:08,585 INFO L87 Difference]: Start difference. First operand 73048 states and 92813 transitions. cyclomatic complexity: 19837 Second operand 3 states. [2018-11-18 15:28:08,686 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:08,686 INFO L93 Difference]: Finished difference Result 52859 states and 67205 transitions. [2018-11-18 15:28:08,689 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:28:08,689 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 52859 states and 67205 transitions. [2018-11-18 15:28:09,000 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 35740 [2018-11-18 15:28:09,063 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 52859 states to 52859 states and 67205 transitions. [2018-11-18 15:28:09,063 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 36064 [2018-11-18 15:28:09,077 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 36064 [2018-11-18 15:28:09,077 INFO L73 IsDeterministic]: Start isDeterministic. Operand 52859 states and 67205 transitions. [2018-11-18 15:28:09,078 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-18 15:28:09,078 INFO L705 BuchiCegarLoop]: Abstraction has 52859 states and 67205 transitions. [2018-11-18 15:28:09,101 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52859 states and 67205 transitions. [2018-11-18 15:28:09,353 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52859 to 52859. [2018-11-18 15:28:09,354 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 52859 states. [2018-11-18 15:28:09,402 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52859 states to 52859 states and 67205 transitions. [2018-11-18 15:28:09,402 INFO L728 BuchiCegarLoop]: Abstraction has 52859 states and 67205 transitions. [2018-11-18 15:28:09,402 INFO L608 BuchiCegarLoop]: Abstraction has 52859 states and 67205 transitions. [2018-11-18 15:28:09,402 INFO L442 BuchiCegarLoop]: ======== Iteration 31============ [2018-11-18 15:28:09,402 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 52859 states and 67205 transitions. [2018-11-18 15:28:09,488 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 35740 [2018-11-18 15:28:09,489 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:28:09,489 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:28:09,489 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:09,490 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:09,490 INFO L794 eck$LassoCheckResult]: Stem: 618378#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 618212#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 618213#L1131 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 618935#L519 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 618578#L526 assume 1 == ~m_i~0;~m_st~0 := 0; 618579#L526-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 618123#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 618124#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 618936#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 618554#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 618009#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 617759#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 617760#L561-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 619267#L759 assume !(0 == ~M_E~0); 619274#L759-2 assume !(0 == ~T1_E~0); 618683#L764-1 assume !(0 == ~T2_E~0); 618273#L769-1 assume !(0 == ~T3_E~0); 617696#L774-1 assume !(0 == ~T4_E~0); 617697#L779-1 assume !(0 == ~T5_E~0); 619076#L784-1 assume !(0 == ~T6_E~0); 618647#L789-1 assume !(0 == ~T7_E~0); 617894#L794-1 assume !(0 == ~E_M~0); 617895#L799-1 assume !(0 == ~E_1~0); 619190#L804-1 assume !(0 == ~E_2~0); 618883#L809-1 assume !(0 == ~E_3~0); 618468#L814-1 assume !(0 == ~E_4~0); 617545#L819-1 assume !(0 == ~E_5~0); 617546#L824-1 assume !(0 == ~E_6~0); 618830#L829-1 assume !(0 == ~E_7~0); 618594#L834-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 618595#L366 assume !(1 == ~m_pc~0); 619046#L366-2 is_master_triggered_~__retres1~0 := 0; 618066#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 617662#L378 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 617663#L945 assume !(0 != activate_threads_~tmp~1); 618274#L945-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 618275#L385 assume !(1 == ~t1_pc~0); 619251#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 618420#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 617969#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 617970#L953 assume !(0 != activate_threads_~tmp___0~0); 619371#L953-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 619372#L404 assume !(1 == ~t2_pc~0); 619382#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 618645#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 618646#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 619018#L961 assume !(0 != activate_threads_~tmp___1~0); 619019#L961-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 617857#L423 assume !(1 == ~t3_pc~0); 617858#L423-2 is_transmit3_triggered_~__retres1~3 := 0; 617868#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 618853#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 618347#L969 assume !(0 != activate_threads_~tmp___2~0); 618348#L969-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 617892#L442 assume !(1 == ~t4_pc~0); 617870#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 617871#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 618940#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 619064#L977 assume !(0 != activate_threads_~tmp___3~0); 619405#L977-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 618241#L461 assume !(1 == ~t5_pc~0); 618242#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 618244#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 619100#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 618890#L985 assume !(0 != activate_threads_~tmp___4~0); 618891#L985-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 618555#L480 assume !(1 == ~t6_pc~0); 618532#L480-2 is_transmit6_triggered_~__retres1~6 := 0; 618533#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 619355#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 618167#L993 assume !(0 != activate_threads_~tmp___5~0); 618168#L993-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 618171#L499 assume !(1 == ~t7_pc~0); 618796#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 617648#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 617649#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 619279#L1001 assume !(0 != activate_threads_~tmp___6~0); 619280#L1001-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 619281#L847 assume !(1 == ~M_E~0); 619273#L847-2 assume !(1 == ~T1_E~0); 618678#L852-1 assume !(1 == ~T2_E~0); 618268#L857-1 assume !(1 == ~T3_E~0); 617690#L862-1 assume !(1 == ~T4_E~0); 617691#L867-1 assume !(1 == ~T5_E~0); 619072#L872-1 assume !(1 == ~T6_E~0); 618496#L877-1 assume !(1 == ~T7_E~0); 617909#L882-1 assume !(1 == ~E_M~0); 617910#L887-1 assume !(1 == ~E_1~0); 619207#L892-1 assume !(1 == ~E_2~0); 618896#L897-1 assume !(1 == ~E_3~0); 618489#L902-1 assume !(1 == ~E_4~0); 617572#L907-1 assume !(1 == ~E_5~0); 617573#L912-1 assume !(1 == ~E_6~0); 618824#L917-1 assume !(1 == ~E_7~0); 618590#L922-1 assume { :end_inline_reset_delta_events } true; 618591#L1168-3 assume true; 629110#L1168-1 assume !false; 641114#L1169 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 641102#L734 [2018-11-18 15:28:09,490 INFO L796 eck$LassoCheckResult]: Loop: 641102#L734 assume true; 641095#L626-1 assume !false; 641087#L627 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 641076#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 641067#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 641058#L617 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 641050#L631 assume 0 != eval_~tmp~0; 641042#L631-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 641033#L639 assume !(0 != eval_~tmp_ndt_1~0); 641024#L636 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 641016#L653 assume !(0 != eval_~tmp_ndt_2~0); 641017#L650 assume !(0 == ~t2_st~0); 641262#L664 assume !(0 == ~t3_st~0); 641258#L678 assume !(0 == ~t4_st~0); 641227#L692 assume !(0 == ~t5_st~0); 641122#L706 assume !(0 == ~t6_st~0); 641118#L720 assume !(0 == ~t7_st~0); 641102#L734 [2018-11-18 15:28:09,490 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:09,490 INFO L82 PathProgramCache]: Analyzing trace with hash 1816264822, now seen corresponding path program 2 times [2018-11-18 15:28:09,490 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:09,491 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:09,491 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:09,491 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:28:09,491 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:09,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:28:09,502 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:28:09,522 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:09,522 INFO L82 PathProgramCache]: Analyzing trace with hash -1153594177, now seen corresponding path program 1 times [2018-11-18 15:28:09,522 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:09,523 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:09,523 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:09,523 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:28:09,523 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:09,524 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:28:09,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:28:09,527 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:09,527 INFO L82 PathProgramCache]: Analyzing trace with hash -236460822, now seen corresponding path program 1 times [2018-11-18 15:28:09,527 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:09,527 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:09,528 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:09,528 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:28:09,528 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:09,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:09,560 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:28:09,560 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:28:09,560 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:28:09,663 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:28:09,663 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:28:09,663 INFO L87 Difference]: Start difference. First operand 52859 states and 67205 transitions. cyclomatic complexity: 14394 Second operand 3 states. [2018-11-18 15:28:09,866 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:09,866 INFO L93 Difference]: Finished difference Result 100948 states and 127822 transitions. [2018-11-18 15:28:09,866 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:28:09,866 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 100948 states and 127822 transitions. [2018-11-18 15:28:10,079 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 68376 [2018-11-18 15:28:10,220 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 100948 states to 100948 states and 127822 transitions. [2018-11-18 15:28:10,220 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 68916 [2018-11-18 15:28:10,251 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 68916 [2018-11-18 15:28:10,251 INFO L73 IsDeterministic]: Start isDeterministic. Operand 100948 states and 127822 transitions. [2018-11-18 15:28:10,251 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-18 15:28:10,251 INFO L705 BuchiCegarLoop]: Abstraction has 100948 states and 127822 transitions. [2018-11-18 15:28:10,294 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100948 states and 127822 transitions. [2018-11-18 15:28:10,995 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100948 to 96088. [2018-11-18 15:28:10,996 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 96088 states. [2018-11-18 15:28:11,090 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 96088 states to 96088 states and 122044 transitions. [2018-11-18 15:28:11,090 INFO L728 BuchiCegarLoop]: Abstraction has 96088 states and 122044 transitions. [2018-11-18 15:28:11,090 INFO L608 BuchiCegarLoop]: Abstraction has 96088 states and 122044 transitions. [2018-11-18 15:28:11,090 INFO L442 BuchiCegarLoop]: ======== Iteration 32============ [2018-11-18 15:28:11,090 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 96088 states and 122044 transitions. [2018-11-18 15:28:11,248 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 65136 [2018-11-18 15:28:11,249 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:28:11,249 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:28:11,249 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:11,250 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:11,250 INFO L794 eck$LassoCheckResult]: Stem: 772209#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 772038#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 772039#L1131 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 772805#L519 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 772409#L526 assume 1 == ~m_i~0;~m_st~0 := 0; 772410#L526-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 771944#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 771945#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 772806#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 772385#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 771832#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 771575#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 771576#L561-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 773144#L759 assume !(0 == ~M_E~0); 773151#L759-2 assume !(0 == ~T1_E~0); 772519#L764-1 assume !(0 == ~T2_E~0); 772105#L769-1 assume !(0 == ~T3_E~0); 771511#L774-1 assume !(0 == ~T4_E~0); 771512#L779-1 assume !(0 == ~T5_E~0); 772949#L784-1 assume !(0 == ~T6_E~0); 772481#L789-1 assume !(0 == ~T7_E~0); 771717#L794-1 assume !(0 == ~E_M~0); 771718#L799-1 assume !(0 == ~E_1~0); 773073#L804-1 assume !(0 == ~E_2~0); 772754#L809-1 assume !(0 == ~E_3~0); 772297#L814-1 assume !(0 == ~E_4~0); 771360#L819-1 assume !(0 == ~E_5~0); 771361#L824-1 assume !(0 == ~E_6~0); 772698#L829-1 assume !(0 == ~E_7~0); 772425#L834-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 772426#L366 assume !(1 == ~m_pc~0); 772918#L366-2 is_master_triggered_~__retres1~0 := 0; 771886#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 771477#L378 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 771478#L945 assume !(0 != activate_threads_~tmp~1); 772106#L945-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 772107#L385 assume !(1 == ~t1_pc~0); 773131#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 772250#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 771792#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 771793#L953 assume !(0 != activate_threads_~tmp___0~0); 773257#L953-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 773258#L404 assume !(1 == ~t2_pc~0); 773270#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 772479#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 772480#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 772889#L961 assume !(0 != activate_threads_~tmp___1~0); 772890#L961-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 771679#L423 assume !(1 == ~t3_pc~0); 771680#L423-2 is_transmit3_triggered_~__retres1~3 := 0; 771690#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 772723#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 772178#L969 assume !(0 != activate_threads_~tmp___2~0); 772179#L969-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 771715#L442 assume !(1 == ~t4_pc~0); 771693#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 771694#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 772809#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 772938#L977 assume !(0 != activate_threads_~tmp___3~0); 773294#L977-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 772072#L461 assume !(1 == ~t5_pc~0); 772073#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 772075#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 772976#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 772762#L985 assume !(0 != activate_threads_~tmp___4~0); 772763#L985-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 772386#L480 assume !(1 == ~t6_pc~0); 772362#L480-2 is_transmit6_triggered_~__retres1~6 := 0; 772363#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 773235#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 771991#L993 assume !(0 != activate_threads_~tmp___5~0); 771992#L993-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 771995#L499 assume !(1 == ~t7_pc~0); 772647#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 771463#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 771464#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 773162#L1001 assume !(0 != activate_threads_~tmp___6~0); 773163#L1001-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 773164#L847 assume !(1 == ~M_E~0); 773150#L847-2 assume !(1 == ~T1_E~0); 772511#L852-1 assume !(1 == ~T2_E~0); 772098#L857-1 assume !(1 == ~T3_E~0); 771505#L862-1 assume !(1 == ~T4_E~0); 771506#L867-1 assume !(1 == ~T5_E~0); 772945#L872-1 assume !(1 == ~T6_E~0); 772327#L877-1 assume !(1 == ~T7_E~0); 771732#L882-1 assume !(1 == ~E_M~0); 771733#L887-1 assume !(1 == ~E_1~0); 773089#L892-1 assume !(1 == ~E_2~0); 772769#L897-1 assume !(1 == ~E_3~0); 772320#L902-1 assume !(1 == ~E_4~0); 771387#L907-1 assume !(1 == ~E_5~0); 771388#L912-1 assume !(1 == ~E_6~0); 772691#L917-1 assume !(1 == ~E_7~0); 772420#L922-1 assume { :end_inline_reset_delta_events } true; 772421#L1168-3 assume true; 789038#L1168-1 assume !false; 816685#L1169 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 816683#L734 [2018-11-18 15:28:11,250 INFO L796 eck$LassoCheckResult]: Loop: 816683#L734 assume true; 816682#L626-1 assume !false; 816681#L627 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 816680#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 816679#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 816678#L617 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 816677#L631 assume 0 != eval_~tmp~0; 816675#L631-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 816672#L639 assume !(0 != eval_~tmp_ndt_1~0); 816671#L636 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 816668#L653 assume !(0 != eval_~tmp_ndt_2~0); 816192#L650 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 816189#L667 assume !(0 != eval_~tmp_ndt_3~0); 816187#L664 assume !(0 == ~t3_st~0); 816181#L678 assume !(0 == ~t4_st~0); 816179#L692 assume !(0 == ~t5_st~0); 816692#L706 assume !(0 == ~t6_st~0); 816689#L720 assume !(0 == ~t7_st~0); 816683#L734 [2018-11-18 15:28:11,250 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:11,250 INFO L82 PathProgramCache]: Analyzing trace with hash 1816264822, now seen corresponding path program 3 times [2018-11-18 15:28:11,250 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:11,250 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:11,251 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:11,251 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:28:11,251 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:11,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:28:11,262 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:28:11,284 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:11,284 INFO L82 PathProgramCache]: Analyzing trace with hash -874988305, now seen corresponding path program 1 times [2018-11-18 15:28:11,284 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:11,284 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:11,285 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:11,285 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:28:11,285 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:11,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:28:11,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:28:11,290 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:11,290 INFO L82 PathProgramCache]: Analyzing trace with hash 1786341924, now seen corresponding path program 1 times [2018-11-18 15:28:11,290 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:11,290 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:11,291 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:11,295 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:28:11,295 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:11,299 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:11,324 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:28:11,324 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:28:11,324 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:28:11,410 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:28:11,410 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:28:11,411 INFO L87 Difference]: Start difference. First operand 96088 states and 122044 transitions. cyclomatic complexity: 26004 Second operand 3 states. [2018-11-18 15:28:11,664 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:11,664 INFO L93 Difference]: Finished difference Result 127150 states and 160795 transitions. [2018-11-18 15:28:11,664 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:28:11,665 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 127150 states and 160795 transitions. [2018-11-18 15:28:11,953 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 86532 [2018-11-18 15:28:12,140 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 127150 states to 127150 states and 160795 transitions. [2018-11-18 15:28:12,140 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 87216 [2018-11-18 15:28:12,178 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 87216 [2018-11-18 15:28:12,179 INFO L73 IsDeterministic]: Start isDeterministic. Operand 127150 states and 160795 transitions. [2018-11-18 15:28:12,179 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-18 15:28:12,179 INFO L705 BuchiCegarLoop]: Abstraction has 127150 states and 160795 transitions. [2018-11-18 15:28:12,232 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 127150 states and 160795 transitions. [2018-11-18 15:28:14,859 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 127150 to 127150. [2018-11-18 15:28:14,859 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 127150 states. [2018-11-18 15:28:14,988 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 127150 states to 127150 states and 160795 transitions. [2018-11-18 15:28:14,989 INFO L728 BuchiCegarLoop]: Abstraction has 127150 states and 160795 transitions. [2018-11-18 15:28:14,989 INFO L608 BuchiCegarLoop]: Abstraction has 127150 states and 160795 transitions. [2018-11-18 15:28:14,989 INFO L442 BuchiCegarLoop]: ======== Iteration 33============ [2018-11-18 15:28:14,989 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 127150 states and 160795 transitions. [2018-11-18 15:28:15,208 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 86532 [2018-11-18 15:28:15,208 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:28:15,208 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:28:15,208 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:15,209 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:15,209 INFO L794 eck$LassoCheckResult]: Stem: 995453#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 995286#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 995287#L1131 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 996037#L519 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 995654#L526 assume 1 == ~m_i~0;~m_st~0 := 0; 995655#L526-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 995191#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 995192#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 996038#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 995630#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 995079#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 994820#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 994821#L561-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 996379#L759 assume !(0 == ~M_E~0); 996386#L759-2 assume !(0 == ~T1_E~0); 995765#L764-1 assume !(0 == ~T2_E~0); 995351#L769-1 assume !(0 == ~T3_E~0); 994754#L774-1 assume !(0 == ~T4_E~0); 994755#L779-1 assume !(0 == ~T5_E~0); 996182#L784-1 assume !(0 == ~T6_E~0); 995729#L789-1 assume !(0 == ~T7_E~0); 994961#L794-1 assume !(0 == ~E_M~0); 994962#L799-1 assume !(0 == ~E_1~0); 996311#L804-1 assume !(0 == ~E_2~0); 995985#L809-1 assume !(0 == ~E_3~0); 995538#L814-1 assume !(0 == ~E_4~0); 994606#L819-1 assume !(0 == ~E_5~0); 994607#L824-1 assume !(0 == ~E_6~0); 995927#L829-1 assume !(0 == ~E_7~0); 995670#L834-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 995671#L366 assume !(1 == ~m_pc~0); 996147#L366-2 is_master_triggered_~__retres1~0 := 0; 995135#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 994722#L378 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 994723#L945 assume !(0 != activate_threads_~tmp~1); 995352#L945-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 995353#L385 assume !(1 == ~t1_pc~0); 996366#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 995489#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 995039#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 995040#L953 assume !(0 != activate_threads_~tmp___0~0); 996482#L953-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 996483#L404 assume !(1 == ~t2_pc~0); 996492#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 995728#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 995656#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 995657#L961 assume !(0 != activate_threads_~tmp___1~0); 996121#L961-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 994924#L423 assume !(1 == ~t3_pc~0); 994925#L423-2 is_transmit3_triggered_~__retres1~3 := 0; 994935#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 995955#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 995424#L969 assume !(0 != activate_threads_~tmp___2~0); 995425#L969-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 994959#L442 assume !(1 == ~t4_pc~0); 994937#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 994938#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 996041#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 996170#L977 assume !(0 != activate_threads_~tmp___3~0); 996515#L977-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 995317#L461 assume !(1 == ~t5_pc~0); 995318#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 995320#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 996214#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 995991#L985 assume !(0 != activate_threads_~tmp___4~0); 995992#L985-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 995631#L480 assume !(1 == ~t6_pc~0); 995607#L480-2 is_transmit6_triggered_~__retres1~6 := 0; 995608#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 996460#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 995236#L993 assume !(0 != activate_threads_~tmp___5~0); 995237#L993-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 995240#L499 assume !(1 == ~t7_pc~0); 995883#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 994709#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 994599#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 994600#L1001 assume !(0 != activate_threads_~tmp___6~0); 996391#L1001-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 996392#L847 assume !(1 == ~M_E~0); 996385#L847-2 assume !(1 == ~T1_E~0); 995760#L852-1 assume !(1 == ~T2_E~0); 995345#L857-1 assume !(1 == ~T3_E~0); 994748#L862-1 assume !(1 == ~T4_E~0); 994749#L867-1 assume !(1 == ~T5_E~0); 996179#L872-1 assume !(1 == ~T6_E~0); 995571#L877-1 assume !(1 == ~T7_E~0); 994977#L882-1 assume !(1 == ~E_M~0); 994978#L887-1 assume !(1 == ~E_1~0); 996329#L892-1 assume !(1 == ~E_2~0); 995998#L897-1 assume !(1 == ~E_3~0); 995564#L902-1 assume !(1 == ~E_4~0); 994633#L907-1 assume !(1 == ~E_5~0); 994634#L912-1 assume !(1 == ~E_6~0); 995919#L917-1 assume !(1 == ~E_7~0); 995666#L922-1 assume { :end_inline_reset_delta_events } true; 995667#L1168-3 assume true; 1021644#L1168-1 assume !false; 1062735#L1169 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 1062732#L734 [2018-11-18 15:28:15,209 INFO L796 eck$LassoCheckResult]: Loop: 1062732#L734 assume true; 1062730#L626-1 assume !false; 1062728#L627 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 1062727#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 1062726#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 1062724#L617 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 1062723#L631 assume 0 != eval_~tmp~0; 1062722#L631-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 1062719#L639 assume !(0 != eval_~tmp_ndt_1~0); 1062718#L636 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 1062717#L653 assume !(0 != eval_~tmp_ndt_2~0); 1057046#L650 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 1057043#L667 assume !(0 != eval_~tmp_ndt_3~0); 1057041#L664 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 1057038#L681 assume !(0 != eval_~tmp_ndt_4~0); 1057039#L678 assume !(0 == ~t4_st~0); 1062771#L692 assume !(0 == ~t5_st~0); 1062743#L706 assume !(0 == ~t6_st~0); 1062739#L720 assume !(0 == ~t7_st~0); 1062732#L734 [2018-11-18 15:28:15,209 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:15,209 INFO L82 PathProgramCache]: Analyzing trace with hash 1816264822, now seen corresponding path program 4 times [2018-11-18 15:28:15,209 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:15,209 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:15,210 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:15,210 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:28:15,210 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:15,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:28:15,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:28:15,243 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:15,243 INFO L82 PathProgramCache]: Analyzing trace with hash 601821557, now seen corresponding path program 1 times [2018-11-18 15:28:15,243 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:15,243 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:15,244 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:15,244 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:28:15,244 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:15,246 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:28:15,247 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:28:15,248 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:15,248 INFO L82 PathProgramCache]: Analyzing trace with hash 1498680032, now seen corresponding path program 1 times [2018-11-18 15:28:15,249 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:15,249 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:15,249 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:15,249 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:28:15,249 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:15,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:15,296 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:28:15,296 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:28:15,297 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:28:15,403 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:28:15,403 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:28:15,403 INFO L87 Difference]: Start difference. First operand 127150 states and 160795 transitions. cyclomatic complexity: 33693 Second operand 3 states. [2018-11-18 15:28:15,837 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:15,837 INFO L93 Difference]: Finished difference Result 236276 states and 298058 transitions. [2018-11-18 15:28:15,838 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:28:15,838 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 236276 states and 298058 transitions. [2018-11-18 15:28:16,394 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 158696 [2018-11-18 15:28:17,191 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 236276 states to 236276 states and 298058 transitions. [2018-11-18 15:28:17,192 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 159956 [2018-11-18 15:28:17,238 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 159956 [2018-11-18 15:28:17,239 INFO L73 IsDeterministic]: Start isDeterministic. Operand 236276 states and 298058 transitions. [2018-11-18 15:28:17,239 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-18 15:28:17,239 INFO L705 BuchiCegarLoop]: Abstraction has 236276 states and 298058 transitions. [2018-11-18 15:28:17,322 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 236276 states and 298058 transitions. [2018-11-18 15:28:18,469 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 236276 to 236276. [2018-11-18 15:28:18,469 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 236276 states. [2018-11-18 15:28:18,739 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 236276 states to 236276 states and 298058 transitions. [2018-11-18 15:28:18,739 INFO L728 BuchiCegarLoop]: Abstraction has 236276 states and 298058 transitions. [2018-11-18 15:28:18,740 INFO L608 BuchiCegarLoop]: Abstraction has 236276 states and 298058 transitions. [2018-11-18 15:28:18,740 INFO L442 BuchiCegarLoop]: ======== Iteration 34============ [2018-11-18 15:28:18,740 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 236276 states and 298058 transitions. [2018-11-18 15:28:19,174 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 158696 [2018-11-18 15:28:19,174 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:28:19,174 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:28:19,175 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:19,175 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:19,176 INFO L794 eck$LassoCheckResult]: Stem: 1358876#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1358706#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1358707#L1131 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 1359466#L519 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1359082#L526 assume 1 == ~m_i~0;~m_st~0 := 0; 1359083#L526-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1358618#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1358619#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1359467#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1359057#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1358505#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1358252#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1358253#L561-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1359803#L759 assume !(0 == ~M_E~0); 1359809#L759-2 assume !(0 == ~T1_E~0); 1359189#L764-1 assume !(0 == ~T2_E~0); 1358774#L769-1 assume !(0 == ~T3_E~0); 1358188#L774-1 assume !(0 == ~T4_E~0); 1358189#L779-1 assume !(0 == ~T5_E~0); 1359614#L784-1 assume !(0 == ~T6_E~0); 1359157#L789-1 assume !(0 == ~T7_E~0); 1358388#L794-1 assume !(0 == ~E_M~0); 1358389#L799-1 assume !(0 == ~E_1~0); 1359735#L804-1 assume !(0 == ~E_2~0); 1359413#L809-1 assume !(0 == ~E_3~0); 1358966#L814-1 assume !(0 == ~E_4~0); 1358040#L819-1 assume !(0 == ~E_5~0); 1358041#L824-1 assume !(0 == ~E_6~0); 1359354#L829-1 assume !(0 == ~E_7~0); 1359099#L834-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1359100#L366 assume !(1 == ~m_pc~0); 1359577#L366-2 is_master_triggered_~__retres1~0 := 0; 1358560#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1358156#L378 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1358157#L945 assume !(0 != activate_threads_~tmp~1); 1358775#L945-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1358776#L385 assume !(1 == ~t1_pc~0); 1359787#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 1358915#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1358465#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1358466#L953 assume !(0 != activate_threads_~tmp___0~0); 1359898#L953-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1359899#L404 assume !(1 == ~t2_pc~0); 1359909#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 1359156#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1359084#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1359085#L961 assume !(0 != activate_threads_~tmp___1~0); 1359555#L961-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1358351#L423 assume !(1 == ~t3_pc~0); 1358352#L423-2 is_transmit3_triggered_~__retres1~3 := 0; 1358362#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1359380#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1358845#L969 assume !(0 != activate_threads_~tmp___2~0); 1358846#L969-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1358386#L442 assume !(1 == ~t4_pc~0); 1358364#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 1358365#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1359470#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1359601#L977 assume !(0 != activate_threads_~tmp___3~0); 1359928#L977-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1358738#L461 assume !(1 == ~t5_pc~0); 1358739#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 1358741#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1359642#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1359420#L985 assume !(0 != activate_threads_~tmp___4~0); 1359421#L985-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1359058#L480 assume !(1 == ~t6_pc~0); 1359029#L480-2 is_transmit6_triggered_~__retres1~6 := 0; 1359030#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1359876#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1358661#L993 assume !(0 != activate_threads_~tmp___5~0); 1358662#L993-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1358665#L499 assume !(1 == ~t7_pc~0); 1359308#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 1358143#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1358033#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1358034#L1001 assume !(0 != activate_threads_~tmp___6~0); 1359812#L1001-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1359813#L847 assume !(1 == ~M_E~0); 1359808#L847-2 assume !(1 == ~T1_E~0); 1359186#L852-1 assume !(1 == ~T2_E~0); 1358767#L857-1 assume !(1 == ~T3_E~0); 1358182#L862-1 assume !(1 == ~T4_E~0); 1358183#L867-1 assume !(1 == ~T5_E~0); 1359611#L872-1 assume !(1 == ~T6_E~0); 1358994#L877-1 assume !(1 == ~T7_E~0); 1358403#L882-1 assume !(1 == ~E_M~0); 1358404#L887-1 assume !(1 == ~E_1~0); 1359749#L892-1 assume !(1 == ~E_2~0); 1359427#L897-1 assume !(1 == ~E_3~0); 1358987#L902-1 assume !(1 == ~E_4~0); 1358067#L907-1 assume !(1 == ~E_5~0); 1358068#L912-1 assume !(1 == ~E_6~0); 1359346#L917-1 assume !(1 == ~E_7~0); 1359094#L922-1 assume { :end_inline_reset_delta_events } true; 1359095#L1168-3 assume true; 1411078#L1168-1 assume !false; 1452937#L1169 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 1452935#L734 [2018-11-18 15:28:19,176 INFO L796 eck$LassoCheckResult]: Loop: 1452935#L734 assume true; 1452934#L626-1 assume !false; 1452933#L627 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 1452931#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 1452929#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 1452927#L617 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 1452926#L631 assume 0 != eval_~tmp~0; 1452924#L631-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 1452921#L639 assume !(0 != eval_~tmp_ndt_1~0); 1452922#L636 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 1467372#L653 assume !(0 != eval_~tmp_ndt_2~0); 1467193#L650 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 1467189#L667 assume !(0 != eval_~tmp_ndt_3~0); 1467190#L664 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 1483149#L681 assume !(0 != eval_~tmp_ndt_4~0); 1452958#L678 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 1452953#L695 assume !(0 != eval_~tmp_ndt_5~0); 1452951#L692 assume !(0 == ~t5_st~0); 1452945#L706 assume !(0 == ~t6_st~0); 1452941#L720 assume !(0 == ~t7_st~0); 1452935#L734 [2018-11-18 15:28:19,176 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:19,176 INFO L82 PathProgramCache]: Analyzing trace with hash 1816264822, now seen corresponding path program 5 times [2018-11-18 15:28:19,176 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:19,176 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:19,177 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:19,177 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:28:19,177 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:19,182 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:28:19,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:28:19,210 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:19,210 INFO L82 PathProgramCache]: Analyzing trace with hash 1262624825, now seen corresponding path program 1 times [2018-11-18 15:28:19,211 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:19,211 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:19,211 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:19,211 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:28:19,211 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:19,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:28:19,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:28:19,216 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:19,216 INFO L82 PathProgramCache]: Analyzing trace with hash -999533522, now seen corresponding path program 1 times [2018-11-18 15:28:19,216 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:19,216 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:19,217 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:19,217 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:28:19,217 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:19,222 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:19,271 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:28:19,271 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:28:19,271 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:28:19,371 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:28:19,371 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:28:19,371 INFO L87 Difference]: Start difference. First operand 236276 states and 298058 transitions. cyclomatic complexity: 61830 Second operand 3 states. [2018-11-18 15:28:20,557 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:20,557 INFO L93 Difference]: Finished difference Result 342451 states and 432115 transitions. [2018-11-18 15:28:20,557 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:28:20,557 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 342451 states and 432115 transitions. [2018-11-18 15:28:21,419 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 230380 [2018-11-18 15:28:21,934 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 342451 states to 342451 states and 432115 transitions. [2018-11-18 15:28:21,934 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 232000 [2018-11-18 15:28:22,034 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 232000 [2018-11-18 15:28:22,034 INFO L73 IsDeterministic]: Start isDeterministic. Operand 342451 states and 432115 transitions. [2018-11-18 15:28:22,035 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-18 15:28:22,035 INFO L705 BuchiCegarLoop]: Abstraction has 342451 states and 432115 transitions. [2018-11-18 15:28:22,176 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 342451 states and 432115 transitions. [2018-11-18 15:28:24,420 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 342451 to 335323. [2018-11-18 15:28:24,420 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 335323 states. [2018-11-18 15:28:24,819 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 335323 states to 335323 states and 423043 transitions. [2018-11-18 15:28:24,819 INFO L728 BuchiCegarLoop]: Abstraction has 335323 states and 423043 transitions. [2018-11-18 15:28:24,819 INFO L608 BuchiCegarLoop]: Abstraction has 335323 states and 423043 transitions. [2018-11-18 15:28:24,819 INFO L442 BuchiCegarLoop]: ======== Iteration 35============ [2018-11-18 15:28:24,819 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 335323 states and 423043 transitions. [2018-11-18 15:28:25,422 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 225628 [2018-11-18 15:28:25,422 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:28:25,422 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:28:25,423 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:25,423 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:25,423 INFO L794 eck$LassoCheckResult]: Stem: 1937648#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 1937464#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1937465#L1131 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 1938278#L519 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1937870#L526 assume 1 == ~m_i~0;~m_st~0 := 0; 1937871#L526-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1937367#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1937368#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1938279#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1937845#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1937253#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1936987#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1936988#L561-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1938647#L759 assume !(0 == ~M_E~0); 1938655#L759-2 assume !(0 == ~T1_E~0); 1937978#L764-1 assume !(0 == ~T2_E~0); 1937543#L769-1 assume !(0 == ~T3_E~0); 1936923#L774-1 assume !(0 == ~T4_E~0); 1936924#L779-1 assume !(0 == ~T5_E~0); 1938431#L784-1 assume !(0 == ~T6_E~0); 1937944#L789-1 assume !(0 == ~T7_E~0); 1937133#L794-1 assume !(0 == ~E_M~0); 1937134#L799-1 assume !(0 == ~E_1~0); 1938559#L804-1 assume !(0 == ~E_2~0); 1938223#L809-1 assume !(0 == ~E_3~0); 1937748#L814-1 assume !(0 == ~E_4~0); 1936775#L819-1 assume !(0 == ~E_5~0); 1936776#L824-1 assume !(0 == ~E_6~0); 1938158#L829-1 assume !(0 == ~E_7~0); 1937886#L834-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1937887#L366 assume !(1 == ~m_pc~0); 1938393#L366-2 is_master_triggered_~__retres1~0 := 0; 1937311#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1936891#L378 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1936892#L945 assume !(0 != activate_threads_~tmp~1); 1937544#L945-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1937545#L385 assume !(1 == ~t1_pc~0); 1938627#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 1937687#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1937211#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1937212#L953 assume !(0 != activate_threads_~tmp___0~0); 1938763#L953-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1938764#L404 assume !(1 == ~t2_pc~0); 1938775#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 1937943#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1937872#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1937873#L961 assume !(0 != activate_threads_~tmp___1~0); 1938363#L961-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1937090#L423 assume !(1 == ~t3_pc~0); 1937091#L423-2 is_transmit3_triggered_~__retres1~3 := 0; 1937106#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1938189#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1937614#L969 assume !(0 != activate_threads_~tmp___2~0); 1937615#L969-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1937131#L442 assume !(1 == ~t4_pc~0); 1937108#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 1937109#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1938282#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1938420#L977 assume !(0 != activate_threads_~tmp___3~0); 1938792#L977-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1937499#L461 assume !(1 == ~t5_pc~0); 1937500#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 1937502#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1938463#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1938231#L985 assume !(0 != activate_threads_~tmp___4~0); 1938232#L985-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1937846#L480 assume !(1 == ~t6_pc~0); 1937815#L480-2 is_transmit6_triggered_~__retres1~6 := 0; 1937816#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1938741#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1937414#L993 assume !(0 != activate_threads_~tmp___5~0); 1937415#L993-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1937418#L499 assume !(1 == ~t7_pc~0); 1938115#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 1936878#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1936768#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1936769#L1001 assume !(0 != activate_threads_~tmp___6~0); 1938664#L1001-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1938665#L847 assume !(1 == ~M_E~0); 1938654#L847-2 assume !(1 == ~T1_E~0); 1937974#L852-1 assume !(1 == ~T2_E~0); 1937536#L857-1 assume !(1 == ~T3_E~0); 1936917#L862-1 assume !(1 == ~T4_E~0); 1936918#L867-1 assume !(1 == ~T5_E~0); 1938428#L872-1 assume !(1 == ~T6_E~0); 1937780#L877-1 assume !(1 == ~T7_E~0); 1937149#L882-1 assume !(1 == ~E_M~0); 1937150#L887-1 assume !(1 == ~E_1~0); 1938575#L892-1 assume !(1 == ~E_2~0); 1938237#L897-1 assume !(1 == ~E_3~0); 1937773#L902-1 assume !(1 == ~E_4~0); 1936802#L907-1 assume !(1 == ~E_5~0); 1936803#L912-1 assume !(1 == ~E_6~0); 1938150#L917-1 assume !(1 == ~E_7~0); 1937882#L922-1 assume { :end_inline_reset_delta_events } true; 1937883#L1168-3 assume true; 1966507#L1168-1 assume !false; 1991171#L1169 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 1991169#L734 [2018-11-18 15:28:25,423 INFO L796 eck$LassoCheckResult]: Loop: 1991169#L734 assume true; 1991167#L626-1 assume !false; 1991162#L627 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 1991157#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 1991155#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 1991153#L617 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 1991151#L631 assume 0 != eval_~tmp~0; 1991149#L631-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 1991146#L639 assume !(0 != eval_~tmp_ndt_1~0); 1991147#L636 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 2024720#L653 assume !(0 != eval_~tmp_ndt_2~0); 1976033#L650 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 1976030#L667 assume !(0 != eval_~tmp_ndt_3~0); 1976028#L664 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 1976026#L681 assume !(0 != eval_~tmp_ndt_4~0); 1976027#L678 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 1991307#L695 assume !(0 != eval_~tmp_ndt_5~0); 1991306#L692 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 1991304#L709 assume !(0 != eval_~tmp_ndt_6~0); 1991179#L706 assume !(0 == ~t6_st~0); 1991175#L720 assume !(0 == ~t7_st~0); 1991169#L734 [2018-11-18 15:28:25,424 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:25,424 INFO L82 PathProgramCache]: Analyzing trace with hash 1816264822, now seen corresponding path program 6 times [2018-11-18 15:28:25,424 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:25,424 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:25,425 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:25,425 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:28:25,425 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:25,430 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:28:25,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:28:25,454 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:25,454 INFO L82 PathProgramCache]: Analyzing trace with hash 479764011, now seen corresponding path program 1 times [2018-11-18 15:28:25,454 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:25,454 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:25,455 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:25,455 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:28:25,455 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:25,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:28:25,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:28:25,458 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:25,459 INFO L82 PathProgramCache]: Analyzing trace with hash -927668010, now seen corresponding path program 1 times [2018-11-18 15:28:25,459 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:25,459 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:25,459 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:25,459 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:28:25,459 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:25,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:25,492 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:28:25,493 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:28:25,493 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:28:25,594 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:28:25,594 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:28:25,594 INFO L87 Difference]: Start difference. First operand 335323 states and 423043 transitions. cyclomatic complexity: 87768 Second operand 3 states. [2018-11-18 15:28:30,101 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:30,101 INFO L93 Difference]: Finished difference Result 610373 states and 769253 transitions. [2018-11-18 15:28:30,101 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:28:30,101 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 610373 states and 769253 transitions. [2018-11-18 15:28:31,692 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 411148 [2018-11-18 15:28:32,593 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 610373 states to 610373 states and 769253 transitions. [2018-11-18 15:28:32,593 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 414280 [2018-11-18 15:28:32,742 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 414280 [2018-11-18 15:28:32,742 INFO L73 IsDeterministic]: Start isDeterministic. Operand 610373 states and 769253 transitions. [2018-11-18 15:28:32,742 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-18 15:28:32,742 INFO L705 BuchiCegarLoop]: Abstraction has 610373 states and 769253 transitions. [2018-11-18 15:28:32,974 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 610373 states and 769253 transitions. [2018-11-18 15:28:37,092 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 610373 to 595793. [2018-11-18 15:28:37,092 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 595793 states. [2018-11-18 15:28:37,873 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 595793 states to 595793 states and 751757 transitions. [2018-11-18 15:28:37,873 INFO L728 BuchiCegarLoop]: Abstraction has 595793 states and 751757 transitions. [2018-11-18 15:28:37,873 INFO L608 BuchiCegarLoop]: Abstraction has 595793 states and 751757 transitions. [2018-11-18 15:28:37,873 INFO L442 BuchiCegarLoop]: ======== Iteration 36============ [2018-11-18 15:28:37,874 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 595793 states and 751757 transitions. [2018-11-18 15:28:39,009 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 401428 [2018-11-18 15:28:39,009 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:28:39,009 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:28:39,009 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:39,009 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:28:39,010 INFO L794 eck$LassoCheckResult]: Stem: 2883351#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 2883171#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 2883172#L1131 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 2883985#L519 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2883574#L526 assume 1 == ~m_i~0;~m_st~0 := 0; 2883575#L526-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2883061#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2883062#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2883986#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2883549#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2882942#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2882684#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2882685#L561-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2884384#L759 assume !(0 == ~M_E~0); 2884392#L759-2 assume !(0 == ~T1_E~0); 2883685#L764-1 assume !(0 == ~T2_E~0); 2883247#L769-1 assume !(0 == ~T3_E~0); 2882621#L774-1 assume !(0 == ~T4_E~0); 2882622#L779-1 assume !(0 == ~T5_E~0); 2884145#L784-1 assume !(0 == ~T6_E~0); 2883647#L789-1 assume !(0 == ~T7_E~0); 2882827#L794-1 assume !(0 == ~E_M~0); 2882828#L799-1 assume !(0 == ~E_1~0); 2884287#L804-1 assume !(0 == ~E_2~0); 2883928#L809-1 assume !(0 == ~E_3~0); 2883449#L814-1 assume !(0 == ~E_4~0); 2882479#L819-1 assume !(0 == ~E_5~0); 2882480#L824-1 assume !(0 == ~E_6~0); 2883863#L829-1 assume !(0 == ~E_7~0); 2883590#L834-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2883591#L366 assume !(1 == ~m_pc~0); 2884108#L366-2 is_master_triggered_~__retres1~0 := 0; 2883002#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2882593#L378 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2882594#L945 assume !(0 != activate_threads_~tmp~1); 2883248#L945-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2883249#L385 assume !(1 == ~t1_pc~0); 2884364#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 2883391#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2882901#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2882902#L953 assume !(0 != activate_threads_~tmp___0~0); 2884498#L953-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2884499#L404 assume !(1 == ~t2_pc~0); 2884510#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 2883646#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2883576#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2883577#L961 assume !(0 != activate_threads_~tmp___1~0); 2884081#L961-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2882785#L423 assume !(1 == ~t3_pc~0); 2882786#L423-2 is_transmit3_triggered_~__retres1~3 := 0; 2882800#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2883897#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2883321#L969 assume !(0 != activate_threads_~tmp___2~0); 2883322#L969-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2882825#L442 assume !(1 == ~t4_pc~0); 2882803#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 2882804#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2883989#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2884131#L977 assume !(0 != activate_threads_~tmp___3~0); 2884542#L977-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2883204#L461 assume !(1 == ~t5_pc~0); 2883205#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 2883208#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2884186#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2883935#L985 assume !(0 != activate_threads_~tmp___4~0); 2883936#L985-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2883550#L480 assume !(1 == ~t6_pc~0); 2883519#L480-2 is_transmit6_triggered_~__retres1~6 := 0; 2883520#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2884474#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2883117#L993 assume !(0 != activate_threads_~tmp___5~0); 2883118#L993-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 2883123#L499 assume !(1 == ~t7_pc~0); 2883816#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 2882580#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 2882472#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2882473#L1001 assume !(0 != activate_threads_~tmp___6~0); 2884395#L1001-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2884396#L847 assume !(1 == ~M_E~0); 2884391#L847-2 assume !(1 == ~T1_E~0); 2883681#L852-1 assume !(1 == ~T2_E~0); 2883240#L857-1 assume !(1 == ~T3_E~0); 2882615#L862-1 assume !(1 == ~T4_E~0); 2882616#L867-1 assume !(1 == ~T5_E~0); 2884142#L872-1 assume !(1 == ~T6_E~0); 2883483#L877-1 assume !(1 == ~T7_E~0); 2882841#L882-1 assume !(1 == ~E_M~0); 2882842#L887-1 assume !(1 == ~E_1~0); 2884307#L892-1 assume !(1 == ~E_2~0); 2883942#L897-1 assume !(1 == ~E_3~0); 2883476#L902-1 assume !(1 == ~E_4~0); 2882506#L907-1 assume !(1 == ~E_5~0); 2882507#L912-1 assume !(1 == ~E_6~0); 2883853#L917-1 assume !(1 == ~E_7~0); 2883586#L922-1 assume { :end_inline_reset_delta_events } true; 2883587#L1168-3 assume true; 2958122#L1168-1 assume !false; 3165015#L1169 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 3165013#L734 [2018-11-18 15:28:39,010 INFO L796 eck$LassoCheckResult]: Loop: 3165013#L734 assume true; 3165011#L626-1 assume !false; 3165009#L627 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 3165007#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 3165004#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 3165002#L617 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 3165000#L631 assume 0 != eval_~tmp~0; 3164999#L631-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 3164997#L639 assume !(0 != eval_~tmp_ndt_1~0); 3164998#L636 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 3339824#L653 assume !(0 != eval_~tmp_ndt_2~0); 3339825#L650 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 3414174#L667 assume !(0 != eval_~tmp_ndt_3~0); 3414419#L664 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 3442087#L681 assume !(0 != eval_~tmp_ndt_4~0); 2934471#L678 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 2934469#L695 assume !(0 != eval_~tmp_ndt_5~0); 2934470#L692 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 3151225#L709 assume !(0 != eval_~tmp_ndt_6~0); 3151224#L706 assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0;eval_~tmp_ndt_7~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 3003708#L723 assume !(0 != eval_~tmp_ndt_7~0); 3151223#L720 assume !(0 == ~t7_st~0); 3165013#L734 [2018-11-18 15:28:39,010 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:39,010 INFO L82 PathProgramCache]: Analyzing trace with hash 1816264822, now seen corresponding path program 7 times [2018-11-18 15:28:39,010 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:39,010 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:39,011 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:39,011 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:28:39,011 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:39,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:28:39,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:28:39,044 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:39,044 INFO L82 PathProgramCache]: Analyzing trace with hash 1987562371, now seen corresponding path program 1 times [2018-11-18 15:28:39,044 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:39,045 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:39,045 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:39,045 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:28:39,045 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:39,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:28:39,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:28:39,050 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:28:39,050 INFO L82 PathProgramCache]: Analyzing trace with hash 1306842680, now seen corresponding path program 1 times [2018-11-18 15:28:39,051 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:28:39,051 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:28:39,051 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:39,051 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:28:39,051 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:28:39,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:28:39,090 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:28:39,090 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:28:39,090 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 15:28:39,197 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:28:39,197 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:28:39,197 INFO L87 Difference]: Start difference. First operand 595793 states and 751757 transitions. cyclomatic complexity: 156012 Second operand 3 states. [2018-11-18 15:28:45,689 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:28:45,689 INFO L93 Difference]: Finished difference Result 1051945 states and 1325002 transitions. [2018-11-18 15:28:45,689 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:28:45,689 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1051945 states and 1325002 transitions. [2018-11-18 15:28:48,988 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 709836 [2018-11-18 15:28:50,391 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1051945 states to 1051945 states and 1325002 transitions. [2018-11-18 15:28:50,392 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 715992 [2018-11-18 15:28:50,612 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 715992 [2018-11-18 15:28:50,612 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1051945 states and 1325002 transitions. [2018-11-18 15:28:50,684 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-18 15:28:50,684 INFO L705 BuchiCegarLoop]: Abstraction has 1051945 states and 1325002 transitions. [2018-11-18 15:28:51,074 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1051945 states and 1325002 transitions. [2018-11-18 15:29:05,944 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1051945 to 1042225. [2018-11-18 15:29:05,945 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1042225 states. [2018-11-18 15:29:07,299 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1042225 states to 1042225 states and 1315282 transitions. [2018-11-18 15:29:07,299 INFO L728 BuchiCegarLoop]: Abstraction has 1042225 states and 1315282 transitions. [2018-11-18 15:29:07,299 INFO L608 BuchiCegarLoop]: Abstraction has 1042225 states and 1315282 transitions. [2018-11-18 15:29:07,299 INFO L442 BuchiCegarLoop]: ======== Iteration 37============ [2018-11-18 15:29:07,299 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1042225 states and 1315282 transitions. [2018-11-18 15:29:10,005 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 703356 [2018-11-18 15:29:10,005 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:29:10,005 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:29:10,006 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:10,006 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:10,006 INFO L794 eck$LassoCheckResult]: Stem: 4531087#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~token~0 := 0;~local~0 := 0; 4530907#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 4530908#L1131 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret19, start_simulation_#t~ret20, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 4531745#L519 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4531310#L526 assume 1 == ~m_i~0;~m_st~0 := 0; 4531311#L526-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4530802#L531-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4530803#L536-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4531746#L541-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4531286#L546-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 4530685#L551-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 4530431#L556-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 4530432#L561-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4532144#L759 assume !(0 == ~M_E~0); 4532151#L759-2 assume !(0 == ~T1_E~0); 4531430#L764-1 assume !(0 == ~T2_E~0); 4530982#L769-1 assume !(0 == ~T3_E~0); 4530367#L774-1 assume !(0 == ~T4_E~0); 4530368#L779-1 assume !(0 == ~T5_E~0); 4531900#L784-1 assume !(0 == ~T6_E~0); 4531384#L789-1 assume !(0 == ~T7_E~0); 4530570#L794-1 assume !(0 == ~E_M~0); 4530571#L799-1 assume !(0 == ~E_1~0); 4532035#L804-1 assume !(0 == ~E_2~0); 4531683#L809-1 assume !(0 == ~E_3~0); 4531192#L814-1 assume !(0 == ~E_4~0); 4530225#L819-1 assume !(0 == ~E_5~0); 4530226#L824-1 assume !(0 == ~E_6~0); 4531617#L829-1 assume !(0 == ~E_7~0); 4531327#L834-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4531328#L366 assume !(1 == ~m_pc~0); 4531863#L366-2 is_master_triggered_~__retres1~0 := 0; 4530749#L377 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4530343#L378 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 4530344#L945 assume !(0 != activate_threads_~tmp~1); 4530983#L945-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4530984#L385 assume !(1 == ~t1_pc~0); 4532116#L385-2 is_transmit1_triggered_~__retres1~1 := 0; 4531136#L396 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4530645#L397 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 4530646#L953 assume !(0 != activate_threads_~tmp___0~0); 4532268#L953-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4532269#L404 assume !(1 == ~t2_pc~0); 4532278#L404-2 is_transmit2_triggered_~__retres1~2 := 0; 4531383#L415 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4531312#L416 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4531313#L961 assume !(0 != activate_threads_~tmp___1~0); 4531836#L961-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4530532#L423 assume !(1 == ~t3_pc~0); 4530533#L423-2 is_transmit3_triggered_~__retres1~3 := 0; 4530544#L434 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4531649#L435 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4531057#L969 assume !(0 != activate_threads_~tmp___2~0); 4531058#L969-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4530568#L442 assume !(1 == ~t4_pc~0); 4530546#L442-2 is_transmit4_triggered_~__retres1~4 := 0; 4530547#L453 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4531749#L454 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4531888#L977 assume !(0 != activate_threads_~tmp___3~0); 4532309#L977-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4530941#L461 assume !(1 == ~t5_pc~0); 4530942#L461-2 is_transmit5_triggered_~__retres1~5 := 0; 4530944#L472 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4531936#L473 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4531689#L985 assume !(0 != activate_threads_~tmp___4~0); 4531690#L985-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 4531287#L480 assume !(1 == ~t6_pc~0); 4531256#L480-2 is_transmit6_triggered_~__retres1~6 := 0; 4531257#L491 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 4532243#L492 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4530856#L993 assume !(0 != activate_threads_~tmp___5~0); 4530857#L993-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 4530861#L499 assume !(1 == ~t7_pc~0); 4531570#L499-2 is_transmit7_triggered_~__retres1~7 := 0; 4530326#L510 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 4530218#L511 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4530219#L1001 assume !(0 != activate_threads_~tmp___6~0); 4532163#L1001-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4532164#L847 assume !(1 == ~M_E~0); 4532150#L847-2 assume !(1 == ~T1_E~0); 4531422#L852-1 assume !(1 == ~T2_E~0); 4530974#L857-1 assume !(1 == ~T3_E~0); 4530361#L862-1 assume !(1 == ~T4_E~0); 4530362#L867-1 assume !(1 == ~T5_E~0); 4531897#L872-1 assume !(1 == ~T6_E~0); 4531223#L877-1 assume !(1 == ~T7_E~0); 4530584#L882-1 assume !(1 == ~E_M~0); 4530585#L887-1 assume !(1 == ~E_1~0); 4532054#L892-1 assume !(1 == ~E_2~0); 4531696#L897-1 assume !(1 == ~E_3~0); 4531214#L902-1 assume !(1 == ~E_4~0); 4530252#L907-1 assume !(1 == ~E_5~0); 4530253#L912-1 assume !(1 == ~E_6~0); 4531609#L917-1 assume !(1 == ~E_7~0); 4531322#L922-1 assume { :end_inline_reset_delta_events } true; 4531323#L1168-3 assume true; 5320147#L1168-1 assume !false; 5503773#L1169 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret1, eval_#t~nondet2, eval_~tmp_ndt_1~0, eval_#t~nondet3, eval_~tmp_ndt_2~0, eval_#t~nondet4, eval_~tmp_ndt_3~0, eval_#t~nondet5, eval_~tmp_ndt_4~0, eval_#t~nondet6, eval_~tmp_ndt_5~0, eval_#t~nondet7, eval_~tmp_ndt_6~0, eval_#t~nondet8, eval_~tmp_ndt_7~0, eval_#t~nondet9, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 4997655#L734 [2018-11-18 15:29:10,006 INFO L796 eck$LassoCheckResult]: Loop: 4997655#L734 assume true; 5503772#L626-1 assume !false; 5503771#L627 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 5503769#L574 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 5503768#L616 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 5503767#L617 eval_#t~ret1 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret1;havoc eval_#t~ret1; 5503765#L631 assume 0 != eval_~tmp~0; 5503764#L631-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 5503762#L639 assume !(0 != eval_~tmp_ndt_1~0); 5503763#L636 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 5509686#L653 assume !(0 != eval_~tmp_ndt_2~0); 5509687#L650 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 4813440#L667 assume !(0 != eval_~tmp_ndt_3~0); 4813438#L664 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 4813435#L681 assume !(0 != eval_~tmp_ndt_4~0); 4813158#L678 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 4813153#L695 assume !(0 != eval_~tmp_ndt_5~0); 4813154#L692 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 4978289#L709 assume !(0 != eval_~tmp_ndt_6~0); 4978286#L706 assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0;eval_~tmp_ndt_7~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 4978165#L723 assume !(0 != eval_~tmp_ndt_7~0); 4978283#L720 assume 0 == ~t7_st~0;havoc eval_~tmp_ndt_8~0;eval_~tmp_ndt_8~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 4837814#L737 assume !(0 != eval_~tmp_ndt_8~0); 4997655#L734 [2018-11-18 15:29:10,006 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:10,006 INFO L82 PathProgramCache]: Analyzing trace with hash 1816264822, now seen corresponding path program 8 times [2018-11-18 15:29:10,006 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:10,006 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:10,007 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:10,007 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:10,007 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:10,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:29:10,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:29:10,038 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:10,038 INFO L82 PathProgramCache]: Analyzing trace with hash 1484886753, now seen corresponding path program 1 times [2018-11-18 15:29:10,038 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:10,038 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:10,038 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:10,039 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:29:10,039 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:10,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:29:10,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:29:10,043 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:10,043 INFO L82 PathProgramCache]: Analyzing trace with hash 1857412812, now seen corresponding path program 1 times [2018-11-18 15:29:10,044 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:10,044 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:10,044 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:10,044 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:10,044 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:10,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:29:10,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:29:10,197 WARN L180 SmtUtils]: Spent 112.00 ms on a formula simplification. DAG size of input: 59 DAG size of output: 57 [2018-11-18 15:29:10,768 WARN L180 SmtUtils]: Spent 529.00 ms on a formula simplification. DAG size of input: 260 DAG size of output: 172 [2018-11-18 15:29:10,884 WARN L180 SmtUtils]: Spent 113.00 ms on a formula simplification that was a NOOP. DAG size: 138 [2018-11-18 15:29:10,916 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 18.11 03:29:10 BoogieIcfgContainer [2018-11-18 15:29:10,916 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2018-11-18 15:29:10,916 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-18 15:29:10,916 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-18 15:29:10,916 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-18 15:29:10,917 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 03:27:54" (3/4) ... [2018-11-18 15:29:10,919 INFO L141 WitnessPrinter]: Generating witness for non-termination counterexample [2018-11-18 15:29:10,972 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_3a6714ee-9413-49e8-b921-8f98627a95b6/bin-2019/uautomizer/witness.graphml [2018-11-18 15:29:10,972 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-18 15:29:10,973 INFO L168 Benchmark]: Toolchain (without parser) took 78295.43 ms. Allocated memory was 1.0 GB in the beginning and 8.3 GB in the end (delta: 7.3 GB). Free memory was 960.9 MB in the beginning and 2.5 GB in the end (delta: -1.5 GB). Peak memory consumption was 5.8 GB. Max. memory is 11.5 GB. [2018-11-18 15:29:10,973 INFO L168 Benchmark]: CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 982.9 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-18 15:29:10,974 INFO L168 Benchmark]: CACSL2BoogieTranslator took 271.66 ms. Allocated memory is still 1.0 GB. Free memory was 955.5 MB in the beginning and 934.0 MB in the end (delta: 21.5 MB). Peak memory consumption was 21.5 MB. Max. memory is 11.5 GB. [2018-11-18 15:29:10,974 INFO L168 Benchmark]: Boogie Procedure Inliner took 110.60 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 147.3 MB). Free memory was 934.0 MB in the beginning and 1.1 GB in the end (delta: -202.4 MB). Peak memory consumption was 15.2 MB. Max. memory is 11.5 GB. [2018-11-18 15:29:10,974 INFO L168 Benchmark]: Boogie Preprocessor took 55.90 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2018-11-18 15:29:10,974 INFO L168 Benchmark]: RCFGBuilder took 1255.44 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 959.1 MB in the end (delta: 171.9 MB). Peak memory consumption was 171.9 MB. Max. memory is 11.5 GB. [2018-11-18 15:29:10,974 INFO L168 Benchmark]: BuchiAutomizer took 76542.24 ms. Allocated memory was 1.2 GB in the beginning and 8.3 GB in the end (delta: 7.2 GB). Free memory was 959.1 MB in the beginning and 2.5 GB in the end (delta: -1.5 GB). Peak memory consumption was 5.6 GB. Max. memory is 11.5 GB. [2018-11-18 15:29:10,975 INFO L168 Benchmark]: Witness Printer took 56.05 ms. Allocated memory is still 8.3 GB. Free memory is still 2.5 GB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-18 15:29:10,976 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 982.9 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 271.66 ms. Allocated memory is still 1.0 GB. Free memory was 955.5 MB in the beginning and 934.0 MB in the end (delta: 21.5 MB). Peak memory consumption was 21.5 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 110.60 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 147.3 MB). Free memory was 934.0 MB in the beginning and 1.1 GB in the end (delta: -202.4 MB). Peak memory consumption was 15.2 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 55.90 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * RCFGBuilder took 1255.44 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 959.1 MB in the end (delta: 171.9 MB). Peak memory consumption was 171.9 MB. Max. memory is 11.5 GB. * BuchiAutomizer took 76542.24 ms. Allocated memory was 1.2 GB in the beginning and 8.3 GB in the end (delta: 7.2 GB). Free memory was 959.1 MB in the beginning and 2.5 GB in the end (delta: -1.5 GB). Peak memory consumption was 5.6 GB. Max. memory is 11.5 GB. * Witness Printer took 56.05 ms. Allocated memory is still 8.3 GB. Free memory is still 2.5 GB. There was no memory consumed. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 37 terminating modules (36 trivial, 1 deterministic, 0 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function -1 * E_5 + 1 and consists of 3 locations. 36 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 1042225 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 76.4s and 37 iterations. TraceHistogramMax:2. Analysis of lassos took 7.8s. Construction of modules took 1.5s. Büchi inclusion checks took 14.9s. Highest rank in rank-based complementation 3. Minimization of det autom 26. Minimization of nondet autom 11. Automata minimization 32.4s AutomataMinimizationTime, 37 MinimizatonAttempts, 84327 StatesRemovedByMinimization, 20 NontrivialMinimizations. Non-live state removal took 12.6s Buchi closure took 0.7s. Biggest automaton had 1042225 states and ocurred in iteration 36. Nontrivial modules had stage [1, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 47925 SDtfs, 54128 SDslu, 47154 SDs, 0 SdLazy, 1352 SolverSat, 648 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 1.5s Time LassoAnalysisResults: nont1 unkn0 SFLI10 SFLT0 conc7 concLT1 SILN1 SILU0 SILI17 SILT0 lasso0 LassoPreprocessingBenchmarks: Lassos: inital277 mio100 ax100 hnf100 lsp3 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq209 hnf86 smp100 dnf189 smp63 tf108 neg92 sie116 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 1ms VariablesStem: 0 VariablesLoop: 1 DisjunctsStem: 1 DisjunctsLoop: 2 SupportingInvariants: 0 MotzkinApplications: 4 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 14 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 1 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.1s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 626]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {E_7=2, t3_st=0, __retres1=0, t5_i=1, __retres1=0, kernel_st=1, \result=0, E_3=2, T6_E=2, t7_i=1, tmp_ndt_8=0, tmp_ndt_4=0, \result=0, m_st=0, t6_pc=0, tmp___2=0, __retres1=0, t3_pc=0, \result=0, m_pc=0, tmp___6=0, t6_st=0, E_6=2, __retres1=0, \result=0, T2_E=2, t5_st=0, __retres1=1, E_2=2, t7_pc=0, tmp=0, M_E=2, tmp_ndt_3=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2464516f=0, T4_E=2, t4_st=0, t3_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@63b70f57=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@41fc70b3=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2e27398a=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4cbcf7fc=0, t5_pc=0, t7_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4ad538e0=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@11434028=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3398c700=0, tmp_ndt_7=0, tmp___3=0, t1_i=1, __retres1=0, token=0, T7_E=2, tmp=1, t2_st=0, t4_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@73855e86=0, t4_pc=0, E_5=2, \result=0, E_1=2, tmp_ndt_2=0, \result=0, __retres1=0, tmp_ndt_6=0, tmp___0=0, tmp=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@32c29218=0, t6_i=1, tmp___4=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@49f22d56=0, \result=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@23379e6c=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@33d937cd=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7a45a745=0, tmp___0=0, t1_pc=0, E_4=2, T1_E=2, tmp_ndt_1=0, T5_E=2, t2_i=1, m_i=1, t1_st=0, tmp_ndt_5=0, local=0, __retres1=0, t2_pc=0, E_M=2, tmp___1=0, T3_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1df5d5b6=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3bda7890=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@fc98344=0, \result=1, tmp___5=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2e70876b=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3c9b427=0} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 626]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L14] int m_pc = 0; [L15] int t1_pc = 0; [L16] int t2_pc = 0; [L17] int t3_pc = 0; [L18] int t4_pc = 0; [L19] int t5_pc = 0; [L20] int t6_pc = 0; [L21] int t7_pc = 0; [L22] int m_st ; [L23] int t1_st ; [L24] int t2_st ; [L25] int t3_st ; [L26] int t4_st ; [L27] int t5_st ; [L28] int t6_st ; [L29] int t7_st ; [L30] int m_i ; [L31] int t1_i ; [L32] int t2_i ; [L33] int t3_i ; [L34] int t4_i ; [L35] int t5_i ; [L36] int t6_i ; [L37] int t7_i ; [L38] int M_E = 2; [L39] int T1_E = 2; [L40] int T2_E = 2; [L41] int T3_E = 2; [L42] int T4_E = 2; [L43] int T5_E = 2; [L44] int T6_E = 2; [L45] int T7_E = 2; [L46] int E_M = 2; [L47] int E_1 = 2; [L48] int E_2 = 2; [L49] int E_3 = 2; [L50] int E_4 = 2; [L51] int E_5 = 2; [L52] int E_6 = 2; [L53] int E_7 = 2; [L63] int token ; [L65] int local ; [L1213] int __retres1 ; [L1217] CALL init_model() [L1122] m_i = 1 [L1123] t1_i = 1 [L1124] t2_i = 1 [L1125] t3_i = 1 [L1126] t4_i = 1 [L1127] t5_i = 1 [L1128] t6_i = 1 [L1129] RET t7_i = 1 [L1217] init_model() [L1218] CALL start_simulation() [L1154] int kernel_st ; [L1155] int tmp ; [L1156] int tmp___0 ; [L1160] kernel_st = 0 [L1161] FCALL update_channels() [L1162] CALL init_threads() [L526] COND TRUE m_i == 1 [L527] m_st = 0 [L531] COND TRUE t1_i == 1 [L532] t1_st = 0 [L536] COND TRUE t2_i == 1 [L537] t2_st = 0 [L541] COND TRUE t3_i == 1 [L542] t3_st = 0 [L546] COND TRUE t4_i == 1 [L547] t4_st = 0 [L551] COND TRUE t5_i == 1 [L552] t5_st = 0 [L556] COND TRUE t6_i == 1 [L557] t6_st = 0 [L561] COND TRUE t7_i == 1 [L562] RET t7_st = 0 [L1162] init_threads() [L1163] CALL fire_delta_events() [L759] COND FALSE !(M_E == 0) [L764] COND FALSE !(T1_E == 0) [L769] COND FALSE !(T2_E == 0) [L774] COND FALSE !(T3_E == 0) [L779] COND FALSE !(T4_E == 0) [L784] COND FALSE !(T5_E == 0) [L789] COND FALSE !(T6_E == 0) [L794] COND FALSE !(T7_E == 0) [L799] COND FALSE !(E_M == 0) [L804] COND FALSE !(E_1 == 0) [L809] COND FALSE !(E_2 == 0) [L814] COND FALSE !(E_3 == 0) [L819] COND FALSE !(E_4 == 0) [L824] COND FALSE !(E_5 == 0) [L829] COND FALSE !(E_6 == 0) [L834] COND FALSE, RET !(E_7 == 0) [L1163] fire_delta_events() [L1164] CALL activate_threads() [L932] int tmp ; [L933] int tmp___0 ; [L934] int tmp___1 ; [L935] int tmp___2 ; [L936] int tmp___3 ; [L937] int tmp___4 ; [L938] int tmp___5 ; [L939] int tmp___6 ; [L943] CALL, EXPR is_master_triggered() [L363] int __retres1 ; [L366] COND FALSE !(m_pc == 1) [L376] __retres1 = 0 [L378] RET return (__retres1); [L943] EXPR is_master_triggered() [L943] tmp = is_master_triggered() [L945] COND FALSE !(\read(tmp)) [L951] CALL, EXPR is_transmit1_triggered() [L382] int __retres1 ; [L385] COND FALSE !(t1_pc == 1) [L395] __retres1 = 0 [L397] RET return (__retres1); [L951] EXPR is_transmit1_triggered() [L951] tmp___0 = is_transmit1_triggered() [L953] COND FALSE !(\read(tmp___0)) [L959] CALL, EXPR is_transmit2_triggered() [L401] int __retres1 ; [L404] COND FALSE !(t2_pc == 1) [L414] __retres1 = 0 [L416] RET return (__retres1); [L959] EXPR is_transmit2_triggered() [L959] tmp___1 = is_transmit2_triggered() [L961] COND FALSE !(\read(tmp___1)) [L967] CALL, EXPR is_transmit3_triggered() [L420] int __retres1 ; [L423] COND FALSE !(t3_pc == 1) [L433] __retres1 = 0 [L435] RET return (__retres1); [L967] EXPR is_transmit3_triggered() [L967] tmp___2 = is_transmit3_triggered() [L969] COND FALSE !(\read(tmp___2)) [L975] CALL, EXPR is_transmit4_triggered() [L439] int __retres1 ; [L442] COND FALSE !(t4_pc == 1) [L452] __retres1 = 0 [L454] RET return (__retres1); [L975] EXPR is_transmit4_triggered() [L975] tmp___3 = is_transmit4_triggered() [L977] COND FALSE !(\read(tmp___3)) [L983] CALL, EXPR is_transmit5_triggered() [L458] int __retres1 ; [L461] COND FALSE !(t5_pc == 1) [L471] __retres1 = 0 [L473] RET return (__retres1); [L983] EXPR is_transmit5_triggered() [L983] tmp___4 = is_transmit5_triggered() [L985] COND FALSE !(\read(tmp___4)) [L991] CALL, EXPR is_transmit6_triggered() [L477] int __retres1 ; [L480] COND FALSE !(t6_pc == 1) [L490] __retres1 = 0 [L492] RET return (__retres1); [L991] EXPR is_transmit6_triggered() [L991] tmp___5 = is_transmit6_triggered() [L993] COND FALSE !(\read(tmp___5)) [L999] CALL, EXPR is_transmit7_triggered() [L496] int __retres1 ; [L499] COND FALSE !(t7_pc == 1) [L509] __retres1 = 0 [L511] RET return (__retres1); [L999] EXPR is_transmit7_triggered() [L999] tmp___6 = is_transmit7_triggered() [L1001] COND FALSE, RET !(\read(tmp___6)) [L1164] activate_threads() [L1165] CALL reset_delta_events() [L847] COND FALSE !(M_E == 1) [L852] COND FALSE !(T1_E == 1) [L857] COND FALSE !(T2_E == 1) [L862] COND FALSE !(T3_E == 1) [L867] COND FALSE !(T4_E == 1) [L872] COND FALSE !(T5_E == 1) [L877] COND FALSE !(T6_E == 1) [L882] COND FALSE !(T7_E == 1) [L887] COND FALSE !(E_M == 1) [L892] COND FALSE !(E_1 == 1) [L897] COND FALSE !(E_2 == 1) [L902] COND FALSE !(E_3 == 1) [L907] COND FALSE !(E_4 == 1) [L912] COND FALSE !(E_5 == 1) [L917] COND FALSE !(E_6 == 1) [L922] COND FALSE, RET !(E_7 == 1) [L1165] reset_delta_events() [L1168] COND TRUE 1 [L1171] kernel_st = 1 [L1172] CALL eval() [L622] int tmp ; Loop: [L626] COND TRUE 1 [L629] CALL, EXPR exists_runnable_thread() [L571] int __retres1 ; [L574] COND TRUE m_st == 0 [L575] __retres1 = 1 [L617] RET return (__retres1); [L629] EXPR exists_runnable_thread() [L629] tmp = exists_runnable_thread() [L631] COND TRUE \read(tmp) [L636] COND TRUE m_st == 0 [L637] int tmp_ndt_1; [L638] tmp_ndt_1 = __VERIFIER_nondet_int() [L639] COND FALSE !(\read(tmp_ndt_1)) [L650] COND TRUE t1_st == 0 [L651] int tmp_ndt_2; [L652] tmp_ndt_2 = __VERIFIER_nondet_int() [L653] COND FALSE !(\read(tmp_ndt_2)) [L664] COND TRUE t2_st == 0 [L665] int tmp_ndt_3; [L666] tmp_ndt_3 = __VERIFIER_nondet_int() [L667] COND FALSE !(\read(tmp_ndt_3)) [L678] COND TRUE t3_st == 0 [L679] int tmp_ndt_4; [L680] tmp_ndt_4 = __VERIFIER_nondet_int() [L681] COND FALSE !(\read(tmp_ndt_4)) [L692] COND TRUE t4_st == 0 [L693] int tmp_ndt_5; [L694] tmp_ndt_5 = __VERIFIER_nondet_int() [L695] COND FALSE !(\read(tmp_ndt_5)) [L706] COND TRUE t5_st == 0 [L707] int tmp_ndt_6; [L708] tmp_ndt_6 = __VERIFIER_nondet_int() [L709] COND FALSE !(\read(tmp_ndt_6)) [L720] COND TRUE t6_st == 0 [L721] int tmp_ndt_7; [L722] tmp_ndt_7 = __VERIFIER_nondet_int() [L723] COND FALSE !(\read(tmp_ndt_7)) [L734] COND TRUE t7_st == 0 [L735] int tmp_ndt_8; [L736] tmp_ndt_8 = __VERIFIER_nondet_int() [L737] COND FALSE !(\read(tmp_ndt_8)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...