./Ultimate.py --spec ../../sv-benchmarks/c/Termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.01_false-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 5842f4b8 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_2bd7126d-33d4-426b-8346-9856ccc05d04/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_2bd7126d-33d4-426b-8346-9856ccc05d04/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_2bd7126d-33d4-426b-8346-9856ccc05d04/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_2bd7126d-33d4-426b-8346-9856ccc05d04/bin-2019/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.01_false-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_2bd7126d-33d4-426b-8346-9856ccc05d04/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_2bd7126d-33d4-426b-8346-9856ccc05d04/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 18c351eab8f6ce363bd7076ce800527c30b2b6c5 ....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.1.23-5842f4b [2018-11-18 08:34:36,719 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-18 08:34:36,720 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-18 08:34:36,728 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-18 08:34:36,729 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-18 08:34:36,729 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-18 08:34:36,730 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-18 08:34:36,731 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-18 08:34:36,733 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-18 08:34:36,733 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-18 08:34:36,734 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-18 08:34:36,734 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-18 08:34:36,735 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-18 08:34:36,735 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-18 08:34:36,736 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-18 08:34:36,737 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-18 08:34:36,737 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-18 08:34:36,738 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-18 08:34:36,740 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-18 08:34:36,741 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-18 08:34:36,742 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-18 08:34:36,743 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-18 08:34:36,744 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-18 08:34:36,745 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-18 08:34:36,745 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-18 08:34:36,745 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-18 08:34:36,746 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-18 08:34:36,747 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-18 08:34:36,747 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-18 08:34:36,748 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-18 08:34:36,748 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-18 08:34:36,749 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-18 08:34:36,749 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-18 08:34:36,749 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-18 08:34:36,750 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-18 08:34:36,750 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-18 08:34:36,750 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_2bd7126d-33d4-426b-8346-9856ccc05d04/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2018-11-18 08:34:36,761 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-18 08:34:36,761 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-18 08:34:36,762 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-18 08:34:36,762 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-18 08:34:36,762 INFO L133 SettingsManager]: * Use SBE=true [2018-11-18 08:34:36,762 INFO L131 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2018-11-18 08:34:36,763 INFO L133 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2018-11-18 08:34:36,763 INFO L133 SettingsManager]: * Use old map elimination=false [2018-11-18 08:34:36,763 INFO L133 SettingsManager]: * Use external solver (rank synthesis)=false [2018-11-18 08:34:36,763 INFO L133 SettingsManager]: * Use only trivial implications for array writes=true [2018-11-18 08:34:36,763 INFO L133 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2018-11-18 08:34:36,763 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-18 08:34:36,763 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-18 08:34:36,764 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-11-18 08:34:36,764 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-18 08:34:36,764 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-18 08:34:36,764 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-18 08:34:36,764 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2018-11-18 08:34:36,764 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2018-11-18 08:34:36,764 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2018-11-18 08:34:36,764 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-18 08:34:36,765 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-18 08:34:36,765 INFO L133 SettingsManager]: * Assume nondeterminstic values are in range=false [2018-11-18 08:34:36,765 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-18 08:34:36,765 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2018-11-18 08:34:36,765 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-18 08:34:36,765 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-18 08:34:36,765 INFO L133 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2018-11-18 08:34:36,766 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-18 08:34:36,766 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-18 08:34:36,766 INFO L133 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2018-11-18 08:34:36,767 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-11-18 08:34:36,767 INFO L133 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_2bd7126d-33d4-426b-8346-9856ccc05d04/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 18c351eab8f6ce363bd7076ce800527c30b2b6c5 [2018-11-18 08:34:36,788 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-18 08:34:36,795 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-18 08:34:36,797 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-18 08:34:36,798 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-18 08:34:36,798 INFO L276 PluginConnector]: CDTParser initialized [2018-11-18 08:34:36,799 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_2bd7126d-33d4-426b-8346-9856ccc05d04/bin-2019/uautomizer/../../sv-benchmarks/c/systemc/transmitter.01_false-unreach-call_false-termination.cil.c [2018-11-18 08:34:36,833 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_2bd7126d-33d4-426b-8346-9856ccc05d04/bin-2019/uautomizer/data/07801e043/ac4261f9d39f49d9808921f4a9302cad/FLAG68a8ca7fa [2018-11-18 08:34:37,234 INFO L307 CDTParser]: Found 1 translation units. [2018-11-18 08:34:37,235 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_2bd7126d-33d4-426b-8346-9856ccc05d04/sv-benchmarks/c/systemc/transmitter.01_false-unreach-call_false-termination.cil.c [2018-11-18 08:34:37,239 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_2bd7126d-33d4-426b-8346-9856ccc05d04/bin-2019/uautomizer/data/07801e043/ac4261f9d39f49d9808921f4a9302cad/FLAG68a8ca7fa [2018-11-18 08:34:37,247 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_2bd7126d-33d4-426b-8346-9856ccc05d04/bin-2019/uautomizer/data/07801e043/ac4261f9d39f49d9808921f4a9302cad [2018-11-18 08:34:37,249 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-18 08:34:37,250 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-18 08:34:37,250 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-18 08:34:37,251 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-18 08:34:37,253 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-18 08:34:37,254 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 08:34:37" (1/1) ... [2018-11-18 08:34:37,256 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4959e04 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:34:37, skipping insertion in model container [2018-11-18 08:34:37,256 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 08:34:37" (1/1) ... [2018-11-18 08:34:37,264 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-18 08:34:37,284 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-18 08:34:37,403 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 08:34:37,406 INFO L191 MainTranslator]: Completed pre-run [2018-11-18 08:34:37,425 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 08:34:37,436 INFO L195 MainTranslator]: Completed translation [2018-11-18 08:34:37,436 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:34:37 WrapperNode [2018-11-18 08:34:37,436 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-18 08:34:37,437 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-18 08:34:37,437 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-18 08:34:37,437 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-18 08:34:37,444 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:34:37" (1/1) ... [2018-11-18 08:34:37,449 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:34:37" (1/1) ... [2018-11-18 08:34:37,472 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-18 08:34:37,472 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-18 08:34:37,473 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-18 08:34:37,473 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-18 08:34:37,517 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:34:37" (1/1) ... [2018-11-18 08:34:37,517 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:34:37" (1/1) ... [2018-11-18 08:34:37,518 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:34:37" (1/1) ... [2018-11-18 08:34:37,519 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:34:37" (1/1) ... [2018-11-18 08:34:37,522 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:34:37" (1/1) ... [2018-11-18 08:34:37,530 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:34:37" (1/1) ... [2018-11-18 08:34:37,532 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:34:37" (1/1) ... [2018-11-18 08:34:37,534 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-18 08:34:37,535 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-18 08:34:37,535 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-18 08:34:37,535 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-18 08:34:37,536 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:34:37" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2bd7126d-33d4-426b-8346-9856ccc05d04/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 08:34:37,573 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-18 08:34:37,574 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-18 08:34:37,897 INFO L278 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-18 08:34:37,898 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 08:34:37 BoogieIcfgContainer [2018-11-18 08:34:37,898 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-18 08:34:37,899 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2018-11-18 08:34:37,899 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2018-11-18 08:34:37,902 INFO L276 PluginConnector]: BuchiAutomizer initialized [2018-11-18 08:34:37,903 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-18 08:34:37,903 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 18.11 08:34:37" (1/3) ... [2018-11-18 08:34:37,904 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@699e661 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 18.11 08:34:37, skipping insertion in model container [2018-11-18 08:34:37,904 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-18 08:34:37,904 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 08:34:37" (2/3) ... [2018-11-18 08:34:37,904 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@699e661 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 18.11 08:34:37, skipping insertion in model container [2018-11-18 08:34:37,904 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-18 08:34:37,904 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 08:34:37" (3/3) ... [2018-11-18 08:34:37,906 INFO L375 chiAutomizerObserver]: Analyzing ICFG transmitter.01_false-unreach-call_false-termination.cil.c [2018-11-18 08:34:37,952 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-18 08:34:37,952 INFO L374 BuchiCegarLoop]: Interprodecural is true [2018-11-18 08:34:37,952 INFO L375 BuchiCegarLoop]: Hoare is false [2018-11-18 08:34:37,953 INFO L376 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2018-11-18 08:34:37,953 INFO L377 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-18 08:34:37,953 INFO L378 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-18 08:34:37,953 INFO L379 BuchiCegarLoop]: Difference is false [2018-11-18 08:34:37,953 INFO L380 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-18 08:34:37,953 INFO L383 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2018-11-18 08:34:37,968 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 138 states. [2018-11-18 08:34:37,991 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 105 [2018-11-18 08:34:37,991 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 08:34:37,991 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 08:34:37,999 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 08:34:37,999 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 08:34:37,999 INFO L442 BuchiCegarLoop]: ======== Iteration 1============ [2018-11-18 08:34:37,999 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 138 states. [2018-11-18 08:34:38,004 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 105 [2018-11-18 08:34:38,004 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 08:34:38,004 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 08:34:38,006 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 08:34:38,006 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 08:34:38,012 INFO L794 eck$LassoCheckResult]: Stem: 121#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 15#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 140#L357true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret6, start_simulation_#t~ret7, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 44#L144true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 129#L151true assume !(1 == ~m_i~0);~m_st~0 := 2; 126#L151-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 134#L156-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 61#L240true assume !(0 == ~M_E~0); 94#L240-2true assume !(0 == ~T1_E~0); 106#L245-1true assume !(0 == ~E_1~0); 132#L250-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 78#L105true assume !(1 == ~m_pc~0); 69#L105-2true is_master_triggered_~__retres1~0 := 0; 79#L116true is_master_triggered_#res := is_master_triggered_~__retres1~0; 38#L117true activate_threads_#t~ret3 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 56#L290true assume !(0 != activate_threads_~tmp~1); 52#L290-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 102#L124true assume 1 == ~t1_pc~0; 29#L125true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 103#L135true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 31#L136true activate_threads_#t~ret4 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 83#L298true assume !(0 != activate_threads_~tmp___0~0); 46#L298-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6#L263true assume !(1 == ~M_E~0); 3#L263-2true assume !(1 == ~T1_E~0); 53#L268-1true assume !(1 == ~E_1~0); 62#L273-1true assume { :end_inline_reset_delta_events } true; 90#L394-3true [2018-11-18 08:34:38,013 INFO L796 eck$LassoCheckResult]: Loop: 90#L394-3true assume true; 84#L394-1true assume !false; 32#L395true start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_~tmp~0;havoc eval_~tmp~0; 112#L215true assume !true; 5#L230true assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 42#L144-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 91#L240-3true assume 0 == ~M_E~0;~M_E~0 := 1; 87#L240-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 104#L245-3true assume 0 == ~E_1~0;~E_1~0 := 1; 130#L250-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 93#L105-6true assume !(1 == ~m_pc~0); 89#L105-8true is_master_triggered_~__retres1~0 := 0; 70#L116-2true is_master_triggered_#res := is_master_triggered_~__retres1~0; 10#L117-2true activate_threads_#t~ret3 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 25#L290-6true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 20#L290-8true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 109#L124-6true assume !(1 == ~t1_pc~0); 80#L124-8true is_transmit1_triggered_~__retres1~1 := 0; 100#L135-2true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 24#L136-2true activate_threads_#t~ret4 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 59#L298-6true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 58#L298-8true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19#L263-3true assume 1 == ~M_E~0;~M_E~0 := 2; 18#L263-5true assume !(1 == ~T1_E~0); 36#L268-3true assume 1 == ~E_1~0;~E_1~0 := 2; 95#L273-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 33#L169-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2 := 1; 125#L181-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 107#L182-1true start_simulation_#t~ret6 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret6;havoc start_simulation_#t~ret6; 110#L413true assume !(0 == start_simulation_~tmp~3); 115#L413-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret5, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 28#L169-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2 := 1; 124#L181-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 81#L182-2true stop_simulation_#t~ret5 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret5;havoc stop_simulation_#t~ret5; 139#L368true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 68#L375true stop_simulation_#res := stop_simulation_~__retres2~0; 4#L376true start_simulation_#t~ret7 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret7;havoc start_simulation_#t~ret7; 135#L426true assume !(0 != start_simulation_~tmp___0~1); 90#L394-3true [2018-11-18 08:34:38,018 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 08:34:38,018 INFO L82 PathProgramCache]: Analyzing trace with hash 920294251, now seen corresponding path program 1 times [2018-11-18 08:34:38,020 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 08:34:38,020 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 08:34:38,059 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:38,060 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 08:34:38,060 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:38,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 08:34:38,123 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 08:34:38,125 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 08:34:38,125 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 08:34:38,129 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 08:34:38,129 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 08:34:38,130 INFO L82 PathProgramCache]: Analyzing trace with hash 507884842, now seen corresponding path program 1 times [2018-11-18 08:34:38,130 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 08:34:38,130 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 08:34:38,131 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:38,131 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 08:34:38,131 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:38,134 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 08:34:38,139 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 08:34:38,140 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 08:34:38,140 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 08:34:38,141 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 08:34:38,153 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 08:34:38,154 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 08:34:38,155 INFO L87 Difference]: Start difference. First operand 138 states. Second operand 3 states. [2018-11-18 08:34:38,173 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 08:34:38,173 INFO L93 Difference]: Finished difference Result 137 states and 193 transitions. [2018-11-18 08:34:38,173 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 08:34:38,175 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 137 states and 193 transitions. [2018-11-18 08:34:38,177 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 102 [2018-11-18 08:34:38,181 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 137 states to 131 states and 187 transitions. [2018-11-18 08:34:38,182 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 131 [2018-11-18 08:34:38,183 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 131 [2018-11-18 08:34:38,183 INFO L73 IsDeterministic]: Start isDeterministic. Operand 131 states and 187 transitions. [2018-11-18 08:34:38,184 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 08:34:38,184 INFO L705 BuchiCegarLoop]: Abstraction has 131 states and 187 transitions. [2018-11-18 08:34:38,195 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 131 states and 187 transitions. [2018-11-18 08:34:38,206 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 131 to 131. [2018-11-18 08:34:38,207 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 131 states. [2018-11-18 08:34:38,208 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 131 states to 131 states and 187 transitions. [2018-11-18 08:34:38,209 INFO L728 BuchiCegarLoop]: Abstraction has 131 states and 187 transitions. [2018-11-18 08:34:38,209 INFO L608 BuchiCegarLoop]: Abstraction has 131 states and 187 transitions. [2018-11-18 08:34:38,209 INFO L442 BuchiCegarLoop]: ======== Iteration 2============ [2018-11-18 08:34:38,209 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 131 states and 187 transitions. [2018-11-18 08:34:38,210 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 102 [2018-11-18 08:34:38,211 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 08:34:38,211 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 08:34:38,211 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 08:34:38,212 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 08:34:38,212 INFO L794 eck$LassoCheckResult]: Stem: 412#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 310#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 311#L357 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret6, start_simulation_#t~ret7, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 366#L144 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 367#L151 assume 1 == ~m_i~0;~m_st~0 := 0; 413#L151-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 414#L156-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 381#L240 assume !(0 == ~M_E~0); 382#L240-2 assume !(0 == ~T1_E~0); 402#L245-1 assume !(0 == ~E_1~0); 405#L250-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 390#L105 assume !(1 == ~m_pc~0); 356#L105-2 is_master_triggered_~__retres1~0 := 0; 357#L116 is_master_triggered_#res := is_master_triggered_~__retres1~0; 358#L117 activate_threads_#t~ret3 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 359#L290 assume !(0 != activate_threads_~tmp~1); 373#L290-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 374#L124 assume 1 == ~t1_pc~0; 337#L125 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 338#L135 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 342#L136 activate_threads_#t~ret4 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 343#L298 assume !(0 != activate_threads_~tmp___0~0); 368#L298-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 293#L263 assume !(1 == ~M_E~0); 284#L263-2 assume !(1 == ~T1_E~0); 285#L268-1 assume !(1 == ~E_1~0); 375#L273-1 assume { :end_inline_reset_delta_events } true; 383#L394-3 [2018-11-18 08:34:38,212 INFO L796 eck$LassoCheckResult]: Loop: 383#L394-3 assume true; 394#L394-1 assume !false; 344#L395 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_~tmp~0;havoc eval_~tmp~0; 345#L215 assume true; 349#L191-1 assume !false; 350#L192 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 351#L169 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2 := 1; 352#L181 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 408#L182 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 403#L196 assume !(0 != eval_~tmp~0); 288#L230 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 289#L144-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 364#L240-3 assume 0 == ~M_E~0;~M_E~0 := 1; 397#L240-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 398#L245-3 assume 0 == ~E_1~0;~E_1~0 := 1; 404#L250-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 401#L105-6 assume 1 == ~m_pc~0; 296#L106-2 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 297#L116-2 is_master_triggered_#res := is_master_triggered_~__retres1~0; 301#L117-2 activate_threads_#t~ret3 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 302#L290-6 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 320#L290-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 321#L124-6 assume 1 == ~t1_pc~0; 324#L125-2 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 325#L135-2 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 327#L136-2 activate_threads_#t~ret4 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 328#L298-6 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 378#L298-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 316#L263-3 assume 1 == ~M_E~0;~M_E~0 := 2; 314#L263-5 assume !(1 == ~T1_E~0); 315#L268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 354#L273-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 346#L169-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2 := 1; 347#L181-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 406#L182-1 start_simulation_#t~ret6 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret6;havoc start_simulation_#t~ret6; 407#L413 assume !(0 == start_simulation_~tmp~3); 409#L413-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret5, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 334#L169-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2 := 1; 335#L181-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 391#L182-2 stop_simulation_#t~ret5 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret5;havoc stop_simulation_#t~ret5; 392#L368 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 387#L375 stop_simulation_#res := stop_simulation_~__retres2~0; 286#L376 start_simulation_#t~ret7 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret7;havoc start_simulation_#t~ret7; 287#L426 assume !(0 != start_simulation_~tmp___0~1); 383#L394-3 [2018-11-18 08:34:38,212 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 08:34:38,212 INFO L82 PathProgramCache]: Analyzing trace with hash -1569234711, now seen corresponding path program 1 times [2018-11-18 08:34:38,213 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 08:34:38,213 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 08:34:38,213 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:38,214 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 08:34:38,214 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:38,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 08:34:38,250 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 08:34:38,250 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 08:34:38,250 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 08:34:38,250 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 08:34:38,251 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 08:34:38,251 INFO L82 PathProgramCache]: Analyzing trace with hash -1841690295, now seen corresponding path program 1 times [2018-11-18 08:34:38,251 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 08:34:38,251 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 08:34:38,252 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:38,252 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 08:34:38,252 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:38,260 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 08:34:38,290 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 08:34:38,291 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 08:34:38,291 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 08:34:38,291 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 08:34:38,291 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 08:34:38,291 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 08:34:38,292 INFO L87 Difference]: Start difference. First operand 131 states and 187 transitions. cyclomatic complexity: 57 Second operand 3 states. [2018-11-18 08:34:38,345 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 08:34:38,345 INFO L93 Difference]: Finished difference Result 228 states and 319 transitions. [2018-11-18 08:34:38,346 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 08:34:38,346 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 228 states and 319 transitions. [2018-11-18 08:34:38,348 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 198 [2018-11-18 08:34:38,349 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 228 states to 228 states and 319 transitions. [2018-11-18 08:34:38,350 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 228 [2018-11-18 08:34:38,350 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 228 [2018-11-18 08:34:38,350 INFO L73 IsDeterministic]: Start isDeterministic. Operand 228 states and 319 transitions. [2018-11-18 08:34:38,351 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 08:34:38,351 INFO L705 BuchiCegarLoop]: Abstraction has 228 states and 319 transitions. [2018-11-18 08:34:38,351 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 228 states and 319 transitions. [2018-11-18 08:34:38,356 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 228 to 223. [2018-11-18 08:34:38,356 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 223 states. [2018-11-18 08:34:38,357 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 223 states to 223 states and 313 transitions. [2018-11-18 08:34:38,357 INFO L728 BuchiCegarLoop]: Abstraction has 223 states and 313 transitions. [2018-11-18 08:34:38,357 INFO L608 BuchiCegarLoop]: Abstraction has 223 states and 313 transitions. [2018-11-18 08:34:38,357 INFO L442 BuchiCegarLoop]: ======== Iteration 3============ [2018-11-18 08:34:38,357 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 223 states and 313 transitions. [2018-11-18 08:34:38,359 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 195 [2018-11-18 08:34:38,359 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 08:34:38,359 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 08:34:38,360 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 08:34:38,360 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 08:34:38,360 INFO L794 eck$LassoCheckResult]: Stem: 787#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 676#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 677#L357 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret6, start_simulation_#t~ret7, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 729#L144 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 730#L151 assume 1 == ~m_i~0;~m_st~0 := 0; 788#L151-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 789#L156-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 744#L240 assume !(0 == ~M_E~0); 745#L240-2 assume !(0 == ~T1_E~0); 770#L245-1 assume !(0 == ~E_1~0); 775#L250-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 755#L105 assume !(1 == ~m_pc~0); 719#L105-2 is_master_triggered_~__retres1~0 := 0; 720#L116 is_master_triggered_#res := is_master_triggered_~__retres1~0; 721#L117 activate_threads_#t~ret3 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 722#L290 assume !(0 != activate_threads_~tmp~1); 736#L290-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 737#L124 assume !(1 == ~t1_pc~0); 772#L124-2 is_transmit1_triggered_~__retres1~1 := 0; 773#L135 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 710#L136 activate_threads_#t~ret4 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 711#L298 assume !(0 != activate_threads_~tmp___0~0); 731#L298-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 659#L263 assume !(1 == ~M_E~0); 650#L263-2 assume !(1 == ~T1_E~0); 651#L268-1 assume !(1 == ~E_1~0); 738#L273-1 assume { :end_inline_reset_delta_events } true; 746#L394-3 [2018-11-18 08:34:38,360 INFO L796 eck$LassoCheckResult]: Loop: 746#L394-3 assume true; 850#L394-1 assume !false; 848#L395 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_~tmp~0;havoc eval_~tmp~0; 847#L215 assume true; 842#L191-1 assume !false; 841#L192 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 838#L169 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2 := 1; 836#L181 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 834#L182 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 830#L196 assume !(0 != eval_~tmp~0); 828#L230 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 826#L144-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 824#L240-3 assume 0 == ~M_E~0;~M_E~0 := 1; 822#L240-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 820#L245-3 assume 0 == ~E_1~0;~E_1~0 := 1; 815#L250-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 809#L105-6 assume !(1 == ~m_pc~0); 805#L105-8 is_master_triggered_~__retres1~0 := 0; 803#L116-2 is_master_triggered_#res := is_master_triggered_~__retres1~0; 801#L117-2 activate_threads_#t~ret3 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 799#L290-6 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 796#L290-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 780#L124-6 assume !(1 == ~t1_pc~0); 756#L124-8 is_transmit1_triggered_~__retres1~1 := 0; 757#L135-2 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 693#L136-2 activate_threads_#t~ret4 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 694#L298-6 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 739#L298-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 682#L263-3 assume 1 == ~M_E~0;~M_E~0 := 2; 680#L263-5 assume !(1 == ~T1_E~0); 681#L268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 714#L273-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 705#L169-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2 := 1; 706#L181-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 776#L182-1 start_simulation_#t~ret6 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret6;havoc start_simulation_#t~ret6; 777#L413 assume !(0 == start_simulation_~tmp~3); 778#L413-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret5, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 864#L169-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2 := 1; 862#L181-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 860#L182-2 stop_simulation_#t~ret5 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret5;havoc stop_simulation_#t~ret5; 858#L368 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 856#L375 stop_simulation_#res := stop_simulation_~__retres2~0; 855#L376 start_simulation_#t~ret7 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret7;havoc start_simulation_#t~ret7; 853#L426 assume !(0 != start_simulation_~tmp___0~1); 746#L394-3 [2018-11-18 08:34:38,360 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 08:34:38,361 INFO L82 PathProgramCache]: Analyzing trace with hash -904654136, now seen corresponding path program 1 times [2018-11-18 08:34:38,361 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 08:34:38,361 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 08:34:38,362 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:38,362 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 08:34:38,362 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:38,367 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 08:34:38,374 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 08:34:38,388 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 08:34:38,388 INFO L82 PathProgramCache]: Analyzing trace with hash 2031451335, now seen corresponding path program 1 times [2018-11-18 08:34:38,388 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 08:34:38,388 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 08:34:38,389 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:38,389 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 08:34:38,389 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:38,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 08:34:38,414 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 08:34:38,415 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 08:34:38,415 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 08:34:38,415 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 08:34:38,415 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 08:34:38,415 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 08:34:38,416 INFO L87 Difference]: Start difference. First operand 223 states and 313 transitions. cyclomatic complexity: 92 Second operand 3 states. [2018-11-18 08:34:38,433 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 08:34:38,433 INFO L93 Difference]: Finished difference Result 275 states and 385 transitions. [2018-11-18 08:34:38,433 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 08:34:38,433 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 275 states and 385 transitions. [2018-11-18 08:34:38,435 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 230 [2018-11-18 08:34:38,436 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 275 states to 275 states and 385 transitions. [2018-11-18 08:34:38,436 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 275 [2018-11-18 08:34:38,436 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 275 [2018-11-18 08:34:38,436 INFO L73 IsDeterministic]: Start isDeterministic. Operand 275 states and 385 transitions. [2018-11-18 08:34:38,437 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 08:34:38,437 INFO L705 BuchiCegarLoop]: Abstraction has 275 states and 385 transitions. [2018-11-18 08:34:38,437 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 275 states and 385 transitions. [2018-11-18 08:34:38,443 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 275 to 275. [2018-11-18 08:34:38,443 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 275 states. [2018-11-18 08:34:38,444 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 275 states to 275 states and 385 transitions. [2018-11-18 08:34:38,445 INFO L728 BuchiCegarLoop]: Abstraction has 275 states and 385 transitions. [2018-11-18 08:34:38,445 INFO L608 BuchiCegarLoop]: Abstraction has 275 states and 385 transitions. [2018-11-18 08:34:38,445 INFO L442 BuchiCegarLoop]: ======== Iteration 4============ [2018-11-18 08:34:38,445 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 275 states and 385 transitions. [2018-11-18 08:34:38,446 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 230 [2018-11-18 08:34:38,446 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 08:34:38,447 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 08:34:38,447 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 08:34:38,447 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 08:34:38,448 INFO L794 eck$LassoCheckResult]: Stem: 1295#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 1180#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 1181#L357 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret6, start_simulation_#t~ret7, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 1233#L144 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1234#L151 assume 1 == ~m_i~0;~m_st~0 := 0; 1296#L151-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1297#L156-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1248#L240 assume !(0 == ~M_E~0); 1249#L240-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1277#L245-1 assume !(0 == ~E_1~0); 1284#L250-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1259#L105 assume !(1 == ~m_pc~0); 1223#L105-2 is_master_triggered_~__retres1~0 := 0; 1224#L116 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1225#L117 activate_threads_#t~ret3 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 1226#L290 assume !(0 != activate_threads_~tmp~1); 1240#L290-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1241#L124 assume !(1 == ~t1_pc~0); 1281#L124-2 is_transmit1_triggered_~__retres1~1 := 0; 1282#L135 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1214#L136 activate_threads_#t~ret4 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 1215#L298 assume !(0 != activate_threads_~tmp___0~0); 1235#L298-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1163#L263 assume !(1 == ~M_E~0); 1154#L263-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1155#L268-1 assume !(1 == ~E_1~0); 1242#L273-1 assume { :end_inline_reset_delta_events } true; 1250#L394-3 [2018-11-18 08:34:38,448 INFO L796 eck$LassoCheckResult]: Loop: 1250#L394-3 assume true; 1388#L394-1 assume !false; 1383#L395 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_~tmp~0;havoc eval_~tmp~0; 1291#L215 assume true; 1216#L191-1 assume !false; 1217#L192 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 1219#L169 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2 := 1; 1220#L181 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 1289#L182 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 1279#L196 assume !(0 != eval_~tmp~0); 1158#L230 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 1159#L144-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 1231#L240-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1270#L240-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1271#L245-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1283#L250-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1274#L105-6 assume !(1 == ~m_pc~0); 1168#L105-8 is_master_triggered_~__retres1~0 := 0; 1167#L116-2 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1171#L117-2 activate_threads_#t~ret3 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 1172#L290-6 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1187#L290-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1188#L124-6 assume !(1 == ~t1_pc~0); 1260#L124-8 is_transmit1_triggered_~__retres1~1 := 0; 1261#L135-2 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1197#L136-2 activate_threads_#t~ret4 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 1198#L298-6 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1243#L298-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1186#L263-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1184#L263-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1185#L268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1218#L273-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 1209#L169-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2 := 1; 1210#L181-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 1285#L182-1 start_simulation_#t~ret6 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret6;havoc start_simulation_#t~ret6; 1286#L413 assume !(0 == start_simulation_~tmp~3); 1287#L413-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret5, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 1292#L169-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2 := 1; 1404#L181-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 1403#L182-2 stop_simulation_#t~ret5 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret5;havoc stop_simulation_#t~ret5; 1402#L368 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1395#L375 stop_simulation_#res := stop_simulation_~__retres2~0; 1393#L376 start_simulation_#t~ret7 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret7;havoc start_simulation_#t~ret7; 1391#L426 assume !(0 != start_simulation_~tmp___0~1); 1250#L394-3 [2018-11-18 08:34:38,448 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 08:34:38,448 INFO L82 PathProgramCache]: Analyzing trace with hash 784287684, now seen corresponding path program 1 times [2018-11-18 08:34:38,448 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 08:34:38,448 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 08:34:38,449 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:38,449 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 08:34:38,449 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:38,452 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 08:34:38,466 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 08:34:38,466 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 08:34:38,466 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 08:34:38,467 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 08:34:38,467 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 08:34:38,467 INFO L82 PathProgramCache]: Analyzing trace with hash -983652283, now seen corresponding path program 1 times [2018-11-18 08:34:38,467 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 08:34:38,467 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 08:34:38,468 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:38,468 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 08:34:38,468 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:38,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 08:34:38,505 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 08:34:38,505 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 08:34:38,505 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 08:34:38,506 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 08:34:38,506 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 08:34:38,506 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 08:34:38,506 INFO L87 Difference]: Start difference. First operand 275 states and 385 transitions. cyclomatic complexity: 112 Second operand 3 states. [2018-11-18 08:34:38,526 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 08:34:38,527 INFO L93 Difference]: Finished difference Result 223 states and 305 transitions. [2018-11-18 08:34:38,527 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 08:34:38,527 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 223 states and 305 transitions. [2018-11-18 08:34:38,529 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 195 [2018-11-18 08:34:38,530 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 223 states to 223 states and 305 transitions. [2018-11-18 08:34:38,530 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 223 [2018-11-18 08:34:38,530 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 223 [2018-11-18 08:34:38,530 INFO L73 IsDeterministic]: Start isDeterministic. Operand 223 states and 305 transitions. [2018-11-18 08:34:38,531 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 08:34:38,531 INFO L705 BuchiCegarLoop]: Abstraction has 223 states and 305 transitions. [2018-11-18 08:34:38,532 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 223 states and 305 transitions. [2018-11-18 08:34:38,536 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 223 to 223. [2018-11-18 08:34:38,536 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 223 states. [2018-11-18 08:34:38,537 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 223 states to 223 states and 305 transitions. [2018-11-18 08:34:38,537 INFO L728 BuchiCegarLoop]: Abstraction has 223 states and 305 transitions. [2018-11-18 08:34:38,537 INFO L608 BuchiCegarLoop]: Abstraction has 223 states and 305 transitions. [2018-11-18 08:34:38,537 INFO L442 BuchiCegarLoop]: ======== Iteration 5============ [2018-11-18 08:34:38,537 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 223 states and 305 transitions. [2018-11-18 08:34:38,538 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 195 [2018-11-18 08:34:38,538 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 08:34:38,539 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 08:34:38,539 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 08:34:38,539 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 08:34:38,539 INFO L794 eck$LassoCheckResult]: Stem: 1797#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 1687#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 1688#L357 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret6, start_simulation_#t~ret7, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 1740#L144 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1741#L151 assume 1 == ~m_i~0;~m_st~0 := 0; 1798#L151-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1799#L156-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1755#L240 assume !(0 == ~M_E~0); 1756#L240-2 assume !(0 == ~T1_E~0); 1781#L245-1 assume !(0 == ~E_1~0); 1787#L250-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1768#L105 assume !(1 == ~m_pc~0); 1730#L105-2 is_master_triggered_~__retres1~0 := 0; 1731#L116 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1732#L117 activate_threads_#t~ret3 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 1733#L290 assume !(0 != activate_threads_~tmp~1); 1747#L290-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1748#L124 assume !(1 == ~t1_pc~0); 1784#L124-2 is_transmit1_triggered_~__retres1~1 := 0; 1785#L135 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1721#L136 activate_threads_#t~ret4 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 1722#L298 assume !(0 != activate_threads_~tmp___0~0); 1742#L298-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1670#L263 assume !(1 == ~M_E~0); 1661#L263-2 assume !(1 == ~T1_E~0); 1662#L268-1 assume !(1 == ~E_1~0); 1749#L273-1 assume { :end_inline_reset_delta_events } true; 1757#L394-3 [2018-11-18 08:34:38,540 INFO L796 eck$LassoCheckResult]: Loop: 1757#L394-3 assume true; 1777#L394-1 assume !false; 1858#L395 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_~tmp~0;havoc eval_~tmp~0; 1857#L215 assume true; 1855#L191-1 assume !false; 1853#L192 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 1850#L169 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2 := 1; 1848#L181 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 1846#L182 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 1844#L196 assume !(0 != eval_~tmp~0); 1665#L230 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 1666#L144-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 1738#L240-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1775#L240-5 assume !(0 == ~T1_E~0); 1776#L245-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1786#L250-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1778#L105-6 assume 1 == ~m_pc~0; 1673#L106-2 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 1674#L116-2 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1678#L117-2 activate_threads_#t~ret3 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 1679#L290-6 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1694#L290-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1695#L124-6 assume !(1 == ~t1_pc~0); 1792#L124-8 is_transmit1_triggered_~__retres1~1 := 0; 1856#L135-2 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1854#L136-2 activate_threads_#t~ret4 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 1852#L298-6 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1849#L298-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1847#L263-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1845#L263-5 assume !(1 == ~T1_E~0); 1843#L268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1840#L273-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 1836#L169-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2 := 1; 1830#L181-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 1827#L182-1 start_simulation_#t~ret6 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret6;havoc start_simulation_#t~ret6; 1824#L413 assume !(0 == start_simulation_~tmp~3); 1794#L413-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret5, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 1709#L169-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2 := 1; 1710#L181-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 1769#L182-2 stop_simulation_#t~ret5 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret5;havoc stop_simulation_#t~ret5; 1770#L368 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1765#L375 stop_simulation_#res := stop_simulation_~__retres2~0; 1663#L376 start_simulation_#t~ret7 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret7;havoc start_simulation_#t~ret7; 1664#L426 assume !(0 != start_simulation_~tmp___0~1); 1757#L394-3 [2018-11-18 08:34:38,540 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 08:34:38,540 INFO L82 PathProgramCache]: Analyzing trace with hash -904654136, now seen corresponding path program 2 times [2018-11-18 08:34:38,540 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 08:34:38,540 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 08:34:38,541 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:38,541 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 08:34:38,541 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:38,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 08:34:38,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 08:34:38,555 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 08:34:38,555 INFO L82 PathProgramCache]: Analyzing trace with hash -1253477078, now seen corresponding path program 1 times [2018-11-18 08:34:38,555 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 08:34:38,555 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 08:34:38,556 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:38,556 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 08:34:38,556 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:38,561 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 08:34:38,587 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 08:34:38,587 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 08:34:38,588 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 08:34:38,588 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 08:34:38,588 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 08:34:38,588 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 08:34:38,588 INFO L87 Difference]: Start difference. First operand 223 states and 305 transitions. cyclomatic complexity: 84 Second operand 5 states. [2018-11-18 08:34:38,676 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 08:34:38,676 INFO L93 Difference]: Finished difference Result 377 states and 504 transitions. [2018-11-18 08:34:38,676 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-18 08:34:38,677 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 377 states and 504 transitions. [2018-11-18 08:34:38,678 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 349 [2018-11-18 08:34:38,679 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 377 states to 377 states and 504 transitions. [2018-11-18 08:34:38,679 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 377 [2018-11-18 08:34:38,680 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 377 [2018-11-18 08:34:38,680 INFO L73 IsDeterministic]: Start isDeterministic. Operand 377 states and 504 transitions. [2018-11-18 08:34:38,680 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 08:34:38,680 INFO L705 BuchiCegarLoop]: Abstraction has 377 states and 504 transitions. [2018-11-18 08:34:38,681 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 377 states and 504 transitions. [2018-11-18 08:34:38,686 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 377 to 229. [2018-11-18 08:34:38,686 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 229 states. [2018-11-18 08:34:38,687 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 229 states to 229 states and 311 transitions. [2018-11-18 08:34:38,687 INFO L728 BuchiCegarLoop]: Abstraction has 229 states and 311 transitions. [2018-11-18 08:34:38,687 INFO L608 BuchiCegarLoop]: Abstraction has 229 states and 311 transitions. [2018-11-18 08:34:38,687 INFO L442 BuchiCegarLoop]: ======== Iteration 6============ [2018-11-18 08:34:38,687 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 229 states and 311 transitions. [2018-11-18 08:34:38,689 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 201 [2018-11-18 08:34:38,689 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 08:34:38,689 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 08:34:38,690 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 08:34:38,690 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 08:34:38,690 INFO L794 eck$LassoCheckResult]: Stem: 2429#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 2303#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 2304#L357 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret6, start_simulation_#t~ret7, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 2357#L144 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2358#L151 assume 1 == ~m_i~0;~m_st~0 := 0; 2430#L151-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2431#L156-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2377#L240 assume !(0 == ~M_E~0); 2378#L240-2 assume !(0 == ~T1_E~0); 2407#L245-1 assume !(0 == ~E_1~0); 2416#L250-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2391#L105 assume !(1 == ~m_pc~0); 2346#L105-2 is_master_triggered_~__retres1~0 := 0; 2347#L116 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2348#L117 activate_threads_#t~ret3 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 2349#L290 assume !(0 != activate_threads_~tmp~1); 2366#L290-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2367#L124 assume !(1 == ~t1_pc~0); 2410#L124-2 is_transmit1_triggered_~__retres1~1 := 0; 2411#L135 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2337#L136 activate_threads_#t~ret4 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 2338#L298 assume !(0 != activate_threads_~tmp___0~0); 2360#L298-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2286#L263 assume !(1 == ~M_E~0); 2277#L263-2 assume !(1 == ~T1_E~0); 2278#L268-1 assume !(1 == ~E_1~0); 2368#L273-1 assume { :end_inline_reset_delta_events } true; 2379#L394-3 [2018-11-18 08:34:38,690 INFO L796 eck$LassoCheckResult]: Loop: 2379#L394-3 assume true; 2397#L394-1 assume !false; 2335#L395 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_~tmp~0;havoc eval_~tmp~0; 2336#L215 assume true; 2339#L191-1 assume !false; 2340#L192 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 2342#L169 assume !(0 == ~m_st~0); 2344#L173 assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2 := 0; 2433#L181 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 2456#L182 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 2454#L196 assume !(0 != eval_~tmp~0); 2281#L230 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 2282#L144-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 2401#L240-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2402#L240-5 assume !(0 == ~T1_E~0); 2451#L245-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2432#L250-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2405#L105-6 assume 1 == ~m_pc~0; 2289#L106-2 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 2290#L116-2 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2294#L117-2 activate_threads_#t~ret3 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 2295#L290-6 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2310#L290-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2311#L124-6 assume !(1 == ~t1_pc~0); 2421#L124-8 is_transmit1_triggered_~__retres1~1 := 0; 2412#L135-2 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2413#L136-2 activate_threads_#t~ret4 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 2373#L298-6 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2374#L298-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2309#L263-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2307#L263-5 assume !(1 == ~T1_E~0); 2308#L268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2341#L273-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 2469#L169-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2 := 1; 2467#L181-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 2466#L182-1 start_simulation_#t~ret6 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret6;havoc start_simulation_#t~ret6; 2464#L413 assume !(0 == start_simulation_~tmp~3); 2424#L413-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret5, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 2425#L169-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2 := 1; 2486#L181-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 2485#L182-2 stop_simulation_#t~ret5 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret5;havoc stop_simulation_#t~ret5; 2484#L368 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2386#L375 stop_simulation_#res := stop_simulation_~__retres2~0; 2279#L376 start_simulation_#t~ret7 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret7;havoc start_simulation_#t~ret7; 2280#L426 assume !(0 != start_simulation_~tmp___0~1); 2379#L394-3 [2018-11-18 08:34:38,690 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 08:34:38,691 INFO L82 PathProgramCache]: Analyzing trace with hash -904654136, now seen corresponding path program 3 times [2018-11-18 08:34:38,691 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 08:34:38,691 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 08:34:38,691 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:38,692 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 08:34:38,692 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:38,695 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 08:34:38,698 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 08:34:38,702 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 08:34:38,702 INFO L82 PathProgramCache]: Analyzing trace with hash -373636911, now seen corresponding path program 1 times [2018-11-18 08:34:38,702 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 08:34:38,702 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 08:34:38,703 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:38,703 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 08:34:38,703 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:38,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 08:34:38,761 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 08:34:38,761 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 08:34:38,761 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 08:34:38,761 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 08:34:38,761 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 08:34:38,762 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 08:34:38,762 INFO L87 Difference]: Start difference. First operand 229 states and 311 transitions. cyclomatic complexity: 84 Second operand 5 states. [2018-11-18 08:34:38,823 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 08:34:38,823 INFO L93 Difference]: Finished difference Result 391 states and 522 transitions. [2018-11-18 08:34:38,823 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 08:34:38,824 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 391 states and 522 transitions. [2018-11-18 08:34:38,825 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 363 [2018-11-18 08:34:38,826 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 391 states to 391 states and 522 transitions. [2018-11-18 08:34:38,827 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 391 [2018-11-18 08:34:38,827 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 391 [2018-11-18 08:34:38,827 INFO L73 IsDeterministic]: Start isDeterministic. Operand 391 states and 522 transitions. [2018-11-18 08:34:38,828 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 08:34:38,828 INFO L705 BuchiCegarLoop]: Abstraction has 391 states and 522 transitions. [2018-11-18 08:34:38,828 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 391 states and 522 transitions. [2018-11-18 08:34:38,832 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 391 to 238. [2018-11-18 08:34:38,832 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 238 states. [2018-11-18 08:34:38,833 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 238 states to 238 states and 316 transitions. [2018-11-18 08:34:38,833 INFO L728 BuchiCegarLoop]: Abstraction has 238 states and 316 transitions. [2018-11-18 08:34:38,833 INFO L608 BuchiCegarLoop]: Abstraction has 238 states and 316 transitions. [2018-11-18 08:34:38,833 INFO L442 BuchiCegarLoop]: ======== Iteration 7============ [2018-11-18 08:34:38,833 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 238 states and 316 transitions. [2018-11-18 08:34:38,834 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 210 [2018-11-18 08:34:38,834 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 08:34:38,834 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 08:34:38,835 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 08:34:38,835 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 08:34:38,835 INFO L794 eck$LassoCheckResult]: Stem: 3056#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 2937#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 2938#L357 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret6, start_simulation_#t~ret7, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 2991#L144 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2992#L151 assume 1 == ~m_i~0;~m_st~0 := 0; 3057#L151-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3058#L156-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3009#L240 assume !(0 == ~M_E~0); 3010#L240-2 assume !(0 == ~T1_E~0); 3037#L245-1 assume !(0 == ~E_1~0); 3045#L250-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3023#L105 assume !(1 == ~m_pc~0); 2981#L105-2 is_master_triggered_~__retres1~0 := 0; 2982#L116 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2983#L117 activate_threads_#t~ret3 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 2984#L290 assume !(0 != activate_threads_~tmp~1); 2999#L290-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3000#L124 assume !(1 == ~t1_pc~0); 3039#L124-2 is_transmit1_triggered_~__retres1~1 := 0; 3040#L135 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2967#L136 activate_threads_#t~ret4 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 2968#L298 assume !(0 != activate_threads_~tmp___0~0); 2994#L298-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2917#L263 assume !(1 == ~M_E~0); 2911#L263-2 assume !(1 == ~T1_E~0); 2912#L268-1 assume !(1 == ~E_1~0); 3001#L273-1 assume { :end_inline_reset_delta_events } true; 3011#L394-3 [2018-11-18 08:34:38,835 INFO L796 eck$LassoCheckResult]: Loop: 3011#L394-3 assume true; 3108#L394-1 assume !false; 3104#L395 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_~tmp~0;havoc eval_~tmp~0; 3102#L215 assume true; 3100#L191-1 assume !false; 3098#L192 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 3096#L169 assume !(0 == ~m_st~0); 3093#L173 assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2 := 0; 3090#L181 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 3088#L182 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 3085#L196 assume !(0 != eval_~tmp~0); 3082#L230 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 3080#L144-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 3078#L240-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3075#L240-5 assume !(0 == ~T1_E~0); 3073#L245-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3072#L250-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3071#L105-6 assume !(1 == ~m_pc~0); 3069#L105-8 is_master_triggered_~__retres1~0 := 0; 3017#L116-2 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2928#L117-2 activate_threads_#t~ret3 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 2929#L290-6 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2956#L290-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3049#L124-6 assume !(1 == ~t1_pc~0); 3050#L124-8 is_transmit1_triggered_~__retres1~1 := 0; 3115#L135-2 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3112#L136-2 activate_threads_#t~ret4 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 3107#L298-6 assume !(0 != activate_threads_~tmp___0~0); 3103#L298-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3101#L263-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3099#L263-5 assume !(1 == ~T1_E~0); 3097#L268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3095#L273-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 3092#L169-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2 := 1; 3089#L181-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 3087#L182-1 start_simulation_#t~ret6 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret6;havoc start_simulation_#t~ret6; 3083#L413 assume !(0 == start_simulation_~tmp~3); 3084#L413-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret5, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 3131#L169-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2 := 1; 3129#L181-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 3127#L182-2 stop_simulation_#t~ret5 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret5;havoc stop_simulation_#t~ret5; 3125#L368 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 3121#L375 stop_simulation_#res := stop_simulation_~__retres2~0; 3119#L376 start_simulation_#t~ret7 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret7;havoc start_simulation_#t~ret7; 3116#L426 assume !(0 != start_simulation_~tmp___0~1); 3011#L394-3 [2018-11-18 08:34:38,836 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 08:34:38,836 INFO L82 PathProgramCache]: Analyzing trace with hash -904654136, now seen corresponding path program 4 times [2018-11-18 08:34:38,836 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 08:34:38,836 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 08:34:38,841 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:38,841 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 08:34:38,842 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:38,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 08:34:38,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 08:34:38,849 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 08:34:38,850 INFO L82 PathProgramCache]: Analyzing trace with hash 1618746670, now seen corresponding path program 1 times [2018-11-18 08:34:38,850 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 08:34:38,850 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 08:34:38,851 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:38,851 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 08:34:38,851 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:38,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 08:34:38,901 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 08:34:38,902 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 08:34:38,902 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 08:34:38,902 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 08:34:38,902 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 08:34:38,902 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 08:34:38,903 INFO L87 Difference]: Start difference. First operand 238 states and 316 transitions. cyclomatic complexity: 80 Second operand 5 states. [2018-11-18 08:34:38,966 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 08:34:38,966 INFO L93 Difference]: Finished difference Result 629 states and 815 transitions. [2018-11-18 08:34:38,967 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 08:34:38,967 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 629 states and 815 transitions. [2018-11-18 08:34:38,969 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 576 [2018-11-18 08:34:38,972 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 629 states to 629 states and 815 transitions. [2018-11-18 08:34:38,972 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 629 [2018-11-18 08:34:38,972 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 629 [2018-11-18 08:34:38,972 INFO L73 IsDeterministic]: Start isDeterministic. Operand 629 states and 815 transitions. [2018-11-18 08:34:38,973 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 08:34:38,973 INFO L705 BuchiCegarLoop]: Abstraction has 629 states and 815 transitions. [2018-11-18 08:34:38,974 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 629 states and 815 transitions. [2018-11-18 08:34:38,979 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 629 to 259. [2018-11-18 08:34:38,979 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 259 states. [2018-11-18 08:34:38,980 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 259 states to 259 states and 337 transitions. [2018-11-18 08:34:38,980 INFO L728 BuchiCegarLoop]: Abstraction has 259 states and 337 transitions. [2018-11-18 08:34:38,980 INFO L608 BuchiCegarLoop]: Abstraction has 259 states and 337 transitions. [2018-11-18 08:34:38,980 INFO L442 BuchiCegarLoop]: ======== Iteration 8============ [2018-11-18 08:34:38,980 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 259 states and 337 transitions. [2018-11-18 08:34:38,981 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 228 [2018-11-18 08:34:38,981 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 08:34:38,982 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 08:34:38,982 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 08:34:38,982 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 08:34:38,983 INFO L794 eck$LassoCheckResult]: Stem: 3950#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 3817#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 3818#L357 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret6, start_simulation_#t~ret7, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 3872#L144 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3873#L151 assume 1 == ~m_i~0;~m_st~0 := 0; 3952#L151-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3953#L156-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3891#L240 assume !(0 == ~M_E~0); 3892#L240-2 assume !(0 == ~T1_E~0); 3931#L245-1 assume !(0 == ~E_1~0); 3939#L250-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3912#L105 assume !(1 == ~m_pc~0); 3861#L105-2 is_master_triggered_~__retres1~0 := 0; 3903#L116 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3913#L117 activate_threads_#t~ret3 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 3884#L290 assume !(0 != activate_threads_~tmp~1); 3881#L290-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3882#L124 assume !(1 == ~t1_pc~0); 3934#L124-2 is_transmit1_triggered_~__retres1~1 := 0; 3935#L135 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3847#L136 activate_threads_#t~ret4 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 3848#L298 assume !(0 != activate_threads_~tmp___0~0); 3874#L298-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3797#L263 assume !(1 == ~M_E~0); 3791#L263-2 assume !(1 == ~T1_E~0); 3792#L268-1 assume !(1 == ~E_1~0); 3883#L273-1 assume { :end_inline_reset_delta_events } true; 3893#L394-3 [2018-11-18 08:34:38,983 INFO L796 eck$LassoCheckResult]: Loop: 3893#L394-3 assume true; 3919#L394-1 assume !false; 3849#L395 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_~tmp~0;havoc eval_~tmp~0; 3850#L215 assume true; 3854#L191-1 assume !false; 3855#L192 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 3958#L169 assume !(0 == ~m_st~0); 4008#L173 assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2 := 0; 4006#L181 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 4004#L182 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 4002#L196 assume !(0 != eval_~tmp~0); 4000#L230 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 3998#L144-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 3995#L240-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3993#L240-5 assume !(0 == ~T1_E~0); 3992#L245-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3989#L250-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3928#L105-6 assume !(1 == ~m_pc~0); 3929#L105-8 is_master_triggered_~__retres1~0 := 0; 3988#L116-2 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3986#L117-2 activate_threads_#t~ret3 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 3984#L290-6 assume !(0 != activate_threads_~tmp~1); 3978#L290-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3944#L124-6 assume !(1 == ~t1_pc~0); 3914#L124-8 is_transmit1_triggered_~__retres1~1 := 0; 3915#L135-2 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3936#L136-2 activate_threads_#t~ret4 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 3888#L298-6 assume !(0 != activate_threads_~tmp___0~0); 3887#L298-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3823#L263-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3821#L263-5 assume !(1 == ~T1_E~0); 3822#L268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3859#L273-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 3851#L169-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2 := 1; 3852#L181-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 3951#L182-1 start_simulation_#t~ret6 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret6;havoc start_simulation_#t~ret6; 3979#L413 assume !(0 == start_simulation_~tmp~3); 3948#L413-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret5, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 3842#L169-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2 := 1; 3843#L181-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 3916#L182-2 stop_simulation_#t~ret5 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret5;havoc stop_simulation_#t~ret5; 3917#L368 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 3902#L375 stop_simulation_#res := stop_simulation_~__retres2~0; 3793#L376 start_simulation_#t~ret7 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret7;havoc start_simulation_#t~ret7; 3794#L426 assume !(0 != start_simulation_~tmp___0~1); 3893#L394-3 [2018-11-18 08:34:38,983 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 08:34:38,983 INFO L82 PathProgramCache]: Analyzing trace with hash -904654136, now seen corresponding path program 5 times [2018-11-18 08:34:38,983 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 08:34:38,983 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 08:34:38,984 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:38,984 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 08:34:38,984 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:38,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 08:34:38,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 08:34:38,997 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 08:34:38,997 INFO L82 PathProgramCache]: Analyzing trace with hash 1484733164, now seen corresponding path program 1 times [2018-11-18 08:34:38,997 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 08:34:38,997 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 08:34:38,998 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:38,998 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 08:34:38,998 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:39,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 08:34:39,019 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 08:34:39,019 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 08:34:39,019 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 08:34:39,019 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 08:34:39,020 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 08:34:39,020 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 08:34:39,020 INFO L87 Difference]: Start difference. First operand 259 states and 337 transitions. cyclomatic complexity: 80 Second operand 3 states. [2018-11-18 08:34:39,043 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 08:34:39,043 INFO L93 Difference]: Finished difference Result 413 states and 523 transitions. [2018-11-18 08:34:39,043 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 08:34:39,044 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 413 states and 523 transitions. [2018-11-18 08:34:39,045 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 382 [2018-11-18 08:34:39,046 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 413 states to 413 states and 523 transitions. [2018-11-18 08:34:39,046 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 413 [2018-11-18 08:34:39,047 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 413 [2018-11-18 08:34:39,047 INFO L73 IsDeterministic]: Start isDeterministic. Operand 413 states and 523 transitions. [2018-11-18 08:34:39,048 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 08:34:39,048 INFO L705 BuchiCegarLoop]: Abstraction has 413 states and 523 transitions. [2018-11-18 08:34:39,048 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 413 states and 523 transitions. [2018-11-18 08:34:39,051 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 413 to 387. [2018-11-18 08:34:39,051 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 387 states. [2018-11-18 08:34:39,052 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 387 states to 387 states and 494 transitions. [2018-11-18 08:34:39,052 INFO L728 BuchiCegarLoop]: Abstraction has 387 states and 494 transitions. [2018-11-18 08:34:39,052 INFO L608 BuchiCegarLoop]: Abstraction has 387 states and 494 transitions. [2018-11-18 08:34:39,052 INFO L442 BuchiCegarLoop]: ======== Iteration 9============ [2018-11-18 08:34:39,053 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 387 states and 494 transitions. [2018-11-18 08:34:39,054 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 356 [2018-11-18 08:34:39,054 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 08:34:39,054 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 08:34:39,055 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 08:34:39,055 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 08:34:39,055 INFO L794 eck$LassoCheckResult]: Stem: 4630#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 4495#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 4496#L357 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret6, start_simulation_#t~ret7, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 4547#L144 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4548#L151 assume 1 == ~m_i~0;~m_st~0 := 0; 4633#L151-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4634#L156-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4568#L240 assume !(0 == ~M_E~0); 4569#L240-2 assume !(0 == ~T1_E~0); 4608#L245-1 assume !(0 == ~E_1~0); 4617#L250-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4592#L105 assume !(1 == ~m_pc~0); 4536#L105-2 is_master_triggered_~__retres1~0 := 0; 4580#L116 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4538#L117 activate_threads_#t~ret3 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 4539#L290 assume !(0 != activate_threads_~tmp~1); 4557#L290-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4558#L124 assume !(1 == ~t1_pc~0); 4612#L124-2 is_transmit1_triggered_~__retres1~1 := 0; 4613#L135 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4528#L136 activate_threads_#t~ret4 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 4529#L298 assume !(0 != activate_threads_~tmp___0~0); 4550#L298-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4478#L263 assume !(1 == ~M_E~0); 4469#L263-2 assume !(1 == ~T1_E~0); 4470#L268-1 assume !(1 == ~E_1~0); 4559#L273-1 assume { :end_inline_reset_delta_events } true; 4570#L394-3 [2018-11-18 08:34:39,055 INFO L796 eck$LassoCheckResult]: Loop: 4570#L394-3 assume true; 4801#L394-1 assume !false; 4800#L395 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_~tmp~0;havoc eval_~tmp~0; 4567#L215 assume true; 4796#L191-1 assume !false; 4795#L192 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 4794#L169 assume !(0 == ~m_st~0); 4667#L173 assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2 := 0; 4666#L181 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 4665#L182 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 4664#L196 assume !(0 != eval_~tmp~0); 4663#L230 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 4544#L144-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 4545#L240-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4601#L240-5 assume !(0 == ~T1_E~0); 4602#L245-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4615#L250-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4607#L105-6 assume 1 == ~m_pc~0; 4481#L106-2 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 4482#L116-2 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4850#L117-2 activate_threads_#t~ret3 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 4849#L290-6 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4502#L290-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4503#L124-6 assume !(1 == ~t1_pc~0); 4593#L124-8 is_transmit1_triggered_~__retres1~1 := 0; 4594#L135-2 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4512#L136-2 activate_threads_#t~ret4 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 4513#L298-6 assume !(0 != activate_threads_~tmp___0~0); 4564#L298-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4833#L263-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4831#L263-5 assume !(1 == ~T1_E~0); 4829#L268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4827#L273-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 4825#L169-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2 := 1; 4823#L181-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 4821#L182-1 start_simulation_#t~ret6 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret6;havoc start_simulation_#t~ret6; 4818#L413 assume !(0 == start_simulation_~tmp~3); 4817#L413-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret5, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 4816#L169-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2 := 1; 4815#L181-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 4813#L182-2 stop_simulation_#t~ret5 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret5;havoc stop_simulation_#t~ret5; 4641#L368 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 4579#L375 stop_simulation_#res := stop_simulation_~__retres2~0; 4471#L376 start_simulation_#t~ret7 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret7;havoc start_simulation_#t~ret7; 4472#L426 assume !(0 != start_simulation_~tmp___0~1); 4570#L394-3 [2018-11-18 08:34:39,055 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 08:34:39,055 INFO L82 PathProgramCache]: Analyzing trace with hash -904654136, now seen corresponding path program 6 times [2018-11-18 08:34:39,056 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 08:34:39,056 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 08:34:39,056 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:39,056 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 08:34:39,057 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:39,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 08:34:39,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 08:34:39,064 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 08:34:39,064 INFO L82 PathProgramCache]: Analyzing trace with hash 1927185679, now seen corresponding path program 1 times [2018-11-18 08:34:39,064 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 08:34:39,064 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 08:34:39,065 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:39,065 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 08:34:39,065 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:39,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 08:34:39,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 08:34:39,081 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 08:34:39,081 INFO L82 PathProgramCache]: Analyzing trace with hash -1926313560, now seen corresponding path program 1 times [2018-11-18 08:34:39,081 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 08:34:39,081 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 08:34:39,082 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:39,082 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 08:34:39,082 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:39,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 08:34:39,116 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 08:34:39,116 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 08:34:39,117 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 08:34:39,294 WARN L180 SmtUtils]: Spent 172.00 ms on a formula simplification. DAG size of input: 86 DAG size of output: 77 [2018-11-18 08:34:39,344 INFO L216 LassoAnalysis]: Preferences: [2018-11-18 08:34:39,345 INFO L124 ssoRankerPreferences]: Compute integeral hull: false [2018-11-18 08:34:39,345 INFO L125 ssoRankerPreferences]: Enable LassoPartitioneer: true [2018-11-18 08:34:39,345 INFO L126 ssoRankerPreferences]: Term annotations enabled: false [2018-11-18 08:34:39,345 INFO L127 ssoRankerPreferences]: Use exernal solver: true [2018-11-18 08:34:39,345 INFO L128 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 08:34:39,346 INFO L129 ssoRankerPreferences]: Dump SMT script to file: false [2018-11-18 08:34:39,346 INFO L130 ssoRankerPreferences]: Path of dumped script: [2018-11-18 08:34:39,346 INFO L131 ssoRankerPreferences]: Filename of dumped script: transmitter.01_false-unreach-call_false-termination.cil.c_Iteration9_Loop [2018-11-18 08:34:39,346 INFO L132 ssoRankerPreferences]: MapElimAlgo: Frank [2018-11-18 08:34:39,346 INFO L282 LassoAnalysis]: Starting lasso preprocessing... [2018-11-18 08:34:39,359 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 08:34:39,366 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 08:34:39,369 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 08:34:39,371 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 08:34:39,372 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 08:34:39,376 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 08:34:39,378 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 08:34:39,381 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 08:34:39,386 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 08:34:39,391 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 08:34:39,394 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 08:34:39,397 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 08:34:39,399 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 08:34:39,400 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 08:34:39,402 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 08:34:39,403 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 08:34:39,407 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 08:34:39,409 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 08:34:39,412 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 08:34:39,413 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 08:34:39,415 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 08:34:39,416 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 08:34:39,422 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 08:34:39,424 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 08:34:39,427 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 08:34:39,576 INFO L300 LassoAnalysis]: Preprocessing complete. [2018-11-18 08:34:39,576 INFO L412 LassoAnalysis]: Checking for nontermination... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2bd7126d-33d4-426b-8346-9856ccc05d04/bin-2019/uautomizer/z3 Starting monitored process 2 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 08:34:39,580 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-18 08:34:39,580 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-18 08:34:39,586 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-18 08:34:39,586 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_~tmp___0~0=0, ULTIMATE.start_is_transmit1_triggered_~__retres1~1=0, ULTIMATE.start_is_transmit1_triggered_#res=0} Honda state: {ULTIMATE.start_activate_threads_~tmp___0~0=0, ULTIMATE.start_is_transmit1_triggered_~__retres1~1=0, ULTIMATE.start_is_transmit1_triggered_#res=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2bd7126d-33d4-426b-8346-9856ccc05d04/bin-2019/uautomizer/z3 Starting monitored process 3 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 08:34:39,603 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-18 08:34:39,603 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-18 08:34:39,606 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-18 08:34:39,606 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret3=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret3=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2bd7126d-33d4-426b-8346-9856ccc05d04/bin-2019/uautomizer/z3 Starting monitored process 4 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 08:34:39,630 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-18 08:34:39,630 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-18 08:34:39,632 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-18 08:34:39,632 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t1_pc~0=4} Honda state: {~t1_pc~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2bd7126d-33d4-426b-8346-9856ccc05d04/bin-2019/uautomizer/z3 Starting monitored process 5 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 08:34:39,650 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-18 08:34:39,650 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-18 08:34:39,653 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-18 08:34:39,653 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet1=0} Honda state: {ULTIMATE.start_eval_#t~nondet1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2bd7126d-33d4-426b-8346-9856ccc05d04/bin-2019/uautomizer/z3 Starting monitored process 6 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 08:34:39,686 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-18 08:34:39,686 INFO L163 nArgumentSynthesizer]: Using integer mode. No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_2bd7126d-33d4-426b-8346-9856ccc05d04/bin-2019/uautomizer/z3 Starting monitored process 7 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 08:34:39,717 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2018-11-18 08:34:39,718 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-18 08:34:39,721 INFO L452 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2018-11-18 08:34:39,735 INFO L216 LassoAnalysis]: Preferences: [2018-11-18 08:34:39,735 INFO L124 ssoRankerPreferences]: Compute integeral hull: false [2018-11-18 08:34:39,735 INFO L125 ssoRankerPreferences]: Enable LassoPartitioneer: true [2018-11-18 08:34:39,735 INFO L126 ssoRankerPreferences]: Term annotations enabled: false [2018-11-18 08:34:39,735 INFO L127 ssoRankerPreferences]: Use exernal solver: false [2018-11-18 08:34:39,735 INFO L128 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 08:34:39,735 INFO L129 ssoRankerPreferences]: Dump SMT script to file: false [2018-11-18 08:34:39,735 INFO L130 ssoRankerPreferences]: Path of dumped script: [2018-11-18 08:34:39,735 INFO L131 ssoRankerPreferences]: Filename of dumped script: transmitter.01_false-unreach-call_false-termination.cil.c_Iteration9_Loop [2018-11-18 08:34:39,735 INFO L132 ssoRankerPreferences]: MapElimAlgo: Frank [2018-11-18 08:34:39,735 INFO L282 LassoAnalysis]: Starting lasso preprocessing... [2018-11-18 08:34:39,737 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 08:34:39,753 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 08:34:39,772 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 08:34:39,774 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 08:34:39,778 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 08:34:39,779 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 08:34:39,783 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 08:34:39,787 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 08:34:39,788 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 08:34:39,789 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 08:34:39,792 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 08:34:39,793 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 08:34:39,795 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 08:34:39,798 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 08:34:39,799 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 08:34:39,800 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 08:34:39,801 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 08:34:39,804 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 08:34:39,808 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 08:34:39,811 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 08:34:39,812 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 08:34:39,813 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 08:34:39,814 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 08:34:39,816 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 08:34:39,819 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 08:34:40,023 INFO L300 LassoAnalysis]: Preprocessing complete. [2018-11-18 08:34:40,029 INFO L497 LassoAnalysis]: Using template 'affine'. [2018-11-18 08:34:40,030 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-18 08:34:40,031 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-18 08:34:40,032 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-18 08:34:40,032 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-18 08:34:40,032 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-18 08:34:40,032 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-18 08:34:40,034 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-18 08:34:40,034 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-18 08:34:40,036 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-18 08:34:40,037 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-18 08:34:40,037 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-18 08:34:40,037 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-18 08:34:40,038 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-18 08:34:40,038 INFO L206 nArgumentSynthesizer]: 2 loop disjuncts [2018-11-18 08:34:40,038 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-18 08:34:40,038 INFO L402 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2018-11-18 08:34:40,038 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-18 08:34:40,039 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-18 08:34:40,039 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-18 08:34:40,040 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-18 08:34:40,040 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-18 08:34:40,040 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-18 08:34:40,040 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-18 08:34:40,040 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-18 08:34:40,045 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-18 08:34:40,045 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-18 08:34:40,045 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-18 08:34:40,046 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-18 08:34:40,046 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-18 08:34:40,046 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-18 08:34:40,046 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-18 08:34:40,046 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-18 08:34:40,046 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-18 08:34:40,047 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-18 08:34:40,047 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-18 08:34:40,049 INFO L421 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2018-11-18 08:34:40,051 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2018-11-18 08:34:40,051 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2018-11-18 08:34:40,052 INFO L437 nArgumentSynthesizer]: Simplifying supporting invariants... [2018-11-18 08:34:40,053 INFO L440 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2018-11-18 08:34:40,053 INFO L518 LassoAnalysis]: Proved termination. [2018-11-18 08:34:40,053 INFO L520 LassoAnalysis]: Termination argument consisting of: Ranking function f(~M_E~0) = -1*~M_E~0 + 1 Supporting invariants [] [2018-11-18 08:34:40,054 INFO L297 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2018-11-18 08:34:40,085 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 08:34:40,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 08:34:40,101 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 08:34:40,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 08:34:40,122 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 08:34:40,163 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 08:34:40,165 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2018-11-18 08:34:40,166 INFO L72 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 387 states and 494 transitions. cyclomatic complexity: 109 Second operand 5 states. [2018-11-18 08:34:40,227 INFO L76 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 387 states and 494 transitions. cyclomatic complexity: 109. Second operand 5 states. Result 929 states and 1185 transitions. Complement of second has 5 states. [2018-11-18 08:34:40,228 INFO L142 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2018-11-18 08:34:40,229 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5 states. [2018-11-18 08:34:40,229 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 153 transitions. [2018-11-18 08:34:40,231 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 153 transitions. Stem has 27 letters. Loop has 45 letters. [2018-11-18 08:34:40,235 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2018-11-18 08:34:40,235 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 153 transitions. Stem has 72 letters. Loop has 45 letters. [2018-11-18 08:34:40,236 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2018-11-18 08:34:40,236 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 153 transitions. Stem has 27 letters. Loop has 90 letters. [2018-11-18 08:34:40,237 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2018-11-18 08:34:40,237 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 929 states and 1185 transitions. [2018-11-18 08:34:40,244 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 620 [2018-11-18 08:34:40,248 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 929 states to 929 states and 1185 transitions. [2018-11-18 08:34:40,249 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 652 [2018-11-18 08:34:40,249 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 659 [2018-11-18 08:34:40,249 INFO L73 IsDeterministic]: Start isDeterministic. Operand 929 states and 1185 transitions. [2018-11-18 08:34:40,250 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-18 08:34:40,250 INFO L705 BuchiCegarLoop]: Abstraction has 929 states and 1185 transitions. [2018-11-18 08:34:40,250 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 929 states and 1185 transitions. [2018-11-18 08:34:40,261 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 929 to 922. [2018-11-18 08:34:40,261 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 922 states. [2018-11-18 08:34:40,263 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 922 states to 922 states and 1172 transitions. [2018-11-18 08:34:40,263 INFO L728 BuchiCegarLoop]: Abstraction has 922 states and 1172 transitions. [2018-11-18 08:34:40,264 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 08:34:40,264 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 08:34:40,264 INFO L87 Difference]: Start difference. First operand 922 states and 1172 transitions. Second operand 3 states. [2018-11-18 08:34:40,296 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 08:34:40,296 INFO L93 Difference]: Finished difference Result 1000 states and 1235 transitions. [2018-11-18 08:34:40,296 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 08:34:40,297 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1000 states and 1235 transitions. [2018-11-18 08:34:40,301 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 672 [2018-11-18 08:34:40,304 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1000 states to 1000 states and 1235 transitions. [2018-11-18 08:34:40,305 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 704 [2018-11-18 08:34:40,305 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 704 [2018-11-18 08:34:40,305 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1000 states and 1235 transitions. [2018-11-18 08:34:40,305 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-18 08:34:40,306 INFO L705 BuchiCegarLoop]: Abstraction has 1000 states and 1235 transitions. [2018-11-18 08:34:40,306 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1000 states and 1235 transitions. [2018-11-18 08:34:40,315 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1000 to 922. [2018-11-18 08:34:40,315 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 922 states. [2018-11-18 08:34:40,317 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 922 states to 922 states and 1148 transitions. [2018-11-18 08:34:40,318 INFO L728 BuchiCegarLoop]: Abstraction has 922 states and 1148 transitions. [2018-11-18 08:34:40,318 INFO L608 BuchiCegarLoop]: Abstraction has 922 states and 1148 transitions. [2018-11-18 08:34:40,318 INFO L442 BuchiCegarLoop]: ======== Iteration 10============ [2018-11-18 08:34:40,318 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 922 states and 1148 transitions. [2018-11-18 08:34:40,321 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 620 [2018-11-18 08:34:40,321 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 08:34:40,321 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 08:34:40,322 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 08:34:40,322 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 08:34:40,322 INFO L794 eck$LassoCheckResult]: Stem: 8223#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 7990#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 7991#L357 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret6, start_simulation_#t~ret7, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 8083#L144 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8084#L151 assume 1 == ~m_i~0;~m_st~0 := 0; 8227#L151-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8228#L156-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8108#L240 assume !(0 == ~M_E~0); 8109#L240-2 assume !(0 == ~T1_E~0); 8178#L245-1 assume !(0 == ~E_1~0); 8198#L250-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8142#L105 assume !(1 == ~m_pc~0); 8066#L105-2 is_master_triggered_~__retres1~0 := 0; 8128#L116 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8068#L117 activate_threads_#t~ret3 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 8069#L290 assume !(0 != activate_threads_~tmp~1); 8092#L290-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8093#L124 assume !(1 == ~t1_pc~0); 8186#L124-2 is_transmit1_triggered_~__retres1~1 := 0; 8187#L135 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8045#L136 activate_threads_#t~ret4 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 8046#L298 assume !(0 != activate_threads_~tmp___0~0); 8085#L298-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7956#L263 assume !(1 == ~M_E~0); 7946#L263-2 assume !(1 == ~T1_E~0); 7947#L268-1 assume !(1 == ~E_1~0); 8094#L273-1 assume { :end_inline_reset_delta_events } true; 8110#L394-3 assume true; 8302#L394-1 [2018-11-18 08:34:40,322 INFO L796 eck$LassoCheckResult]: Loop: 8302#L394-1 assume !false; 8728#L395 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_~tmp~0;havoc eval_~tmp~0; 8727#L215 assume true; 8726#L191-1 assume !false; 8724#L192 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 8722#L169 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2 := 1; 8720#L181 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 8718#L182 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 8716#L196 assume 0 != eval_~tmp~0; 8711#L196-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 8706#L204 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1;assume { :begin_inline_master } true; 8702#L31 assume !(0 == ~m_pc~0); 8696#L34 assume 1 == ~m_pc~0; 8679#L35 assume true; 8677#L50-1 assume !false; 8531#L51 ~m_pc~0 := 1;~m_st~0 := 2; 8525#L61 assume { :end_inline_master } true; 8523#L201 assume !(0 == ~t1_st~0); 8521#L215 assume true; 8590#L191-1 assume !false; 8589#L192 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 8588#L169 assume !(0 == ~m_st~0); 8236#L173 assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2 := 0; 8238#L181 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 8586#L182 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 8580#L196 assume !(0 != eval_~tmp~0); 7952#L230 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 7953#L144-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 8078#L240-3 assume !(0 == ~M_E~0); 8166#L240-5 assume !(0 == ~T1_E~0); 8768#L245-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8809#L250-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8808#L105-6 assume 1 == ~m_pc~0; 8806#L106-2 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 8805#L116-2 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8804#L117-2 activate_threads_#t~ret3 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 8803#L290-6 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 8801#L290-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8800#L124-6 assume !(1 == ~t1_pc~0); 8799#L124-8 is_transmit1_triggered_~__retres1~1 := 0; 8798#L135-2 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8797#L136-2 activate_threads_#t~ret4 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 8796#L298-6 assume !(0 != activate_threads_~tmp___0~0); 8795#L298-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8794#L263-3 assume !(1 == ~M_E~0); 8793#L263-5 assume !(1 == ~T1_E~0); 8791#L268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8789#L273-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 8051#L169-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2 := 1; 8052#L181-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 8199#L182-1 start_simulation_#t~ret6 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret6;havoc start_simulation_#t~ret6; 8200#L413 assume !(0 == start_simulation_~tmp~3); 8770#L413-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret5, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 8766#L169-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2 := 1; 8763#L181-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 8760#L182-2 stop_simulation_#t~ret5 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret5;havoc stop_simulation_#t~ret5; 8757#L368 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 8754#L375 stop_simulation_#res := stop_simulation_~__retres2~0; 8751#L376 start_simulation_#t~ret7 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret7;havoc start_simulation_#t~ret7; 8748#L426 assume !(0 != start_simulation_~tmp___0~1); 8744#L394-3 assume true; 8302#L394-1 [2018-11-18 08:34:40,322 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 08:34:40,322 INFO L82 PathProgramCache]: Analyzing trace with hash 2020492967, now seen corresponding path program 1 times [2018-11-18 08:34:40,323 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 08:34:40,323 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 08:34:40,323 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:40,323 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 08:34:40,323 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:40,326 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 08:34:40,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 08:34:40,330 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 08:34:40,330 INFO L82 PathProgramCache]: Analyzing trace with hash -1927874556, now seen corresponding path program 1 times [2018-11-18 08:34:40,331 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 08:34:40,331 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 08:34:40,331 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:40,331 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 08:34:40,331 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:40,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 08:34:40,350 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-11-18 08:34:40,351 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 08:34:40,351 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 08:34:40,351 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 08:34:40,351 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 08:34:40,351 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 08:34:40,351 INFO L87 Difference]: Start difference. First operand 922 states and 1148 transitions. cyclomatic complexity: 232 Second operand 3 states. [2018-11-18 08:34:40,430 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 08:34:40,430 INFO L93 Difference]: Finished difference Result 1253 states and 1522 transitions. [2018-11-18 08:34:40,430 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 08:34:40,430 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1253 states and 1522 transitions. [2018-11-18 08:34:40,436 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 642 [2018-11-18 08:34:40,440 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1253 states to 1183 states and 1438 transitions. [2018-11-18 08:34:40,440 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 809 [2018-11-18 08:34:40,441 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 809 [2018-11-18 08:34:40,441 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1183 states and 1438 transitions. [2018-11-18 08:34:40,441 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-18 08:34:40,441 INFO L705 BuchiCegarLoop]: Abstraction has 1183 states and 1438 transitions. [2018-11-18 08:34:40,442 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1183 states and 1438 transitions. [2018-11-18 08:34:40,452 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1183 to 1154. [2018-11-18 08:34:40,453 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1154 states. [2018-11-18 08:34:40,455 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1154 states to 1154 states and 1406 transitions. [2018-11-18 08:34:40,455 INFO L728 BuchiCegarLoop]: Abstraction has 1154 states and 1406 transitions. [2018-11-18 08:34:40,455 INFO L608 BuchiCegarLoop]: Abstraction has 1154 states and 1406 transitions. [2018-11-18 08:34:40,455 INFO L442 BuchiCegarLoop]: ======== Iteration 11============ [2018-11-18 08:34:40,455 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1154 states and 1406 transitions. [2018-11-18 08:34:40,459 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 625 [2018-11-18 08:34:40,459 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 08:34:40,459 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 08:34:40,460 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 08:34:40,460 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 08:34:40,460 INFO L794 eck$LassoCheckResult]: Stem: 10395#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 10168#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 10169#L357 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret6, start_simulation_#t~ret7, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 10258#L144 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10259#L151 assume 1 == ~m_i~0;~m_st~0 := 0; 10399#L151-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10400#L156-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10289#L240 assume 0 == ~M_E~0;~M_E~0 := 1; 10290#L240-2 assume !(0 == ~T1_E~0); 10359#L245-1 assume !(0 == ~E_1~0); 10410#L250-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10322#L105 assume !(1 == ~m_pc~0); 10323#L105-2 is_master_triggered_~__retres1~0 := 0; 10426#L116 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10425#L117 activate_threads_#t~ret3 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 10423#L290 assume !(0 != activate_threads_~tmp~1); 10421#L290-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10420#L124 assume !(1 == ~t1_pc~0); 10419#L124-2 is_transmit1_triggered_~__retres1~1 := 0; 10418#L135 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10417#L136 activate_threads_#t~ret4 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 10416#L298 assume !(0 != activate_threads_~tmp___0~0); 10415#L298-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10137#L263 assume 1 == ~M_E~0;~M_E~0 := 2; 10127#L263-2 assume !(1 == ~T1_E~0); 10128#L268-1 assume !(1 == ~E_1~0); 10272#L273-1 assume { :end_inline_reset_delta_events } true; 10292#L394-3 assume true; 10475#L394-1 assume !false; 10956#L395 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_~tmp~0;havoc eval_~tmp~0; 10954#L215 [2018-11-18 08:34:40,460 INFO L796 eck$LassoCheckResult]: Loop: 10954#L215 assume true; 10952#L191-1 assume !false; 10950#L192 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 10948#L169 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2 := 1; 10946#L181 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 10944#L182 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 10942#L196 assume 0 != eval_~tmp~0; 10940#L196-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 10937#L204 assume !(0 != eval_~tmp_ndt_1~0); 10938#L201 assume !(0 == ~t1_st~0); 10954#L215 [2018-11-18 08:34:40,460 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 08:34:40,460 INFO L82 PathProgramCache]: Analyzing trace with hash 398958213, now seen corresponding path program 1 times [2018-11-18 08:34:40,460 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 08:34:40,460 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 08:34:40,461 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:40,461 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 08:34:40,461 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:40,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 08:34:40,489 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 08:34:40,489 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 08:34:40,489 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 08:34:40,490 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 08:34:40,490 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 08:34:40,490 INFO L82 PathProgramCache]: Analyzing trace with hash 2142040002, now seen corresponding path program 1 times [2018-11-18 08:34:40,490 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 08:34:40,490 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 08:34:40,491 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:40,491 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 08:34:40,491 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:40,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 08:34:40,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 08:34:40,524 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 08:34:40,524 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 08:34:40,525 INFO L87 Difference]: Start difference. First operand 1154 states and 1406 transitions. cyclomatic complexity: 261 Second operand 3 states. [2018-11-18 08:34:40,541 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 08:34:40,542 INFO L93 Difference]: Finished difference Result 715 states and 860 transitions. [2018-11-18 08:34:40,542 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 08:34:40,543 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 715 states and 860 transitions. [2018-11-18 08:34:40,545 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 436 [2018-11-18 08:34:40,547 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 715 states to 517 states and 621 transitions. [2018-11-18 08:34:40,547 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 517 [2018-11-18 08:34:40,548 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 517 [2018-11-18 08:34:40,548 INFO L73 IsDeterministic]: Start isDeterministic. Operand 517 states and 621 transitions. [2018-11-18 08:34:40,551 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 08:34:40,551 INFO L705 BuchiCegarLoop]: Abstraction has 517 states and 621 transitions. [2018-11-18 08:34:40,552 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 517 states and 621 transitions. [2018-11-18 08:34:40,555 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 517 to 318. [2018-11-18 08:34:40,555 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 318 states. [2018-11-18 08:34:40,556 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 318 states to 318 states and 380 transitions. [2018-11-18 08:34:40,559 INFO L728 BuchiCegarLoop]: Abstraction has 318 states and 380 transitions. [2018-11-18 08:34:40,559 INFO L608 BuchiCegarLoop]: Abstraction has 318 states and 380 transitions. [2018-11-18 08:34:40,559 INFO L442 BuchiCegarLoop]: ======== Iteration 12============ [2018-11-18 08:34:40,559 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 318 states and 380 transitions. [2018-11-18 08:34:40,560 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 290 [2018-11-18 08:34:40,560 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 08:34:40,560 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 08:34:40,561 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 08:34:40,561 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 08:34:40,561 INFO L794 eck$LassoCheckResult]: Stem: 12160#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 12025#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 12026#L357 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret6, start_simulation_#t~ret7, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 12076#L144 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12077#L151 assume 1 == ~m_i~0;~m_st~0 := 0; 12163#L151-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12164#L156-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12098#L240 assume !(0 == ~M_E~0); 12099#L240-2 assume !(0 == ~T1_E~0); 12138#L245-1 assume !(0 == ~E_1~0); 12146#L250-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12120#L105 assume !(1 == ~m_pc~0); 12065#L105-2 is_master_triggered_~__retres1~0 := 0; 12107#L116 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12066#L117 activate_threads_#t~ret3 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 12067#L290 assume !(0 != activate_threads_~tmp~1); 12086#L290-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12087#L124 assume !(1 == ~t1_pc~0); 12141#L124-2 is_transmit1_triggered_~__retres1~1 := 0; 12142#L135 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12053#L136 activate_threads_#t~ret4 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 12054#L298 assume !(0 != activate_threads_~tmp___0~0); 12079#L298-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12008#L263 assume !(1 == ~M_E~0); 12002#L263-2 assume !(1 == ~T1_E~0); 12003#L268-1 assume !(1 == ~E_1~0); 12088#L273-1 assume { :end_inline_reset_delta_events } true; 12100#L394-3 [2018-11-18 08:34:40,561 INFO L796 eck$LassoCheckResult]: Loop: 12100#L394-3 assume true; 12266#L394-1 assume !false; 12264#L395 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_~tmp~0;havoc eval_~tmp~0; 12262#L215 assume true; 12234#L191-1 assume !false; 12232#L192 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 12230#L169 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2 := 1; 12228#L181 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 12226#L182 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 12225#L196 assume 0 != eval_~tmp~0; 12224#L196-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 12152#L204 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1;assume { :begin_inline_master } true; 12125#L31 assume !(0 == ~m_pc~0); 12091#L34 assume 1 == ~m_pc~0; 12092#L35 assume true; 12170#L50-1 assume !false; 12015#L51 ~m_pc~0 := 1;~m_st~0 := 2; 12016#L61 assume { :end_inline_master } true; 12301#L201 assume !(0 == ~t1_st~0); 12298#L215 assume true; 12297#L191-1 assume !false; 12296#L192 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 12295#L169 assume !(0 == ~m_st~0); 12293#L173 assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2 := 0; 12292#L181 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 12291#L182 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 12287#L196 assume !(0 != eval_~tmp~0); 12286#L230 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 12073#L144-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 12074#L240-3 assume !(0 == ~M_E~0); 12135#L240-5 assume !(0 == ~T1_E~0); 12200#L245-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12199#L250-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12197#L105-6 assume !(1 == ~m_pc~0); 12133#L105-8 is_master_triggered_~__retres1~0 := 0; 12108#L116-2 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12017#L117-2 activate_threads_#t~ret3 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 12018#L290-6 assume !(0 != activate_threads_~tmp~1); 12032#L290-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12033#L124-6 assume !(1 == ~t1_pc~0); 12121#L124-8 is_transmit1_triggered_~__retres1~1 := 0; 12122#L135-2 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12042#L136-2 activate_threads_#t~ret4 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 12043#L298-6 assume !(0 != activate_threads_~tmp___0~0); 12094#L298-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12095#L263-3 assume !(1 == ~M_E~0); 12207#L263-5 assume !(1 == ~T1_E~0); 12206#L268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12205#L273-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 12057#L169-1 assume !(0 == ~m_st~0); 12058#L173-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~2 := 1; 12191#L181-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 12189#L182-1 start_simulation_#t~ret6 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret6;havoc start_simulation_#t~ret6; 12185#L413 assume 0 == start_simulation_~tmp~3;start_simulation_~kernel_st~0 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 12168#L324 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12169#L105-9 assume 1 == ~m_pc~0; 12009#L106-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 12010#L116-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12196#L117-3 activate_threads_#t~ret3 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 12195#L290-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 12068#L290-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12069#L124-9 assume !(1 == ~t1_pc~0); 12284#L124-11 is_transmit1_triggered_~__retres1~1 := 0; 12283#L135-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12282#L136-3 activate_threads_#t~ret4 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 12281#L298-9 assume !(0 != activate_threads_~tmp___0~0); 12280#L298-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 12279#L331 assume 1 == ~M_E~0;~M_E~0 := 2; 12278#L331-2 assume !(1 == ~T1_E~0); 12277#L336-1 assume 1 == ~E_1~0;~E_1~0 := 2; 12276#L341-1 assume { :end_inline_reset_time_events } true; 12275#L413-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret5, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 12274#L169-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2 := 1; 12273#L181-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 12272#L182-2 stop_simulation_#t~ret5 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret5;havoc stop_simulation_#t~ret5; 12271#L368 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 12270#L375 stop_simulation_#res := stop_simulation_~__retres2~0; 12269#L376 start_simulation_#t~ret7 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret7;havoc start_simulation_#t~ret7; 12268#L426 assume !(0 != start_simulation_~tmp___0~1); 12100#L394-3 [2018-11-18 08:34:40,561 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 08:34:40,562 INFO L82 PathProgramCache]: Analyzing trace with hash -904654136, now seen corresponding path program 7 times [2018-11-18 08:34:40,562 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 08:34:40,562 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 08:34:40,562 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:40,562 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 08:34:40,563 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:40,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 08:34:40,567 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 08:34:40,572 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 08:34:40,572 INFO L82 PathProgramCache]: Analyzing trace with hash 2097108902, now seen corresponding path program 1 times [2018-11-18 08:34:40,572 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 08:34:40,572 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 08:34:40,573 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:40,573 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 08:34:40,573 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:40,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 08:34:40,601 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 08:34:40,601 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 08:34:40,601 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 08:34:40,601 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 08:34:40,602 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 08:34:40,602 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 08:34:40,602 INFO L87 Difference]: Start difference. First operand 318 states and 380 transitions. cyclomatic complexity: 64 Second operand 3 states. [2018-11-18 08:34:40,639 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 08:34:40,639 INFO L93 Difference]: Finished difference Result 394 states and 463 transitions. [2018-11-18 08:34:40,639 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 08:34:40,639 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 394 states and 463 transitions. [2018-11-18 08:34:40,641 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 272 [2018-11-18 08:34:40,642 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 394 states to 394 states and 463 transitions. [2018-11-18 08:34:40,643 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 394 [2018-11-18 08:34:40,643 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 394 [2018-11-18 08:34:40,643 INFO L73 IsDeterministic]: Start isDeterministic. Operand 394 states and 463 transitions. [2018-11-18 08:34:40,643 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 08:34:40,643 INFO L705 BuchiCegarLoop]: Abstraction has 394 states and 463 transitions. [2018-11-18 08:34:40,644 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 394 states and 463 transitions. [2018-11-18 08:34:40,647 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 394 to 360. [2018-11-18 08:34:40,647 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 360 states. [2018-11-18 08:34:40,648 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 360 states to 360 states and 426 transitions. [2018-11-18 08:34:40,648 INFO L728 BuchiCegarLoop]: Abstraction has 360 states and 426 transitions. [2018-11-18 08:34:40,648 INFO L608 BuchiCegarLoop]: Abstraction has 360 states and 426 transitions. [2018-11-18 08:34:40,648 INFO L442 BuchiCegarLoop]: ======== Iteration 13============ [2018-11-18 08:34:40,648 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 360 states and 426 transitions. [2018-11-18 08:34:40,649 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 272 [2018-11-18 08:34:40,649 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 08:34:40,649 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 08:34:40,650 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 08:34:40,650 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 08:34:40,650 INFO L794 eck$LassoCheckResult]: Stem: 12869#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 12743#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 12744#L357 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret6, start_simulation_#t~ret7, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 12795#L144 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12796#L151 assume 1 == ~m_i~0;~m_st~0 := 0; 12873#L151-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12874#L156-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12812#L240 assume !(0 == ~M_E~0); 12813#L240-2 assume !(0 == ~T1_E~0); 12847#L245-1 assume !(0 == ~E_1~0); 12856#L250-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12832#L105 assume 1 == ~m_pc~0; 12783#L106 assume !(1 == ~M_E~0); 12784#L105-2 is_master_triggered_~__retres1~0 := 0; 12823#L116 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12785#L117 activate_threads_#t~ret3 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 12786#L290 assume !(0 != activate_threads_~tmp~1); 12804#L290-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12805#L124 assume !(1 == ~t1_pc~0); 12850#L124-2 is_transmit1_triggered_~__retres1~1 := 0; 12851#L135 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12771#L136 activate_threads_#t~ret4 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 12772#L298 assume !(0 != activate_threads_~tmp___0~0); 12799#L298-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12726#L263 assume !(1 == ~M_E~0); 12720#L263-2 assume !(1 == ~T1_E~0); 12721#L268-1 assume !(1 == ~E_1~0); 12806#L273-1 assume { :end_inline_reset_delta_events } true; 12814#L394-3 [2018-11-18 08:34:40,650 INFO L796 eck$LassoCheckResult]: Loop: 12814#L394-3 assume true; 12838#L394-1 assume !false; 12773#L395 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_~tmp~0;havoc eval_~tmp~0; 12774#L215 assume true; 12777#L191-1 assume !false; 12778#L192 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 12779#L169 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2 := 1; 12780#L181 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 13011#L182 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 13008#L196 assume 0 != eval_~tmp~0; 13005#L196-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 13003#L204 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1;assume { :begin_inline_master } true; 12837#L31 assume !(0 == ~m_pc~0); 12807#L34 assume 1 == ~m_pc~0; 12790#L35 assume true; 12882#L50-1 assume !false; 12733#L51 ~m_pc~0 := 1;~m_st~0 := 2; 12734#L61 assume { :end_inline_master } true; 12910#L201 assume !(0 == ~t1_st~0); 12906#L215 assume true; 12905#L191-1 assume !false; 12904#L192 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 12903#L169 assume !(0 == ~m_st~0); 12901#L173 assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2 := 0; 12900#L181 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 12899#L182 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 12897#L196 assume !(0 != eval_~tmp~0); 12896#L230 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 12895#L144-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 12894#L240-3 assume !(0 == ~M_E~0); 12893#L240-5 assume !(0 == ~T1_E~0); 12892#L245-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12891#L250-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12890#L105-6 assume 1 == ~m_pc~0; 12731#L106-2 assume !(1 == ~M_E~0); 12732#L105-8 is_master_triggered_~__retres1~0 := 0; 12824#L116-2 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12735#L117-2 activate_threads_#t~ret3 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 12736#L290-6 assume !(0 != activate_threads_~tmp~1); 12750#L290-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12751#L124-6 assume !(1 == ~t1_pc~0); 12860#L124-8 is_transmit1_triggered_~__retres1~1 := 0; 12978#L135-2 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12974#L136-2 activate_threads_#t~ret4 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 12970#L298-6 assume !(0 != activate_threads_~tmp___0~0); 12808#L298-8 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12749#L263-3 assume !(1 == ~M_E~0); 12747#L263-5 assume !(1 == ~T1_E~0); 12748#L268-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12958#L273-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 12956#L169-1 assume !(0 == ~m_st~0); 12954#L173-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~2 := 1; 12952#L181-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 12949#L182-1 start_simulation_#t~ret6 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret6;havoc start_simulation_#t~ret6; 12946#L413 assume 0 == start_simulation_~tmp~3;start_simulation_~kernel_st~0 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 12880#L324 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12840#L105-9 assume 1 == ~m_pc~0; 12727#L106-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 12728#L116-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12976#L117-3 activate_threads_#t~ret3 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 12972#L290-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 12787#L290-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12788#L124-9 assume !(1 == ~t1_pc~0); 12820#L124-11 is_transmit1_triggered_~__retres1~1 := 0; 12821#L135-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12755#L136-3 activate_threads_#t~ret4 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 12756#L298-9 assume !(0 != activate_threads_~tmp___0~0); 12800#L298-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 12801#L331 assume 1 == ~M_E~0;~M_E~0 := 2; 13061#L331-2 assume !(1 == ~T1_E~0); 13059#L336-1 assume 1 == ~E_1~0;~E_1~0 := 2; 13057#L341-1 assume { :end_inline_reset_time_events } true; 13055#L413-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret5, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 13054#L169-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2 := 1; 12870#L181-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 12871#L182-2 stop_simulation_#t~ret5 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret5;havoc stop_simulation_#t~ret5; 12883#L368 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 12822#L375 stop_simulation_#res := stop_simulation_~__retres2~0; 12722#L376 start_simulation_#t~ret7 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret7;havoc start_simulation_#t~ret7; 12723#L426 assume !(0 != start_simulation_~tmp___0~1); 12814#L394-3 [2018-11-18 08:34:40,651 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 08:34:40,651 INFO L82 PathProgramCache]: Analyzing trace with hash -831988783, now seen corresponding path program 1 times [2018-11-18 08:34:40,651 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 08:34:40,651 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 08:34:40,651 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:40,652 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 08:34:40,652 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:40,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 08:34:40,678 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 08:34:40,678 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 08:34:40,678 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 08:34:40,678 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 08:34:40,678 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 08:34:40,678 INFO L82 PathProgramCache]: Analyzing trace with hash 1155272634, now seen corresponding path program 1 times [2018-11-18 08:34:40,678 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 08:34:40,679 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 08:34:40,679 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:40,679 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 08:34:40,679 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:40,683 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 08:34:40,705 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 08:34:40,705 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 08:34:40,705 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 08:34:40,706 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 08:34:40,706 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 08:34:40,706 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 08:34:40,706 INFO L87 Difference]: Start difference. First operand 360 states and 426 transitions. cyclomatic complexity: 70 Second operand 3 states. [2018-11-18 08:34:40,720 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 08:34:40,720 INFO L93 Difference]: Finished difference Result 348 states and 408 transitions. [2018-11-18 08:34:40,720 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 08:34:40,721 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 348 states and 408 transitions. [2018-11-18 08:34:40,722 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 272 [2018-11-18 08:34:40,723 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 348 states to 348 states and 408 transitions. [2018-11-18 08:34:40,723 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 348 [2018-11-18 08:34:40,724 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 348 [2018-11-18 08:34:40,724 INFO L73 IsDeterministic]: Start isDeterministic. Operand 348 states and 408 transitions. [2018-11-18 08:34:40,724 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 08:34:40,724 INFO L705 BuchiCegarLoop]: Abstraction has 348 states and 408 transitions. [2018-11-18 08:34:40,724 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 348 states and 408 transitions. [2018-11-18 08:34:40,727 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 348 to 342. [2018-11-18 08:34:40,727 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 342 states. [2018-11-18 08:34:40,728 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 342 states to 342 states and 402 transitions. [2018-11-18 08:34:40,728 INFO L728 BuchiCegarLoop]: Abstraction has 342 states and 402 transitions. [2018-11-18 08:34:40,728 INFO L608 BuchiCegarLoop]: Abstraction has 342 states and 402 transitions. [2018-11-18 08:34:40,728 INFO L442 BuchiCegarLoop]: ======== Iteration 14============ [2018-11-18 08:34:40,728 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 342 states and 402 transitions. [2018-11-18 08:34:40,729 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 272 [2018-11-18 08:34:40,729 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 08:34:40,730 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 08:34:40,730 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 08:34:40,730 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 08:34:40,730 INFO L794 eck$LassoCheckResult]: Stem: 13586#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 13456#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 13457#L357 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret6, start_simulation_#t~ret7, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 13506#L144 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13507#L151 assume 1 == ~m_i~0;~m_st~0 := 0; 13590#L151-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13591#L156-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13523#L240 assume !(0 == ~M_E~0); 13524#L240-2 assume !(0 == ~T1_E~0); 13563#L245-1 assume !(0 == ~E_1~0); 13573#L250-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 13544#L105 assume !(1 == ~m_pc~0); 13533#L105-2 is_master_triggered_~__retres1~0 := 0; 13534#L116 is_master_triggered_#res := is_master_triggered_~__retres1~0; 13496#L117 activate_threads_#t~ret3 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 13497#L290 assume !(0 != activate_threads_~tmp~1); 13514#L290-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 13515#L124 assume !(1 == ~t1_pc~0); 13566#L124-2 is_transmit1_triggered_~__retres1~1 := 0; 13567#L135 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 13487#L136 activate_threads_#t~ret4 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 13488#L298 assume !(0 != activate_threads_~tmp___0~0); 13509#L298-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13441#L263 assume !(1 == ~M_E~0); 13435#L263-2 assume !(1 == ~T1_E~0); 13436#L268-1 assume !(1 == ~E_1~0); 13516#L273-1 assume { :end_inline_reset_delta_events } true; 13525#L394-3 assume true; 13740#L394-1 assume !false; 13738#L395 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_~tmp~0;havoc eval_~tmp~0; 13706#L215 [2018-11-18 08:34:40,730 INFO L796 eck$LassoCheckResult]: Loop: 13706#L215 assume true; 13733#L191-1 assume !false; 13729#L192 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 13725#L169 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2 := 1; 13722#L181 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 13719#L182 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 13716#L196 assume 0 != eval_~tmp~0; 13714#L196-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 13696#L204 assume !(0 != eval_~tmp_ndt_1~0); 13697#L201 assume !(0 == ~t1_st~0); 13706#L215 [2018-11-18 08:34:40,730 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 08:34:40,730 INFO L82 PathProgramCache]: Analyzing trace with hash 368527241, now seen corresponding path program 1 times [2018-11-18 08:34:40,730 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 08:34:40,731 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 08:34:40,731 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:40,731 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 08:34:40,731 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:40,733 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 08:34:40,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 08:34:40,740 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 08:34:40,740 INFO L82 PathProgramCache]: Analyzing trace with hash 2142040002, now seen corresponding path program 2 times [2018-11-18 08:34:40,740 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 08:34:40,740 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 08:34:40,741 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:40,741 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 08:34:40,741 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:40,742 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 08:34:40,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 08:34:40,744 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 08:34:40,744 INFO L82 PathProgramCache]: Analyzing trace with hash 1408658762, now seen corresponding path program 1 times [2018-11-18 08:34:40,744 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 08:34:40,744 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 08:34:40,744 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:40,745 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 08:34:40,745 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:40,747 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 08:34:40,774 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 08:34:40,774 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 08:34:40,774 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 08:34:40,801 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 08:34:40,802 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 08:34:40,802 INFO L87 Difference]: Start difference. First operand 342 states and 402 transitions. cyclomatic complexity: 64 Second operand 3 states. [2018-11-18 08:34:40,823 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 08:34:40,824 INFO L93 Difference]: Finished difference Result 595 states and 685 transitions. [2018-11-18 08:34:40,825 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 08:34:40,825 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 595 states and 685 transitions. [2018-11-18 08:34:40,827 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 401 [2018-11-18 08:34:40,829 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 595 states to 595 states and 685 transitions. [2018-11-18 08:34:40,829 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 595 [2018-11-18 08:34:40,830 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 595 [2018-11-18 08:34:40,830 INFO L73 IsDeterministic]: Start isDeterministic. Operand 595 states and 685 transitions. [2018-11-18 08:34:40,830 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 08:34:40,830 INFO L705 BuchiCegarLoop]: Abstraction has 595 states and 685 transitions. [2018-11-18 08:34:40,831 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 595 states and 685 transitions. [2018-11-18 08:34:40,835 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 595 to 520. [2018-11-18 08:34:40,835 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 520 states. [2018-11-18 08:34:40,836 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 520 states to 520 states and 603 transitions. [2018-11-18 08:34:40,836 INFO L728 BuchiCegarLoop]: Abstraction has 520 states and 603 transitions. [2018-11-18 08:34:40,837 INFO L608 BuchiCegarLoop]: Abstraction has 520 states and 603 transitions. [2018-11-18 08:34:40,837 INFO L442 BuchiCegarLoop]: ======== Iteration 15============ [2018-11-18 08:34:40,837 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 520 states and 603 transitions. [2018-11-18 08:34:40,838 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 379 [2018-11-18 08:34:40,838 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 08:34:40,838 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 08:34:40,839 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 08:34:40,839 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 08:34:40,839 INFO L794 eck$LassoCheckResult]: Stem: 14528#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 14401#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 14402#L357 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret6, start_simulation_#t~ret7, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 14450#L144 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14451#L151 assume 1 == ~m_i~0;~m_st~0 := 0; 14531#L151-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 14532#L156-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14472#L240 assume !(0 == ~M_E~0); 14473#L240-2 assume !(0 == ~T1_E~0); 14506#L245-1 assume !(0 == ~E_1~0); 14762#L250-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 14761#L105 assume !(1 == ~m_pc~0); 14760#L105-2 is_master_triggered_~__retres1~0 := 0; 14759#L116 is_master_triggered_#res := is_master_triggered_~__retres1~0; 14758#L117 activate_threads_#t~ret3 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 14757#L290 assume !(0 != activate_threads_~tmp~1); 14756#L290-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 14755#L124 assume !(1 == ~t1_pc~0); 14754#L124-2 is_transmit1_triggered_~__retres1~1 := 0; 14753#L135 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14752#L136 activate_threads_#t~ret4 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 14751#L298 assume !(0 != activate_threads_~tmp___0~0); 14749#L298-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14747#L263 assume !(1 == ~M_E~0); 14746#L263-2 assume !(1 == ~T1_E~0); 14461#L268-1 assume !(1 == ~E_1~0); 14462#L273-1 assume { :end_inline_reset_delta_events } true; 14474#L394-3 assume true; 14763#L394-1 assume !false; 14716#L395 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_~tmp~0;havoc eval_~tmp~0; 14715#L215 [2018-11-18 08:34:40,839 INFO L796 eck$LassoCheckResult]: Loop: 14715#L215 assume true; 14713#L191-1 assume !false; 14711#L192 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 14709#L169 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2 := 1; 14707#L181 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 14705#L182 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 14703#L196 assume 0 != eval_~tmp~0; 14701#L196-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 14698#L204 assume !(0 != eval_~tmp_ndt_1~0); 14699#L201 assume !(0 == ~t1_st~0); 14715#L215 [2018-11-18 08:34:40,839 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 08:34:40,839 INFO L82 PathProgramCache]: Analyzing trace with hash 509075851, now seen corresponding path program 1 times [2018-11-18 08:34:40,839 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 08:34:40,839 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 08:34:40,840 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:40,840 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 08:34:40,840 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:40,842 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 08:34:40,857 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 08:34:40,857 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 08:34:40,857 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 08:34:40,857 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 08:34:40,858 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 08:34:40,858 INFO L82 PathProgramCache]: Analyzing trace with hash 2142040002, now seen corresponding path program 3 times [2018-11-18 08:34:40,858 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 08:34:40,858 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 08:34:40,858 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:40,858 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 08:34:40,859 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:40,860 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 08:34:40,861 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 08:34:40,888 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 08:34:40,888 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 08:34:40,888 INFO L87 Difference]: Start difference. First operand 520 states and 603 transitions. cyclomatic complexity: 88 Second operand 3 states. [2018-11-18 08:34:40,895 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 08:34:40,895 INFO L93 Difference]: Finished difference Result 350 states and 410 transitions. [2018-11-18 08:34:40,896 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 08:34:40,896 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 350 states and 410 transitions. [2018-11-18 08:34:40,897 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 264 [2018-11-18 08:34:40,899 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 350 states to 350 states and 410 transitions. [2018-11-18 08:34:40,899 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 350 [2018-11-18 08:34:40,899 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 350 [2018-11-18 08:34:40,899 INFO L73 IsDeterministic]: Start isDeterministic. Operand 350 states and 410 transitions. [2018-11-18 08:34:40,899 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 08:34:40,900 INFO L705 BuchiCegarLoop]: Abstraction has 350 states and 410 transitions. [2018-11-18 08:34:40,900 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 350 states and 410 transitions. [2018-11-18 08:34:40,903 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 350 to 350. [2018-11-18 08:34:40,903 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 350 states. [2018-11-18 08:34:40,904 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 350 states to 350 states and 410 transitions. [2018-11-18 08:34:40,904 INFO L728 BuchiCegarLoop]: Abstraction has 350 states and 410 transitions. [2018-11-18 08:34:40,904 INFO L608 BuchiCegarLoop]: Abstraction has 350 states and 410 transitions. [2018-11-18 08:34:40,904 INFO L442 BuchiCegarLoop]: ======== Iteration 16============ [2018-11-18 08:34:40,904 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 350 states and 410 transitions. [2018-11-18 08:34:40,905 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 264 [2018-11-18 08:34:40,905 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 08:34:40,905 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 08:34:40,906 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 08:34:40,906 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 08:34:40,906 INFO L794 eck$LassoCheckResult]: Stem: 15397#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 15277#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~3;havoc main_~__retres1~3;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 15278#L357 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret6, start_simulation_#t~ret7, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 15325#L144 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15326#L151 assume 1 == ~m_i~0;~m_st~0 := 0; 15399#L151-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15400#L156-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15343#L240 assume !(0 == ~M_E~0); 15344#L240-2 assume !(0 == ~T1_E~0); 15377#L245-1 assume !(0 == ~E_1~0); 15383#L250-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret3, activate_threads_#t~ret4, activate_threads_~tmp~1, activate_threads_~tmp___0~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15363#L105 assume !(1 == ~m_pc~0); 15353#L105-2 is_master_triggered_~__retres1~0 := 0; 15354#L116 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15316#L117 activate_threads_#t~ret3 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret3;havoc activate_threads_#t~ret3; 15317#L290 assume !(0 != activate_threads_~tmp~1); 15333#L290-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15334#L124 assume !(1 == ~t1_pc~0); 15379#L124-2 is_transmit1_triggered_~__retres1~1 := 0; 15380#L135 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 15305#L136 activate_threads_#t~ret4 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 15306#L298 assume !(0 != activate_threads_~tmp___0~0); 15328#L298-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15262#L263 assume !(1 == ~M_E~0); 15256#L263-2 assume !(1 == ~T1_E~0); 15257#L268-1 assume !(1 == ~E_1~0); 15335#L273-1 assume { :end_inline_reset_delta_events } true; 15345#L394-3 assume true; 15605#L394-1 assume !false; 15603#L395 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_~tmp~0;havoc eval_~tmp~0; 15602#L215 [2018-11-18 08:34:40,906 INFO L796 eck$LassoCheckResult]: Loop: 15602#L215 assume true; 15601#L191-1 assume !false; 15600#L192 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~2;havoc exists_runnable_thread_~__retres1~2; 15599#L169 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2 := 1; 15598#L181 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~2; 15386#L182 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 15378#L196 assume 0 != eval_~tmp~0; 15374#L196-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 15375#L204 assume !(0 != eval_~tmp_ndt_1~0); 15389#L201 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 15604#L218 assume !(0 != eval_~tmp_ndt_2~0); 15602#L215 [2018-11-18 08:34:40,906 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 08:34:40,906 INFO L82 PathProgramCache]: Analyzing trace with hash 368527241, now seen corresponding path program 2 times [2018-11-18 08:34:40,906 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 08:34:40,906 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 08:34:40,907 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:40,907 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 08:34:40,907 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:40,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 08:34:40,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 08:34:40,914 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 08:34:40,914 INFO L82 PathProgramCache]: Analyzing trace with hash 1978729647, now seen corresponding path program 1 times [2018-11-18 08:34:40,914 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 08:34:40,914 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 08:34:40,915 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:40,915 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 08:34:40,915 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:40,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 08:34:40,919 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 08:34:40,920 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 08:34:40,920 INFO L82 PathProgramCache]: Analyzing trace with hash 718747687, now seen corresponding path program 1 times [2018-11-18 08:34:40,920 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 08:34:40,920 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 08:34:40,921 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:40,921 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 08:34:40,921 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 08:34:40,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 08:34:40,926 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 08:34:41,121 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 18.11 08:34:41 BoogieIcfgContainer [2018-11-18 08:34:41,122 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2018-11-18 08:34:41,122 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-18 08:34:41,122 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-18 08:34:41,122 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-18 08:34:41,123 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 08:34:37" (3/4) ... [2018-11-18 08:34:41,125 INFO L141 WitnessPrinter]: Generating witness for non-termination counterexample [2018-11-18 08:34:41,169 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_2bd7126d-33d4-426b-8346-9856ccc05d04/bin-2019/uautomizer/witness.graphml [2018-11-18 08:34:41,169 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-18 08:34:41,170 INFO L168 Benchmark]: Toolchain (without parser) took 3920.23 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 220.2 MB). Free memory was 959.1 MB in the beginning and 844.4 MB in the end (delta: 114.8 MB). Peak memory consumption was 335.0 MB. Max. memory is 11.5 GB. [2018-11-18 08:34:41,170 INFO L168 Benchmark]: CDTParser took 0.13 ms. Allocated memory is still 1.0 GB. Free memory is still 985.4 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-18 08:34:41,170 INFO L168 Benchmark]: CACSL2BoogieTranslator took 186.01 ms. Allocated memory is still 1.0 GB. Free memory was 959.1 MB in the beginning and 943.0 MB in the end (delta: 16.2 MB). Peak memory consumption was 16.2 MB. Max. memory is 11.5 GB. [2018-11-18 08:34:41,171 INFO L168 Benchmark]: Boogie Procedure Inliner took 35.59 ms. Allocated memory is still 1.0 GB. Free memory is still 943.0 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-18 08:34:41,171 INFO L168 Benchmark]: Boogie Preprocessor took 61.91 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 148.9 MB). Free memory was 943.0 MB in the beginning and 1.1 GB in the end (delta: -200.2 MB). Peak memory consumption was 15.2 MB. Max. memory is 11.5 GB. [2018-11-18 08:34:41,171 INFO L168 Benchmark]: RCFGBuilder took 363.58 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 48.4 MB). Peak memory consumption was 48.4 MB. Max. memory is 11.5 GB. [2018-11-18 08:34:41,171 INFO L168 Benchmark]: BuchiAutomizer took 3223.15 ms. Allocated memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 71.3 MB). Free memory was 1.1 GB in the beginning and 849.6 MB in the end (delta: 245.2 MB). Peak memory consumption was 316.5 MB. Max. memory is 11.5 GB. [2018-11-18 08:34:41,172 INFO L168 Benchmark]: Witness Printer took 47.09 ms. Allocated memory is still 1.2 GB. Free memory was 849.6 MB in the beginning and 844.4 MB in the end (delta: 5.3 MB). Peak memory consumption was 5.3 MB. Max. memory is 11.5 GB. [2018-11-18 08:34:41,173 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.13 ms. Allocated memory is still 1.0 GB. Free memory is still 985.4 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 186.01 ms. Allocated memory is still 1.0 GB. Free memory was 959.1 MB in the beginning and 943.0 MB in the end (delta: 16.2 MB). Peak memory consumption was 16.2 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 35.59 ms. Allocated memory is still 1.0 GB. Free memory is still 943.0 MB. There was no memory consumed. Max. memory is 11.5 GB. * Boogie Preprocessor took 61.91 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 148.9 MB). Free memory was 943.0 MB in the beginning and 1.1 GB in the end (delta: -200.2 MB). Peak memory consumption was 15.2 MB. Max. memory is 11.5 GB. * RCFGBuilder took 363.58 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 48.4 MB). Peak memory consumption was 48.4 MB. Max. memory is 11.5 GB. * BuchiAutomizer took 3223.15 ms. Allocated memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 71.3 MB). Free memory was 1.1 GB in the beginning and 849.6 MB in the end (delta: 245.2 MB). Peak memory consumption was 316.5 MB. Max. memory is 11.5 GB. * Witness Printer took 47.09 ms. Allocated memory is still 1.2 GB. Free memory was 849.6 MB in the beginning and 844.4 MB in the end (delta: 5.3 MB). Peak memory consumption was 5.3 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 16 terminating modules (15 trivial, 1 deterministic, 0 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function -1 * M_E + 1 and consists of 3 locations. 15 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 350 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 3.1s and 16 iterations. TraceHistogramMax:2. Analysis of lassos took 2.0s. Construction of modules took 0.3s. Büchi inclusion checks took 0.3s. Highest rank in rank-based complementation 3. Minimization of det autom 13. Minimization of nondet autom 3. Automata minimization 0.1s AutomataMinimizationTime, 16 MinimizatonAttempts, 1130 StatesRemovedByMinimization, 12 NontrivialMinimizations. Non-live state removal took 0.0s Buchi closure took 0.0s. Biggest automaton had 1154 states and ocurred in iteration 10. Nontrivial modules had stage [1, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 2986 SDtfs, 2722 SDslu, 3125 SDs, 0 SdLazy, 284 SolverSat, 106 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.3s Time LassoAnalysisResults: nont1 unkn0 SFLI7 SFLT0 conc1 concLT1 SILN2 SILU0 SILI4 SILT0 lasso0 LassoPreprocessingBenchmarks: Lassos: inital85 mio100 ax100 hnf100 lsp12 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq209 hnf86 smp100 dnf189 smp63 tf108 neg92 sie116 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 2ms VariablesStem: 0 VariablesLoop: 1 DisjunctsStem: 1 DisjunctsLoop: 2 SupportingInvariants: 0 MotzkinApplications: 4 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 4 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 1 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 191]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3e93d092=0, \result=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@578589eb=0, tmp=1, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5bfb29cf=0, kernel_st=1, __retres1=0, tmp___0=0, t1_pc=0, __retres1=1, T1_E=2, \result=0, E_1=2, tmp_ndt_1=0, M_E=2, tmp_ndt_2=0, tmp=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2ddb598d=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2fbd6ddb=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@74a8876=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@12f96d66=0, t1_st=0, m_st=0, tmp___0=0, tmp=0, __retres1=0, t1_i=1, m_pc=0, \result=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 191]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int m_st ; [L18] int t1_st ; [L19] int m_i ; [L20] int t1_i ; [L21] int M_E = 2; [L22] int T1_E = 2; [L23] int E_1 = 2; [L439] int __retres1 ; [L443] CALL init_model() [L354] m_i = 1 [L355] RET t1_i = 1 [L443] init_model() [L444] CALL start_simulation() [L380] int kernel_st ; [L381] int tmp ; [L382] int tmp___0 ; [L386] kernel_st = 0 [L387] FCALL update_channels() [L388] CALL init_threads() [L151] COND TRUE m_i == 1 [L152] m_st = 0 [L156] COND TRUE t1_i == 1 [L157] RET t1_st = 0 [L388] init_threads() [L389] CALL fire_delta_events() [L240] COND FALSE !(M_E == 0) [L245] COND FALSE !(T1_E == 0) [L250] COND FALSE, RET !(E_1 == 0) [L389] fire_delta_events() [L390] CALL activate_threads() [L283] int tmp ; [L284] int tmp___0 ; [L288] CALL, EXPR is_master_triggered() [L102] int __retres1 ; [L105] COND FALSE !(m_pc == 1) [L115] __retres1 = 0 [L117] RET return (__retres1); [L288] EXPR is_master_triggered() [L288] tmp = is_master_triggered() [L290] COND FALSE !(\read(tmp)) [L296] CALL, EXPR is_transmit1_triggered() [L121] int __retres1 ; [L124] COND FALSE !(t1_pc == 1) [L134] __retres1 = 0 [L136] RET return (__retres1); [L296] EXPR is_transmit1_triggered() [L296] tmp___0 = is_transmit1_triggered() [L298] COND FALSE, RET !(\read(tmp___0)) [L390] activate_threads() [L391] CALL reset_delta_events() [L263] COND FALSE !(M_E == 1) [L268] COND FALSE !(T1_E == 1) [L273] COND FALSE, RET !(E_1 == 1) [L391] reset_delta_events() [L394] COND TRUE 1 [L397] kernel_st = 1 [L398] CALL eval() [L187] int tmp ; Loop: [L191] COND TRUE 1 [L194] CALL, EXPR exists_runnable_thread() [L166] int __retres1 ; [L169] COND TRUE m_st == 0 [L170] __retres1 = 1 [L182] RET return (__retres1); [L194] EXPR exists_runnable_thread() [L194] tmp = exists_runnable_thread() [L196] COND TRUE \read(tmp) [L201] COND TRUE m_st == 0 [L202] int tmp_ndt_1; [L203] tmp_ndt_1 = __VERIFIER_nondet_int() [L204] COND FALSE !(\read(tmp_ndt_1)) [L215] COND TRUE t1_st == 0 [L216] int tmp_ndt_2; [L217] tmp_ndt_2 = __VERIFIER_nondet_int() [L218] COND FALSE !(\read(tmp_ndt_2)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...