./Ultimate.py --spec ../../sv-benchmarks/c/Termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.02_false-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 5842f4b8 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_f1ace5c2-b60b-4914-a76b-55dab06ad999/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_f1ace5c2-b60b-4914-a76b-55dab06ad999/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_f1ace5c2-b60b-4914-a76b-55dab06ad999/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_f1ace5c2-b60b-4914-a76b-55dab06ad999/bin-2019/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.02_false-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_f1ace5c2-b60b-4914-a76b-55dab06ad999/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_f1ace5c2-b60b-4914-a76b-55dab06ad999/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 0c244c639ec9718adcbacffa967b748c52a23cd0 ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.1.23-5842f4b [2018-11-18 15:12:46,669 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-18 15:12:46,670 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-18 15:12:46,676 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-18 15:12:46,676 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-18 15:12:46,676 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-18 15:12:46,677 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-18 15:12:46,678 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-18 15:12:46,679 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-18 15:12:46,680 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-18 15:12:46,680 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-18 15:12:46,681 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-18 15:12:46,681 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-18 15:12:46,682 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-18 15:12:46,682 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-18 15:12:46,683 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-18 15:12:46,683 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-18 15:12:46,684 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-18 15:12:46,685 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-18 15:12:46,686 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-18 15:12:46,687 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-18 15:12:46,688 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-18 15:12:46,689 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-18 15:12:46,689 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-18 15:12:46,690 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-18 15:12:46,690 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-18 15:12:46,691 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-18 15:12:46,691 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-18 15:12:46,692 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-18 15:12:46,692 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-18 15:12:46,692 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-18 15:12:46,693 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-18 15:12:46,693 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-18 15:12:46,693 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-18 15:12:46,694 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-18 15:12:46,694 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-18 15:12:46,694 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_f1ace5c2-b60b-4914-a76b-55dab06ad999/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2018-11-18 15:12:46,705 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-18 15:12:46,705 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-18 15:12:46,706 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-18 15:12:46,706 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-18 15:12:46,706 INFO L133 SettingsManager]: * Use SBE=true [2018-11-18 15:12:46,706 INFO L131 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2018-11-18 15:12:46,706 INFO L133 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2018-11-18 15:12:46,707 INFO L133 SettingsManager]: * Use old map elimination=false [2018-11-18 15:12:46,707 INFO L133 SettingsManager]: * Use external solver (rank synthesis)=false [2018-11-18 15:12:46,707 INFO L133 SettingsManager]: * Use only trivial implications for array writes=true [2018-11-18 15:12:46,707 INFO L133 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2018-11-18 15:12:46,707 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-18 15:12:46,707 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-18 15:12:46,707 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-11-18 15:12:46,707 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-18 15:12:46,708 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-18 15:12:46,708 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-18 15:12:46,708 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2018-11-18 15:12:46,708 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2018-11-18 15:12:46,708 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2018-11-18 15:12:46,708 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-18 15:12:46,708 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-18 15:12:46,709 INFO L133 SettingsManager]: * Assume nondeterminstic values are in range=false [2018-11-18 15:12:46,709 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-18 15:12:46,709 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2018-11-18 15:12:46,709 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-18 15:12:46,709 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-18 15:12:46,709 INFO L133 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2018-11-18 15:12:46,709 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-18 15:12:46,709 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-18 15:12:46,710 INFO L133 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2018-11-18 15:12:46,710 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-11-18 15:12:46,710 INFO L133 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_f1ace5c2-b60b-4914-a76b-55dab06ad999/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 0c244c639ec9718adcbacffa967b748c52a23cd0 [2018-11-18 15:12:46,732 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-18 15:12:46,741 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-18 15:12:46,744 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-18 15:12:46,745 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-18 15:12:46,745 INFO L276 PluginConnector]: CDTParser initialized [2018-11-18 15:12:46,745 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_f1ace5c2-b60b-4914-a76b-55dab06ad999/bin-2019/uautomizer/../../sv-benchmarks/c/systemc/transmitter.02_false-unreach-call_false-termination.cil.c [2018-11-18 15:12:46,782 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_f1ace5c2-b60b-4914-a76b-55dab06ad999/bin-2019/uautomizer/data/df0513b17/a1ca1503043849e2b347a67261211d0a/FLAGec6d6bdf9 [2018-11-18 15:12:47,214 INFO L307 CDTParser]: Found 1 translation units. [2018-11-18 15:12:47,215 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_f1ace5c2-b60b-4914-a76b-55dab06ad999/sv-benchmarks/c/systemc/transmitter.02_false-unreach-call_false-termination.cil.c [2018-11-18 15:12:47,221 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_f1ace5c2-b60b-4914-a76b-55dab06ad999/bin-2019/uautomizer/data/df0513b17/a1ca1503043849e2b347a67261211d0a/FLAGec6d6bdf9 [2018-11-18 15:12:47,231 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_f1ace5c2-b60b-4914-a76b-55dab06ad999/bin-2019/uautomizer/data/df0513b17/a1ca1503043849e2b347a67261211d0a [2018-11-18 15:12:47,233 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-18 15:12:47,234 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-18 15:12:47,235 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-18 15:12:47,235 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-18 15:12:47,237 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-18 15:12:47,237 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 03:12:47" (1/1) ... [2018-11-18 15:12:47,239 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@44c74022 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:12:47, skipping insertion in model container [2018-11-18 15:12:47,239 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 03:12:47" (1/1) ... [2018-11-18 15:12:47,245 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-18 15:12:47,268 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-18 15:12:47,400 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 15:12:47,405 INFO L191 MainTranslator]: Completed pre-run [2018-11-18 15:12:47,432 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 15:12:47,442 INFO L195 MainTranslator]: Completed translation [2018-11-18 15:12:47,443 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:12:47 WrapperNode [2018-11-18 15:12:47,443 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-18 15:12:47,443 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-18 15:12:47,443 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-18 15:12:47,443 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-18 15:12:47,448 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:12:47" (1/1) ... [2018-11-18 15:12:47,453 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:12:47" (1/1) ... [2018-11-18 15:12:47,511 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-18 15:12:47,511 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-18 15:12:47,511 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-18 15:12:47,511 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-18 15:12:47,517 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:12:47" (1/1) ... [2018-11-18 15:12:47,518 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:12:47" (1/1) ... [2018-11-18 15:12:47,519 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:12:47" (1/1) ... [2018-11-18 15:12:47,519 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:12:47" (1/1) ... [2018-11-18 15:12:47,522 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:12:47" (1/1) ... [2018-11-18 15:12:47,528 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:12:47" (1/1) ... [2018-11-18 15:12:47,530 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:12:47" (1/1) ... [2018-11-18 15:12:47,533 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-18 15:12:47,533 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-18 15:12:47,534 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-18 15:12:47,534 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-18 15:12:47,534 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:12:47" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_f1ace5c2-b60b-4914-a76b-55dab06ad999/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 15:12:47,569 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-18 15:12:47,569 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-18 15:12:48,038 INFO L278 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-18 15:12:48,039 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 03:12:48 BoogieIcfgContainer [2018-11-18 15:12:48,039 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-18 15:12:48,039 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2018-11-18 15:12:48,039 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2018-11-18 15:12:48,041 INFO L276 PluginConnector]: BuchiAutomizer initialized [2018-11-18 15:12:48,042 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-18 15:12:48,042 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 18.11 03:12:47" (1/3) ... [2018-11-18 15:12:48,043 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3f7b7123 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 18.11 03:12:48, skipping insertion in model container [2018-11-18 15:12:48,043 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-18 15:12:48,043 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:12:47" (2/3) ... [2018-11-18 15:12:48,043 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3f7b7123 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 18.11 03:12:48, skipping insertion in model container [2018-11-18 15:12:48,043 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-18 15:12:48,043 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 03:12:48" (3/3) ... [2018-11-18 15:12:48,045 INFO L375 chiAutomizerObserver]: Analyzing ICFG transmitter.02_false-unreach-call_false-termination.cil.c [2018-11-18 15:12:48,076 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-18 15:12:48,077 INFO L374 BuchiCegarLoop]: Interprodecural is true [2018-11-18 15:12:48,077 INFO L375 BuchiCegarLoop]: Hoare is false [2018-11-18 15:12:48,077 INFO L376 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2018-11-18 15:12:48,077 INFO L377 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-18 15:12:48,077 INFO L378 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-18 15:12:48,077 INFO L379 BuchiCegarLoop]: Difference is false [2018-11-18 15:12:48,077 INFO L380 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-18 15:12:48,077 INFO L383 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2018-11-18 15:12:48,091 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 211 states. [2018-11-18 15:12:48,113 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 166 [2018-11-18 15:12:48,114 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:12:48,114 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:12:48,120 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:12:48,120 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:12:48,120 INFO L442 BuchiCegarLoop]: ======== Iteration 1============ [2018-11-18 15:12:48,120 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 211 states. [2018-11-18 15:12:48,126 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 166 [2018-11-18 15:12:48,126 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:12:48,126 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:12:48,128 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:12:48,128 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:12:48,133 INFO L794 eck$LassoCheckResult]: Stem: 95#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 12#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 208#L481true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 83#L204true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 209#L211true assume !(1 == ~m_i~0);~m_st~0 := 2; 206#L211-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 134#L216-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 144#L221-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 106#L324true assume !(0 == ~M_E~0); 108#L324-2true assume !(0 == ~T1_E~0); 15#L329-1true assume !(0 == ~T2_E~0); 47#L334-1true assume 0 == ~E_1~0;~E_1~0 := 1; 67#L339-1true assume !(0 == ~E_2~0); 185#L344-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 171#L146true assume !(1 == ~m_pc~0); 163#L146-2true is_master_triggered_~__retres1~0 := 0; 172#L157true is_master_triggered_#res := is_master_triggered_~__retres1~0; 38#L158true activate_threads_#t~ret4 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 35#L395true assume !(0 != activate_threads_~tmp~1); 13#L395-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 88#L165true assume 1 == ~t1_pc~0; 142#L166true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 89#L176true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 143#L177true activate_threads_#t~ret5 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 132#L403true assume !(0 != activate_threads_~tmp___0~0); 135#L403-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 202#L184true assume !(1 == ~t2_pc~0); 199#L184-2true is_transmit2_triggered_~__retres1~2 := 0; 203#L195true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 77#L196true activate_threads_#t~ret6 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 54#L411true assume !(0 != activate_threads_~tmp___1~0); 44#L411-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 115#L357true assume !(1 == ~M_E~0); 107#L357-2true assume !(1 == ~T1_E~0); 14#L362-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 45#L367-1true assume !(1 == ~E_1~0); 63#L372-1true assume !(1 == ~E_2~0); 184#L377-1true assume { :end_inline_reset_delta_events } true; 156#L518-3true [2018-11-18 15:12:48,134 INFO L796 eck$LassoCheckResult]: Loop: 156#L518-3true assume true; 158#L518-1true assume !false; 122#L519true start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 120#L299true assume !true; 85#L314true assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 82#L204-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 110#L324-3true assume 0 == ~M_E~0;~M_E~0 := 1; 112#L324-5true assume !(0 == ~T1_E~0); 18#L329-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 50#L334-3true assume 0 == ~E_1~0;~E_1~0 := 1; 73#L339-3true assume 0 == ~E_2~0;~E_2~0 := 1; 189#L344-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 61#L146-9true assume 1 == ~m_pc~0; 24#L147-3true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 160#L157-3true is_master_triggered_#res := is_master_triggered_~__retres1~0; 26#L158-3true activate_threads_#t~ret4 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 6#L395-9true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 10#L395-11true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 80#L165-9true assume 1 == ~t1_pc~0; 151#L166-3true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 100#L176-3true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 153#L177-3true activate_threads_#t~ret5 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 130#L403-9true assume !(0 != activate_threads_~tmp___0~0); 121#L403-11true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 182#L184-9true assume 1 == ~t2_pc~0; 66#L185-3true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 198#L195-3true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 68#L196-3true activate_threads_#t~ret6 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 40#L411-9true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 42#L411-11true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 109#L357-3true assume !(1 == ~M_E~0); 111#L357-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 17#L362-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 48#L367-3true assume 1 == ~E_1~0;~E_1~0 := 2; 71#L372-3true assume 1 == ~E_2~0;~E_2~0 := 2; 187#L377-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 175#L234-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 56#L251-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 5#L252-1true start_simulation_#t~ret8 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 162#L537true assume !(0 == start_simulation_~tmp~3); 169#L537-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret7, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 173#L234-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 76#L251-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 3#L252-2true stop_simulation_#t~ret7 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret7;havoc stop_simulation_#t~ret7; 207#L492true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 52#L499true stop_simulation_#res := stop_simulation_~__retres2~0; 113#L500true start_simulation_#t~ret9 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 105#L550true assume !(0 != start_simulation_~tmp___0~1); 156#L518-3true [2018-11-18 15:12:48,138 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:12:48,139 INFO L82 PathProgramCache]: Analyzing trace with hash -886407522, now seen corresponding path program 1 times [2018-11-18 15:12:48,140 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:12:48,141 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:12:48,175 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:48,175 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:12:48,175 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:48,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:12:48,233 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:12:48,235 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:12:48,236 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:12:48,239 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 15:12:48,240 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:12:48,240 INFO L82 PathProgramCache]: Analyzing trace with hash 1174536082, now seen corresponding path program 1 times [2018-11-18 15:12:48,240 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:12:48,240 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:12:48,241 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:48,241 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:12:48,241 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:48,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:12:48,248 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:12:48,248 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:12:48,249 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 15:12:48,250 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:12:48,259 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:12:48,259 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:12:48,261 INFO L87 Difference]: Start difference. First operand 211 states. Second operand 3 states. [2018-11-18 15:12:48,278 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:12:48,278 INFO L93 Difference]: Finished difference Result 210 states and 305 transitions. [2018-11-18 15:12:48,279 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:12:48,280 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 210 states and 305 transitions. [2018-11-18 15:12:48,287 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 163 [2018-11-18 15:12:48,291 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 210 states to 204 states and 299 transitions. [2018-11-18 15:12:48,292 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 204 [2018-11-18 15:12:48,293 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 204 [2018-11-18 15:12:48,293 INFO L73 IsDeterministic]: Start isDeterministic. Operand 204 states and 299 transitions. [2018-11-18 15:12:48,294 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:12:48,294 INFO L705 BuchiCegarLoop]: Abstraction has 204 states and 299 transitions. [2018-11-18 15:12:48,311 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 204 states and 299 transitions. [2018-11-18 15:12:48,324 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 204 to 204. [2018-11-18 15:12:48,324 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 204 states. [2018-11-18 15:12:48,325 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 204 states to 204 states and 299 transitions. [2018-11-18 15:12:48,326 INFO L728 BuchiCegarLoop]: Abstraction has 204 states and 299 transitions. [2018-11-18 15:12:48,326 INFO L608 BuchiCegarLoop]: Abstraction has 204 states and 299 transitions. [2018-11-18 15:12:48,326 INFO L442 BuchiCegarLoop]: ======== Iteration 2============ [2018-11-18 15:12:48,326 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 204 states and 299 transitions. [2018-11-18 15:12:48,328 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 163 [2018-11-18 15:12:48,328 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:12:48,328 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:12:48,329 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:12:48,329 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:12:48,330 INFO L794 eck$LassoCheckResult]: Stem: 574#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 449#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 450#L481 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 557#L204 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 558#L211 assume 1 == ~m_i~0;~m_st~0 := 0; 633#L211-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 611#L216-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 612#L221-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 584#L324 assume !(0 == ~M_E~0); 585#L324-2 assume !(0 == ~T1_E~0); 455#L329-1 assume !(0 == ~T2_E~0); 456#L334-1 assume 0 == ~E_1~0;~E_1~0 := 1; 510#L339-1 assume !(0 == ~E_2~0); 533#L344-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 629#L146 assume !(1 == ~m_pc~0); 498#L146-2 is_master_triggered_~__retres1~0 := 0; 497#L157 is_master_triggered_#res := is_master_triggered_~__retres1~0; 499#L158 activate_threads_#t~ret4 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 494#L395 assume !(0 != activate_threads_~tmp~1); 451#L395-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 452#L165 assume 1 == ~t1_pc~0; 566#L166 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 568#L176 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 569#L177 activate_threads_#t~ret5 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 608#L403 assume !(0 != activate_threads_~tmp___0~0); 609#L403-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 613#L184 assume !(1 == ~t2_pc~0); 546#L184-2 is_transmit2_triggered_~__retres1~2 := 0; 547#L195 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 549#L196 activate_threads_#t~ret6 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 517#L411 assume !(0 != activate_threads_~tmp___1~0); 505#L411-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 506#L357 assume !(1 == ~M_E~0); 586#L357-2 assume !(1 == ~T1_E~0); 453#L362-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 454#L367-1 assume !(1 == ~E_1~0); 507#L372-1 assume !(1 == ~E_2~0); 528#L377-1 assume { :end_inline_reset_delta_events } true; 583#L518-3 [2018-11-18 15:12:48,330 INFO L796 eck$LassoCheckResult]: Loop: 583#L518-3 assume true; 622#L518-1 assume !false; 596#L519 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 445#L299 assume true; 593#L261-1 assume !false; 521#L262 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 522#L234 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 520#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 438#L252 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 439#L266 assume !(0 != eval_~tmp~0); 561#L314 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 555#L204-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 556#L324-3 assume 0 == ~M_E~0;~M_E~0 := 1; 588#L324-5 assume !(0 == ~T1_E~0); 461#L329-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 462#L334-3 assume 0 == ~E_1~0;~E_1~0 := 1; 512#L339-3 assume 0 == ~E_2~0;~E_2~0 := 1; 543#L344-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 524#L146-9 assume 1 == ~m_pc~0; 473#L147-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 474#L157-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 476#L158-3 activate_threads_#t~ret4 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 436#L395-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 437#L395-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 446#L165-9 assume !(1 == ~t1_pc~0); 550#L165-11 is_transmit1_triggered_~__retres1~1 := 0; 551#L176-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 578#L177-3 activate_threads_#t~ret5 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 607#L403-9 assume !(0 != activate_threads_~tmp___0~0); 594#L403-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 595#L184-9 assume 1 == ~t2_pc~0; 530#L185-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 531#L195-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 534#L196-3 activate_threads_#t~ret6 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 501#L411-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 502#L411-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 503#L357-3 assume !(1 == ~M_E~0); 587#L357-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 459#L362-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 460#L367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 511#L372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 539#L377-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 631#L234-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 519#L251-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 434#L252-1 start_simulation_#t~ret8 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 435#L537 assume !(0 == start_simulation_~tmp~3); 601#L537-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret7, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 628#L234-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 548#L251-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 430#L252-2 stop_simulation_#t~ret7 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret7;havoc stop_simulation_#t~ret7; 431#L492 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 514#L499 stop_simulation_#res := stop_simulation_~__retres2~0; 515#L500 start_simulation_#t~ret9 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 582#L550 assume !(0 != start_simulation_~tmp___0~1); 583#L518-3 [2018-11-18 15:12:48,330 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:12:48,330 INFO L82 PathProgramCache]: Analyzing trace with hash 1357575776, now seen corresponding path program 1 times [2018-11-18 15:12:48,330 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:12:48,331 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:12:48,331 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:48,331 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:12:48,331 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:48,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:12:48,365 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:12:48,365 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:12:48,365 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:12:48,366 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 15:12:48,366 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:12:48,366 INFO L82 PathProgramCache]: Analyzing trace with hash -1857470970, now seen corresponding path program 1 times [2018-11-18 15:12:48,366 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:12:48,366 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:12:48,367 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:48,367 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:12:48,367 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:48,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:12:48,410 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:12:48,410 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:12:48,410 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:12:48,410 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:12:48,411 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:12:48,411 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:12:48,411 INFO L87 Difference]: Start difference. First operand 204 states and 299 transitions. cyclomatic complexity: 96 Second operand 3 states. [2018-11-18 15:12:48,434 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:12:48,434 INFO L93 Difference]: Finished difference Result 204 states and 298 transitions. [2018-11-18 15:12:48,434 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:12:48,435 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 204 states and 298 transitions. [2018-11-18 15:12:48,436 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 163 [2018-11-18 15:12:48,438 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 204 states to 204 states and 298 transitions. [2018-11-18 15:12:48,438 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 204 [2018-11-18 15:12:48,438 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 204 [2018-11-18 15:12:48,438 INFO L73 IsDeterministic]: Start isDeterministic. Operand 204 states and 298 transitions. [2018-11-18 15:12:48,439 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:12:48,439 INFO L705 BuchiCegarLoop]: Abstraction has 204 states and 298 transitions. [2018-11-18 15:12:48,440 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 204 states and 298 transitions. [2018-11-18 15:12:48,445 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 204 to 204. [2018-11-18 15:12:48,445 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 204 states. [2018-11-18 15:12:48,446 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 204 states to 204 states and 298 transitions. [2018-11-18 15:12:48,446 INFO L728 BuchiCegarLoop]: Abstraction has 204 states and 298 transitions. [2018-11-18 15:12:48,446 INFO L608 BuchiCegarLoop]: Abstraction has 204 states and 298 transitions. [2018-11-18 15:12:48,446 INFO L442 BuchiCegarLoop]: ======== Iteration 3============ [2018-11-18 15:12:48,446 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 204 states and 298 transitions. [2018-11-18 15:12:48,448 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 163 [2018-11-18 15:12:48,448 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:12:48,448 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:12:48,449 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:12:48,449 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:12:48,449 INFO L794 eck$LassoCheckResult]: Stem: 989#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 864#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 865#L481 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 972#L204 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 973#L211 assume 1 == ~m_i~0;~m_st~0 := 0; 1048#L211-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1026#L216-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1027#L221-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 999#L324 assume !(0 == ~M_E~0); 1000#L324-2 assume !(0 == ~T1_E~0); 870#L329-1 assume !(0 == ~T2_E~0); 871#L334-1 assume 0 == ~E_1~0;~E_1~0 := 1; 925#L339-1 assume !(0 == ~E_2~0); 948#L344-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1044#L146 assume !(1 == ~m_pc~0); 913#L146-2 is_master_triggered_~__retres1~0 := 0; 912#L157 is_master_triggered_#res := is_master_triggered_~__retres1~0; 914#L158 activate_threads_#t~ret4 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 909#L395 assume !(0 != activate_threads_~tmp~1); 866#L395-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 867#L165 assume 1 == ~t1_pc~0; 981#L166 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 983#L176 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 984#L177 activate_threads_#t~ret5 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 1023#L403 assume !(0 != activate_threads_~tmp___0~0); 1024#L403-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1028#L184 assume !(1 == ~t2_pc~0); 961#L184-2 is_transmit2_triggered_~__retres1~2 := 0; 962#L195 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 964#L196 activate_threads_#t~ret6 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 932#L411 assume !(0 != activate_threads_~tmp___1~0); 920#L411-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 921#L357 assume !(1 == ~M_E~0); 1001#L357-2 assume !(1 == ~T1_E~0); 868#L362-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 869#L367-1 assume !(1 == ~E_1~0); 922#L372-1 assume !(1 == ~E_2~0); 943#L377-1 assume { :end_inline_reset_delta_events } true; 998#L518-3 [2018-11-18 15:12:48,449 INFO L796 eck$LassoCheckResult]: Loop: 998#L518-3 assume true; 1037#L518-1 assume !false; 1011#L519 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 860#L299 assume true; 1008#L261-1 assume !false; 936#L262 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 937#L234 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 935#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 853#L252 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 854#L266 assume !(0 != eval_~tmp~0); 976#L314 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 970#L204-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 971#L324-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1003#L324-5 assume !(0 == ~T1_E~0); 876#L329-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 877#L334-3 assume 0 == ~E_1~0;~E_1~0 := 1; 927#L339-3 assume 0 == ~E_2~0;~E_2~0 := 1; 958#L344-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 939#L146-9 assume 1 == ~m_pc~0; 888#L147-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 889#L157-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 891#L158-3 activate_threads_#t~ret4 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 851#L395-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 852#L395-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 861#L165-9 assume !(1 == ~t1_pc~0); 965#L165-11 is_transmit1_triggered_~__retres1~1 := 0; 966#L176-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 993#L177-3 activate_threads_#t~ret5 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 1022#L403-9 assume !(0 != activate_threads_~tmp___0~0); 1009#L403-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1010#L184-9 assume 1 == ~t2_pc~0; 945#L185-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 946#L195-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 949#L196-3 activate_threads_#t~ret6 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 916#L411-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 917#L411-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 918#L357-3 assume !(1 == ~M_E~0); 1002#L357-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 874#L362-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 875#L367-3 assume 1 == ~E_1~0;~E_1~0 := 2; 926#L372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 954#L377-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1046#L234-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 934#L251-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 849#L252-1 start_simulation_#t~ret8 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 850#L537 assume !(0 == start_simulation_~tmp~3); 1016#L537-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret7, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1043#L234-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 963#L251-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 845#L252-2 stop_simulation_#t~ret7 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret7;havoc stop_simulation_#t~ret7; 846#L492 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 929#L499 stop_simulation_#res := stop_simulation_~__retres2~0; 930#L500 start_simulation_#t~ret9 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 997#L550 assume !(0 != start_simulation_~tmp___0~1); 998#L518-3 [2018-11-18 15:12:48,450 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:12:48,450 INFO L82 PathProgramCache]: Analyzing trace with hash 1082816162, now seen corresponding path program 1 times [2018-11-18 15:12:48,450 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:12:48,450 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:12:48,451 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:48,451 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:12:48,451 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:48,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:12:48,474 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:12:48,474 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:12:48,475 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 15:12:48,475 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 15:12:48,475 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:12:48,475 INFO L82 PathProgramCache]: Analyzing trace with hash -1857470970, now seen corresponding path program 2 times [2018-11-18 15:12:48,475 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:12:48,475 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:12:48,476 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:48,476 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:12:48,476 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:48,483 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:12:48,507 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:12:48,507 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:12:48,507 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:12:48,508 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:12:48,508 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:12:48,508 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:12:48,508 INFO L87 Difference]: Start difference. First operand 204 states and 298 transitions. cyclomatic complexity: 95 Second operand 3 states. [2018-11-18 15:12:48,533 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:12:48,534 INFO L93 Difference]: Finished difference Result 204 states and 289 transitions. [2018-11-18 15:12:48,534 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:12:48,534 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 204 states and 289 transitions. [2018-11-18 15:12:48,535 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 163 [2018-11-18 15:12:48,537 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 204 states to 204 states and 289 transitions. [2018-11-18 15:12:48,537 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 204 [2018-11-18 15:12:48,537 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 204 [2018-11-18 15:12:48,537 INFO L73 IsDeterministic]: Start isDeterministic. Operand 204 states and 289 transitions. [2018-11-18 15:12:48,538 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:12:48,538 INFO L705 BuchiCegarLoop]: Abstraction has 204 states and 289 transitions. [2018-11-18 15:12:48,539 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 204 states and 289 transitions. [2018-11-18 15:12:48,543 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 204 to 204. [2018-11-18 15:12:48,543 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 204 states. [2018-11-18 15:12:48,544 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 204 states to 204 states and 289 transitions. [2018-11-18 15:12:48,544 INFO L728 BuchiCegarLoop]: Abstraction has 204 states and 289 transitions. [2018-11-18 15:12:48,544 INFO L608 BuchiCegarLoop]: Abstraction has 204 states and 289 transitions. [2018-11-18 15:12:48,544 INFO L442 BuchiCegarLoop]: ======== Iteration 4============ [2018-11-18 15:12:48,544 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 204 states and 289 transitions. [2018-11-18 15:12:48,545 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 163 [2018-11-18 15:12:48,546 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:12:48,546 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:12:48,547 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:12:48,547 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:12:48,547 INFO L794 eck$LassoCheckResult]: Stem: 1404#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 1279#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 1280#L481 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 1387#L204 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1388#L211 assume 1 == ~m_i~0;~m_st~0 := 0; 1463#L211-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1441#L216-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1442#L221-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1414#L324 assume !(0 == ~M_E~0); 1415#L324-2 assume !(0 == ~T1_E~0); 1285#L329-1 assume !(0 == ~T2_E~0); 1286#L334-1 assume !(0 == ~E_1~0); 1340#L339-1 assume !(0 == ~E_2~0); 1363#L344-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1459#L146 assume !(1 == ~m_pc~0); 1328#L146-2 is_master_triggered_~__retres1~0 := 0; 1327#L157 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1329#L158 activate_threads_#t~ret4 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 1324#L395 assume !(0 != activate_threads_~tmp~1); 1281#L395-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1282#L165 assume !(1 == ~t1_pc~0); 1397#L165-2 is_transmit1_triggered_~__retres1~1 := 0; 1398#L176 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1399#L177 activate_threads_#t~ret5 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 1438#L403 assume !(0 != activate_threads_~tmp___0~0); 1439#L403-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1443#L184 assume !(1 == ~t2_pc~0); 1376#L184-2 is_transmit2_triggered_~__retres1~2 := 0; 1377#L195 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1379#L196 activate_threads_#t~ret6 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 1347#L411 assume !(0 != activate_threads_~tmp___1~0); 1335#L411-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1336#L357 assume !(1 == ~M_E~0); 1416#L357-2 assume !(1 == ~T1_E~0); 1283#L362-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1284#L367-1 assume !(1 == ~E_1~0); 1337#L372-1 assume !(1 == ~E_2~0); 1358#L377-1 assume { :end_inline_reset_delta_events } true; 1413#L518-3 [2018-11-18 15:12:48,547 INFO L796 eck$LassoCheckResult]: Loop: 1413#L518-3 assume true; 1452#L518-1 assume !false; 1426#L519 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 1275#L299 assume true; 1423#L261-1 assume !false; 1351#L262 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1352#L234 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 1350#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1268#L252 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 1269#L266 assume !(0 != eval_~tmp~0); 1391#L314 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 1385#L204-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 1386#L324-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1418#L324-5 assume !(0 == ~T1_E~0); 1291#L329-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1292#L334-3 assume !(0 == ~E_1~0); 1342#L339-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1373#L344-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1354#L146-9 assume 1 == ~m_pc~0; 1303#L147-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 1304#L157-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1306#L158-3 activate_threads_#t~ret4 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 1266#L395-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1267#L395-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1276#L165-9 assume !(1 == ~t1_pc~0); 1380#L165-11 is_transmit1_triggered_~__retres1~1 := 0; 1381#L176-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1408#L177-3 activate_threads_#t~ret5 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 1437#L403-9 assume !(0 != activate_threads_~tmp___0~0); 1424#L403-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1425#L184-9 assume 1 == ~t2_pc~0; 1360#L185-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1361#L195-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1364#L196-3 activate_threads_#t~ret6 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 1331#L411-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1332#L411-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1333#L357-3 assume !(1 == ~M_E~0); 1417#L357-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1289#L362-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1290#L367-3 assume !(1 == ~E_1~0); 1341#L372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1369#L377-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1461#L234-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 1349#L251-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1264#L252-1 start_simulation_#t~ret8 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 1265#L537 assume !(0 == start_simulation_~tmp~3); 1431#L537-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret7, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1458#L234-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 1378#L251-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1260#L252-2 stop_simulation_#t~ret7 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret7;havoc stop_simulation_#t~ret7; 1261#L492 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1344#L499 stop_simulation_#res := stop_simulation_~__retres2~0; 1345#L500 start_simulation_#t~ret9 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 1412#L550 assume !(0 != start_simulation_~tmp___0~1); 1413#L518-3 [2018-11-18 15:12:48,547 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:12:48,547 INFO L82 PathProgramCache]: Analyzing trace with hash -148571389, now seen corresponding path program 1 times [2018-11-18 15:12:48,548 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:12:48,548 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:12:48,549 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:48,549 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:12:48,549 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:48,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:12:48,576 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:12:48,576 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:12:48,576 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 15:12:48,577 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 15:12:48,577 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:12:48,577 INFO L82 PathProgramCache]: Analyzing trace with hash -687734518, now seen corresponding path program 1 times [2018-11-18 15:12:48,577 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:12:48,577 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:12:48,578 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:48,578 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:12:48,578 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:48,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:12:48,621 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:12:48,621 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:12:48,621 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:12:48,621 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:12:48,621 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:12:48,622 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:12:48,622 INFO L87 Difference]: Start difference. First operand 204 states and 289 transitions. cyclomatic complexity: 86 Second operand 3 states. [2018-11-18 15:12:48,643 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:12:48,644 INFO L93 Difference]: Finished difference Result 204 states and 284 transitions. [2018-11-18 15:12:48,644 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:12:48,644 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 204 states and 284 transitions. [2018-11-18 15:12:48,645 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 163 [2018-11-18 15:12:48,646 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 204 states to 204 states and 284 transitions. [2018-11-18 15:12:48,646 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 204 [2018-11-18 15:12:48,647 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 204 [2018-11-18 15:12:48,647 INFO L73 IsDeterministic]: Start isDeterministic. Operand 204 states and 284 transitions. [2018-11-18 15:12:48,647 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:12:48,648 INFO L705 BuchiCegarLoop]: Abstraction has 204 states and 284 transitions. [2018-11-18 15:12:48,648 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 204 states and 284 transitions. [2018-11-18 15:12:48,652 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 204 to 204. [2018-11-18 15:12:48,652 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 204 states. [2018-11-18 15:12:48,653 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 204 states to 204 states and 284 transitions. [2018-11-18 15:12:48,653 INFO L728 BuchiCegarLoop]: Abstraction has 204 states and 284 transitions. [2018-11-18 15:12:48,653 INFO L608 BuchiCegarLoop]: Abstraction has 204 states and 284 transitions. [2018-11-18 15:12:48,653 INFO L442 BuchiCegarLoop]: ======== Iteration 5============ [2018-11-18 15:12:48,653 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 204 states and 284 transitions. [2018-11-18 15:12:48,654 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 163 [2018-11-18 15:12:48,654 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:12:48,654 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:12:48,655 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:12:48,655 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:12:48,656 INFO L794 eck$LassoCheckResult]: Stem: 1820#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 1694#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 1695#L481 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 1802#L204 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1803#L211 assume 1 == ~m_i~0;~m_st~0 := 0; 1878#L211-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1856#L216-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1857#L221-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1829#L324 assume !(0 == ~M_E~0); 1830#L324-2 assume !(0 == ~T1_E~0); 1702#L329-1 assume !(0 == ~T2_E~0); 1703#L334-1 assume !(0 == ~E_1~0); 1755#L339-1 assume !(0 == ~E_2~0); 1779#L344-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1874#L146 assume !(1 == ~m_pc~0); 1743#L146-2 is_master_triggered_~__retres1~0 := 0; 1742#L157 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1744#L158 activate_threads_#t~ret4 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 1740#L395 assume !(0 != activate_threads_~tmp~1); 1696#L395-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1697#L165 assume !(1 == ~t1_pc~0); 1812#L165-2 is_transmit1_triggered_~__retres1~1 := 0; 1814#L176 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1815#L177 activate_threads_#t~ret5 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 1853#L403 assume !(0 != activate_threads_~tmp___0~0); 1854#L403-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1858#L184 assume !(1 == ~t2_pc~0); 1792#L184-2 is_transmit2_triggered_~__retres1~2 := 0; 1793#L195 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1794#L196 activate_threads_#t~ret6 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 1762#L411 assume !(0 != activate_threads_~tmp___1~0); 1750#L411-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1751#L357 assume !(1 == ~M_E~0); 1831#L357-2 assume !(1 == ~T1_E~0); 1698#L362-1 assume !(1 == ~T2_E~0); 1699#L367-1 assume !(1 == ~E_1~0); 1752#L372-1 assume !(1 == ~E_2~0); 1774#L377-1 assume { :end_inline_reset_delta_events } true; 1828#L518-3 [2018-11-18 15:12:48,656 INFO L796 eck$LassoCheckResult]: Loop: 1828#L518-3 assume true; 1867#L518-1 assume !false; 1843#L519 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 1690#L299 assume true; 1840#L261-1 assume !false; 1767#L262 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1768#L234 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 1765#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1683#L252 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 1684#L266 assume !(0 != eval_~tmp~0); 1808#L314 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 1800#L204-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 1801#L324-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1833#L324-5 assume !(0 == ~T1_E~0); 1706#L329-3 assume !(0 == ~T2_E~0); 1707#L334-3 assume !(0 == ~E_1~0); 1757#L339-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1788#L344-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1769#L146-9 assume 1 == ~m_pc~0; 1718#L147-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 1719#L157-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1721#L158-3 activate_threads_#t~ret4 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 1681#L395-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1682#L395-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1691#L165-9 assume !(1 == ~t1_pc~0); 1795#L165-11 is_transmit1_triggered_~__retres1~1 := 0; 1796#L176-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1823#L177-3 activate_threads_#t~ret5 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 1852#L403-9 assume !(0 != activate_threads_~tmp___0~0); 1838#L403-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1839#L184-9 assume !(1 == ~t2_pc~0); 1777#L184-11 is_transmit2_triggered_~__retres1~2 := 0; 1776#L195-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1778#L196-3 activate_threads_#t~ret6 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 1746#L411-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1747#L411-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1748#L357-3 assume !(1 == ~M_E~0); 1832#L357-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1704#L362-3 assume !(1 == ~T2_E~0); 1705#L367-3 assume !(1 == ~E_1~0); 1756#L372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1784#L377-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1876#L234-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 1764#L251-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1679#L252-1 start_simulation_#t~ret8 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 1680#L537 assume !(0 == start_simulation_~tmp~3); 1846#L537-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret7, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 1873#L234-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 1790#L251-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 1675#L252-2 stop_simulation_#t~ret7 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret7;havoc stop_simulation_#t~ret7; 1676#L492 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1759#L499 stop_simulation_#res := stop_simulation_~__retres2~0; 1760#L500 start_simulation_#t~ret9 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 1827#L550 assume !(0 != start_simulation_~tmp___0~1); 1828#L518-3 [2018-11-18 15:12:48,656 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:12:48,656 INFO L82 PathProgramCache]: Analyzing trace with hash -148511807, now seen corresponding path program 1 times [2018-11-18 15:12:48,656 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:12:48,657 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:12:48,666 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:48,666 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:12:48,666 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:48,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:12:48,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:12:48,692 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:12:48,692 INFO L82 PathProgramCache]: Analyzing trace with hash -376037851, now seen corresponding path program 1 times [2018-11-18 15:12:48,693 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:12:48,693 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:12:48,693 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:48,694 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:12:48,694 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:48,699 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:12:48,721 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:12:48,721 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:12:48,721 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:12:48,721 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:12:48,722 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:12:48,722 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:12:48,722 INFO L87 Difference]: Start difference. First operand 204 states and 284 transitions. cyclomatic complexity: 81 Second operand 3 states. [2018-11-18 15:12:48,786 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:12:48,787 INFO L93 Difference]: Finished difference Result 342 states and 468 transitions. [2018-11-18 15:12:48,787 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:12:48,788 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 342 states and 468 transitions. [2018-11-18 15:12:48,790 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 274 [2018-11-18 15:12:48,792 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 342 states to 342 states and 468 transitions. [2018-11-18 15:12:48,792 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 342 [2018-11-18 15:12:48,792 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 342 [2018-11-18 15:12:48,792 INFO L73 IsDeterministic]: Start isDeterministic. Operand 342 states and 468 transitions. [2018-11-18 15:12:48,793 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:12:48,793 INFO L705 BuchiCegarLoop]: Abstraction has 342 states and 468 transitions. [2018-11-18 15:12:48,795 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 342 states and 468 transitions. [2018-11-18 15:12:48,801 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 342 to 342. [2018-11-18 15:12:48,802 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 342 states. [2018-11-18 15:12:48,803 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 342 states to 342 states and 468 transitions. [2018-11-18 15:12:48,803 INFO L728 BuchiCegarLoop]: Abstraction has 342 states and 468 transitions. [2018-11-18 15:12:48,803 INFO L608 BuchiCegarLoop]: Abstraction has 342 states and 468 transitions. [2018-11-18 15:12:48,803 INFO L442 BuchiCegarLoop]: ======== Iteration 6============ [2018-11-18 15:12:48,803 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 342 states and 468 transitions. [2018-11-18 15:12:48,805 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 274 [2018-11-18 15:12:48,805 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:12:48,807 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:12:48,808 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:12:48,808 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:12:48,808 INFO L794 eck$LassoCheckResult]: Stem: 2373#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 2246#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 2247#L481 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 2354#L204 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2355#L211 assume 1 == ~m_i~0;~m_st~0 := 0; 2450#L211-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2416#L216-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2417#L221-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2382#L324 assume 0 == ~M_E~0;~M_E~0 := 1; 2383#L324-2 assume !(0 == ~T1_E~0); 2252#L329-1 assume !(0 == ~T2_E~0); 2253#L334-1 assume !(0 == ~E_1~0); 2302#L339-1 assume !(0 == ~E_2~0); 2329#L344-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2437#L146 assume !(1 == ~m_pc~0); 2433#L146-2 is_master_triggered_~__retres1~0 := 0; 2290#L157 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2291#L158 activate_threads_#t~ret4 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 2288#L395 assume !(0 != activate_threads_~tmp~1); 2248#L395-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2249#L165 assume !(1 == ~t1_pc~0); 2364#L165-2 is_transmit1_triggered_~__retres1~1 := 0; 2366#L176 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2367#L177 activate_threads_#t~ret5 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 2413#L403 assume !(0 != activate_threads_~tmp___0~0); 2414#L403-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2418#L184 assume !(1 == ~t2_pc~0); 2488#L184-2 is_transmit2_triggered_~__retres1~2 := 0; 2478#L195 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2477#L196 activate_threads_#t~ret6 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 2475#L411 assume !(0 != activate_threads_~tmp___1~0); 2297#L411-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2298#L357 assume 1 == ~M_E~0;~M_E~0 := 2; 2385#L357-2 assume !(1 == ~T1_E~0); 2250#L362-1 assume !(1 == ~T2_E~0); 2251#L367-1 assume !(1 == ~E_1~0); 2299#L372-1 assume !(1 == ~E_2~0); 2324#L377-1 assume { :end_inline_reset_delta_events } true; 2381#L518-3 [2018-11-18 15:12:48,808 INFO L796 eck$LassoCheckResult]: Loop: 2381#L518-3 assume true; 2427#L518-1 assume !false; 2402#L519 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 2242#L299 assume true; 2461#L261-1 assume !false; 2460#L262 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2459#L234 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 2313#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2235#L252 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 2236#L266 assume !(0 != eval_~tmp~0); 2454#L314 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 2453#L204-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 2452#L324-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2388#L324-5 assume !(0 == ~T1_E~0); 2536#L329-3 assume !(0 == ~T2_E~0); 2535#L334-3 assume !(0 == ~E_1~0); 2340#L339-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2341#L344-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2319#L146-9 assume 1 == ~m_pc~0; 2269#L147-3 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 2270#L157-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2271#L158-3 activate_threads_#t~ret4 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 2233#L395-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2234#L395-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2243#L165-9 assume !(1 == ~t1_pc~0); 2347#L165-11 is_transmit1_triggered_~__retres1~1 := 0; 2348#L176-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2376#L177-3 activate_threads_#t~ret5 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 2411#L403-9 assume !(0 != activate_threads_~tmp___0~0); 2412#L403-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2476#L184-9 assume 1 == ~t2_pc~0; 2473#L185-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2472#L195-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2471#L196-3 activate_threads_#t~ret6 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 2470#L411-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2469#L411-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2386#L357-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2387#L357-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2256#L362-3 assume !(1 == ~T2_E~0); 2257#L367-3 assume !(1 == ~E_1~0); 2303#L372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2335#L377-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2439#L234-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 2312#L251-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2231#L252-1 start_simulation_#t~ret8 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 2232#L537 assume !(0 == start_simulation_~tmp~3); 2405#L537-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret7, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2436#L234-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 2342#L251-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2227#L252-2 stop_simulation_#t~ret7 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret7;havoc stop_simulation_#t~ret7; 2228#L492 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2306#L499 stop_simulation_#res := stop_simulation_~__retres2~0; 2307#L500 start_simulation_#t~ret9 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 2380#L550 assume !(0 != start_simulation_~tmp___0~1); 2381#L518-3 [2018-11-18 15:12:48,809 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:12:48,809 INFO L82 PathProgramCache]: Analyzing trace with hash -228402363, now seen corresponding path program 1 times [2018-11-18 15:12:48,809 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:12:48,809 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:12:48,810 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:48,810 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:12:48,810 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:48,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:12:48,840 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:12:48,840 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:12:48,840 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 15:12:48,841 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 15:12:48,841 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:12:48,841 INFO L82 PathProgramCache]: Analyzing trace with hash -1086465464, now seen corresponding path program 1 times [2018-11-18 15:12:48,841 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:12:48,841 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:12:48,842 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:48,842 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:12:48,842 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:48,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:12:48,876 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:12:48,877 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:12:48,877 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 15:12:48,877 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:12:48,877 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:12:48,877 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:12:48,878 INFO L87 Difference]: Start difference. First operand 342 states and 468 transitions. cyclomatic complexity: 127 Second operand 3 states. [2018-11-18 15:12:48,914 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:12:48,914 INFO L93 Difference]: Finished difference Result 204 states and 274 transitions. [2018-11-18 15:12:48,915 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:12:48,915 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 204 states and 274 transitions. [2018-11-18 15:12:48,916 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 163 [2018-11-18 15:12:48,917 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 204 states to 204 states and 274 transitions. [2018-11-18 15:12:48,918 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 204 [2018-11-18 15:12:48,918 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 204 [2018-11-18 15:12:48,918 INFO L73 IsDeterministic]: Start isDeterministic. Operand 204 states and 274 transitions. [2018-11-18 15:12:48,918 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:12:48,918 INFO L705 BuchiCegarLoop]: Abstraction has 204 states and 274 transitions. [2018-11-18 15:12:48,919 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 204 states and 274 transitions. [2018-11-18 15:12:48,921 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 204 to 204. [2018-11-18 15:12:48,923 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 204 states. [2018-11-18 15:12:48,924 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 204 states to 204 states and 274 transitions. [2018-11-18 15:12:48,924 INFO L728 BuchiCegarLoop]: Abstraction has 204 states and 274 transitions. [2018-11-18 15:12:48,924 INFO L608 BuchiCegarLoop]: Abstraction has 204 states and 274 transitions. [2018-11-18 15:12:48,924 INFO L442 BuchiCegarLoop]: ======== Iteration 7============ [2018-11-18 15:12:48,924 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 204 states and 274 transitions. [2018-11-18 15:12:48,925 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 163 [2018-11-18 15:12:48,926 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:12:48,926 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:12:48,926 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:12:48,926 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:12:48,927 INFO L794 eck$LassoCheckResult]: Stem: 2923#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 2801#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 2802#L481 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 2906#L204 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2907#L211 assume 1 == ~m_i~0;~m_st~0 := 0; 2985#L211-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2960#L216-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2961#L221-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2933#L324 assume !(0 == ~M_E~0); 2934#L324-2 assume !(0 == ~T1_E~0); 2807#L329-1 assume !(0 == ~T2_E~0); 2808#L334-1 assume !(0 == ~E_1~0); 2857#L339-1 assume !(0 == ~E_2~0); 2882#L344-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2981#L146 assume !(1 == ~m_pc~0); 2845#L146-2 is_master_triggered_~__retres1~0 := 0; 2976#L157 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2846#L158 activate_threads_#t~ret4 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 2842#L395 assume !(0 != activate_threads_~tmp~1); 2803#L395-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2804#L165 assume !(1 == ~t1_pc~0); 2916#L165-2 is_transmit1_triggered_~__retres1~1 := 0; 2917#L176 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2918#L177 activate_threads_#t~ret5 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 2957#L403 assume !(0 != activate_threads_~tmp___0~0); 2958#L403-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2962#L184 assume !(1 == ~t2_pc~0); 2895#L184-2 is_transmit2_triggered_~__retres1~2 := 0; 2896#L195 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2898#L196 activate_threads_#t~ret6 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 2864#L411 assume !(0 != activate_threads_~tmp___1~0); 2852#L411-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2853#L357 assume !(1 == ~M_E~0); 2935#L357-2 assume !(1 == ~T1_E~0); 2805#L362-1 assume !(1 == ~T2_E~0); 2806#L367-1 assume !(1 == ~E_1~0); 2854#L372-1 assume !(1 == ~E_2~0); 2877#L377-1 assume { :end_inline_reset_delta_events } true; 2932#L518-3 [2018-11-18 15:12:48,927 INFO L796 eck$LassoCheckResult]: Loop: 2932#L518-3 assume true; 2971#L518-1 assume !false; 2945#L519 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 2797#L299 assume true; 2942#L261-1 assume !false; 2868#L262 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2869#L234 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 2867#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2790#L252 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 2791#L266 assume !(0 != eval_~tmp~0); 2910#L314 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 2904#L204-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 2905#L324-3 assume !(0 == ~M_E~0); 2937#L324-5 assume !(0 == ~T1_E~0); 2813#L329-3 assume !(0 == ~T2_E~0); 2814#L334-3 assume !(0 == ~E_1~0); 2859#L339-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2892#L344-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2873#L146-9 assume !(1 == ~m_pc~0); 2825#L146-11 is_master_triggered_~__retres1~0 := 0; 2872#L157-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2826#L158-3 activate_threads_#t~ret4 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 2788#L395-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2789#L395-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2798#L165-9 assume !(1 == ~t1_pc~0); 2899#L165-11 is_transmit1_triggered_~__retres1~1 := 0; 2900#L176-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2927#L177-3 activate_threads_#t~ret5 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 2956#L403-9 assume !(0 != activate_threads_~tmp___0~0); 2943#L403-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2944#L184-9 assume !(1 == ~t2_pc~0); 2881#L184-11 is_transmit2_triggered_~__retres1~2 := 0; 2880#L195-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2883#L196-3 activate_threads_#t~ret6 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 2848#L411-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2849#L411-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2850#L357-3 assume !(1 == ~M_E~0); 2936#L357-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2811#L362-3 assume !(1 == ~T2_E~0); 2812#L367-3 assume !(1 == ~E_1~0); 2858#L372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2888#L377-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2983#L234-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 2866#L251-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2786#L252-1 start_simulation_#t~ret8 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 2787#L537 assume !(0 == start_simulation_~tmp~3); 2950#L537-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret7, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 2980#L234-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 2897#L251-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 2782#L252-2 stop_simulation_#t~ret7 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret7;havoc stop_simulation_#t~ret7; 2783#L492 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2861#L499 stop_simulation_#res := stop_simulation_~__retres2~0; 2862#L500 start_simulation_#t~ret9 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 2931#L550 assume !(0 != start_simulation_~tmp___0~1); 2932#L518-3 [2018-11-18 15:12:48,927 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:12:48,927 INFO L82 PathProgramCache]: Analyzing trace with hash -148511807, now seen corresponding path program 2 times [2018-11-18 15:12:48,927 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:12:48,927 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:12:48,928 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:48,928 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:12:48,928 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:48,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:12:48,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:12:48,939 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:12:48,939 INFO L82 PathProgramCache]: Analyzing trace with hash -1892707966, now seen corresponding path program 1 times [2018-11-18 15:12:48,939 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:12:48,939 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:12:48,940 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:48,940 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:12:48,940 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:48,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:12:48,988 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:12:48,988 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:12:48,988 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 15:12:48,989 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:12:48,989 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 15:12:48,989 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:12:48,989 INFO L87 Difference]: Start difference. First operand 204 states and 274 transitions. cyclomatic complexity: 71 Second operand 5 states. [2018-11-18 15:12:49,041 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:12:49,041 INFO L93 Difference]: Finished difference Result 333 states and 443 transitions. [2018-11-18 15:12:49,041 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-18 15:12:49,042 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 333 states and 443 transitions. [2018-11-18 15:12:49,044 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 292 [2018-11-18 15:12:49,045 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 333 states to 333 states and 443 transitions. [2018-11-18 15:12:49,045 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 333 [2018-11-18 15:12:49,045 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 333 [2018-11-18 15:12:49,046 INFO L73 IsDeterministic]: Start isDeterministic. Operand 333 states and 443 transitions. [2018-11-18 15:12:49,046 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:12:49,046 INFO L705 BuchiCegarLoop]: Abstraction has 333 states and 443 transitions. [2018-11-18 15:12:49,047 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 333 states and 443 transitions. [2018-11-18 15:12:49,048 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 333 to 207. [2018-11-18 15:12:49,049 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 207 states. [2018-11-18 15:12:49,049 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 207 states to 207 states and 277 transitions. [2018-11-18 15:12:49,049 INFO L728 BuchiCegarLoop]: Abstraction has 207 states and 277 transitions. [2018-11-18 15:12:49,050 INFO L608 BuchiCegarLoop]: Abstraction has 207 states and 277 transitions. [2018-11-18 15:12:49,050 INFO L442 BuchiCegarLoop]: ======== Iteration 8============ [2018-11-18 15:12:49,050 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 207 states and 277 transitions. [2018-11-18 15:12:49,051 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 166 [2018-11-18 15:12:49,051 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:12:49,051 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:12:49,052 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:12:49,052 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:12:49,052 INFO L794 eck$LassoCheckResult]: Stem: 3479#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 3354#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 3355#L481 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 3460#L204 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3461#L211 assume 1 == ~m_i~0;~m_st~0 := 0; 3540#L211-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3515#L216-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3516#L221-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3488#L324 assume !(0 == ~M_E~0); 3489#L324-2 assume !(0 == ~T1_E~0); 3362#L329-1 assume !(0 == ~T2_E~0); 3363#L334-1 assume !(0 == ~E_1~0); 3410#L339-1 assume !(0 == ~E_2~0); 3437#L344-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3536#L146 assume !(1 == ~m_pc~0); 3398#L146-2 is_master_triggered_~__retres1~0 := 0; 3531#L157 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3399#L158 activate_threads_#t~ret4 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 3396#L395 assume !(0 != activate_threads_~tmp~1); 3356#L395-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3357#L165 assume !(1 == ~t1_pc~0); 3470#L165-2 is_transmit1_triggered_~__retres1~1 := 0; 3472#L176 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3473#L177 activate_threads_#t~ret5 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 3512#L403 assume !(0 != activate_threads_~tmp___0~0); 3513#L403-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3517#L184 assume !(1 == ~t2_pc~0); 3450#L184-2 is_transmit2_triggered_~__retres1~2 := 0; 3451#L195 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3452#L196 activate_threads_#t~ret6 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 3417#L411 assume !(0 != activate_threads_~tmp___1~0); 3405#L411-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3406#L357 assume !(1 == ~M_E~0); 3490#L357-2 assume !(1 == ~T1_E~0); 3358#L362-1 assume !(1 == ~T2_E~0); 3359#L367-1 assume !(1 == ~E_1~0); 3407#L372-1 assume !(1 == ~E_2~0); 3432#L377-1 assume { :end_inline_reset_delta_events } true; 3487#L518-3 [2018-11-18 15:12:49,052 INFO L796 eck$LassoCheckResult]: Loop: 3487#L518-3 assume true; 3526#L518-1 assume !false; 3500#L519 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 3350#L299 assume true; 3499#L261-1 assume !false; 3422#L262 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 3423#L234 assume !(0 == ~m_st~0); 3520#L238 assume !(0 == ~t1_st~0); 3475#L242 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; 3420#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 3421#L252 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 3541#L266 assume !(0 != eval_~tmp~0); 3466#L314 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 3458#L204-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 3459#L324-3 assume !(0 == ~M_E~0); 3492#L324-5 assume !(0 == ~T1_E~0); 3366#L329-3 assume !(0 == ~T2_E~0); 3367#L334-3 assume !(0 == ~E_1~0); 3412#L339-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3446#L344-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3427#L146-9 assume !(1 == ~m_pc~0); 3378#L146-11 is_master_triggered_~__retres1~0 := 0; 3426#L157-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3379#L158-3 activate_threads_#t~ret4 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 3341#L395-9 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3342#L395-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3351#L165-9 assume !(1 == ~t1_pc~0); 3453#L165-11 is_transmit1_triggered_~__retres1~1 := 0; 3454#L176-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3482#L177-3 activate_threads_#t~ret5 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 3511#L403-9 assume !(0 != activate_threads_~tmp___0~0); 3497#L403-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3498#L184-9 assume 1 == ~t2_pc~0; 3433#L185-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3434#L195-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3436#L196-3 activate_threads_#t~ret6 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 3401#L411-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3402#L411-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3403#L357-3 assume !(1 == ~M_E~0); 3491#L357-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3364#L362-3 assume !(1 == ~T2_E~0); 3365#L367-3 assume !(1 == ~E_1~0); 3411#L372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3442#L377-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 3538#L234-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 3419#L251-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 3339#L252-1 start_simulation_#t~ret8 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 3340#L537 assume !(0 == start_simulation_~tmp~3); 3505#L537-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret7, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 3535#L234-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 3448#L251-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 3335#L252-2 stop_simulation_#t~ret7 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret7;havoc stop_simulation_#t~ret7; 3336#L492 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 3414#L499 stop_simulation_#res := stop_simulation_~__retres2~0; 3415#L500 start_simulation_#t~ret9 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 3486#L550 assume !(0 != start_simulation_~tmp___0~1); 3487#L518-3 [2018-11-18 15:12:49,052 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:12:49,052 INFO L82 PathProgramCache]: Analyzing trace with hash -148511807, now seen corresponding path program 3 times [2018-11-18 15:12:49,053 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:12:49,053 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:12:49,053 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:49,053 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:12:49,053 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:49,056 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:12:49,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:12:49,062 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:12:49,063 INFO L82 PathProgramCache]: Analyzing trace with hash 1989587644, now seen corresponding path program 1 times [2018-11-18 15:12:49,063 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:12:49,063 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:12:49,063 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:49,063 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:12:49,064 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:49,068 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:12:49,131 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:12:49,131 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:12:49,131 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 15:12:49,132 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:12:49,132 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 15:12:49,132 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:12:49,132 INFO L87 Difference]: Start difference. First operand 207 states and 277 transitions. cyclomatic complexity: 71 Second operand 5 states. [2018-11-18 15:12:49,183 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:12:49,183 INFO L93 Difference]: Finished difference Result 374 states and 496 transitions. [2018-11-18 15:12:49,184 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 15:12:49,184 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 374 states and 496 transitions. [2018-11-18 15:12:49,186 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 333 [2018-11-18 15:12:49,187 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 374 states to 374 states and 496 transitions. [2018-11-18 15:12:49,187 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 374 [2018-11-18 15:12:49,187 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 374 [2018-11-18 15:12:49,187 INFO L73 IsDeterministic]: Start isDeterministic. Operand 374 states and 496 transitions. [2018-11-18 15:12:49,188 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:12:49,188 INFO L705 BuchiCegarLoop]: Abstraction has 374 states and 496 transitions. [2018-11-18 15:12:49,188 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 374 states and 496 transitions. [2018-11-18 15:12:49,190 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 374 to 210. [2018-11-18 15:12:49,190 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 210 states. [2018-11-18 15:12:49,191 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 210 states to 210 states and 276 transitions. [2018-11-18 15:12:49,191 INFO L728 BuchiCegarLoop]: Abstraction has 210 states and 276 transitions. [2018-11-18 15:12:49,191 INFO L608 BuchiCegarLoop]: Abstraction has 210 states and 276 transitions. [2018-11-18 15:12:49,191 INFO L442 BuchiCegarLoop]: ======== Iteration 9============ [2018-11-18 15:12:49,191 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 210 states and 276 transitions. [2018-11-18 15:12:49,192 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 169 [2018-11-18 15:12:49,192 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:12:49,193 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:12:49,193 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:12:49,193 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:12:49,194 INFO L794 eck$LassoCheckResult]: Stem: 4074#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 3948#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 3949#L481 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 4055#L204 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4056#L211 assume 1 == ~m_i~0;~m_st~0 := 0; 4136#L211-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4110#L216-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4111#L221-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4083#L324 assume !(0 == ~M_E~0); 4084#L324-2 assume !(0 == ~T1_E~0); 3956#L329-1 assume !(0 == ~T2_E~0); 3957#L334-1 assume !(0 == ~E_1~0); 4005#L339-1 assume !(0 == ~E_2~0); 4031#L344-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4131#L146 assume !(1 == ~m_pc~0); 3993#L146-2 is_master_triggered_~__retres1~0 := 0; 4126#L157 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3994#L158 activate_threads_#t~ret4 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 3991#L395 assume !(0 != activate_threads_~tmp~1); 3952#L395-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3953#L165 assume !(1 == ~t1_pc~0); 4065#L165-2 is_transmit1_triggered_~__retres1~1 := 0; 4067#L176 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4068#L177 activate_threads_#t~ret5 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 4107#L403 assume !(0 != activate_threads_~tmp___0~0); 4108#L403-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4112#L184 assume !(1 == ~t2_pc~0); 4043#L184-2 is_transmit2_triggered_~__retres1~2 := 0; 4044#L195 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4046#L196 activate_threads_#t~ret6 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 4012#L411 assume !(0 != activate_threads_~tmp___1~0); 4000#L411-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4001#L357 assume !(1 == ~M_E~0); 4085#L357-2 assume !(1 == ~T1_E~0); 3950#L362-1 assume !(1 == ~T2_E~0); 3951#L367-1 assume !(1 == ~E_1~0); 4002#L372-1 assume !(1 == ~E_2~0); 4025#L377-1 assume { :end_inline_reset_delta_events } true; 4082#L518-3 [2018-11-18 15:12:49,194 INFO L796 eck$LassoCheckResult]: Loop: 4082#L518-3 assume true; 4121#L518-1 assume !false; 4095#L519 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 3944#L299 assume true; 4092#L261-1 assume !false; 4016#L262 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 4017#L234 assume !(0 == ~m_st~0); 4115#L238 assume !(0 == ~t1_st~0); 4070#L242 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; 4071#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 4138#L252 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 4137#L266 assume !(0 != eval_~tmp~0); 4059#L314 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 4053#L204-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 4054#L324-3 assume !(0 == ~M_E~0); 4087#L324-5 assume !(0 == ~T1_E~0); 3960#L329-3 assume !(0 == ~T2_E~0); 3961#L334-3 assume !(0 == ~E_1~0); 4007#L339-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4040#L344-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4021#L146-9 assume !(1 == ~m_pc~0); 3973#L146-11 is_master_triggered_~__retres1~0 := 0; 4020#L157-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3974#L158-3 activate_threads_#t~ret4 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 3935#L395-9 assume !(0 != activate_threads_~tmp~1); 3936#L395-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3945#L165-9 assume !(1 == ~t1_pc~0); 4048#L165-11 is_transmit1_triggered_~__retres1~1 := 0; 4049#L176-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4077#L177-3 activate_threads_#t~ret5 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 4106#L403-9 assume !(0 != activate_threads_~tmp___0~0); 4093#L403-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4094#L184-9 assume 1 == ~t2_pc~0; 4027#L185-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4028#L195-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4030#L196-3 activate_threads_#t~ret6 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 3996#L411-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3997#L411-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3998#L357-3 assume !(1 == ~M_E~0); 4086#L357-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3958#L362-3 assume !(1 == ~T2_E~0); 3959#L367-3 assume !(1 == ~E_1~0); 4006#L372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4036#L377-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 4133#L234-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 4014#L251-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 3933#L252-1 start_simulation_#t~ret8 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 3934#L537 assume !(0 == start_simulation_~tmp~3); 4100#L537-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret7, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 4130#L234-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 4045#L251-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 3929#L252-2 stop_simulation_#t~ret7 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret7;havoc stop_simulation_#t~ret7; 3930#L492 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 4009#L499 stop_simulation_#res := stop_simulation_~__retres2~0; 4010#L500 start_simulation_#t~ret9 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 4081#L550 assume !(0 != start_simulation_~tmp___0~1); 4082#L518-3 [2018-11-18 15:12:49,194 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:12:49,194 INFO L82 PathProgramCache]: Analyzing trace with hash -148511807, now seen corresponding path program 4 times [2018-11-18 15:12:49,194 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:12:49,194 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:12:49,195 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:49,195 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:12:49,195 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:49,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:12:49,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:12:49,205 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:12:49,205 INFO L82 PathProgramCache]: Analyzing trace with hash -2030620038, now seen corresponding path program 1 times [2018-11-18 15:12:49,205 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:12:49,205 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:12:49,206 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:49,206 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:12:49,206 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:49,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:12:49,233 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:12:49,233 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:12:49,233 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:12:49,234 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:12:49,234 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:12:49,234 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:12:49,234 INFO L87 Difference]: Start difference. First operand 210 states and 276 transitions. cyclomatic complexity: 67 Second operand 3 states. [2018-11-18 15:12:49,284 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:12:49,284 INFO L93 Difference]: Finished difference Result 289 states and 375 transitions. [2018-11-18 15:12:49,285 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:12:49,285 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 289 states and 375 transitions. [2018-11-18 15:12:49,287 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 248 [2018-11-18 15:12:49,288 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 289 states to 289 states and 375 transitions. [2018-11-18 15:12:49,288 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 289 [2018-11-18 15:12:49,288 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 289 [2018-11-18 15:12:49,288 INFO L73 IsDeterministic]: Start isDeterministic. Operand 289 states and 375 transitions. [2018-11-18 15:12:49,289 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:12:49,289 INFO L705 BuchiCegarLoop]: Abstraction has 289 states and 375 transitions. [2018-11-18 15:12:49,289 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 289 states and 375 transitions. [2018-11-18 15:12:49,292 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 289 to 289. [2018-11-18 15:12:49,292 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 289 states. [2018-11-18 15:12:49,293 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 289 states to 289 states and 375 transitions. [2018-11-18 15:12:49,293 INFO L728 BuchiCegarLoop]: Abstraction has 289 states and 375 transitions. [2018-11-18 15:12:49,293 INFO L608 BuchiCegarLoop]: Abstraction has 289 states and 375 transitions. [2018-11-18 15:12:49,293 INFO L442 BuchiCegarLoop]: ======== Iteration 10============ [2018-11-18 15:12:49,293 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 289 states and 375 transitions. [2018-11-18 15:12:49,295 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 248 [2018-11-18 15:12:49,295 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:12:49,295 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:12:49,295 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:12:49,296 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:12:49,296 INFO L794 eck$LassoCheckResult]: Stem: 4577#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 4453#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 4454#L481 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 4559#L204 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4560#L211 assume 1 == ~m_i~0;~m_st~0 := 0; 4641#L211-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4615#L216-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4616#L221-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4587#L324 assume !(0 == ~M_E~0); 4588#L324-2 assume !(0 == ~T1_E~0); 4459#L329-1 assume !(0 == ~T2_E~0); 4460#L334-1 assume !(0 == ~E_1~0); 4509#L339-1 assume !(0 == ~E_2~0); 4534#L344-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4636#L146 assume !(1 == ~m_pc~0); 4497#L146-2 is_master_triggered_~__retres1~0 := 0; 4631#L157 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4498#L158 activate_threads_#t~ret4 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 4494#L395 assume !(0 != activate_threads_~tmp~1); 4455#L395-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4456#L165 assume !(1 == ~t1_pc~0); 4569#L165-2 is_transmit1_triggered_~__retres1~1 := 0; 4570#L176 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4571#L177 activate_threads_#t~ret5 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 4612#L403 assume !(0 != activate_threads_~tmp___0~0); 4613#L403-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4617#L184 assume !(1 == ~t2_pc~0); 4547#L184-2 is_transmit2_triggered_~__retres1~2 := 0; 4548#L195 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4550#L196 activate_threads_#t~ret6 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 4516#L411 assume !(0 != activate_threads_~tmp___1~0); 4504#L411-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4505#L357 assume !(1 == ~M_E~0); 4589#L357-2 assume !(1 == ~T1_E~0); 4457#L362-1 assume !(1 == ~T2_E~0); 4458#L367-1 assume !(1 == ~E_1~0); 4506#L372-1 assume !(1 == ~E_2~0); 4529#L377-1 assume { :end_inline_reset_delta_events } true; 4639#L518-3 [2018-11-18 15:12:49,296 INFO L796 eck$LassoCheckResult]: Loop: 4639#L518-3 assume true; 4658#L518-1 assume !false; 4655#L519 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 4651#L299 assume true; 4650#L261-1 assume !false; 4649#L262 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 4648#L234 assume !(0 == ~m_st~0); 4620#L238 assume !(0 == ~t1_st~0); 4574#L242 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; 4575#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 4643#L252 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 4642#L266 assume !(0 != eval_~tmp~0); 4563#L314 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 4557#L204-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 4558#L324-3 assume !(0 == ~M_E~0); 4591#L324-5 assume !(0 == ~T1_E~0); 4465#L329-3 assume !(0 == ~T2_E~0); 4466#L334-3 assume !(0 == ~E_1~0); 4511#L339-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4544#L344-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4525#L146-9 assume !(1 == ~m_pc~0); 4477#L146-11 is_master_triggered_~__retres1~0 := 0; 4524#L157-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4478#L158-3 activate_threads_#t~ret4 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 4440#L395-9 assume !(0 != activate_threads_~tmp~1); 4441#L395-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4450#L165-9 assume !(1 == ~t1_pc~0); 4552#L165-11 is_transmit1_triggered_~__retres1~1 := 0; 4553#L176-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4581#L177-3 activate_threads_#t~ret5 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 4611#L403-9 assume !(0 != activate_threads_~tmp___0~0); 4597#L403-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4598#L184-9 assume 1 == ~t2_pc~0; 4531#L185-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4532#L195-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4535#L196-3 activate_threads_#t~ret6 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 4500#L411-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4501#L411-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4502#L357-3 assume !(1 == ~M_E~0); 4590#L357-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4463#L362-3 assume !(1 == ~T2_E~0); 4464#L367-3 assume !(1 == ~E_1~0); 4510#L372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4540#L377-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 4638#L234-1 assume !(0 == ~m_st~0); 4618#L238-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~3 := 1; 4518#L251-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 4438#L252-1 start_simulation_#t~ret8 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 4439#L537 assume 0 == start_simulation_~tmp~3;start_simulation_~kernel_st~0 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 4630#L437 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4522#L146-12 assume 1 == ~m_pc~0; 4469#L147-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 4470#L157-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4722#L158-4 activate_threads_#t~ret4 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 4721#L395-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4720#L395-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4719#L165-12 assume !(1 == ~t1_pc~0); 4717#L165-14 is_transmit1_triggered_~__retres1~1 := 0; 4716#L176-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4715#L177-4 activate_threads_#t~ret5 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 4712#L403-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4710#L403-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4708#L184-12 assume 1 == ~t2_pc~0; 4705#L185-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4703#L195-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4701#L196-4 activate_threads_#t~ret6 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 4698#L411-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4696#L411-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 4694#L444 assume 1 == ~M_E~0;~M_E~0 := 2; 4692#L444-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4690#L449-1 assume !(1 == ~T2_E~0); 4688#L454-1 assume !(1 == ~E_1~0); 4686#L459-1 assume 1 == ~E_2~0;~E_2~0 := 2; 4683#L464-1 assume { :end_inline_reset_time_events } true; 4681#L537-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret7, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 4679#L234-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 4677#L251-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 4675#L252-2 stop_simulation_#t~ret7 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret7;havoc stop_simulation_#t~ret7; 4674#L492 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 4670#L499 stop_simulation_#res := stop_simulation_~__retres2~0; 4668#L500 start_simulation_#t~ret9 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 4665#L550 assume !(0 != start_simulation_~tmp___0~1); 4639#L518-3 [2018-11-18 15:12:49,297 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:12:49,297 INFO L82 PathProgramCache]: Analyzing trace with hash -148511807, now seen corresponding path program 5 times [2018-11-18 15:12:49,297 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:12:49,302 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:12:49,303 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:49,303 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:12:49,303 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:49,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:12:49,317 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:12:49,321 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:12:49,321 INFO L82 PathProgramCache]: Analyzing trace with hash 992140466, now seen corresponding path program 1 times [2018-11-18 15:12:49,322 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:12:49,322 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:12:49,322 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:49,322 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:12:49,322 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:49,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:12:49,350 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:12:49,350 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:12:49,350 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:12:49,350 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:12:49,350 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:12:49,350 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:12:49,351 INFO L87 Difference]: Start difference. First operand 289 states and 375 transitions. cyclomatic complexity: 87 Second operand 3 states. [2018-11-18 15:12:49,405 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:12:49,405 INFO L93 Difference]: Finished difference Result 509 states and 654 transitions. [2018-11-18 15:12:49,406 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:12:49,406 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 509 states and 654 transitions. [2018-11-18 15:12:49,410 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 433 [2018-11-18 15:12:49,412 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 509 states to 509 states and 654 transitions. [2018-11-18 15:12:49,412 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 509 [2018-11-18 15:12:49,412 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 509 [2018-11-18 15:12:49,413 INFO L73 IsDeterministic]: Start isDeterministic. Operand 509 states and 654 transitions. [2018-11-18 15:12:49,413 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:12:49,413 INFO L705 BuchiCegarLoop]: Abstraction has 509 states and 654 transitions. [2018-11-18 15:12:49,414 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 509 states and 654 transitions. [2018-11-18 15:12:49,424 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 509 to 485. [2018-11-18 15:12:49,424 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 485 states. [2018-11-18 15:12:49,425 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 485 states to 485 states and 624 transitions. [2018-11-18 15:12:49,425 INFO L728 BuchiCegarLoop]: Abstraction has 485 states and 624 transitions. [2018-11-18 15:12:49,425 INFO L608 BuchiCegarLoop]: Abstraction has 485 states and 624 transitions. [2018-11-18 15:12:49,425 INFO L442 BuchiCegarLoop]: ======== Iteration 11============ [2018-11-18 15:12:49,425 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 485 states and 624 transitions. [2018-11-18 15:12:49,427 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 409 [2018-11-18 15:12:49,427 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:12:49,427 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:12:49,428 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:12:49,428 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:12:49,429 INFO L794 eck$LassoCheckResult]: Stem: 5396#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 5257#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 5258#L481 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 5376#L204 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5377#L211 assume 1 == ~m_i~0;~m_st~0 := 0; 5496#L211-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 5497#L216-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5706#L221-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5705#L324 assume !(0 == ~M_E~0); 5704#L324-2 assume !(0 == ~T1_E~0); 5703#L329-1 assume !(0 == ~T2_E~0); 5702#L334-1 assume !(0 == ~E_1~0); 5701#L339-1 assume !(0 == ~E_2~0); 5700#L344-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5623#L146 assume !(1 == ~m_pc~0); 5621#L146-2 is_master_triggered_~__retres1~0 := 0; 5620#L157 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5619#L158 activate_threads_#t~ret4 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 5618#L395 assume !(0 != activate_threads_~tmp~1); 5617#L395-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5616#L165 assume !(1 == ~t1_pc~0); 5404#L165-2 is_transmit1_triggered_~__retres1~1 := 0; 5387#L176 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5388#L177 activate_threads_#t~ret5 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 5440#L403 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5441#L403-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5605#L184 assume !(1 == ~t2_pc~0); 5602#L184-2 is_transmit2_triggered_~__retres1~2 := 0; 5600#L195 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5598#L196 activate_threads_#t~ret6 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 5596#L411 assume !(0 != activate_threads_~tmp___1~0); 5594#L411-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5592#L357 assume !(1 == ~M_E~0); 5590#L357-2 assume !(1 == ~T1_E~0); 5588#L362-1 assume !(1 == ~T2_E~0); 5586#L367-1 assume !(1 == ~E_1~0); 5551#L372-1 assume !(1 == ~E_2~0); 5548#L377-1 assume { :end_inline_reset_delta_events } true; 5546#L518-3 [2018-11-18 15:12:49,429 INFO L796 eck$LassoCheckResult]: Loop: 5546#L518-3 assume true; 5545#L518-1 assume !false; 5524#L519 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 5520#L299 assume true; 5519#L261-1 assume !false; 5518#L262 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 5516#L234 assume !(0 == ~m_st~0); 5517#L238 assume !(0 == ~t1_st~0); 5392#L242 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; 5393#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 5502#L252 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 5500#L266 assume !(0 != eval_~tmp~0); 5382#L314 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 5374#L204-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 5375#L324-3 assume !(0 == ~M_E~0); 5415#L324-5 assume !(0 == ~T1_E~0); 5269#L329-3 assume !(0 == ~T2_E~0); 5270#L334-3 assume !(0 == ~E_1~0); 5320#L339-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5360#L344-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5339#L146-9 assume !(1 == ~m_pc~0); 5283#L146-11 is_master_triggered_~__retres1~0 := 0; 5338#L157-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5284#L158-3 activate_threads_#t~ret4 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 5244#L395-9 assume !(0 != activate_threads_~tmp~1); 5245#L395-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5254#L165-9 assume !(1 == ~t1_pc~0); 5369#L165-11 is_transmit1_triggered_~__retres1~1 := 0; 5370#L176-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5403#L177-3 activate_threads_#t~ret5 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 5438#L403-9 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5439#L403-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5511#L184-9 assume 1 == ~t2_pc~0; 5509#L185-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5508#L195-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5349#L196-3 activate_threads_#t~ret6 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 5350#L411-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 5310#L411-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5311#L357-3 assume !(1 == ~M_E~0); 5414#L357-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5267#L362-3 assume !(1 == ~T2_E~0); 5268#L367-3 assume !(1 == ~E_1~0); 5319#L372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5503#L377-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 5479#L234-1 assume !(0 == ~m_st~0); 5480#L238-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~3 := 1; 5330#L251-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 5331#L252-1 start_simulation_#t~ret8 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 5468#L537 assume 0 == start_simulation_~tmp~3;start_simulation_~kernel_st~0 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 5469#L437 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5649#L146-12 assume 1 == ~m_pc~0; 5274#L147-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 5275#L157-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5681#L158-4 activate_threads_#t~ret4 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 5678#L395-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 5676#L395-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5675#L165-12 assume !(1 == ~t1_pc~0); 5673#L165-14 is_transmit1_triggered_~__retres1~1 := 0; 5671#L176-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5670#L177-4 activate_threads_#t~ret5 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 5669#L403-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5637#L403-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5668#L184-12 assume 1 == ~t2_pc~0; 5666#L185-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5665#L195-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5614#L196-4 activate_threads_#t~ret6 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 5613#L411-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 5611#L411-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 5609#L444 assume 1 == ~M_E~0;~M_E~0 := 2; 5607#L444-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5606#L449-1 assume !(1 == ~T2_E~0); 5604#L454-1 assume !(1 == ~E_1~0); 5601#L459-1 assume 1 == ~E_2~0;~E_2~0 := 2; 5599#L464-1 assume { :end_inline_reset_time_events } true; 5597#L537-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret7, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 5595#L234-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 5593#L251-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 5591#L252-2 stop_simulation_#t~ret7 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret7;havoc stop_simulation_#t~ret7; 5589#L492 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5587#L499 stop_simulation_#res := stop_simulation_~__retres2~0; 5552#L500 start_simulation_#t~ret9 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 5549#L550 assume !(0 != start_simulation_~tmp___0~1); 5546#L518-3 [2018-11-18 15:12:49,429 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:12:49,429 INFO L82 PathProgramCache]: Analyzing trace with hash 790218885, now seen corresponding path program 1 times [2018-11-18 15:12:49,429 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:12:49,430 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:12:49,430 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:49,430 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:12:49,430 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:49,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:12:49,447 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:12:49,447 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:12:49,447 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:12:49,447 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 15:12:49,448 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:12:49,448 INFO L82 PathProgramCache]: Analyzing trace with hash -546199564, now seen corresponding path program 1 times [2018-11-18 15:12:49,448 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:12:49,448 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:12:49,448 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:49,449 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:12:49,450 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:49,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:12:49,485 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:12:49,486 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:12:49,486 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:12:49,486 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:12:49,486 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:12:49,486 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:12:49,486 INFO L87 Difference]: Start difference. First operand 485 states and 624 transitions. cyclomatic complexity: 140 Second operand 3 states. [2018-11-18 15:12:49,492 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:12:49,492 INFO L93 Difference]: Finished difference Result 450 states and 578 transitions. [2018-11-18 15:12:49,493 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:12:49,493 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 450 states and 578 transitions. [2018-11-18 15:12:49,495 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 409 [2018-11-18 15:12:49,496 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 450 states to 450 states and 578 transitions. [2018-11-18 15:12:49,496 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 450 [2018-11-18 15:12:49,497 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 450 [2018-11-18 15:12:49,497 INFO L73 IsDeterministic]: Start isDeterministic. Operand 450 states and 578 transitions. [2018-11-18 15:12:49,497 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:12:49,498 INFO L705 BuchiCegarLoop]: Abstraction has 450 states and 578 transitions. [2018-11-18 15:12:49,498 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 450 states and 578 transitions. [2018-11-18 15:12:49,503 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 450 to 450. [2018-11-18 15:12:49,503 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 450 states. [2018-11-18 15:12:49,504 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 450 states to 450 states and 578 transitions. [2018-11-18 15:12:49,504 INFO L728 BuchiCegarLoop]: Abstraction has 450 states and 578 transitions. [2018-11-18 15:12:49,504 INFO L608 BuchiCegarLoop]: Abstraction has 450 states and 578 transitions. [2018-11-18 15:12:49,504 INFO L442 BuchiCegarLoop]: ======== Iteration 12============ [2018-11-18 15:12:49,504 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 450 states and 578 transitions. [2018-11-18 15:12:49,506 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 409 [2018-11-18 15:12:49,506 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:12:49,506 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:12:49,507 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:12:49,507 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:12:49,507 INFO L794 eck$LassoCheckResult]: Stem: 6334#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 6199#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 6200#L481 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 6314#L204 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6315#L211 assume 1 == ~m_i~0;~m_st~0 := 0; 6432#L211-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6383#L216-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6384#L221-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6349#L324 assume !(0 == ~M_E~0); 6350#L324-2 assume !(0 == ~T1_E~0); 6205#L329-1 assume !(0 == ~T2_E~0); 6206#L334-1 assume !(0 == ~E_1~0); 6257#L339-1 assume !(0 == ~E_2~0); 6285#L344-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6415#L146 assume !(1 == ~m_pc~0); 6243#L146-2 is_master_triggered_~__retres1~0 := 0; 6409#L157 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6244#L158 activate_threads_#t~ret4 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 6240#L395 assume !(0 != activate_threads_~tmp~1); 6201#L395-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6202#L165 assume !(1 == ~t1_pc~0); 6324#L165-2 is_transmit1_triggered_~__retres1~1 := 0; 6325#L176 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6326#L177 activate_threads_#t~ret5 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 6380#L403 assume !(0 != activate_threads_~tmp___0~0); 6381#L403-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6385#L184 assume !(1 == ~t2_pc~0); 6302#L184-2 is_transmit2_triggered_~__retres1~2 := 0; 6303#L195 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6304#L196 activate_threads_#t~ret6 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 6266#L411 assume !(0 != activate_threads_~tmp___1~0); 6252#L411-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6253#L357 assume !(1 == ~M_E~0); 6351#L357-2 assume !(1 == ~T1_E~0); 6203#L362-1 assume !(1 == ~T2_E~0); 6204#L367-1 assume !(1 == ~E_1~0); 6254#L372-1 assume !(1 == ~E_2~0); 6279#L377-1 assume { :end_inline_reset_delta_events } true; 6421#L518-3 [2018-11-18 15:12:49,507 INFO L796 eck$LassoCheckResult]: Loop: 6421#L518-3 assume true; 6489#L518-1 assume !false; 6481#L519 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 6459#L299 assume true; 6460#L261-1 assume !false; 6455#L262 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 6456#L234 assume !(0 == ~m_st~0); 6424#L238 assume !(0 == ~t1_st~0); 6330#L242 assume !(0 == ~t2_st~0);exists_runnable_thread_~__retres1~3 := 0; 6332#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 6437#L252 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 6436#L266 assume !(0 != eval_~tmp~0); 6318#L314 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 6312#L204-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 6313#L324-3 assume !(0 == ~M_E~0); 6353#L324-5 assume !(0 == ~T1_E~0); 6211#L329-3 assume !(0 == ~T2_E~0); 6212#L334-3 assume !(0 == ~E_1~0); 6260#L339-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6297#L344-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6275#L146-9 assume !(1 == ~m_pc~0); 6223#L146-11 is_master_triggered_~__retres1~0 := 0; 6274#L157-3 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6224#L158-3 activate_threads_#t~ret4 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 6186#L395-9 assume !(0 != activate_threads_~tmp~1); 6187#L395-11 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6196#L165-9 assume !(1 == ~t1_pc~0); 6307#L165-11 is_transmit1_triggered_~__retres1~1 := 0; 6308#L176-3 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6341#L177-3 activate_threads_#t~ret5 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 6378#L403-9 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 6379#L403-11 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6420#L184-9 assume 1 == ~t2_pc~0; 6282#L185-3 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 6283#L195-3 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6286#L196-3 activate_threads_#t~ret6 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 6287#L411-9 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 6249#L411-11 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6250#L357-3 assume !(1 == ~M_E~0); 6352#L357-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6442#L362-3 assume !(1 == ~T2_E~0); 6441#L367-3 assume !(1 == ~E_1~0); 6292#L372-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6293#L377-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 6417#L234-1 assume !(0 == ~m_st~0); 6418#L238-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~3 := 1; 6438#L251-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 6559#L252-1 start_simulation_#t~ret8 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret8;havoc start_simulation_#t~ret8; 6557#L537 assume 0 == start_simulation_~tmp~3;start_simulation_~kernel_st~0 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 6433#L437 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6272#L146-12 assume 1 == ~m_pc~0; 6215#L147-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 6216#L157-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6555#L158-4 activate_threads_#t~ret4 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 6552#L395-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 6550#L395-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6548#L165-12 assume !(1 == ~t1_pc~0); 6545#L165-14 is_transmit1_triggered_~__retres1~1 := 0; 6543#L176-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6540#L177-4 activate_threads_#t~ret5 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 6538#L403-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 6534#L403-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6535#L184-12 assume 1 == ~t2_pc~0; 6530#L185-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 6528#L195-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6525#L196-4 activate_threads_#t~ret6 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 6523#L411-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 6521#L411-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 6519#L444 assume 1 == ~M_E~0;~M_E~0 := 2; 6517#L444-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6515#L449-1 assume !(1 == ~T2_E~0); 6513#L454-1 assume !(1 == ~E_1~0); 6511#L459-1 assume 1 == ~E_2~0;~E_2~0 := 2; 6509#L464-1 assume { :end_inline_reset_time_events } true; 6507#L537-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret7, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 6504#L234-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 6502#L251-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 6500#L252-2 stop_simulation_#t~ret7 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret7;havoc stop_simulation_#t~ret7; 6498#L492 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 6496#L499 stop_simulation_#res := stop_simulation_~__retres2~0; 6494#L500 start_simulation_#t~ret9 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret9;havoc start_simulation_#t~ret9; 6492#L550 assume !(0 != start_simulation_~tmp___0~1); 6421#L518-3 [2018-11-18 15:12:49,507 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:12:49,507 INFO L82 PathProgramCache]: Analyzing trace with hash -148511807, now seen corresponding path program 6 times [2018-11-18 15:12:49,507 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:12:49,508 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:12:49,508 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:49,508 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:12:49,508 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:49,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:12:49,513 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:12:49,516 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:12:49,516 INFO L82 PathProgramCache]: Analyzing trace with hash -546199564, now seen corresponding path program 2 times [2018-11-18 15:12:49,516 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:12:49,516 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:12:49,517 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:49,517 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:12:49,517 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:49,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:12:49,545 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:12:49,545 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:12:49,545 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:12:49,546 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:12:49,546 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:12:49,546 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:12:49,546 INFO L87 Difference]: Start difference. First operand 450 states and 578 transitions. cyclomatic complexity: 129 Second operand 3 states. [2018-11-18 15:12:49,626 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:12:49,626 INFO L93 Difference]: Finished difference Result 724 states and 926 transitions. [2018-11-18 15:12:49,627 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:12:49,627 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 724 states and 926 transitions. [2018-11-18 15:12:49,630 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 675 [2018-11-18 15:12:49,632 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 724 states to 724 states and 926 transitions. [2018-11-18 15:12:49,632 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 724 [2018-11-18 15:12:49,633 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 724 [2018-11-18 15:12:49,633 INFO L73 IsDeterministic]: Start isDeterministic. Operand 724 states and 926 transitions. [2018-11-18 15:12:49,634 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:12:49,634 INFO L705 BuchiCegarLoop]: Abstraction has 724 states and 926 transitions. [2018-11-18 15:12:49,635 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 724 states and 926 transitions. [2018-11-18 15:12:49,642 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 724 to 718. [2018-11-18 15:12:49,642 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 718 states. [2018-11-18 15:12:49,644 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 718 states to 718 states and 920 transitions. [2018-11-18 15:12:49,644 INFO L728 BuchiCegarLoop]: Abstraction has 718 states and 920 transitions. [2018-11-18 15:12:49,644 INFO L608 BuchiCegarLoop]: Abstraction has 718 states and 920 transitions. [2018-11-18 15:12:49,644 INFO L442 BuchiCegarLoop]: ======== Iteration 13============ [2018-11-18 15:12:49,644 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 718 states and 920 transitions. [2018-11-18 15:12:49,646 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 669 [2018-11-18 15:12:49,647 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:12:49,647 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:12:49,647 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:12:49,647 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:12:49,647 INFO L794 eck$LassoCheckResult]: Stem: 7512#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 7380#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 7381#L481 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 7493#L204 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7494#L211 assume 1 == ~m_i~0;~m_st~0 := 0; 7617#L211-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7561#L216-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7562#L221-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7523#L324 assume !(0 == ~M_E~0); 7524#L324-2 assume !(0 == ~T1_E~0); 7386#L329-1 assume !(0 == ~T2_E~0); 7387#L334-1 assume !(0 == ~E_1~0); 7434#L339-1 assume !(0 == ~E_2~0); 7463#L344-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7594#L146 assume !(1 == ~m_pc~0); 7586#L146-2 is_master_triggered_~__retres1~0 := 0; 7587#L157 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7423#L158 activate_threads_#t~ret4 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 7422#L395 assume !(0 != activate_threads_~tmp~1); 7382#L395-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7383#L165 assume !(1 == ~t1_pc~0); 7503#L165-2 is_transmit1_triggered_~__retres1~1 := 0; 7504#L176 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7505#L177 activate_threads_#t~ret5 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 7557#L403 assume !(0 != activate_threads_~tmp___0~0); 7558#L403-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7563#L184 assume !(1 == ~t2_pc~0); 7479#L184-2 is_transmit2_triggered_~__retres1~2 := 0; 7480#L195 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7481#L196 activate_threads_#t~ret6 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 7443#L411 assume !(0 != activate_threads_~tmp___1~0); 7429#L411-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7430#L357 assume !(1 == ~M_E~0); 7525#L357-2 assume !(1 == ~T1_E~0); 7384#L362-1 assume !(1 == ~T2_E~0); 7385#L367-1 assume !(1 == ~E_1~0); 7431#L372-1 assume !(1 == ~E_2~0); 7459#L377-1 assume { :end_inline_reset_delta_events } true; 7604#L518-3 assume true; 7761#L518-1 assume !false; 7758#L519 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 7754#L299 [2018-11-18 15:12:49,648 INFO L796 eck$LassoCheckResult]: Loop: 7754#L299 assume true; 7752#L261-1 assume !false; 7750#L262 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 7748#L234 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 7746#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 7734#L252 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 7730#L266 assume 0 != eval_~tmp~0; 7724#L266-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 7719#L274 assume !(0 != eval_~tmp_ndt_1~0); 7707#L271 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 7708#L288 assume !(0 != eval_~tmp_ndt_2~0); 7759#L285 assume !(0 == ~t2_st~0); 7754#L299 [2018-11-18 15:12:49,648 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:12:49,648 INFO L82 PathProgramCache]: Analyzing trace with hash -498764411, now seen corresponding path program 1 times [2018-11-18 15:12:49,648 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:12:49,648 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:12:49,649 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:49,649 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:12:49,649 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:49,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:12:49,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:12:49,657 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:12:49,658 INFO L82 PathProgramCache]: Analyzing trace with hash -466793719, now seen corresponding path program 1 times [2018-11-18 15:12:49,658 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:12:49,658 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:12:49,658 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:49,658 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:12:49,659 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:49,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:12:49,666 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:12:49,667 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:12:49,667 INFO L82 PathProgramCache]: Analyzing trace with hash 1685756557, now seen corresponding path program 1 times [2018-11-18 15:12:49,667 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:12:49,667 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:12:49,668 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:49,668 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:12:49,668 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:49,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:12:49,699 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:12:49,699 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:12:49,699 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 15:12:49,755 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:12:49,757 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:12:49,757 INFO L87 Difference]: Start difference. First operand 718 states and 920 transitions. cyclomatic complexity: 205 Second operand 3 states. [2018-11-18 15:12:49,906 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:12:49,906 INFO L93 Difference]: Finished difference Result 1256 states and 1598 transitions. [2018-11-18 15:12:49,908 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:12:49,908 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1256 states and 1598 transitions. [2018-11-18 15:12:49,913 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1201 [2018-11-18 15:12:49,917 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1256 states to 1256 states and 1598 transitions. [2018-11-18 15:12:49,917 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1256 [2018-11-18 15:12:49,918 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1256 [2018-11-18 15:12:49,918 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1256 states and 1598 transitions. [2018-11-18 15:12:49,919 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:12:49,919 INFO L705 BuchiCegarLoop]: Abstraction has 1256 states and 1598 transitions. [2018-11-18 15:12:49,920 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1256 states and 1598 transitions. [2018-11-18 15:12:49,931 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1256 to 1256. [2018-11-18 15:12:49,931 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1256 states. [2018-11-18 15:12:49,933 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1256 states to 1256 states and 1598 transitions. [2018-11-18 15:12:49,933 INFO L728 BuchiCegarLoop]: Abstraction has 1256 states and 1598 transitions. [2018-11-18 15:12:49,933 INFO L608 BuchiCegarLoop]: Abstraction has 1256 states and 1598 transitions. [2018-11-18 15:12:49,933 INFO L442 BuchiCegarLoop]: ======== Iteration 14============ [2018-11-18 15:12:49,933 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1256 states and 1598 transitions. [2018-11-18 15:12:49,937 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1201 [2018-11-18 15:12:49,937 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:12:49,937 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:12:49,937 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:12:49,938 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:12:49,938 INFO L794 eck$LassoCheckResult]: Stem: 9494#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2; 9361#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~4;havoc main_~__retres1~4;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1; 9362#L481 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8, start_simulation_#t~ret9, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 9473#L204 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9474#L211 assume 1 == ~m_i~0;~m_st~0 := 0; 9587#L211-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9539#L216-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9540#L221-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9505#L324 assume !(0 == ~M_E~0); 9506#L324-2 assume !(0 == ~T1_E~0); 9369#L329-1 assume !(0 == ~T2_E~0); 9370#L334-1 assume !(0 == ~E_1~0); 9417#L339-1 assume !(0 == ~E_2~0); 9446#L344-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret4, activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9575#L146 assume !(1 == ~m_pc~0); 9565#L146-2 is_master_triggered_~__retres1~0 := 0; 9566#L157 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9405#L158 activate_threads_#t~ret4 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret4;havoc activate_threads_#t~ret4; 9404#L395 assume !(0 != activate_threads_~tmp~1); 9363#L395-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9364#L165 assume !(1 == ~t1_pc~0); 9484#L165-2 is_transmit1_triggered_~__retres1~1 := 0; 9487#L176 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9488#L177 activate_threads_#t~ret5 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 9536#L403 assume !(0 != activate_threads_~tmp___0~0); 9537#L403-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9541#L184 assume !(1 == ~t2_pc~0); 9460#L184-2 is_transmit2_triggered_~__retres1~2 := 0; 9461#L195 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9463#L196 activate_threads_#t~ret6 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 9424#L411 assume !(0 != activate_threads_~tmp___1~0); 9412#L411-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9413#L357 assume !(1 == ~M_E~0); 9507#L357-2 assume !(1 == ~T1_E~0); 9365#L362-1 assume !(1 == ~T2_E~0); 9366#L367-1 assume !(1 == ~E_1~0); 9414#L372-1 assume !(1 == ~E_2~0); 9440#L377-1 assume { :end_inline_reset_delta_events } true; 9584#L518-3 assume true; 9988#L518-1 assume !false; 9987#L519 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_~tmp~0;havoc eval_~tmp~0; 9985#L299 [2018-11-18 15:12:49,938 INFO L796 eck$LassoCheckResult]: Loop: 9985#L299 assume true; 9984#L261-1 assume !false; 9983#L262 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~3;havoc exists_runnable_thread_~__retres1~3; 9979#L234 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~3 := 1; 9978#L251 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~3; 9977#L252 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 9976#L266 assume 0 != eval_~tmp~0; 9974#L266-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 9352#L274 assume !(0 != eval_~tmp_ndt_1~0); 9354#L271 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 10064#L288 assume !(0 != eval_~tmp_ndt_2~0); 9989#L285 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 9986#L302 assume !(0 != eval_~tmp_ndt_3~0); 9985#L299 [2018-11-18 15:12:49,938 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:12:49,938 INFO L82 PathProgramCache]: Analyzing trace with hash -498764411, now seen corresponding path program 2 times [2018-11-18 15:12:49,938 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:12:49,938 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:12:49,939 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:49,939 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:12:49,939 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:49,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:12:49,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:12:49,948 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:12:49,948 INFO L82 PathProgramCache]: Analyzing trace with hash -1585704182, now seen corresponding path program 1 times [2018-11-18 15:12:49,948 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:12:49,948 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:12:49,948 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:49,948 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:12:49,949 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:49,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:12:49,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:12:49,952 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:12:49,953 INFO L82 PathProgramCache]: Analyzing trace with hash 718844934, now seen corresponding path program 1 times [2018-11-18 15:12:49,953 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:12:49,953 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:12:49,953 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:49,953 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:12:49,953 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:12:49,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:12:49,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:12:50,232 WARN L180 SmtUtils]: Spent 201.00 ms on a formula simplification. DAG size of input: 95 DAG size of output: 66 [2018-11-18 15:12:50,302 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 18.11 03:12:50 BoogieIcfgContainer [2018-11-18 15:12:50,302 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2018-11-18 15:12:50,302 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-18 15:12:50,302 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-18 15:12:50,302 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-18 15:12:50,303 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 03:12:48" (3/4) ... [2018-11-18 15:12:50,305 INFO L141 WitnessPrinter]: Generating witness for non-termination counterexample [2018-11-18 15:12:50,348 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_f1ace5c2-b60b-4914-a76b-55dab06ad999/bin-2019/uautomizer/witness.graphml [2018-11-18 15:12:50,348 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-18 15:12:50,349 INFO L168 Benchmark]: Toolchain (without parser) took 3115.19 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 140.5 MB). Free memory was 958.2 MB in the beginning and 921.9 MB in the end (delta: 36.3 MB). Peak memory consumption was 176.8 MB. Max. memory is 11.5 GB. [2018-11-18 15:12:50,349 INFO L168 Benchmark]: CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 985.6 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-18 15:12:50,350 INFO L168 Benchmark]: CACSL2BoogieTranslator took 208.33 ms. Allocated memory is still 1.0 GB. Free memory was 958.2 MB in the beginning and 942.1 MB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. [2018-11-18 15:12:50,350 INFO L168 Benchmark]: Boogie Procedure Inliner took 67.46 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 140.5 MB). Free memory was 942.1 MB in the beginning and 1.1 GB in the end (delta: -195.7 MB). Peak memory consumption was 14.7 MB. Max. memory is 11.5 GB. [2018-11-18 15:12:50,350 INFO L168 Benchmark]: Boogie Preprocessor took 22.34 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. [2018-11-18 15:12:50,350 INFO L168 Benchmark]: RCFGBuilder took 505.24 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 50.4 MB). Peak memory consumption was 50.4 MB. Max. memory is 11.5 GB. [2018-11-18 15:12:50,351 INFO L168 Benchmark]: BuchiAutomizer took 2262.87 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 925.4 MB in the end (delta: 159.4 MB). Peak memory consumption was 159.4 MB. Max. memory is 11.5 GB. [2018-11-18 15:12:50,351 INFO L168 Benchmark]: Witness Printer took 46.22 ms. Allocated memory is still 1.2 GB. Free memory was 925.4 MB in the beginning and 921.9 MB in the end (delta: 3.5 MB). Peak memory consumption was 3.5 MB. Max. memory is 11.5 GB. [2018-11-18 15:12:50,352 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 985.6 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 208.33 ms. Allocated memory is still 1.0 GB. Free memory was 958.2 MB in the beginning and 942.1 MB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 67.46 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 140.5 MB). Free memory was 942.1 MB in the beginning and 1.1 GB in the end (delta: -195.7 MB). Peak memory consumption was 14.7 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 22.34 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. * RCFGBuilder took 505.24 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 50.4 MB). Peak memory consumption was 50.4 MB. Max. memory is 11.5 GB. * BuchiAutomizer took 2262.87 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 925.4 MB in the end (delta: 159.4 MB). Peak memory consumption was 159.4 MB. Max. memory is 11.5 GB. * Witness Printer took 46.22 ms. Allocated memory is still 1.2 GB. Free memory was 925.4 MB in the beginning and 921.9 MB in the end (delta: 3.5 MB). Peak memory consumption was 3.5 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 13 terminating modules (13 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.13 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 1256 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 2.2s and 14 iterations. TraceHistogramMax:1. Analysis of lassos took 1.2s. Construction of modules took 0.4s. Büchi inclusion checks took 0.2s. Highest rank in rank-based complementation 0. Minimization of det autom 13. Minimization of nondet autom 0. Automata minimization 0.1s AutomataMinimizationTime, 13 MinimizatonAttempts, 320 StatesRemovedByMinimization, 4 NontrivialMinimizations. Non-live state removal took 0.0s Buchi closure took 0.0s. Biggest automaton had 1256 states and ocurred in iteration 13. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 3847 SDtfs, 3705 SDslu, 2437 SDs, 0 SdLazy, 190 SolverSat, 105 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.4s Time LassoAnalysisResults: nont1 unkn0 SFLI6 SFLT0 conc1 concLT0 SILN0 SILU0 SILI6 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 261]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {\result=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@459ffd32=0, tmp=1, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2ade5404=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7c47c576=0, T2_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3b547b43=0, kernel_st=1, __retres1=0, tmp___0=0, t2_st=0, t1_pc=0, E_2=2, __retres1=1, T1_E=2, \result=0, E_1=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@66f9f51d=0, tmp_ndt_1=0, M_E=2, tmp_ndt_2=0, tmp=0, tmp_ndt_3=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@af957dd=0, __retres1=0, t2_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@523d0a04=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@52ae2471=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@67dab32f=0, t1_st=0, \result=0, t2_pc=0, m_st=0, tmp___1=0, tmp___0=0, tmp=0, __retres1=0, t1_i=1, m_pc=0, \result=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 261]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int m_st ; [L19] int t1_st ; [L20] int t2_st ; [L21] int m_i ; [L22] int t1_i ; [L23] int t2_i ; [L24] int M_E = 2; [L25] int T1_E = 2; [L26] int T2_E = 2; [L27] int E_1 = 2; [L28] int E_2 = 2; [L563] int __retres1 ; [L567] CALL init_model() [L477] m_i = 1 [L478] t1_i = 1 [L479] RET t2_i = 1 [L567] init_model() [L568] CALL start_simulation() [L504] int kernel_st ; [L505] int tmp ; [L506] int tmp___0 ; [L510] kernel_st = 0 [L511] FCALL update_channels() [L512] CALL init_threads() [L211] COND TRUE m_i == 1 [L212] m_st = 0 [L216] COND TRUE t1_i == 1 [L217] t1_st = 0 [L221] COND TRUE t2_i == 1 [L222] RET t2_st = 0 [L512] init_threads() [L513] CALL fire_delta_events() [L324] COND FALSE !(M_E == 0) [L329] COND FALSE !(T1_E == 0) [L334] COND FALSE !(T2_E == 0) [L339] COND FALSE !(E_1 == 0) [L344] COND FALSE, RET !(E_2 == 0) [L513] fire_delta_events() [L514] CALL activate_threads() [L387] int tmp ; [L388] int tmp___0 ; [L389] int tmp___1 ; [L393] CALL, EXPR is_master_triggered() [L143] int __retres1 ; [L146] COND FALSE !(m_pc == 1) [L156] __retres1 = 0 [L158] RET return (__retres1); [L393] EXPR is_master_triggered() [L393] tmp = is_master_triggered() [L395] COND FALSE !(\read(tmp)) [L401] CALL, EXPR is_transmit1_triggered() [L162] int __retres1 ; [L165] COND FALSE !(t1_pc == 1) [L175] __retres1 = 0 [L177] RET return (__retres1); [L401] EXPR is_transmit1_triggered() [L401] tmp___0 = is_transmit1_triggered() [L403] COND FALSE !(\read(tmp___0)) [L409] CALL, EXPR is_transmit2_triggered() [L181] int __retres1 ; [L184] COND FALSE !(t2_pc == 1) [L194] __retres1 = 0 [L196] RET return (__retres1); [L409] EXPR is_transmit2_triggered() [L409] tmp___1 = is_transmit2_triggered() [L411] COND FALSE, RET !(\read(tmp___1)) [L514] activate_threads() [L515] CALL reset_delta_events() [L357] COND FALSE !(M_E == 1) [L362] COND FALSE !(T1_E == 1) [L367] COND FALSE !(T2_E == 1) [L372] COND FALSE !(E_1 == 1) [L377] COND FALSE, RET !(E_2 == 1) [L515] reset_delta_events() [L518] COND TRUE 1 [L521] kernel_st = 1 [L522] CALL eval() [L257] int tmp ; Loop: [L261] COND TRUE 1 [L264] CALL, EXPR exists_runnable_thread() [L231] int __retres1 ; [L234] COND TRUE m_st == 0 [L235] __retres1 = 1 [L252] RET return (__retres1); [L264] EXPR exists_runnable_thread() [L264] tmp = exists_runnable_thread() [L266] COND TRUE \read(tmp) [L271] COND TRUE m_st == 0 [L272] int tmp_ndt_1; [L273] tmp_ndt_1 = __VERIFIER_nondet_int() [L274] COND FALSE !(\read(tmp_ndt_1)) [L285] COND TRUE t1_st == 0 [L286] int tmp_ndt_2; [L287] tmp_ndt_2 = __VERIFIER_nondet_int() [L288] COND FALSE !(\read(tmp_ndt_2)) [L299] COND TRUE t2_st == 0 [L300] int tmp_ndt_3; [L301] tmp_ndt_3 = __VERIFIER_nondet_int() [L302] COND FALSE !(\read(tmp_ndt_3)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...