./Ultimate.py --spec ../../sv-benchmarks/c/Termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.03_false-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 5842f4b8 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_9edd41f0-bb38-47c2-83e2-42ee9941d34f/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_9edd41f0-bb38-47c2-83e2-42ee9941d34f/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_9edd41f0-bb38-47c2-83e2-42ee9941d34f/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_9edd41f0-bb38-47c2-83e2-42ee9941d34f/bin-2019/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.03_false-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_9edd41f0-bb38-47c2-83e2-42ee9941d34f/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_9edd41f0-bb38-47c2-83e2-42ee9941d34f/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 447c919af4e106e36f468570351956f4c77293d2 ................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.1.23-5842f4b [2018-11-18 14:06:27,429 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-18 14:06:27,430 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-18 14:06:27,436 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-18 14:06:27,436 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-18 14:06:27,437 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-18 14:06:27,438 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-18 14:06:27,439 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-18 14:06:27,440 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-18 14:06:27,440 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-18 14:06:27,441 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-18 14:06:27,441 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-18 14:06:27,442 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-18 14:06:27,442 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-18 14:06:27,443 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-18 14:06:27,443 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-18 14:06:27,443 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-18 14:06:27,444 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-18 14:06:27,446 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-18 14:06:27,447 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-18 14:06:27,447 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-18 14:06:27,448 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-18 14:06:27,449 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-18 14:06:27,449 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-18 14:06:27,449 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-18 14:06:27,450 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-18 14:06:27,450 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-18 14:06:27,451 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-18 14:06:27,451 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-18 14:06:27,452 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-18 14:06:27,452 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-18 14:06:27,453 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-18 14:06:27,453 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-18 14:06:27,453 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-18 14:06:27,454 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-18 14:06:27,454 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-18 14:06:27,454 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_9edd41f0-bb38-47c2-83e2-42ee9941d34f/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2018-11-18 14:06:27,463 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-18 14:06:27,463 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-18 14:06:27,464 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-18 14:06:27,464 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-18 14:06:27,464 INFO L133 SettingsManager]: * Use SBE=true [2018-11-18 14:06:27,464 INFO L131 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2018-11-18 14:06:27,465 INFO L133 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2018-11-18 14:06:27,465 INFO L133 SettingsManager]: * Use old map elimination=false [2018-11-18 14:06:27,465 INFO L133 SettingsManager]: * Use external solver (rank synthesis)=false [2018-11-18 14:06:27,465 INFO L133 SettingsManager]: * Use only trivial implications for array writes=true [2018-11-18 14:06:27,465 INFO L133 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2018-11-18 14:06:27,465 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-18 14:06:27,465 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-18 14:06:27,465 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-11-18 14:06:27,466 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-18 14:06:27,466 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-18 14:06:27,466 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-18 14:06:27,466 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2018-11-18 14:06:27,466 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2018-11-18 14:06:27,466 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2018-11-18 14:06:27,466 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-18 14:06:27,467 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-18 14:06:27,467 INFO L133 SettingsManager]: * Assume nondeterminstic values are in range=false [2018-11-18 14:06:27,467 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-18 14:06:27,467 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2018-11-18 14:06:27,467 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-18 14:06:27,467 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-18 14:06:27,467 INFO L133 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2018-11-18 14:06:27,468 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-18 14:06:27,468 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-18 14:06:27,468 INFO L133 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2018-11-18 14:06:27,468 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-11-18 14:06:27,469 INFO L133 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_9edd41f0-bb38-47c2-83e2-42ee9941d34f/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 447c919af4e106e36f468570351956f4c77293d2 [2018-11-18 14:06:27,495 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-18 14:06:27,504 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-18 14:06:27,507 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-18 14:06:27,508 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-18 14:06:27,508 INFO L276 PluginConnector]: CDTParser initialized [2018-11-18 14:06:27,509 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_9edd41f0-bb38-47c2-83e2-42ee9941d34f/bin-2019/uautomizer/../../sv-benchmarks/c/systemc/transmitter.03_false-unreach-call_false-termination.cil.c [2018-11-18 14:06:27,552 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_9edd41f0-bb38-47c2-83e2-42ee9941d34f/bin-2019/uautomizer/data/0f57f8077/d70f2d46034742cf9ee4a7e21b3dfaba/FLAGd4619eaaf [2018-11-18 14:06:27,968 INFO L307 CDTParser]: Found 1 translation units. [2018-11-18 14:06:27,968 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_9edd41f0-bb38-47c2-83e2-42ee9941d34f/sv-benchmarks/c/systemc/transmitter.03_false-unreach-call_false-termination.cil.c [2018-11-18 14:06:27,974 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_9edd41f0-bb38-47c2-83e2-42ee9941d34f/bin-2019/uautomizer/data/0f57f8077/d70f2d46034742cf9ee4a7e21b3dfaba/FLAGd4619eaaf [2018-11-18 14:06:27,985 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_9edd41f0-bb38-47c2-83e2-42ee9941d34f/bin-2019/uautomizer/data/0f57f8077/d70f2d46034742cf9ee4a7e21b3dfaba [2018-11-18 14:06:27,988 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-18 14:06:27,989 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-18 14:06:27,990 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-18 14:06:27,990 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-18 14:06:27,993 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-18 14:06:27,994 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 02:06:27" (1/1) ... [2018-11-18 14:06:27,996 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@482e4025 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 02:06:27, skipping insertion in model container [2018-11-18 14:06:27,996 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 02:06:27" (1/1) ... [2018-11-18 14:06:28,002 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-18 14:06:28,029 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-18 14:06:28,163 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 14:06:28,167 INFO L191 MainTranslator]: Completed pre-run [2018-11-18 14:06:28,191 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 14:06:28,203 INFO L195 MainTranslator]: Completed translation [2018-11-18 14:06:28,203 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 02:06:28 WrapperNode [2018-11-18 14:06:28,203 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-18 14:06:28,204 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-18 14:06:28,204 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-18 14:06:28,204 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-18 14:06:28,209 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 02:06:28" (1/1) ... [2018-11-18 14:06:28,214 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 02:06:28" (1/1) ... [2018-11-18 14:06:28,271 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-18 14:06:28,272 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-18 14:06:28,272 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-18 14:06:28,272 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-18 14:06:28,278 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 02:06:28" (1/1) ... [2018-11-18 14:06:28,278 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 02:06:28" (1/1) ... [2018-11-18 14:06:28,280 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 02:06:28" (1/1) ... [2018-11-18 14:06:28,280 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 02:06:28" (1/1) ... [2018-11-18 14:06:28,287 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 02:06:28" (1/1) ... [2018-11-18 14:06:28,298 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 02:06:28" (1/1) ... [2018-11-18 14:06:28,300 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 02:06:28" (1/1) ... [2018-11-18 14:06:28,304 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-18 14:06:28,305 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-18 14:06:28,305 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-18 14:06:28,305 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-18 14:06:28,305 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 02:06:28" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9edd41f0-bb38-47c2-83e2-42ee9941d34f/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 14:06:28,338 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-18 14:06:28,338 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-18 14:06:28,903 INFO L278 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-18 14:06:28,903 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 02:06:28 BoogieIcfgContainer [2018-11-18 14:06:28,904 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-18 14:06:28,904 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2018-11-18 14:06:28,904 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2018-11-18 14:06:28,907 INFO L276 PluginConnector]: BuchiAutomizer initialized [2018-11-18 14:06:28,908 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-18 14:06:28,908 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 18.11 02:06:27" (1/3) ... [2018-11-18 14:06:28,909 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@772db99f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 18.11 02:06:28, skipping insertion in model container [2018-11-18 14:06:28,909 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-18 14:06:28,909 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 02:06:28" (2/3) ... [2018-11-18 14:06:28,909 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@772db99f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 18.11 02:06:28, skipping insertion in model container [2018-11-18 14:06:28,909 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-18 14:06:28,909 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 02:06:28" (3/3) ... [2018-11-18 14:06:28,911 INFO L375 chiAutomizerObserver]: Analyzing ICFG transmitter.03_false-unreach-call_false-termination.cil.c [2018-11-18 14:06:28,954 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-18 14:06:28,954 INFO L374 BuchiCegarLoop]: Interprodecural is true [2018-11-18 14:06:28,954 INFO L375 BuchiCegarLoop]: Hoare is false [2018-11-18 14:06:28,955 INFO L376 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2018-11-18 14:06:28,955 INFO L377 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-18 14:06:28,955 INFO L378 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-18 14:06:28,955 INFO L379 BuchiCegarLoop]: Difference is false [2018-11-18 14:06:28,955 INFO L380 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-18 14:06:28,955 INFO L383 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2018-11-18 14:06:28,972 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 298 states. [2018-11-18 14:06:28,999 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 241 [2018-11-18 14:06:29,000 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:06:29,000 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:06:29,008 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:06:29,008 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:06:29,008 INFO L442 BuchiCegarLoop]: ======== Iteration 1============ [2018-11-18 14:06:29,009 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 298 states. [2018-11-18 14:06:29,016 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 241 [2018-11-18 14:06:29,016 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:06:29,016 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:06:29,018 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:06:29,018 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:06:29,025 INFO L794 eck$LassoCheckResult]: Stem: 99#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 9#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 128#L605true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 95#L264true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 176#L271true assume !(1 == ~m_i~0);~m_st~0 := 2; 185#L271-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 198#L276-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 78#L281-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 93#L286-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 209#L408true assume !(0 == ~M_E~0); 211#L408-2true assume !(0 == ~T1_E~0); 71#L413-1true assume 0 == ~T2_E~0;~T2_E~0 := 1; 116#L418-1true assume !(0 == ~T3_E~0); 150#L423-1true assume !(0 == ~E_1~0); 26#L428-1true assume !(0 == ~E_2~0); 33#L433-1true assume !(0 == ~E_3~0); 231#L438-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 89#L187true assume !(1 == ~m_pc~0); 109#L187-2true is_master_triggered_~__retres1~0 := 0; 90#L198true is_master_triggered_#res := is_master_triggered_~__retres1~0; 195#L199true activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 140#L500true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 145#L500-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 275#L206true assume 1 == ~t1_pc~0; 35#L207true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 276#L217true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 36#L218true activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 171#L508true assume !(0 != activate_threads_~tmp___0~0); 175#L508-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 146#L225true assume !(1 == ~t2_pc~0); 141#L225-2true is_transmit2_triggered_~__retres1~2 := 0; 147#L236true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 74#L237true activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 21#L516true assume !(0 != activate_threads_~tmp___1~0); 23#L516-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 291#L244true assume 1 == ~t3_pc~0; 254#L245true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 165#L255true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 255#L256true activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 196#L524true assume !(0 != activate_threads_~tmp___2~0); 199#L524-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 111#L451true assume !(1 == ~M_E~0); 117#L451-2true assume !(1 == ~T1_E~0); 148#L456-1true assume !(1 == ~T2_E~0); 24#L461-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 32#L466-1true assume !(1 == ~E_1~0); 226#L471-1true assume !(1 == ~E_2~0); 258#L476-1true assume !(1 == ~E_3~0); 288#L481-1true assume { :end_inline_reset_delta_events } true; 39#L642-3true [2018-11-18 14:06:29,026 INFO L796 eck$LassoCheckResult]: Loop: 39#L642-3true assume true; 37#L642-1true assume !false; 4#L643true start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 233#L383true assume !true; 154#L398true assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 91#L264-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 214#L408-3true assume 0 == ~M_E~0;~M_E~0 := 1; 200#L408-5true assume !(0 == ~T1_E~0); 81#L413-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 123#L418-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 136#L423-3true assume 0 == ~E_1~0;~E_1~0 := 1; 10#L428-3true assume 0 == ~E_2~0;~E_2~0 := 1; 31#L433-3true assume 0 == ~E_3~0;~E_3~0 := 1; 44#L438-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 58#L187-12true assume 1 == ~m_pc~0; 204#L188-4true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 104#L198-4true is_master_triggered_#res := is_master_triggered_~__retres1~0; 205#L199-4true activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 126#L500-12true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 130#L500-14true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 257#L206-12true assume !(1 == ~t1_pc~0); 256#L206-14true is_transmit1_triggered_~__retres1~1 := 0; 266#L217-4true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 47#L218-4true activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 297#L508-12true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 279#L508-14true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 125#L225-12true assume !(1 == ~t2_pc~0); 96#L225-14true is_transmit2_triggered_~__retres1~2 := 0; 118#L236-4true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 217#L237-4true activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 5#L516-12true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 6#L516-14true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 263#L244-12true assume !(1 == ~t3_pc~0); 261#L244-14true is_transmit3_triggered_~__retres1~3 := 0; 281#L255-4true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 224#L256-4true activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 181#L524-12true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 167#L524-14true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 119#L451-3true assume 1 == ~M_E~0;~M_E~0 := 2; 98#L451-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 151#L456-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 28#L461-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 34#L466-3true assume 1 == ~E_1~0;~E_1~0 := 2; 41#L471-3true assume !(1 == ~E_2~0); 238#L476-3true assume 1 == ~E_3~0;~E_3~0 := 2; 267#L481-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 166#L299-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 161#L321-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 245#L322-1true start_simulation_#t~ret10 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 62#L661true assume !(0 == start_simulation_~tmp~3); 218#L661-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 290#L299-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 164#L321-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 248#L322-2true stop_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 127#L616true assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 208#L623true stop_simulation_#res := stop_simulation_~__retres2~0; 298#L624true start_simulation_#t~ret11 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 262#L674true assume !(0 != start_simulation_~tmp___0~1); 39#L642-3true [2018-11-18 14:06:29,030 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:06:29,030 INFO L82 PathProgramCache]: Analyzing trace with hash -1773697160, now seen corresponding path program 1 times [2018-11-18 14:06:29,032 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:06:29,032 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:06:29,072 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:29,072 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:06:29,072 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:29,096 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:06:29,136 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:06:29,138 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:06:29,138 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:06:29,141 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 14:06:29,141 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:06:29,141 INFO L82 PathProgramCache]: Analyzing trace with hash 812904875, now seen corresponding path program 1 times [2018-11-18 14:06:29,142 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:06:29,142 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:06:29,142 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:29,143 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:06:29,143 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:29,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:06:29,156 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:06:29,156 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:06:29,156 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 14:06:29,158 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 14:06:29,167 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 14:06:29,168 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 14:06:29,169 INFO L87 Difference]: Start difference. First operand 298 states. Second operand 3 states. [2018-11-18 14:06:29,197 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:06:29,197 INFO L93 Difference]: Finished difference Result 297 states and 437 transitions. [2018-11-18 14:06:29,198 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 14:06:29,200 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 297 states and 437 transitions. [2018-11-18 14:06:29,203 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 238 [2018-11-18 14:06:29,208 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 297 states to 291 states and 431 transitions. [2018-11-18 14:06:29,209 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 291 [2018-11-18 14:06:29,209 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 291 [2018-11-18 14:06:29,210 INFO L73 IsDeterministic]: Start isDeterministic. Operand 291 states and 431 transitions. [2018-11-18 14:06:29,211 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:06:29,211 INFO L705 BuchiCegarLoop]: Abstraction has 291 states and 431 transitions. [2018-11-18 14:06:29,222 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 291 states and 431 transitions. [2018-11-18 14:06:29,239 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 291 to 291. [2018-11-18 14:06:29,239 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 291 states. [2018-11-18 14:06:29,240 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 291 states to 291 states and 431 transitions. [2018-11-18 14:06:29,241 INFO L728 BuchiCegarLoop]: Abstraction has 291 states and 431 transitions. [2018-11-18 14:06:29,241 INFO L608 BuchiCegarLoop]: Abstraction has 291 states and 431 transitions. [2018-11-18 14:06:29,241 INFO L442 BuchiCegarLoop]: ======== Iteration 2============ [2018-11-18 14:06:29,241 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 291 states and 431 transitions. [2018-11-18 14:06:29,242 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 238 [2018-11-18 14:06:29,242 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:06:29,242 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:06:29,244 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:06:29,244 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:06:29,244 INFO L794 eck$LassoCheckResult]: Stem: 780#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 615#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 616#L605 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 772#L264 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 773#L271 assume 1 == ~m_i~0;~m_st~0 := 0; 847#L271-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 855#L276-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 740#L281-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 741#L286-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 771#L408 assume !(0 == ~M_E~0); 863#L408-2 assume !(0 == ~T1_E~0); 729#L413-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 730#L418-1 assume !(0 == ~T3_E~0); 794#L423-1 assume !(0 == ~E_1~0); 649#L428-1 assume !(0 == ~E_2~0); 650#L433-1 assume !(0 == ~E_3~0); 657#L438-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 760#L187 assume !(1 == ~m_pc~0); 761#L187-2 is_master_triggered_~__retres1~0 := 0; 763#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 764#L199 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 815#L500 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 816#L500-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 818#L206 assume 1 == ~t1_pc~0; 659#L207 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 660#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 662#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 663#L508 assume !(0 != activate_threads_~tmp___0~0); 843#L508-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 819#L225 assume !(1 == ~t2_pc~0); 733#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 732#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 736#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 642#L516 assume !(0 != activate_threads_~tmp___1~0); 643#L516-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 644#L244 assume 1 == ~t3_pc~0; 888#L245 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 834#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 835#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 858#L524 assume !(0 != activate_threads_~tmp___2~0); 859#L524-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 790#L451 assume !(1 == ~M_E~0); 791#L451-2 assume !(1 == ~T1_E~0); 795#L456-1 assume !(1 == ~T2_E~0); 645#L461-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 646#L466-1 assume !(1 == ~E_1~0); 656#L471-1 assume !(1 == ~E_2~0); 878#L476-1 assume !(1 == ~E_3~0); 890#L481-1 assume { :end_inline_reset_delta_events } true; 666#L642-3 [2018-11-18 14:06:29,244 INFO L796 eck$LassoCheckResult]: Loop: 666#L642-3 assume true; 664#L642-1 assume !false; 606#L643 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 607#L383 assume true; 864#L331-1 assume !false; 824#L332 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 825#L299 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 622#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 826#L322 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 742#L336 assume !(0 != eval_~tmp~0); 744#L398 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 765#L264-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 766#L408-3 assume 0 == ~M_E~0;~M_E~0 := 1; 861#L408-5 assume !(0 == ~T1_E~0); 746#L413-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 747#L418-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 799#L423-3 assume 0 == ~E_1~0;~E_1~0 := 1; 617#L428-3 assume 0 == ~E_2~0;~E_2~0 := 1; 618#L433-3 assume 0 == ~E_3~0;~E_3~0 := 1; 655#L438-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 678#L187-12 assume !(1 == ~m_pc~0); 704#L187-14 is_master_triggered_~__retres1~0 := 0; 739#L198-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 784#L199-4 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 806#L500-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 807#L500-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 808#L206-12 assume 1 == ~t1_pc~0; 679#L207-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 681#L217-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 682#L218-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 683#L508-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 892#L508-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 802#L225-12 assume 1 == ~t2_pc~0; 803#L226-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 775#L236-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 796#L237-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 608#L516-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 609#L516-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 610#L244-12 assume 1 == ~t3_pc~0; 870#L245-4 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 871#L255-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 873#L256-4 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 850#L524-12 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 837#L524-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 797#L451-3 assume 1 == ~M_E~0;~M_E~0 := 2; 776#L451-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 777#L456-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 651#L461-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 652#L466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 658#L471-3 assume !(1 == ~E_2~0); 667#L476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 886#L481-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 836#L299-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 630#L321-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 831#L322-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 711#L661 assume !(0 == start_simulation_~tmp~3); 665#L661-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 865#L299-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 637#L321-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 833#L322-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 804#L616 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 805#L623 stop_simulation_#res := stop_simulation_~__retres2~0; 862#L624 start_simulation_#t~ret11 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 891#L674 assume !(0 != start_simulation_~tmp___0~1); 666#L642-3 [2018-11-18 14:06:29,245 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:06:29,245 INFO L82 PathProgramCache]: Analyzing trace with hash 1627783798, now seen corresponding path program 1 times [2018-11-18 14:06:29,245 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:06:29,245 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:06:29,246 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:29,246 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:06:29,246 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:29,253 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:06:29,274 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:06:29,274 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:06:29,274 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:06:29,275 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 14:06:29,275 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:06:29,275 INFO L82 PathProgramCache]: Analyzing trace with hash 1082341580, now seen corresponding path program 1 times [2018-11-18 14:06:29,275 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:06:29,275 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:06:29,276 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:29,276 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:06:29,276 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:29,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:06:29,327 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:06:29,327 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:06:29,327 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:06:29,328 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 14:06:29,328 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 14:06:29,328 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 14:06:29,328 INFO L87 Difference]: Start difference. First operand 291 states and 431 transitions. cyclomatic complexity: 141 Second operand 3 states. [2018-11-18 14:06:29,341 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:06:29,341 INFO L93 Difference]: Finished difference Result 291 states and 430 transitions. [2018-11-18 14:06:29,342 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 14:06:29,342 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 291 states and 430 transitions. [2018-11-18 14:06:29,345 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 238 [2018-11-18 14:06:29,346 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 291 states to 291 states and 430 transitions. [2018-11-18 14:06:29,347 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 291 [2018-11-18 14:06:29,347 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 291 [2018-11-18 14:06:29,347 INFO L73 IsDeterministic]: Start isDeterministic. Operand 291 states and 430 transitions. [2018-11-18 14:06:29,348 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:06:29,348 INFO L705 BuchiCegarLoop]: Abstraction has 291 states and 430 transitions. [2018-11-18 14:06:29,349 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 291 states and 430 transitions. [2018-11-18 14:06:29,357 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 291 to 291. [2018-11-18 14:06:29,357 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 291 states. [2018-11-18 14:06:29,358 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 291 states to 291 states and 430 transitions. [2018-11-18 14:06:29,359 INFO L728 BuchiCegarLoop]: Abstraction has 291 states and 430 transitions. [2018-11-18 14:06:29,359 INFO L608 BuchiCegarLoop]: Abstraction has 291 states and 430 transitions. [2018-11-18 14:06:29,359 INFO L442 BuchiCegarLoop]: ======== Iteration 3============ [2018-11-18 14:06:29,359 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 291 states and 430 transitions. [2018-11-18 14:06:29,360 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 238 [2018-11-18 14:06:29,361 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:06:29,361 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:06:29,362 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:06:29,362 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:06:29,362 INFO L794 eck$LassoCheckResult]: Stem: 1369#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 1204#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 1205#L605 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 1361#L264 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1362#L271 assume 1 == ~m_i~0;~m_st~0 := 0; 1436#L271-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1444#L276-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1329#L281-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1330#L286-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1360#L408 assume !(0 == ~M_E~0); 1452#L408-2 assume !(0 == ~T1_E~0); 1318#L413-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1319#L418-1 assume !(0 == ~T3_E~0); 1383#L423-1 assume !(0 == ~E_1~0); 1238#L428-1 assume !(0 == ~E_2~0); 1239#L433-1 assume !(0 == ~E_3~0); 1246#L438-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1349#L187 assume !(1 == ~m_pc~0); 1350#L187-2 is_master_triggered_~__retres1~0 := 0; 1352#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1353#L199 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 1404#L500 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1405#L500-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1407#L206 assume 1 == ~t1_pc~0; 1248#L207 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1249#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1251#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 1252#L508 assume !(0 != activate_threads_~tmp___0~0); 1432#L508-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1408#L225 assume !(1 == ~t2_pc~0); 1322#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 1321#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1326#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1231#L516 assume !(0 != activate_threads_~tmp___1~0); 1232#L516-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1233#L244 assume 1 == ~t3_pc~0; 1477#L245 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1423#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1424#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 1447#L524 assume !(0 != activate_threads_~tmp___2~0); 1448#L524-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1379#L451 assume !(1 == ~M_E~0); 1380#L451-2 assume !(1 == ~T1_E~0); 1384#L456-1 assume !(1 == ~T2_E~0); 1234#L461-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1235#L466-1 assume !(1 == ~E_1~0); 1245#L471-1 assume !(1 == ~E_2~0); 1467#L476-1 assume !(1 == ~E_3~0); 1479#L481-1 assume { :end_inline_reset_delta_events } true; 1255#L642-3 [2018-11-18 14:06:29,363 INFO L796 eck$LassoCheckResult]: Loop: 1255#L642-3 assume true; 1253#L642-1 assume !false; 1195#L643 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 1196#L383 assume true; 1453#L331-1 assume !false; 1413#L332 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1414#L299 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1211#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1415#L322 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 1331#L336 assume !(0 != eval_~tmp~0); 1333#L398 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 1354#L264-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 1355#L408-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1450#L408-5 assume !(0 == ~T1_E~0); 1335#L413-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1336#L418-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1388#L423-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1206#L428-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1207#L433-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1244#L438-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1265#L187-12 assume 1 == ~m_pc~0; 1291#L188-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 1324#L198-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1373#L199-4 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 1393#L500-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1394#L500-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1397#L206-12 assume 1 == ~t1_pc~0; 1268#L207-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1270#L217-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1271#L218-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 1272#L508-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1481#L508-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1391#L225-12 assume 1 == ~t2_pc~0; 1392#L226-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1364#L236-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1385#L237-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1197#L516-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1198#L516-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1199#L244-12 assume 1 == ~t3_pc~0; 1459#L245-4 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1460#L255-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1462#L256-4 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 1439#L524-12 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1426#L524-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1386#L451-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1365#L451-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1366#L456-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1240#L461-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1241#L466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1247#L471-3 assume !(1 == ~E_2~0); 1256#L476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1475#L481-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1425#L299-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1219#L321-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1420#L322-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 1300#L661 assume !(0 == start_simulation_~tmp~3); 1254#L661-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 1454#L299-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1226#L321-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 1422#L322-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 1395#L616 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 1396#L623 stop_simulation_#res := stop_simulation_~__retres2~0; 1451#L624 start_simulation_#t~ret11 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 1480#L674 assume !(0 != start_simulation_~tmp___0~1); 1255#L642-3 [2018-11-18 14:06:29,363 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:06:29,363 INFO L82 PathProgramCache]: Analyzing trace with hash -1769790220, now seen corresponding path program 1 times [2018-11-18 14:06:29,363 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:06:29,363 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:06:29,364 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:29,364 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:06:29,364 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:29,369 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:06:29,381 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:06:29,382 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:06:29,382 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:06:29,382 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 14:06:29,382 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:06:29,382 INFO L82 PathProgramCache]: Analyzing trace with hash -1937523027, now seen corresponding path program 1 times [2018-11-18 14:06:29,382 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:06:29,382 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:06:29,383 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:29,383 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:06:29,383 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:29,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:06:29,429 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:06:29,429 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:06:29,429 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:06:29,429 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 14:06:29,430 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 14:06:29,430 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 14:06:29,430 INFO L87 Difference]: Start difference. First operand 291 states and 430 transitions. cyclomatic complexity: 140 Second operand 3 states. [2018-11-18 14:06:29,436 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:06:29,436 INFO L93 Difference]: Finished difference Result 291 states and 429 transitions. [2018-11-18 14:06:29,437 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 14:06:29,437 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 291 states and 429 transitions. [2018-11-18 14:06:29,439 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 238 [2018-11-18 14:06:29,440 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 291 states to 291 states and 429 transitions. [2018-11-18 14:06:29,440 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 291 [2018-11-18 14:06:29,441 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 291 [2018-11-18 14:06:29,441 INFO L73 IsDeterministic]: Start isDeterministic. Operand 291 states and 429 transitions. [2018-11-18 14:06:29,442 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:06:29,442 INFO L705 BuchiCegarLoop]: Abstraction has 291 states and 429 transitions. [2018-11-18 14:06:29,442 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 291 states and 429 transitions. [2018-11-18 14:06:29,448 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 291 to 291. [2018-11-18 14:06:29,448 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 291 states. [2018-11-18 14:06:29,450 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 291 states to 291 states and 429 transitions. [2018-11-18 14:06:29,450 INFO L728 BuchiCegarLoop]: Abstraction has 291 states and 429 transitions. [2018-11-18 14:06:29,450 INFO L608 BuchiCegarLoop]: Abstraction has 291 states and 429 transitions. [2018-11-18 14:06:29,450 INFO L442 BuchiCegarLoop]: ======== Iteration 4============ [2018-11-18 14:06:29,450 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 291 states and 429 transitions. [2018-11-18 14:06:29,451 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 238 [2018-11-18 14:06:29,452 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:06:29,452 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:06:29,453 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:06:29,453 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:06:29,453 INFO L794 eck$LassoCheckResult]: Stem: 1958#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 1793#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 1794#L605 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 1950#L264 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1951#L271 assume 1 == ~m_i~0;~m_st~0 := 0; 2025#L271-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2033#L276-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1918#L281-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1919#L286-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1949#L408 assume !(0 == ~M_E~0); 2041#L408-2 assume !(0 == ~T1_E~0); 1907#L413-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1908#L418-1 assume !(0 == ~T3_E~0); 1973#L423-1 assume !(0 == ~E_1~0); 1827#L428-1 assume !(0 == ~E_2~0); 1828#L433-1 assume !(0 == ~E_3~0); 1835#L438-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1938#L187 assume !(1 == ~m_pc~0); 1939#L187-2 is_master_triggered_~__retres1~0 := 0; 1941#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1942#L199 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 1993#L500 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1994#L500-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1996#L206 assume 1 == ~t1_pc~0; 1837#L207 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1838#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1840#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 1841#L508 assume !(0 != activate_threads_~tmp___0~0); 2021#L508-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1997#L225 assume !(1 == ~t2_pc~0); 1912#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 1911#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1917#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1820#L516 assume !(0 != activate_threads_~tmp___1~0); 1821#L516-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1822#L244 assume 1 == ~t3_pc~0; 2066#L245 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2012#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2013#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2036#L524 assume !(0 != activate_threads_~tmp___2~0); 2037#L524-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1966#L451 assume !(1 == ~M_E~0); 1967#L451-2 assume !(1 == ~T1_E~0); 1972#L456-1 assume !(1 == ~T2_E~0); 1823#L461-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1824#L466-1 assume !(1 == ~E_1~0); 1834#L471-1 assume !(1 == ~E_2~0); 2055#L476-1 assume !(1 == ~E_3~0); 2068#L481-1 assume { :end_inline_reset_delta_events } true; 1844#L642-3 [2018-11-18 14:06:29,454 INFO L796 eck$LassoCheckResult]: Loop: 1844#L642-3 assume true; 1842#L642-1 assume !false; 1784#L643 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 1785#L383 assume true; 2042#L331-1 assume !false; 2002#L332 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2003#L299 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1800#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 2004#L322 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 1920#L336 assume !(0 != eval_~tmp~0); 1922#L398 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 1943#L264-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 1944#L408-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2039#L408-5 assume !(0 == ~T1_E~0); 1924#L413-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1925#L418-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1977#L423-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1795#L428-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1796#L433-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1833#L438-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1856#L187-12 assume 1 == ~m_pc~0; 1881#L188-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 1915#L198-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1962#L199-4 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 1982#L500-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1983#L500-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1986#L206-12 assume 1 == ~t1_pc~0; 1857#L207-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1859#L217-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1860#L218-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 1861#L508-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2070#L508-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1980#L225-12 assume !(1 == ~t2_pc~0); 1952#L225-14 is_transmit2_triggered_~__retres1~2 := 0; 1953#L236-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1974#L237-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1786#L516-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1787#L516-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1788#L244-12 assume 1 == ~t3_pc~0; 2048#L245-4 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2049#L255-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2051#L256-4 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2028#L524-12 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2015#L524-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1975#L451-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1956#L451-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1957#L456-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1829#L461-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1830#L466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1836#L471-3 assume !(1 == ~E_2~0); 1848#L476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2064#L481-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2014#L299-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1808#L321-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 2009#L322-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 1889#L661 assume !(0 == start_simulation_~tmp~3); 1843#L661-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2043#L299-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 1815#L321-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 2011#L322-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 1984#L616 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 1985#L623 stop_simulation_#res := stop_simulation_~__retres2~0; 2040#L624 start_simulation_#t~ret11 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 2069#L674 assume !(0 != start_simulation_~tmp___0~1); 1844#L642-3 [2018-11-18 14:06:29,454 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:06:29,454 INFO L82 PathProgramCache]: Analyzing trace with hash -2017936714, now seen corresponding path program 1 times [2018-11-18 14:06:29,454 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:06:29,454 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:06:29,455 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:29,455 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:06:29,455 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:29,459 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:06:29,499 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:06:29,500 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:06:29,500 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 14:06:29,500 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 14:06:29,500 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:06:29,500 INFO L82 PathProgramCache]: Analyzing trace with hash -1018548404, now seen corresponding path program 1 times [2018-11-18 14:06:29,501 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:06:29,501 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:06:29,501 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:29,501 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:06:29,502 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:29,509 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:06:29,533 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:06:29,533 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:06:29,533 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:06:29,534 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 14:06:29,534 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 14:06:29,534 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 14:06:29,534 INFO L87 Difference]: Start difference. First operand 291 states and 429 transitions. cyclomatic complexity: 139 Second operand 3 states. [2018-11-18 14:06:29,558 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:06:29,559 INFO L93 Difference]: Finished difference Result 291 states and 424 transitions. [2018-11-18 14:06:29,559 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 14:06:29,559 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 291 states and 424 transitions. [2018-11-18 14:06:29,561 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 238 [2018-11-18 14:06:29,563 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 291 states to 291 states and 424 transitions. [2018-11-18 14:06:29,563 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 291 [2018-11-18 14:06:29,563 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 291 [2018-11-18 14:06:29,564 INFO L73 IsDeterministic]: Start isDeterministic. Operand 291 states and 424 transitions. [2018-11-18 14:06:29,564 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:06:29,564 INFO L705 BuchiCegarLoop]: Abstraction has 291 states and 424 transitions. [2018-11-18 14:06:29,565 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 291 states and 424 transitions. [2018-11-18 14:06:29,569 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 291 to 291. [2018-11-18 14:06:29,570 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 291 states. [2018-11-18 14:06:29,570 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 291 states to 291 states and 424 transitions. [2018-11-18 14:06:29,571 INFO L728 BuchiCegarLoop]: Abstraction has 291 states and 424 transitions. [2018-11-18 14:06:29,571 INFO L608 BuchiCegarLoop]: Abstraction has 291 states and 424 transitions. [2018-11-18 14:06:29,571 INFO L442 BuchiCegarLoop]: ======== Iteration 5============ [2018-11-18 14:06:29,571 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 291 states and 424 transitions. [2018-11-18 14:06:29,572 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 238 [2018-11-18 14:06:29,572 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:06:29,573 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:06:29,573 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:06:29,574 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:06:29,574 INFO L794 eck$LassoCheckResult]: Stem: 2547#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 2382#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 2383#L605 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 2539#L264 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2540#L271 assume 1 == ~m_i~0;~m_st~0 := 0; 2613#L271-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2621#L276-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2507#L281-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2508#L286-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2536#L408 assume !(0 == ~M_E~0); 2630#L408-2 assume !(0 == ~T1_E~0); 2496#L413-1 assume !(0 == ~T2_E~0); 2497#L418-1 assume !(0 == ~T3_E~0); 2561#L423-1 assume !(0 == ~E_1~0); 2416#L428-1 assume !(0 == ~E_2~0); 2417#L433-1 assume !(0 == ~E_3~0); 2424#L438-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2527#L187 assume !(1 == ~m_pc~0); 2528#L187-2 is_master_triggered_~__retres1~0 := 0; 2530#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2531#L199 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 2582#L500 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2583#L500-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2585#L206 assume 1 == ~t1_pc~0; 2426#L207 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2427#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2429#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 2430#L508 assume !(0 != activate_threads_~tmp___0~0); 2609#L508-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2586#L225 assume !(1 == ~t2_pc~0); 2500#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 2499#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2502#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 2409#L516 assume !(0 != activate_threads_~tmp___1~0); 2410#L516-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2411#L244 assume 1 == ~t3_pc~0; 2655#L245 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2601#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2602#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2625#L524 assume !(0 != activate_threads_~tmp___2~0); 2626#L524-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2555#L451 assume !(1 == ~M_E~0); 2556#L451-2 assume !(1 == ~T1_E~0); 2562#L456-1 assume !(1 == ~T2_E~0); 2412#L461-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2413#L466-1 assume !(1 == ~E_1~0); 2423#L471-1 assume !(1 == ~E_2~0); 2644#L476-1 assume !(1 == ~E_3~0); 2657#L481-1 assume { :end_inline_reset_delta_events } true; 2433#L642-3 [2018-11-18 14:06:29,574 INFO L796 eck$LassoCheckResult]: Loop: 2433#L642-3 assume true; 2431#L642-1 assume !false; 2373#L643 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 2374#L383 assume true; 2631#L331-1 assume !false; 2591#L332 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2592#L299 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 2389#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 2593#L322 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 2509#L336 assume !(0 != eval_~tmp~0); 2511#L398 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 2532#L264-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 2533#L408-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2628#L408-5 assume !(0 == ~T1_E~0); 2513#L413-3 assume !(0 == ~T2_E~0); 2514#L418-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2566#L423-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2384#L428-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2385#L433-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2422#L438-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2445#L187-12 assume 1 == ~m_pc~0; 2470#L188-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 2505#L198-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2551#L199-4 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 2571#L500-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2572#L500-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2575#L206-12 assume 1 == ~t1_pc~0; 2446#L207-4 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2448#L217-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2449#L218-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 2450#L508-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2659#L508-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2569#L225-12 assume 1 == ~t2_pc~0; 2570#L226-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2542#L236-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2563#L237-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 2375#L516-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2376#L516-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2377#L244-12 assume 1 == ~t3_pc~0; 2637#L245-4 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2638#L255-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2640#L256-4 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2617#L524-12 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2604#L524-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2564#L451-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2545#L451-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2546#L456-3 assume !(1 == ~T2_E~0); 2418#L461-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2419#L466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2425#L471-3 assume !(1 == ~E_2~0); 2437#L476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2653#L481-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2603#L299-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 2397#L321-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 2598#L322-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 2478#L661 assume !(0 == start_simulation_~tmp~3); 2432#L661-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 2632#L299-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 2404#L321-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 2600#L322-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 2573#L616 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 2574#L623 stop_simulation_#res := stop_simulation_~__retres2~0; 2629#L624 start_simulation_#t~ret11 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 2658#L674 assume !(0 != start_simulation_~tmp___0~1); 2433#L642-3 [2018-11-18 14:06:29,574 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:06:29,574 INFO L82 PathProgramCache]: Analyzing trace with hash 1247671284, now seen corresponding path program 1 times [2018-11-18 14:06:29,574 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:06:29,574 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:06:29,575 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:29,575 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:06:29,575 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:29,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:06:29,606 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:06:29,606 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:06:29,606 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 14:06:29,606 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 14:06:29,606 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:06:29,607 INFO L82 PathProgramCache]: Analyzing trace with hash -117780695, now seen corresponding path program 1 times [2018-11-18 14:06:29,607 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:06:29,607 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:06:29,608 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:29,608 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:06:29,608 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:29,613 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:06:29,647 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:06:29,648 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:06:29,648 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:06:29,648 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 14:06:29,648 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 14:06:29,648 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 14:06:29,649 INFO L87 Difference]: Start difference. First operand 291 states and 424 transitions. cyclomatic complexity: 134 Second operand 3 states. [2018-11-18 14:06:29,718 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:06:29,719 INFO L93 Difference]: Finished difference Result 493 states and 711 transitions. [2018-11-18 14:06:29,719 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 14:06:29,719 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 493 states and 711 transitions. [2018-11-18 14:06:29,722 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 439 [2018-11-18 14:06:29,725 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 493 states to 493 states and 711 transitions. [2018-11-18 14:06:29,725 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 493 [2018-11-18 14:06:29,725 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 493 [2018-11-18 14:06:29,725 INFO L73 IsDeterministic]: Start isDeterministic. Operand 493 states and 711 transitions. [2018-11-18 14:06:29,729 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:06:29,730 INFO L705 BuchiCegarLoop]: Abstraction has 493 states and 711 transitions. [2018-11-18 14:06:29,730 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 493 states and 711 transitions. [2018-11-18 14:06:29,737 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 493 to 490. [2018-11-18 14:06:29,737 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 490 states. [2018-11-18 14:06:29,739 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 490 states to 490 states and 708 transitions. [2018-11-18 14:06:29,739 INFO L728 BuchiCegarLoop]: Abstraction has 490 states and 708 transitions. [2018-11-18 14:06:29,739 INFO L608 BuchiCegarLoop]: Abstraction has 490 states and 708 transitions. [2018-11-18 14:06:29,739 INFO L442 BuchiCegarLoop]: ======== Iteration 6============ [2018-11-18 14:06:29,739 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 490 states and 708 transitions. [2018-11-18 14:06:29,741 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 436 [2018-11-18 14:06:29,741 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:06:29,742 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:06:29,743 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:06:29,743 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:06:29,744 INFO L794 eck$LassoCheckResult]: Stem: 3338#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 3173#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 3174#L605 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 3330#L264 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3331#L271 assume 1 == ~m_i~0;~m_st~0 := 0; 3406#L271-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3414#L276-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3298#L281-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3299#L286-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3329#L408 assume !(0 == ~M_E~0); 3423#L408-2 assume !(0 == ~T1_E~0); 3285#L413-1 assume !(0 == ~T2_E~0); 3286#L418-1 assume !(0 == ~T3_E~0); 3353#L423-1 assume !(0 == ~E_1~0); 3206#L428-1 assume !(0 == ~E_2~0); 3207#L433-1 assume !(0 == ~E_3~0); 3214#L438-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3318#L187 assume !(1 == ~m_pc~0); 3319#L187-2 is_master_triggered_~__retres1~0 := 0; 3321#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3322#L199 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 3374#L500 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3375#L500-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3377#L206 assume !(1 == ~t1_pc~0); 3461#L206-2 is_transmit1_triggered_~__retres1~1 := 0; 3462#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3216#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 3217#L508 assume !(0 != activate_threads_~tmp___0~0); 3402#L508-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3378#L225 assume !(1 == ~t2_pc~0); 3289#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 3288#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3293#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 3199#L516 assume !(0 != activate_threads_~tmp___1~0); 3200#L516-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3201#L244 assume 1 == ~t3_pc~0; 3455#L245 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3394#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3395#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 3418#L524 assume !(0 != activate_threads_~tmp___2~0); 3419#L524-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3349#L451 assume !(1 == ~M_E~0); 3350#L451-2 assume !(1 == ~T1_E~0); 3354#L456-1 assume !(1 == ~T2_E~0); 3202#L461-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3203#L466-1 assume !(1 == ~E_1~0); 3213#L471-1 assume !(1 == ~E_2~0); 3439#L476-1 assume !(1 == ~E_3~0); 3458#L481-1 assume { :end_inline_reset_delta_events } true; 3220#L642-3 [2018-11-18 14:06:29,744 INFO L796 eck$LassoCheckResult]: Loop: 3220#L642-3 assume true; 3218#L642-1 assume !false; 3164#L643 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 3165#L383 assume true; 3424#L331-1 assume !false; 3384#L332 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 3385#L299 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 3180#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 3386#L322 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 3300#L336 assume !(0 != eval_~tmp~0); 3302#L398 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 3651#L264-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 3650#L408-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3649#L408-5 assume !(0 == ~T1_E~0); 3648#L413-3 assume !(0 == ~T2_E~0); 3647#L418-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3646#L423-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3645#L428-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3644#L433-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3232#L438-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3233#L187-12 assume 1 == ~m_pc~0; 3259#L188-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 3297#L198-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3342#L199-4 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 3365#L500-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3366#L500-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3367#L206-12 assume !(1 == ~t1_pc~0); 3457#L206-14 is_transmit1_triggered_~__retres1~1 := 0; 3643#L217-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3642#L218-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 3640#L508-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3638#L508-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3636#L225-12 assume 1 == ~t2_pc~0; 3633#L226-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3630#L236-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3628#L237-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 3626#L516-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3624#L516-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3622#L244-12 assume !(1 == ~t3_pc~0); 3619#L244-14 is_transmit3_triggered_~__retres1~3 := 0; 3616#L255-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3614#L256-4 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 3612#L524-12 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 3610#L524-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3608#L451-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3606#L451-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3604#L456-3 assume !(1 == ~T2_E~0); 3602#L461-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3600#L466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3598#L471-3 assume !(1 == ~E_2~0); 3596#L476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3594#L481-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 3592#L299-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 3588#L321-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 3587#L322-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 3267#L661 assume !(0 == start_simulation_~tmp~3); 3219#L661-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 3425#L299-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 3194#L321-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 3393#L322-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 3363#L616 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 3364#L623 stop_simulation_#res := stop_simulation_~__retres2~0; 3422#L624 start_simulation_#t~ret11 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 3460#L674 assume !(0 != start_simulation_~tmp___0~1); 3220#L642-3 [2018-11-18 14:06:29,744 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:06:29,744 INFO L82 PathProgramCache]: Analyzing trace with hash 1886455763, now seen corresponding path program 1 times [2018-11-18 14:06:29,745 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:06:29,745 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:06:29,745 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:29,748 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:06:29,748 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:29,753 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:06:29,785 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:06:29,785 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:06:29,785 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 14:06:29,785 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 14:06:29,785 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:06:29,786 INFO L82 PathProgramCache]: Analyzing trace with hash 1044324455, now seen corresponding path program 1 times [2018-11-18 14:06:29,786 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:06:29,786 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:06:29,786 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:29,787 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:06:29,787 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:29,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:06:29,822 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:06:29,822 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:06:29,822 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:06:29,823 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 14:06:29,823 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 14:06:29,823 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 14:06:29,823 INFO L87 Difference]: Start difference. First operand 490 states and 708 transitions. cyclomatic complexity: 220 Second operand 3 states. [2018-11-18 14:06:29,860 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:06:29,860 INFO L93 Difference]: Finished difference Result 916 states and 1309 transitions. [2018-11-18 14:06:29,860 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 14:06:29,860 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 916 states and 1309 transitions. [2018-11-18 14:06:29,864 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 857 [2018-11-18 14:06:29,866 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 916 states to 916 states and 1309 transitions. [2018-11-18 14:06:29,866 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 916 [2018-11-18 14:06:29,867 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 916 [2018-11-18 14:06:29,867 INFO L73 IsDeterministic]: Start isDeterministic. Operand 916 states and 1309 transitions. [2018-11-18 14:06:29,868 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:06:29,868 INFO L705 BuchiCegarLoop]: Abstraction has 916 states and 1309 transitions. [2018-11-18 14:06:29,869 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 916 states and 1309 transitions. [2018-11-18 14:06:29,877 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 916 to 906. [2018-11-18 14:06:29,877 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 906 states. [2018-11-18 14:06:29,879 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 906 states to 906 states and 1297 transitions. [2018-11-18 14:06:29,879 INFO L728 BuchiCegarLoop]: Abstraction has 906 states and 1297 transitions. [2018-11-18 14:06:29,879 INFO L608 BuchiCegarLoop]: Abstraction has 906 states and 1297 transitions. [2018-11-18 14:06:29,879 INFO L442 BuchiCegarLoop]: ======== Iteration 7============ [2018-11-18 14:06:29,879 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 906 states and 1297 transitions. [2018-11-18 14:06:29,882 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 851 [2018-11-18 14:06:29,882 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:06:29,882 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:06:29,883 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:06:29,883 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:06:29,883 INFO L794 eck$LassoCheckResult]: Stem: 4752#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 4586#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 4587#L605 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 4744#L264 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4745#L271 assume 1 == ~m_i~0;~m_st~0 := 0; 4829#L271-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4839#L276-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4711#L281-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4712#L286-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4743#L408 assume !(0 == ~M_E~0); 4851#L408-2 assume !(0 == ~T1_E~0); 4699#L413-1 assume !(0 == ~T2_E~0); 4700#L418-1 assume !(0 == ~T3_E~0); 4770#L423-1 assume !(0 == ~E_1~0); 4620#L428-1 assume !(0 == ~E_2~0); 4621#L433-1 assume !(0 == ~E_3~0); 4629#L438-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4731#L187 assume !(1 == ~m_pc~0); 4732#L187-2 is_master_triggered_~__retres1~0 := 0; 4734#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4735#L199 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 4794#L500 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4795#L500-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4798#L206 assume !(1 == ~t1_pc~0); 4891#L206-2 is_transmit1_triggered_~__retres1~1 := 0; 4892#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4631#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 4632#L508 assume !(0 != activate_threads_~tmp___0~0); 4824#L508-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4799#L225 assume !(1 == ~t2_pc~0); 4703#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 4702#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4707#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 4612#L516 assume !(0 != activate_threads_~tmp___1~0); 4613#L516-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4615#L244 assume !(1 == ~t3_pc~0); 4901#L244-2 is_transmit3_triggered_~__retres1~3 := 0; 4815#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4816#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 4845#L524 assume !(0 != activate_threads_~tmp___2~0); 4846#L524-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4765#L451 assume !(1 == ~M_E~0); 4766#L451-2 assume !(1 == ~T1_E~0); 4771#L456-1 assume !(1 == ~T2_E~0); 4616#L461-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4617#L466-1 assume !(1 == ~E_1~0); 4628#L471-1 assume !(1 == ~E_2~0); 4870#L476-1 assume !(1 == ~E_3~0); 4883#L481-1 assume { :end_inline_reset_delta_events } true; 4902#L642-3 [2018-11-18 14:06:29,884 INFO L796 eck$LassoCheckResult]: Loop: 4902#L642-3 assume true; 5210#L642-1 assume !false; 5204#L643 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 5201#L383 assume true; 5198#L331-1 assume !false; 5179#L332 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 5172#L299 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 5169#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 5165#L322 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 5161#L336 assume !(0 != eval_~tmp~0); 5162#L398 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 5478#L264-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 5477#L408-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5476#L408-5 assume !(0 == ~T1_E~0); 5475#L413-3 assume !(0 == ~T2_E~0); 5474#L418-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5473#L423-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5472#L428-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4626#L433-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4627#L438-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5447#L187-12 assume 1 == ~m_pc~0; 5445#L188-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 5444#L198-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5443#L199-4 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 5442#L500-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 5440#L500-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5438#L206-12 assume !(1 == ~t1_pc~0); 5436#L206-14 is_transmit1_triggered_~__retres1~1 := 0; 5434#L217-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5432#L218-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 5430#L508-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4897#L508-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4778#L225-12 assume !(1 == ~t2_pc~0); 4746#L225-14 is_transmit2_triggered_~__retres1~2 := 0; 4747#L236-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4772#L237-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 4579#L516-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4580#L516-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4581#L244-12 assume !(1 == ~t3_pc~0); 4885#L244-14 is_transmit3_triggered_~__retres1~3 := 0; 4886#L255-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4898#L256-4 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 5295#L524-12 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 5292#L524-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5289#L451-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5286#L451-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5283#L456-3 assume !(1 == ~T2_E~0); 5280#L461-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5277#L466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5274#L471-3 assume !(1 == ~E_2~0); 5270#L476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5267#L481-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 5264#L299-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 5258#L321-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 5255#L322-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 5252#L661 assume !(0 == start_simulation_~tmp~3); 5248#L661-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 5244#L299-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 5239#L321-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 5235#L322-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 5232#L616 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 5227#L623 stop_simulation_#res := stop_simulation_~__retres2~0; 5223#L624 start_simulation_#t~ret11 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 5219#L674 assume !(0 != start_simulation_~tmp___0~1); 4902#L642-3 [2018-11-18 14:06:29,884 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:06:29,884 INFO L82 PathProgramCache]: Analyzing trace with hash 882094642, now seen corresponding path program 1 times [2018-11-18 14:06:29,884 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:06:29,884 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:06:29,885 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:29,885 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:06:29,885 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:29,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:06:29,920 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:06:29,920 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:06:29,920 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 14:06:29,921 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 14:06:29,921 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:06:29,921 INFO L82 PathProgramCache]: Analyzing trace with hash 1963299078, now seen corresponding path program 1 times [2018-11-18 14:06:29,921 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:06:29,921 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:06:29,922 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:29,922 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:06:29,922 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:29,926 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:06:29,949 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:06:29,949 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:06:29,949 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:06:29,950 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 14:06:29,960 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 14:06:29,960 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 14:06:29,960 INFO L87 Difference]: Start difference. First operand 906 states and 1297 transitions. cyclomatic complexity: 395 Second operand 3 states. [2018-11-18 14:06:29,975 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:06:29,975 INFO L93 Difference]: Finished difference Result 906 states and 1283 transitions. [2018-11-18 14:06:29,975 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 14:06:29,976 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 906 states and 1283 transitions. [2018-11-18 14:06:29,978 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 851 [2018-11-18 14:06:29,980 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 906 states to 906 states and 1283 transitions. [2018-11-18 14:06:29,980 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 906 [2018-11-18 14:06:29,981 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 906 [2018-11-18 14:06:29,981 INFO L73 IsDeterministic]: Start isDeterministic. Operand 906 states and 1283 transitions. [2018-11-18 14:06:29,982 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:06:29,983 INFO L705 BuchiCegarLoop]: Abstraction has 906 states and 1283 transitions. [2018-11-18 14:06:29,983 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 906 states and 1283 transitions. [2018-11-18 14:06:29,994 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 906 to 906. [2018-11-18 14:06:29,994 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 906 states. [2018-11-18 14:06:29,996 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 906 states to 906 states and 1283 transitions. [2018-11-18 14:06:29,996 INFO L728 BuchiCegarLoop]: Abstraction has 906 states and 1283 transitions. [2018-11-18 14:06:29,996 INFO L608 BuchiCegarLoop]: Abstraction has 906 states and 1283 transitions. [2018-11-18 14:06:29,996 INFO L442 BuchiCegarLoop]: ======== Iteration 8============ [2018-11-18 14:06:29,996 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 906 states and 1283 transitions. [2018-11-18 14:06:29,999 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 851 [2018-11-18 14:06:29,999 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:06:29,999 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:06:30,000 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:06:30,000 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:06:30,001 INFO L794 eck$LassoCheckResult]: Stem: 6571#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 6405#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 6406#L605 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 6562#L264 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6563#L271 assume 1 == ~m_i~0;~m_st~0 := 0; 6649#L271-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6657#L276-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6530#L281-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6531#L286-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6561#L408 assume !(0 == ~M_E~0); 6674#L408-2 assume !(0 == ~T1_E~0); 6517#L413-1 assume !(0 == ~T2_E~0); 6518#L418-1 assume !(0 == ~T3_E~0); 6590#L423-1 assume !(0 == ~E_1~0); 6438#L428-1 assume !(0 == ~E_2~0); 6439#L433-1 assume !(0 == ~E_3~0); 6446#L438-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6550#L187 assume !(1 == ~m_pc~0); 6551#L187-2 is_master_triggered_~__retres1~0 := 0; 6553#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6554#L199 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 6613#L500 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 6614#L500-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6616#L206 assume !(1 == ~t1_pc~0); 6717#L206-2 is_transmit1_triggered_~__retres1~1 := 0; 6718#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6448#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 6449#L508 assume !(0 != activate_threads_~tmp___0~0); 6644#L508-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6617#L225 assume !(1 == ~t2_pc~0); 6521#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 6520#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6525#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 6431#L516 assume !(0 != activate_threads_~tmp___1~0); 6432#L516-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6433#L244 assume !(1 == ~t3_pc~0); 6725#L244-2 is_transmit3_triggered_~__retres1~3 := 0; 6635#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6636#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 6666#L524 assume !(0 != activate_threads_~tmp___2~0); 6667#L524-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6586#L451 assume !(1 == ~M_E~0); 6587#L451-2 assume !(1 == ~T1_E~0); 6591#L456-1 assume !(1 == ~T2_E~0); 6434#L461-1 assume !(1 == ~T3_E~0); 6435#L466-1 assume !(1 == ~E_1~0); 6445#L471-1 assume !(1 == ~E_2~0); 6689#L476-1 assume !(1 == ~E_3~0); 6708#L481-1 assume { :end_inline_reset_delta_events } true; 6727#L642-3 [2018-11-18 14:06:30,001 INFO L796 eck$LassoCheckResult]: Loop: 6727#L642-3 assume true; 6924#L642-1 assume !false; 6861#L643 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 6859#L383 assume true; 6857#L331-1 assume !false; 6855#L332 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 6851#L299 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 6847#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 6845#L322 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 6842#L336 assume !(0 != eval_~tmp~0); 6843#L398 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 7033#L264-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 7031#L408-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7029#L408-5 assume !(0 == ~T1_E~0); 7027#L413-3 assume !(0 == ~T2_E~0); 7026#L418-3 assume !(0 == ~T3_E~0); 7025#L423-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7024#L428-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7023#L433-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7022#L438-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7021#L187-12 assume 1 == ~m_pc~0; 7019#L188-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 7018#L198-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7017#L199-4 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 7015#L500-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 7012#L500-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7010#L206-12 assume !(1 == ~t1_pc~0); 7008#L206-14 is_transmit1_triggered_~__retres1~1 := 0; 7006#L217-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7004#L218-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 7002#L508-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 7000#L508-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6998#L225-12 assume 1 == ~t2_pc~0; 6995#L226-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 6993#L236-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6991#L237-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 6989#L516-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 6986#L516-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6984#L244-12 assume !(1 == ~t3_pc~0); 6982#L244-14 is_transmit3_triggered_~__retres1~3 := 0; 6980#L255-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6978#L256-4 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 6976#L524-12 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 6974#L524-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6972#L451-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6970#L451-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6968#L456-3 assume !(1 == ~T2_E~0); 6966#L461-3 assume !(1 == ~T3_E~0); 6964#L466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6962#L471-3 assume !(1 == ~E_2~0); 6960#L476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6958#L481-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 6956#L299-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 6951#L321-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 6949#L322-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 6947#L661 assume !(0 == start_simulation_~tmp~3); 6942#L661-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 6938#L299-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 6934#L321-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 6933#L322-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 6929#L616 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 6927#L623 stop_simulation_#res := stop_simulation_~__retres2~0; 6926#L624 start_simulation_#t~ret11 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 6925#L674 assume !(0 != start_simulation_~tmp___0~1); 6727#L642-3 [2018-11-18 14:06:30,001 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:06:30,001 INFO L82 PathProgramCache]: Analyzing trace with hash 883941684, now seen corresponding path program 1 times [2018-11-18 14:06:30,001 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:06:30,001 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:06:30,002 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:30,002 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:06:30,003 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:30,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:06:30,056 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:06:30,056 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:06:30,056 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 14:06:30,056 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 14:06:30,056 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:06:30,056 INFO L82 PathProgramCache]: Analyzing trace with hash -559542165, now seen corresponding path program 1 times [2018-11-18 14:06:30,056 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:06:30,057 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:06:30,057 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:30,057 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:06:30,057 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:30,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:06:30,071 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:06:30,072 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:06:30,072 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:06:30,072 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 14:06:30,072 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 14:06:30,072 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 14:06:30,073 INFO L87 Difference]: Start difference. First operand 906 states and 1283 transitions. cyclomatic complexity: 381 Second operand 5 states. [2018-11-18 14:06:30,170 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:06:30,170 INFO L93 Difference]: Finished difference Result 2513 states and 3518 transitions. [2018-11-18 14:06:30,171 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 14:06:30,171 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2513 states and 3518 transitions. [2018-11-18 14:06:30,178 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2391 [2018-11-18 14:06:30,183 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2513 states to 2513 states and 3518 transitions. [2018-11-18 14:06:30,183 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2513 [2018-11-18 14:06:30,185 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2513 [2018-11-18 14:06:30,185 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2513 states and 3518 transitions. [2018-11-18 14:06:30,187 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:06:30,187 INFO L705 BuchiCegarLoop]: Abstraction has 2513 states and 3518 transitions. [2018-11-18 14:06:30,188 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2513 states and 3518 transitions. [2018-11-18 14:06:30,198 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2513 to 963. [2018-11-18 14:06:30,198 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 963 states. [2018-11-18 14:06:30,199 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 963 states to 963 states and 1340 transitions. [2018-11-18 14:06:30,200 INFO L728 BuchiCegarLoop]: Abstraction has 963 states and 1340 transitions. [2018-11-18 14:06:30,200 INFO L608 BuchiCegarLoop]: Abstraction has 963 states and 1340 transitions. [2018-11-18 14:06:30,200 INFO L442 BuchiCegarLoop]: ======== Iteration 9============ [2018-11-18 14:06:30,200 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 963 states and 1340 transitions. [2018-11-18 14:06:30,202 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 905 [2018-11-18 14:06:30,202 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:06:30,202 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:06:30,203 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:06:30,203 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:06:30,203 INFO L794 eck$LassoCheckResult]: Stem: 10006#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 9837#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 9838#L605 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 9997#L264 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9998#L271 assume 1 == ~m_i~0;~m_st~0 := 0; 10085#L271-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10095#L276-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9964#L281-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9965#L286-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9996#L408 assume !(0 == ~M_E~0); 10119#L408-2 assume !(0 == ~T1_E~0); 9951#L413-1 assume !(0 == ~T2_E~0); 9952#L418-1 assume !(0 == ~T3_E~0); 10027#L423-1 assume !(0 == ~E_1~0); 9871#L428-1 assume !(0 == ~E_2~0); 9872#L433-1 assume !(0 == ~E_3~0); 9880#L438-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9985#L187 assume !(1 == ~m_pc~0); 9986#L187-2 is_master_triggered_~__retres1~0 := 0; 9988#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9989#L199 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 10050#L500 assume !(0 != activate_threads_~tmp~1); 10051#L500-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10053#L206 assume !(1 == ~t1_pc~0); 10159#L206-2 is_transmit1_triggered_~__retres1~1 := 0; 10160#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9882#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 9883#L508 assume !(0 != activate_threads_~tmp___0~0); 10080#L508-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10054#L225 assume !(1 == ~t2_pc~0); 9956#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 9955#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9960#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 9863#L516 assume !(0 != activate_threads_~tmp___1~0); 9864#L516-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9866#L244 assume !(1 == ~t3_pc~0); 10167#L244-2 is_transmit3_triggered_~__retres1~3 := 0; 10071#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 10072#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 10105#L524 assume !(0 != activate_threads_~tmp___2~0); 10106#L524-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10023#L451 assume !(1 == ~M_E~0); 10024#L451-2 assume !(1 == ~T1_E~0); 10028#L456-1 assume !(1 == ~T2_E~0); 9867#L461-1 assume !(1 == ~T3_E~0); 9868#L466-1 assume !(1 == ~E_1~0); 9879#L471-1 assume !(1 == ~E_2~0); 10137#L476-1 assume !(1 == ~E_3~0); 10153#L481-1 assume { :end_inline_reset_delta_events } true; 9886#L642-3 [2018-11-18 14:06:30,203 INFO L796 eck$LassoCheckResult]: Loop: 9886#L642-3 assume true; 9884#L642-1 assume !false; 9828#L643 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 9829#L383 assume true; 10120#L331-1 assume !false; 10061#L332 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 10062#L299 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 9844#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 10063#L322 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 9966#L336 assume !(0 != eval_~tmp~0); 9968#L398 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 10788#L264-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 10787#L408-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10785#L408-5 assume !(0 == ~T1_E~0); 10783#L413-3 assume !(0 == ~T2_E~0); 10781#L418-3 assume !(0 == ~T3_E~0); 10779#L423-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10771#L428-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9877#L433-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9878#L438-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9896#L187-12 assume 1 == ~m_pc~0; 10112#L188-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 10113#L198-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10114#L199-4 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 10115#L500-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 10039#L500-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10042#L206-12 assume !(1 == ~t1_pc~0); 10151#L206-14 is_transmit1_triggered_~__retres1~1 := 0; 10152#L217-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9902#L218-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 9903#L508-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 10164#L508-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10036#L225-12 assume 1 == ~t2_pc~0; 10037#L226-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 10000#L236-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10029#L237-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 9830#L516-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 9831#L516-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9832#L244-12 assume !(1 == ~t3_pc~0); 10156#L244-14 is_transmit3_triggered_~__retres1~3 := 0; 10776#L255-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 10775#L256-4 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 10774#L524-12 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 10773#L524-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10772#L451-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10004#L451-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10005#L456-3 assume !(1 == ~T2_E~0); 10769#L461-3 assume !(1 == ~T3_E~0); 10735#L466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10682#L471-3 assume !(1 == ~E_2~0); 10681#L476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10680#L481-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 10073#L299-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 9852#L321-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 10068#L322-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 9933#L661 assume !(0 == start_simulation_~tmp~3); 9885#L661-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 10121#L299-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 9858#L321-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 10070#L322-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 10040#L616 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 10041#L623 stop_simulation_#res := stop_simulation_~__retres2~0; 10118#L624 start_simulation_#t~ret11 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 10155#L674 assume !(0 != start_simulation_~tmp___0~1); 9886#L642-3 [2018-11-18 14:06:30,203 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:06:30,204 INFO L82 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 1 times [2018-11-18 14:06:30,204 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:06:30,204 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:06:30,204 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:30,204 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:06:30,205 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:30,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:06:30,211 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:06:30,230 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:06:30,230 INFO L82 PathProgramCache]: Analyzing trace with hash -559542165, now seen corresponding path program 2 times [2018-11-18 14:06:30,230 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:06:30,230 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:06:30,231 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:30,231 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:06:30,231 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:30,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:06:30,251 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:06:30,251 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:06:30,252 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:06:30,252 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 14:06:30,252 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 14:06:30,252 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 14:06:30,252 INFO L87 Difference]: Start difference. First operand 963 states and 1340 transitions. cyclomatic complexity: 381 Second operand 3 states. [2018-11-18 14:06:30,289 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:06:30,289 INFO L93 Difference]: Finished difference Result 1664 states and 2286 transitions. [2018-11-18 14:06:30,289 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 14:06:30,290 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1664 states and 2286 transitions. [2018-11-18 14:06:30,294 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1565 [2018-11-18 14:06:30,297 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1664 states to 1664 states and 2286 transitions. [2018-11-18 14:06:30,297 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1664 [2018-11-18 14:06:30,298 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1664 [2018-11-18 14:06:30,298 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1664 states and 2286 transitions. [2018-11-18 14:06:30,300 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:06:30,300 INFO L705 BuchiCegarLoop]: Abstraction has 1664 states and 2286 transitions. [2018-11-18 14:06:30,301 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1664 states and 2286 transitions. [2018-11-18 14:06:30,310 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1664 to 1662. [2018-11-18 14:06:30,310 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1662 states. [2018-11-18 14:06:30,313 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1662 states to 1662 states and 2284 transitions. [2018-11-18 14:06:30,313 INFO L728 BuchiCegarLoop]: Abstraction has 1662 states and 2284 transitions. [2018-11-18 14:06:30,313 INFO L608 BuchiCegarLoop]: Abstraction has 1662 states and 2284 transitions. [2018-11-18 14:06:30,313 INFO L442 BuchiCegarLoop]: ======== Iteration 10============ [2018-11-18 14:06:30,313 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1662 states and 2284 transitions. [2018-11-18 14:06:30,317 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1563 [2018-11-18 14:06:30,317 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:06:30,317 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:06:30,318 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:06:30,318 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:06:30,318 INFO L794 eck$LassoCheckResult]: Stem: 12633#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 12470#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 12471#L605 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 12625#L264 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12626#L271 assume 1 == ~m_i~0;~m_st~0 := 0; 12721#L271-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12732#L276-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12593#L281-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12594#L286-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12624#L408 assume !(0 == ~M_E~0); 12752#L408-2 assume !(0 == ~T1_E~0); 12581#L413-1 assume !(0 == ~T2_E~0); 12582#L418-1 assume !(0 == ~T3_E~0); 12654#L423-1 assume !(0 == ~E_1~0); 12504#L428-1 assume 0 == ~E_2~0;~E_2~0 := 1; 12505#L433-1 assume !(0 == ~E_3~0); 12773#L438-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12774#L187 assume !(1 == ~m_pc~0); 12642#L187-2 is_master_triggered_~__retres1~0 := 0; 12616#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12617#L199 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 12681#L500 assume !(0 != activate_threads_~tmp~1); 12682#L500-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12799#L206 assume !(1 == ~t1_pc~0); 12800#L206-2 is_transmit1_triggered_~__retres1~1 := 0; 12801#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12802#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 12714#L508 assume !(0 != activate_threads_~tmp___0~0); 12715#L508-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12857#L225 assume !(1 == ~t2_pc~0); 12856#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 12584#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12587#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 12496#L516 assume !(0 != activate_threads_~tmp___1~0); 12497#L516-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 12499#L244 assume !(1 == ~t3_pc~0); 12809#L244-2 is_transmit3_triggered_~__retres1~3 := 0; 12706#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 12707#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 12744#L524 assume !(0 != activate_threads_~tmp___2~0); 12745#L524-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12646#L451 assume !(1 == ~M_E~0); 12647#L451-2 assume !(1 == ~T1_E~0); 12655#L456-1 assume !(1 == ~T2_E~0); 12500#L461-1 assume !(1 == ~T3_E~0); 12501#L466-1 assume !(1 == ~E_1~0); 12512#L471-1 assume 1 == ~E_2~0;~E_2~0 := 2; 12767#L476-1 assume !(1 == ~E_3~0); 12789#L481-1 assume { :end_inline_reset_delta_events } true; 12810#L642-3 [2018-11-18 14:06:30,318 INFO L796 eck$LassoCheckResult]: Loop: 12810#L642-3 assume true; 13686#L642-1 assume !false; 12461#L643 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 12462#L383 assume true; 13614#L331-1 assume !false; 13612#L332 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 13608#L299 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 13607#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 13606#L322 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 13603#L336 assume !(0 != eval_~tmp~0); 13604#L398 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 14012#L264-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 14009#L408-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14007#L408-5 assume !(0 == ~T1_E~0); 14005#L413-3 assume !(0 == ~T2_E~0); 14003#L418-3 assume !(0 == ~T3_E~0); 14001#L423-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13981#L428-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13979#L433-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13977#L438-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 13975#L187-12 assume !(1 == ~m_pc~0); 13971#L187-14 is_master_triggered_~__retres1~0 := 0; 13969#L198-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 13967#L199-4 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 13965#L500-12 assume !(0 != activate_threads_~tmp~1); 13962#L500-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 13960#L206-12 assume !(1 == ~t1_pc~0); 13958#L206-14 is_transmit1_triggered_~__retres1~1 := 0; 13957#L217-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 13956#L218-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 13955#L508-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 13953#L508-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 13952#L225-12 assume 1 == ~t2_pc~0; 13950#L226-4 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 13949#L236-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 13947#L237-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 13945#L516-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 13944#L516-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 13940#L244-12 assume !(1 == ~t3_pc~0); 13938#L244-14 is_transmit3_triggered_~__retres1~3 := 0; 13936#L255-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 13934#L256-4 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 13931#L524-12 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 13929#L524-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13927#L451-3 assume 1 == ~M_E~0;~M_E~0 := 2; 13924#L451-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13922#L456-3 assume !(1 == ~T2_E~0); 13920#L461-3 assume !(1 == ~T3_E~0); 13918#L466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13916#L471-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12780#L476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12781#L481-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 12978#L299-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 12973#L321-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 12971#L322-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 12968#L661 assume !(0 == start_simulation_~tmp~3); 12969#L661-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 13703#L299-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 13699#L321-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 13697#L322-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 13694#L616 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 13693#L623 stop_simulation_#res := stop_simulation_~__retres2~0; 13691#L624 start_simulation_#t~ret11 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 13689#L674 assume !(0 != start_simulation_~tmp___0~1); 12810#L642-3 [2018-11-18 14:06:30,318 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:06:30,318 INFO L82 PathProgramCache]: Analyzing trace with hash 1218472174, now seen corresponding path program 1 times [2018-11-18 14:06:30,318 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:06:30,319 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:06:30,319 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:30,319 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 14:06:30,319 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:30,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:06:30,334 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:06:30,335 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:06:30,335 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 14:06:30,335 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 14:06:30,335 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:06:30,335 INFO L82 PathProgramCache]: Analyzing trace with hash -1926588474, now seen corresponding path program 1 times [2018-11-18 14:06:30,335 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:06:30,335 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:06:30,336 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:30,336 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:06:30,336 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:30,340 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:06:30,359 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:06:30,359 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:06:30,359 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 14:06:30,359 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 14:06:30,360 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 14:06:30,360 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 14:06:30,360 INFO L87 Difference]: Start difference. First operand 1662 states and 2284 transitions. cyclomatic complexity: 626 Second operand 3 states. [2018-11-18 14:06:30,388 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:06:30,389 INFO L93 Difference]: Finished difference Result 963 states and 1307 transitions. [2018-11-18 14:06:30,389 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 14:06:30,389 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 963 states and 1307 transitions. [2018-11-18 14:06:30,392 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 905 [2018-11-18 14:06:30,394 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 963 states to 963 states and 1307 transitions. [2018-11-18 14:06:30,394 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 963 [2018-11-18 14:06:30,395 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 963 [2018-11-18 14:06:30,395 INFO L73 IsDeterministic]: Start isDeterministic. Operand 963 states and 1307 transitions. [2018-11-18 14:06:30,396 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:06:30,396 INFO L705 BuchiCegarLoop]: Abstraction has 963 states and 1307 transitions. [2018-11-18 14:06:30,397 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 963 states and 1307 transitions. [2018-11-18 14:06:30,403 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 963 to 963. [2018-11-18 14:06:30,403 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 963 states. [2018-11-18 14:06:30,405 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 963 states to 963 states and 1307 transitions. [2018-11-18 14:06:30,405 INFO L728 BuchiCegarLoop]: Abstraction has 963 states and 1307 transitions. [2018-11-18 14:06:30,405 INFO L608 BuchiCegarLoop]: Abstraction has 963 states and 1307 transitions. [2018-11-18 14:06:30,405 INFO L442 BuchiCegarLoop]: ======== Iteration 11============ [2018-11-18 14:06:30,405 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 963 states and 1307 transitions. [2018-11-18 14:06:30,408 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 905 [2018-11-18 14:06:30,408 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:06:30,408 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:06:30,408 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:06:30,409 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:06:30,409 INFO L794 eck$LassoCheckResult]: Stem: 15264#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 15104#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 15105#L605 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 15255#L264 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15256#L271 assume 1 == ~m_i~0;~m_st~0 := 0; 15350#L271-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15360#L276-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15223#L281-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15224#L286-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15254#L408 assume !(0 == ~M_E~0); 15378#L408-2 assume !(0 == ~T1_E~0); 15212#L413-1 assume !(0 == ~T2_E~0); 15213#L418-1 assume !(0 == ~T3_E~0); 15288#L423-1 assume !(0 == ~E_1~0); 15138#L428-1 assume !(0 == ~E_2~0); 15139#L433-1 assume !(0 == ~E_3~0); 15146#L438-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15243#L187 assume !(1 == ~m_pc~0); 15244#L187-2 is_master_triggered_~__retres1~0 := 0; 15246#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15247#L199 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 15313#L500 assume !(0 != activate_threads_~tmp~1); 15314#L500-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15317#L206 assume !(1 == ~t1_pc~0); 15424#L206-2 is_transmit1_triggered_~__retres1~1 := 0; 15425#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 15148#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 15149#L508 assume !(0 != activate_threads_~tmp___0~0); 15346#L508-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15318#L225 assume !(1 == ~t2_pc~0); 15216#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 15315#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 15222#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 15130#L516 assume !(0 != activate_threads_~tmp___1~0); 15131#L516-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 15133#L244 assume !(1 == ~t3_pc~0); 15428#L244-2 is_transmit3_triggered_~__retres1~3 := 0; 15337#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 15338#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 15368#L524 assume !(0 != activate_threads_~tmp___2~0); 15369#L524-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15281#L451 assume !(1 == ~M_E~0); 15282#L451-2 assume !(1 == ~T1_E~0); 15289#L456-1 assume !(1 == ~T2_E~0); 15134#L461-1 assume !(1 == ~T3_E~0); 15135#L466-1 assume !(1 == ~E_1~0); 15145#L471-1 assume !(1 == ~E_2~0); 15396#L476-1 assume !(1 == ~E_3~0); 15415#L481-1 assume { :end_inline_reset_delta_events } true; 15429#L642-3 [2018-11-18 14:06:30,409 INFO L796 eck$LassoCheckResult]: Loop: 15429#L642-3 assume true; 15601#L642-1 assume !false; 15593#L643 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 15591#L383 assume true; 15583#L331-1 assume !false; 15578#L332 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 15539#L299 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 15535#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 15533#L322 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 15530#L336 assume !(0 != eval_~tmp~0); 15531#L398 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 15790#L264-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 15788#L408-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15786#L408-5 assume !(0 == ~T1_E~0); 15784#L413-3 assume !(0 == ~T2_E~0); 15782#L418-3 assume !(0 == ~T3_E~0); 15780#L423-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15778#L428-3 assume !(0 == ~E_2~0); 15776#L433-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15775#L438-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15774#L187-12 assume !(1 == ~m_pc~0); 15772#L187-14 is_master_triggered_~__retres1~0 := 0; 15770#L198-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15768#L199-4 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 15767#L500-12 assume !(0 != activate_threads_~tmp~1); 15765#L500-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15763#L206-12 assume !(1 == ~t1_pc~0); 15762#L206-14 is_transmit1_triggered_~__retres1~1 := 0; 15761#L217-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 15760#L218-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 15759#L508-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 15755#L508-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15753#L225-12 assume !(1 == ~t2_pc~0); 15750#L225-14 is_transmit2_triggered_~__retres1~2 := 0; 15748#L236-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 15745#L237-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 15743#L516-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 15741#L516-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 15739#L244-12 assume !(1 == ~t3_pc~0); 15737#L244-14 is_transmit3_triggered_~__retres1~3 := 0; 15735#L255-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 15733#L256-4 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 15731#L524-12 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 15728#L524-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15726#L451-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15724#L451-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15722#L456-3 assume !(1 == ~T2_E~0); 15720#L461-3 assume !(1 == ~T3_E~0); 15718#L466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15716#L471-3 assume !(1 == ~E_2~0); 15714#L476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15712#L481-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 15711#L299-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 15701#L321-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 15690#L322-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 15688#L661 assume !(0 == start_simulation_~tmp~3); 15686#L661-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 15635#L299-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 15630#L321-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 15628#L322-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 15626#L616 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 15624#L623 stop_simulation_#res := stop_simulation_~__retres2~0; 15622#L624 start_simulation_#t~ret11 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 15613#L674 assume !(0 != start_simulation_~tmp___0~1); 15429#L642-3 [2018-11-18 14:06:30,409 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:06:30,409 INFO L82 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 2 times [2018-11-18 14:06:30,409 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:06:30,409 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:06:30,410 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:30,410 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:06:30,410 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:30,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:06:30,416 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:06:30,422 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:06:30,423 INFO L82 PathProgramCache]: Analyzing trace with hash 1654401385, now seen corresponding path program 1 times [2018-11-18 14:06:30,423 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:06:30,423 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:06:30,423 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:30,423 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 14:06:30,424 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:30,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:06:30,444 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:06:30,444 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:06:30,444 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 14:06:30,444 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 14:06:30,444 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 14:06:30,444 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 14:06:30,445 INFO L87 Difference]: Start difference. First operand 963 states and 1307 transitions. cyclomatic complexity: 348 Second operand 5 states. [2018-11-18 14:06:30,514 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:06:30,514 INFO L93 Difference]: Finished difference Result 1676 states and 2244 transitions. [2018-11-18 14:06:30,515 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-18 14:06:30,515 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1676 states and 2244 transitions. [2018-11-18 14:06:30,520 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1614 [2018-11-18 14:06:30,523 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1676 states to 1676 states and 2244 transitions. [2018-11-18 14:06:30,524 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1676 [2018-11-18 14:06:30,525 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1676 [2018-11-18 14:06:30,525 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1676 states and 2244 transitions. [2018-11-18 14:06:30,526 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:06:30,526 INFO L705 BuchiCegarLoop]: Abstraction has 1676 states and 2244 transitions. [2018-11-18 14:06:30,528 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1676 states and 2244 transitions. [2018-11-18 14:06:30,535 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1676 to 975. [2018-11-18 14:06:30,536 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 975 states. [2018-11-18 14:06:30,537 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 975 states to 975 states and 1319 transitions. [2018-11-18 14:06:30,537 INFO L728 BuchiCegarLoop]: Abstraction has 975 states and 1319 transitions. [2018-11-18 14:06:30,537 INFO L608 BuchiCegarLoop]: Abstraction has 975 states and 1319 transitions. [2018-11-18 14:06:30,537 INFO L442 BuchiCegarLoop]: ======== Iteration 12============ [2018-11-18 14:06:30,537 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 975 states and 1319 transitions. [2018-11-18 14:06:30,540 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 917 [2018-11-18 14:06:30,540 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:06:30,541 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:06:30,541 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:06:30,541 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:06:30,541 INFO L794 eck$LassoCheckResult]: Stem: 17922#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 17760#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 17761#L605 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 17914#L264 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17915#L271 assume 1 == ~m_i~0;~m_st~0 := 0; 18007#L271-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18016#L276-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17882#L281-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17883#L286-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17913#L408 assume !(0 == ~M_E~0); 18036#L408-2 assume !(0 == ~T1_E~0); 17870#L413-1 assume !(0 == ~T2_E~0); 17871#L418-1 assume !(0 == ~T3_E~0); 17944#L423-1 assume !(0 == ~E_1~0); 17793#L428-1 assume !(0 == ~E_2~0); 17794#L433-1 assume !(0 == ~E_3~0); 17802#L438-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 17902#L187 assume !(1 == ~m_pc~0); 17903#L187-2 is_master_triggered_~__retres1~0 := 0; 17934#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 18098#L199 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 17970#L500 assume !(0 != activate_threads_~tmp~1); 17971#L500-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 17975#L206 assume !(1 == ~t1_pc~0); 18086#L206-2 is_transmit1_triggered_~__retres1~1 := 0; 18087#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 17804#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 17805#L508 assume !(0 != activate_threads_~tmp___0~0); 18002#L508-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 17976#L225 assume !(1 == ~t2_pc~0); 17874#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 17972#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 17881#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 17786#L516 assume !(0 != activate_threads_~tmp___1~0); 17787#L516-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 17788#L244 assume !(1 == ~t3_pc~0); 18092#L244-2 is_transmit3_triggered_~__retres1~3 := 0; 17993#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 17994#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 18023#L524 assume !(0 != activate_threads_~tmp___2~0); 18024#L524-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17938#L451 assume !(1 == ~M_E~0); 17939#L451-2 assume !(1 == ~T1_E~0); 17945#L456-1 assume !(1 == ~T2_E~0); 17789#L461-1 assume !(1 == ~T3_E~0); 17790#L466-1 assume !(1 == ~E_1~0); 17801#L471-1 assume !(1 == ~E_2~0); 18056#L476-1 assume !(1 == ~E_3~0); 18075#L481-1 assume { :end_inline_reset_delta_events } true; 17808#L642-3 [2018-11-18 14:06:30,542 INFO L796 eck$LassoCheckResult]: Loop: 17808#L642-3 assume true; 17806#L642-1 assume !false; 17750#L643 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 17751#L383 assume true; 18039#L331-1 assume !false; 17982#L332 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 17983#L299 assume !(0 == ~m_st~0); 17845#L303 assume !(0 == ~t1_st~0); 17766#L307 assume !(0 == ~t2_st~0); 17768#L311 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4 := 0; 18067#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 18486#L322 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 18124#L336 assume !(0 != eval_~tmp~0); 18125#L398 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 18652#L264-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 18651#L408-3 assume 0 == ~M_E~0;~M_E~0 := 1; 18650#L408-5 assume !(0 == ~T1_E~0); 18649#L413-3 assume !(0 == ~T2_E~0); 18648#L418-3 assume !(0 == ~T3_E~0); 17964#L423-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17965#L428-3 assume !(0 == ~E_2~0); 17799#L433-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17800#L438-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 18647#L187-12 assume 1 == ~m_pc~0; 18646#L188-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 18644#L198-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 18642#L199-4 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 18109#L500-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 18110#L500-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 18073#L206-12 assume !(1 == ~t1_pc~0); 18074#L206-14 is_transmit1_triggered_~__retres1~1 := 0; 18371#L217-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 18157#L218-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 18158#L508-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 18153#L508-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 18154#L225-12 assume !(1 == ~t2_pc~0); 17916#L225-14 is_transmit2_triggered_~__retres1~2 := 0; 17917#L236-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 17946#L237-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 17752#L516-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 17753#L516-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 18368#L244-12 assume !(1 == ~t3_pc~0); 18367#L244-14 is_transmit3_triggered_~__retres1~3 := 0; 18366#L255-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 18365#L256-4 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 18364#L524-12 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 18363#L524-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18362#L451-3 assume 1 == ~M_E~0;~M_E~0 := 2; 18361#L451-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 18360#L456-3 assume !(1 == ~T2_E~0); 18359#L461-3 assume !(1 == ~T3_E~0); 18358#L466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 18357#L471-3 assume !(1 == ~E_2~0); 18356#L476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 18355#L481-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 18354#L299-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 18350#L321-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 18349#L322-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 18347#L661 assume !(0 == start_simulation_~tmp~3); 18348#L661-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 18093#L299-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 17781#L321-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 17992#L322-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 17958#L616 assume !(0 != stop_simulation_~tmp~2);stop_simulation_~__retres2~0 := 1; 17959#L623 stop_simulation_#res := stop_simulation_~__retres2~0; 18035#L624 start_simulation_#t~ret11 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 18080#L674 assume !(0 != start_simulation_~tmp___0~1); 17808#L642-3 [2018-11-18 14:06:30,542 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:06:30,542 INFO L82 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 3 times [2018-11-18 14:06:30,542 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:06:30,542 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:06:30,543 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:30,543 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:06:30,543 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:30,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:06:30,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:06:30,554 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:06:30,554 INFO L82 PathProgramCache]: Analyzing trace with hash -880731976, now seen corresponding path program 1 times [2018-11-18 14:06:30,554 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:06:30,555 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:06:30,555 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:30,555 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 14:06:30,555 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:30,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:06:30,585 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:06:30,585 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:06:30,585 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 14:06:30,585 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 14:06:30,586 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 14:06:30,586 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 14:06:30,586 INFO L87 Difference]: Start difference. First operand 975 states and 1319 transitions. cyclomatic complexity: 348 Second operand 5 states. [2018-11-18 14:06:30,660 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:06:30,660 INFO L93 Difference]: Finished difference Result 3122 states and 4182 transitions. [2018-11-18 14:06:30,661 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-18 14:06:30,661 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3122 states and 4182 transitions. [2018-11-18 14:06:30,669 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3052 [2018-11-18 14:06:30,676 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3122 states to 3122 states and 4182 transitions. [2018-11-18 14:06:30,676 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3122 [2018-11-18 14:06:30,678 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3122 [2018-11-18 14:06:30,678 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3122 states and 4182 transitions. [2018-11-18 14:06:30,681 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:06:30,681 INFO L705 BuchiCegarLoop]: Abstraction has 3122 states and 4182 transitions. [2018-11-18 14:06:30,682 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3122 states and 4182 transitions. [2018-11-18 14:06:30,694 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3122 to 987. [2018-11-18 14:06:30,694 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 987 states. [2018-11-18 14:06:30,695 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 987 states to 987 states and 1331 transitions. [2018-11-18 14:06:30,696 INFO L728 BuchiCegarLoop]: Abstraction has 987 states and 1331 transitions. [2018-11-18 14:06:30,696 INFO L608 BuchiCegarLoop]: Abstraction has 987 states and 1331 transitions. [2018-11-18 14:06:30,696 INFO L442 BuchiCegarLoop]: ======== Iteration 13============ [2018-11-18 14:06:30,696 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 987 states and 1331 transitions. [2018-11-18 14:06:30,698 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 929 [2018-11-18 14:06:30,698 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:06:30,698 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:06:30,699 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:06:30,699 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:06:30,699 INFO L794 eck$LassoCheckResult]: Stem: 22032#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 21873#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 21874#L605 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 22024#L264 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22025#L271 assume 1 == ~m_i~0;~m_st~0 := 0; 22119#L271-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22128#L276-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21993#L281-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21994#L286-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22021#L408 assume !(0 == ~M_E~0); 22143#L408-2 assume !(0 == ~T1_E~0); 21982#L413-1 assume !(0 == ~T2_E~0); 21983#L418-1 assume !(0 == ~T3_E~0); 22051#L423-1 assume !(0 == ~E_1~0); 21906#L428-1 assume !(0 == ~E_2~0); 21907#L433-1 assume !(0 == ~E_3~0); 21914#L438-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 22012#L187 assume !(1 == ~m_pc~0); 22013#L187-2 is_master_triggered_~__retres1~0 := 0; 22041#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 22211#L199 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 22081#L500 assume !(0 != activate_threads_~tmp~1); 22082#L500-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 22086#L206 assume !(1 == ~t1_pc~0); 22191#L206-2 is_transmit1_triggered_~__retres1~1 := 0; 22192#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 21916#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 21917#L508 assume !(0 != activate_threads_~tmp___0~0); 22115#L508-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 22087#L225 assume !(1 == ~t2_pc~0); 21985#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 22083#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 21987#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 21899#L516 assume !(0 != activate_threads_~tmp___1~0); 21900#L516-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 21901#L244 assume !(1 == ~t3_pc~0); 22200#L244-2 is_transmit3_triggered_~__retres1~3 := 0; 22107#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 22108#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 22135#L524 assume !(0 != activate_threads_~tmp___2~0); 22136#L524-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22043#L451 assume !(1 == ~M_E~0); 22044#L451-2 assume !(1 == ~T1_E~0); 22052#L456-1 assume !(1 == ~T2_E~0); 21902#L461-1 assume !(1 == ~T3_E~0); 21903#L466-1 assume !(1 == ~E_1~0); 21913#L471-1 assume !(1 == ~E_2~0); 22164#L476-1 assume !(1 == ~E_3~0); 22186#L481-1 assume { :end_inline_reset_delta_events } true; 22202#L642-3 [2018-11-18 14:06:30,699 INFO L796 eck$LassoCheckResult]: Loop: 22202#L642-3 assume true; 22556#L642-1 assume !false; 22553#L643 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 22530#L383 assume true; 22527#L331-1 assume !false; 22396#L332 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 22394#L299 assume !(0 == ~m_st~0); 22391#L303 assume !(0 == ~t1_st~0); 22390#L307 assume !(0 == ~t2_st~0); 22389#L311 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4 := 0; 22388#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 22387#L322 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 22386#L336 assume !(0 != eval_~tmp~0); 22385#L398 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 22383#L264-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 22381#L408-3 assume 0 == ~M_E~0;~M_E~0 := 1; 22379#L408-5 assume !(0 == ~T1_E~0); 22377#L413-3 assume !(0 == ~T2_E~0); 22375#L418-3 assume !(0 == ~T3_E~0); 22373#L423-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22371#L428-3 assume !(0 == ~E_2~0); 22368#L433-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22366#L438-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 22364#L187-12 assume 1 == ~m_pc~0; 22361#L188-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 22362#L198-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 22395#L199-4 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 22348#L500-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 22349#L500-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 22184#L206-12 assume !(1 == ~t1_pc~0); 22185#L206-14 is_transmit1_triggered_~__retres1~1 := 0; 22617#L217-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 22616#L218-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 22615#L508-12 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 22195#L508-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 22062#L225-12 assume !(1 == ~t2_pc~0); 22026#L225-14 is_transmit2_triggered_~__retres1~2 := 0; 22027#L236-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 22146#L237-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 22147#L516-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 22611#L516-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 22610#L244-12 assume !(1 == ~t3_pc~0); 22609#L244-14 is_transmit3_triggered_~__retres1~3 := 0; 22608#L255-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 22607#L256-4 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 22606#L524-12 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 22605#L524-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22604#L451-3 assume 1 == ~M_E~0;~M_E~0 := 2; 22603#L451-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 22602#L456-3 assume !(1 == ~T2_E~0); 22601#L461-3 assume !(1 == ~T3_E~0); 22600#L466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22599#L471-3 assume !(1 == ~E_2~0); 22598#L476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22597#L481-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 22596#L299-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 22589#L321-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 22587#L322-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 22584#L661 assume !(0 == start_simulation_~tmp~3); 22574#L661-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 22572#L299-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 22569#L321-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 22567#L322-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 22565#L616 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 22563#L623 stop_simulation_#res := stop_simulation_~__retres2~0; 22562#L624 start_simulation_#t~ret11 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 22557#L674 assume !(0 != start_simulation_~tmp___0~1); 22202#L642-3 [2018-11-18 14:06:30,700 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:06:30,700 INFO L82 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 4 times [2018-11-18 14:06:30,700 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:06:30,700 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:06:30,700 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:30,701 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:06:30,701 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:30,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:06:30,706 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:06:30,712 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:06:30,713 INFO L82 PathProgramCache]: Analyzing trace with hash -880791558, now seen corresponding path program 1 times [2018-11-18 14:06:30,713 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:06:30,713 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:06:30,713 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:30,713 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 14:06:30,713 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:30,718 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:06:30,751 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:06:30,751 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:06:30,751 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 14:06:30,751 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 14:06:30,751 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 14:06:30,751 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 14:06:30,752 INFO L87 Difference]: Start difference. First operand 987 states and 1331 transitions. cyclomatic complexity: 348 Second operand 5 states. [2018-11-18 14:06:30,854 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:06:30,854 INFO L93 Difference]: Finished difference Result 1811 states and 2422 transitions. [2018-11-18 14:06:30,855 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 14:06:30,855 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1811 states and 2422 transitions. [2018-11-18 14:06:30,859 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1753 [2018-11-18 14:06:30,862 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1811 states to 1811 states and 2422 transitions. [2018-11-18 14:06:30,862 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1811 [2018-11-18 14:06:30,863 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1811 [2018-11-18 14:06:30,864 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1811 states and 2422 transitions. [2018-11-18 14:06:30,865 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:06:30,865 INFO L705 BuchiCegarLoop]: Abstraction has 1811 states and 2422 transitions. [2018-11-18 14:06:30,866 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1811 states and 2422 transitions. [2018-11-18 14:06:30,874 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1811 to 1017. [2018-11-18 14:06:30,874 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1017 states. [2018-11-18 14:06:30,875 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1017 states to 1017 states and 1352 transitions. [2018-11-18 14:06:30,875 INFO L728 BuchiCegarLoop]: Abstraction has 1017 states and 1352 transitions. [2018-11-18 14:06:30,876 INFO L608 BuchiCegarLoop]: Abstraction has 1017 states and 1352 transitions. [2018-11-18 14:06:30,876 INFO L442 BuchiCegarLoop]: ======== Iteration 14============ [2018-11-18 14:06:30,876 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1017 states and 1352 transitions. [2018-11-18 14:06:30,878 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 959 [2018-11-18 14:06:30,878 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:06:30,878 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:06:30,879 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:06:30,879 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:06:30,879 INFO L794 eck$LassoCheckResult]: Stem: 24844#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 24685#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 24686#L605 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 24836#L264 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24837#L271 assume 1 == ~m_i~0;~m_st~0 := 0; 24932#L271-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24940#L276-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 24804#L281-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 24805#L286-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24835#L408 assume !(0 == ~M_E~0); 24958#L408-2 assume !(0 == ~T1_E~0); 24794#L413-1 assume !(0 == ~T2_E~0); 24795#L418-1 assume !(0 == ~T3_E~0); 24864#L423-1 assume !(0 == ~E_1~0); 24718#L428-1 assume !(0 == ~E_2~0); 24719#L433-1 assume !(0 == ~E_3~0); 24726#L438-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 24824#L187 assume !(1 == ~m_pc~0); 24825#L187-2 is_master_triggered_~__retres1~0 := 0; 24854#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 25033#L199 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 24891#L500 assume !(0 != activate_threads_~tmp~1); 24892#L500-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 24895#L206 assume !(1 == ~t1_pc~0); 25015#L206-2 is_transmit1_triggered_~__retres1~1 := 0; 25016#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 24728#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 24729#L508 assume !(0 != activate_threads_~tmp___0~0); 24928#L508-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 24896#L225 assume !(1 == ~t2_pc~0); 24797#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 24893#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 24799#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 24711#L516 assume !(0 != activate_threads_~tmp___1~0); 24712#L516-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 24713#L244 assume !(1 == ~t3_pc~0); 25025#L244-2 is_transmit3_triggered_~__retres1~3 := 0; 24918#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 24919#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 24948#L524 assume !(0 != activate_threads_~tmp___2~0); 24949#L524-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24856#L451 assume !(1 == ~M_E~0); 24857#L451-2 assume !(1 == ~T1_E~0); 24865#L456-1 assume !(1 == ~T2_E~0); 24714#L461-1 assume !(1 == ~T3_E~0); 24715#L466-1 assume !(1 == ~E_1~0); 24725#L471-1 assume !(1 == ~E_2~0); 24974#L476-1 assume !(1 == ~E_3~0); 25003#L481-1 assume { :end_inline_reset_delta_events } true; 25027#L642-3 [2018-11-18 14:06:30,879 INFO L796 eck$LassoCheckResult]: Loop: 25027#L642-3 assume true; 25239#L642-1 assume !false; 25231#L643 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 25223#L383 assume true; 25224#L331-1 assume !false; 25187#L332 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 25188#L299 assume !(0 == ~m_st~0); 25226#L303 assume !(0 == ~t1_st~0); 25227#L307 assume !(0 == ~t2_st~0); 25225#L311 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4 := 0; 25174#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 25175#L322 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 25131#L336 assume !(0 != eval_~tmp~0); 25132#L398 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 25125#L264-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 25126#L408-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25112#L408-5 assume !(0 == ~T1_E~0); 25113#L413-3 assume !(0 == ~T2_E~0); 25104#L418-3 assume !(0 == ~T3_E~0); 25105#L423-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25096#L428-3 assume !(0 == ~E_2~0); 25097#L433-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25088#L438-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 25089#L187-12 assume 1 == ~m_pc~0; 25074#L188-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 25075#L198-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 25058#L199-4 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 25059#L500-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 25047#L500-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 25048#L206-12 assume !(1 == ~t1_pc~0); 25481#L206-14 is_transmit1_triggered_~__retres1~1 := 0; 25479#L217-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 25477#L218-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 25474#L508-12 assume !(0 != activate_threads_~tmp___0~0); 25472#L508-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 25470#L225-12 assume !(1 == ~t2_pc~0); 25467#L225-14 is_transmit2_triggered_~__retres1~2 := 0; 25465#L236-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 25463#L237-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 25461#L516-12 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 25458#L516-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 25456#L244-12 assume !(1 == ~t3_pc~0); 25454#L244-14 is_transmit3_triggered_~__retres1~3 := 0; 25452#L255-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 25450#L256-4 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 25448#L524-12 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 25446#L524-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25444#L451-3 assume 1 == ~M_E~0;~M_E~0 := 2; 25441#L451-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25438#L456-3 assume !(1 == ~T2_E~0); 25435#L461-3 assume !(1 == ~T3_E~0); 25431#L466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25427#L471-3 assume !(1 == ~E_2~0); 25420#L476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25308#L481-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 25306#L299-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 25299#L321-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 25297#L322-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 25294#L661 assume !(0 == start_simulation_~tmp~3); 25291#L661-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 25285#L299-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 25280#L321-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 25278#L322-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 25276#L616 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 25274#L623 stop_simulation_#res := stop_simulation_~__retres2~0; 25272#L624 start_simulation_#t~ret11 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 25270#L674 assume !(0 != start_simulation_~tmp___0~1); 25027#L642-3 [2018-11-18 14:06:30,879 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:06:30,879 INFO L82 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 5 times [2018-11-18 14:06:30,879 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:06:30,879 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:06:30,880 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:30,880 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:06:30,880 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:30,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:06:30,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:06:30,892 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:06:30,892 INFO L82 PathProgramCache]: Analyzing trace with hash 1170192440, now seen corresponding path program 1 times [2018-11-18 14:06:30,892 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:06:30,892 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:06:30,893 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:30,893 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 14:06:30,893 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:30,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:06:30,942 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:06:30,942 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:06:30,942 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 14:06:30,942 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 14:06:30,942 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 14:06:30,943 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 14:06:30,943 INFO L87 Difference]: Start difference. First operand 1017 states and 1352 transitions. cyclomatic complexity: 339 Second operand 5 states. [2018-11-18 14:06:31,005 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:06:31,005 INFO L93 Difference]: Finished difference Result 1445 states and 1913 transitions. [2018-11-18 14:06:31,006 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 14:06:31,006 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1445 states and 1913 transitions. [2018-11-18 14:06:31,009 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1387 [2018-11-18 14:06:31,012 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1445 states to 1445 states and 1913 transitions. [2018-11-18 14:06:31,012 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1445 [2018-11-18 14:06:31,013 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1445 [2018-11-18 14:06:31,014 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1445 states and 1913 transitions. [2018-11-18 14:06:31,016 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:06:31,016 INFO L705 BuchiCegarLoop]: Abstraction has 1445 states and 1913 transitions. [2018-11-18 14:06:31,017 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1445 states and 1913 transitions. [2018-11-18 14:06:31,025 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1445 to 1023. [2018-11-18 14:06:31,025 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1023 states. [2018-11-18 14:06:31,027 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1023 states to 1023 states and 1341 transitions. [2018-11-18 14:06:31,027 INFO L728 BuchiCegarLoop]: Abstraction has 1023 states and 1341 transitions. [2018-11-18 14:06:31,027 INFO L608 BuchiCegarLoop]: Abstraction has 1023 states and 1341 transitions. [2018-11-18 14:06:31,027 INFO L442 BuchiCegarLoop]: ======== Iteration 15============ [2018-11-18 14:06:31,028 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1023 states and 1341 transitions. [2018-11-18 14:06:31,030 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 965 [2018-11-18 14:06:31,030 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:06:31,030 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:06:31,031 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:06:31,031 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:06:31,031 INFO L794 eck$LassoCheckResult]: Stem: 27330#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 27161#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 27162#L605 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 27322#L264 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27323#L271 assume 1 == ~m_i~0;~m_st~0 := 0; 27420#L271-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 27432#L276-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27290#L281-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27291#L286-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27321#L408 assume !(0 == ~M_E~0); 27454#L408-2 assume !(0 == ~T1_E~0); 27278#L413-1 assume !(0 == ~T2_E~0); 27279#L418-1 assume !(0 == ~T3_E~0); 27350#L423-1 assume !(0 == ~E_1~0); 27195#L428-1 assume !(0 == ~E_2~0); 27196#L433-1 assume !(0 == ~E_3~0); 27204#L438-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 27310#L187 assume !(1 == ~m_pc~0); 27311#L187-2 is_master_triggered_~__retres1~0 := 0; 27313#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 27314#L199 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 27380#L500 assume !(0 != activate_threads_~tmp~1); 27381#L500-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 27385#L206 assume !(1 == ~t1_pc~0); 27507#L206-2 is_transmit1_triggered_~__retres1~1 := 0; 27508#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 27206#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 27207#L508 assume !(0 != activate_threads_~tmp___0~0); 27415#L508-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 27386#L225 assume !(1 == ~t2_pc~0); 27281#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 27382#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 27289#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 27188#L516 assume !(0 != activate_threads_~tmp___1~0); 27189#L516-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 27190#L244 assume !(1 == ~t3_pc~0); 27515#L244-2 is_transmit3_triggered_~__retres1~3 := 0; 27407#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 27408#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 27440#L524 assume !(0 != activate_threads_~tmp___2~0); 27441#L524-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27343#L451 assume !(1 == ~M_E~0); 27344#L451-2 assume !(1 == ~T1_E~0); 27351#L456-1 assume !(1 == ~T2_E~0); 27191#L461-1 assume !(1 == ~T3_E~0); 27192#L466-1 assume !(1 == ~E_1~0); 27203#L471-1 assume !(1 == ~E_2~0); 27474#L476-1 assume !(1 == ~E_3~0); 27498#L481-1 assume { :end_inline_reset_delta_events } true; 27517#L642-3 [2018-11-18 14:06:31,031 INFO L796 eck$LassoCheckResult]: Loop: 27517#L642-3 assume true; 28032#L642-1 assume !false; 28031#L643 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 27766#L383 assume true; 28029#L331-1 assume !false; 28028#L332 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 28023#L299 assume !(0 == ~m_st~0); 28024#L303 assume !(0 == ~t1_st~0); 28027#L307 assume !(0 == ~t2_st~0); 28025#L311 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4 := 0; 28026#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 28018#L322 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 28019#L336 assume !(0 != eval_~tmp~0); 28138#L398 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 28137#L264-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 28136#L408-3 assume 0 == ~M_E~0;~M_E~0 := 1; 28135#L408-5 assume !(0 == ~T1_E~0); 28098#L413-3 assume !(0 == ~T2_E~0); 28057#L418-3 assume !(0 == ~T3_E~0); 28056#L423-3 assume 0 == ~E_1~0;~E_1~0 := 1; 28054#L428-3 assume !(0 == ~E_2~0); 28053#L433-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27225#L438-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 27226#L187-12 assume 1 == ~m_pc~0; 27253#L188-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 27448#L198-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 27449#L199-4 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 27450#L500-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 27367#L500-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 27369#L206-12 assume !(1 == ~t1_pc~0); 27496#L206-14 is_transmit1_triggered_~__retres1~1 := 0; 27497#L217-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 27230#L218-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 27231#L508-12 assume !(0 != activate_threads_~tmp___0~0); 27511#L508-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 27362#L225-12 assume !(1 == ~t2_pc~0); 27324#L225-14 is_transmit2_triggered_~__retres1~2 := 0; 27325#L236-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 27352#L237-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 27154#L516-12 assume !(0 != activate_threads_~tmp___1~0); 27155#L516-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 27156#L244-12 assume !(1 == ~t3_pc~0); 27502#L244-14 is_transmit3_triggered_~__retres1~3 := 0; 27503#L255-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 27468#L256-4 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 27426#L524-12 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 27410#L524-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27353#L451-3 assume 1 == ~M_E~0;~M_E~0 := 2; 27326#L451-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27327#L456-3 assume !(1 == ~T2_E~0); 27197#L461-3 assume !(1 == ~T3_E~0); 27198#L466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 27205#L471-3 assume !(1 == ~E_2~0); 27214#L476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 27484#L481-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 27409#L299-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 27176#L321-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 27402#L322-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 27261#L661 assume !(0 == start_simulation_~tmp~3); 27262#L661-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 28045#L299-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 28041#L321-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 28039#L322-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 28038#L616 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 28036#L623 stop_simulation_#res := stop_simulation_~__retres2~0; 28035#L624 start_simulation_#t~ret11 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 28034#L674 assume !(0 != start_simulation_~tmp___0~1); 27517#L642-3 [2018-11-18 14:06:31,032 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:06:31,032 INFO L82 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 6 times [2018-11-18 14:06:31,032 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:06:31,032 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:06:31,032 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:31,033 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:06:31,033 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:31,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:06:31,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:06:31,044 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:06:31,045 INFO L82 PathProgramCache]: Analyzing trace with hash 660719350, now seen corresponding path program 1 times [2018-11-18 14:06:31,045 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:06:31,045 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:06:31,045 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:31,045 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 14:06:31,045 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:31,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:06:31,095 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:06:31,095 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:06:31,096 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 14:06:31,096 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 14:06:31,096 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 14:06:31,096 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 14:06:31,096 INFO L87 Difference]: Start difference. First operand 1023 states and 1341 transitions. cyclomatic complexity: 322 Second operand 5 states. [2018-11-18 14:06:31,173 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:06:31,174 INFO L93 Difference]: Finished difference Result 1702 states and 2228 transitions. [2018-11-18 14:06:31,174 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 14:06:31,175 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1702 states and 2228 transitions. [2018-11-18 14:06:31,178 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1640 [2018-11-18 14:06:31,183 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1702 states to 1702 states and 2228 transitions. [2018-11-18 14:06:31,183 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1702 [2018-11-18 14:06:31,184 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1702 [2018-11-18 14:06:31,184 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1702 states and 2228 transitions. [2018-11-18 14:06:31,185 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:06:31,185 INFO L705 BuchiCegarLoop]: Abstraction has 1702 states and 2228 transitions. [2018-11-18 14:06:31,186 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1702 states and 2228 transitions. [2018-11-18 14:06:31,194 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1702 to 1050. [2018-11-18 14:06:31,194 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1050 states. [2018-11-18 14:06:31,195 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1050 states to 1050 states and 1358 transitions. [2018-11-18 14:06:31,196 INFO L728 BuchiCegarLoop]: Abstraction has 1050 states and 1358 transitions. [2018-11-18 14:06:31,196 INFO L608 BuchiCegarLoop]: Abstraction has 1050 states and 1358 transitions. [2018-11-18 14:06:31,196 INFO L442 BuchiCegarLoop]: ======== Iteration 16============ [2018-11-18 14:06:31,196 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1050 states and 1358 transitions. [2018-11-18 14:06:31,198 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 992 [2018-11-18 14:06:31,198 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:06:31,198 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:06:31,199 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:06:31,199 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:06:31,199 INFO L794 eck$LassoCheckResult]: Stem: 30064#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 29900#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 29901#L605 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 30056#L264 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30057#L271 assume 1 == ~m_i~0;~m_st~0 := 0; 30145#L271-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 30153#L276-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 30024#L281-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30025#L286-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30055#L408 assume !(0 == ~M_E~0); 30167#L408-2 assume !(0 == ~T1_E~0); 30014#L413-1 assume !(0 == ~T2_E~0); 30015#L418-1 assume !(0 == ~T3_E~0); 30084#L423-1 assume !(0 == ~E_1~0); 29935#L428-1 assume !(0 == ~E_2~0); 29936#L433-1 assume !(0 == ~E_3~0); 29945#L438-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 30043#L187 assume !(1 == ~m_pc~0); 30044#L187-2 is_master_triggered_~__retres1~0 := 0; 30074#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 30232#L199 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 30108#L500 assume !(0 != activate_threads_~tmp~1); 30109#L500-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 30113#L206 assume !(1 == ~t1_pc~0); 30215#L206-2 is_transmit1_triggered_~__retres1~1 := 0; 30216#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 29947#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 29948#L508 assume !(0 != activate_threads_~tmp___0~0); 30141#L508-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 30114#L225 assume !(1 == ~t2_pc~0); 30018#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 30110#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 30023#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 29928#L516 assume !(0 != activate_threads_~tmp___1~0); 29929#L516-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 29930#L244 assume !(1 == ~t3_pc~0); 30224#L244-2 is_transmit3_triggered_~__retres1~3 := 0; 30132#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 30133#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 30159#L524 assume !(0 != activate_threads_~tmp___2~0); 30160#L524-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30078#L451 assume !(1 == ~M_E~0); 30079#L451-2 assume !(1 == ~T1_E~0); 30085#L456-1 assume !(1 == ~T2_E~0); 29931#L461-1 assume !(1 == ~T3_E~0); 29932#L466-1 assume !(1 == ~E_1~0); 29944#L471-1 assume !(1 == ~E_2~0); 30187#L476-1 assume !(1 == ~E_3~0); 30206#L481-1 assume { :end_inline_reset_delta_events } true; 30227#L642-3 [2018-11-18 14:06:31,199 INFO L796 eck$LassoCheckResult]: Loop: 30227#L642-3 assume true; 30613#L642-1 assume !false; 30610#L643 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 30609#L383 assume true; 30608#L331-1 assume !false; 30607#L332 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 30606#L299 assume !(0 == ~m_st~0); 30605#L303 assume !(0 == ~t1_st~0); 30604#L307 assume !(0 == ~t2_st~0); 30602#L311 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4 := 0; 30601#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 30600#L322 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 30599#L336 assume !(0 != eval_~tmp~0); 30598#L398 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 30597#L264-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 30596#L408-3 assume 0 == ~M_E~0;~M_E~0 := 1; 30595#L408-5 assume !(0 == ~T1_E~0); 30594#L413-3 assume !(0 == ~T2_E~0); 30593#L418-3 assume !(0 == ~T3_E~0); 30592#L423-3 assume 0 == ~E_1~0;~E_1~0 := 1; 30591#L428-3 assume !(0 == ~E_2~0); 30590#L433-3 assume 0 == ~E_3~0;~E_3~0 := 1; 30589#L438-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 30588#L187-12 assume 1 == ~m_pc~0; 30585#L188-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 30582#L198-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 30579#L199-4 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 30576#L500-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 30574#L500-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 30572#L206-12 assume !(1 == ~t1_pc~0); 30570#L206-14 is_transmit1_triggered_~__retres1~1 := 0; 30567#L217-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 30563#L218-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 30559#L508-12 assume !(0 != activate_threads_~tmp___0~0); 30555#L508-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 30550#L225-12 assume !(1 == ~t2_pc~0); 30545#L225-14 is_transmit2_triggered_~__retres1~2 := 0; 30541#L236-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 30536#L237-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 30532#L516-12 assume !(0 != activate_threads_~tmp___1~0); 30528#L516-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 30211#L244-12 assume !(1 == ~t3_pc~0); 30212#L244-14 is_transmit3_triggered_~__retres1~3 := 0; 30731#L255-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 30730#L256-4 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 30729#L524-12 assume !(0 != activate_threads_~tmp___2~0); 30728#L524-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30727#L451-3 assume 1 == ~M_E~0;~M_E~0 := 2; 30725#L451-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 30722#L456-3 assume !(1 == ~T2_E~0); 30719#L461-3 assume !(1 == ~T3_E~0); 30716#L466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 30712#L471-3 assume !(1 == ~E_2~0); 30708#L476-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30704#L481-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 30700#L299-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 30694#L321-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 30690#L322-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 30685#L661 assume !(0 == start_simulation_~tmp~3); 30681#L661-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 30677#L299-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 30672#L321-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 30669#L322-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 30664#L616 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 30661#L623 stop_simulation_#res := stop_simulation_~__retres2~0; 30659#L624 start_simulation_#t~ret11 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 30657#L674 assume !(0 != start_simulation_~tmp___0~1); 30227#L642-3 [2018-11-18 14:06:31,199 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:06:31,200 INFO L82 PathProgramCache]: Analyzing trace with hash 374468594, now seen corresponding path program 7 times [2018-11-18 14:06:31,200 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:06:31,200 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:06:31,200 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:31,200 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:06:31,200 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:31,203 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:06:31,206 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:06:31,211 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:06:31,211 INFO L82 PathProgramCache]: Analyzing trace with hash 879574068, now seen corresponding path program 1 times [2018-11-18 14:06:31,211 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:06:31,211 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:06:31,212 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:31,212 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:06:31,212 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:31,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:06:31,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:06:31,226 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:06:31,226 INFO L82 PathProgramCache]: Analyzing trace with hash 715358883, now seen corresponding path program 1 times [2018-11-18 14:06:31,226 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:06:31,226 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:06:31,227 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:31,227 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:06:31,227 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:31,231 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:06:31,266 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:06:31,266 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:06:31,266 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:06:31,504 WARN L180 SmtUtils]: Spent 232.00 ms on a formula simplification. DAG size of input: 134 DAG size of output: 121 [2018-11-18 14:06:31,631 WARN L180 SmtUtils]: Spent 119.00 ms on a formula simplification that was a NOOP. DAG size: 103 [2018-11-18 14:06:31,642 INFO L216 LassoAnalysis]: Preferences: [2018-11-18 14:06:31,643 INFO L124 ssoRankerPreferences]: Compute integeral hull: false [2018-11-18 14:06:31,643 INFO L125 ssoRankerPreferences]: Enable LassoPartitioneer: true [2018-11-18 14:06:31,643 INFO L126 ssoRankerPreferences]: Term annotations enabled: false [2018-11-18 14:06:31,643 INFO L127 ssoRankerPreferences]: Use exernal solver: true [2018-11-18 14:06:31,643 INFO L128 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 14:06:31,644 INFO L129 ssoRankerPreferences]: Dump SMT script to file: false [2018-11-18 14:06:31,644 INFO L130 ssoRankerPreferences]: Path of dumped script: [2018-11-18 14:06:31,644 INFO L131 ssoRankerPreferences]: Filename of dumped script: transmitter.03_false-unreach-call_false-termination.cil.c_Iteration16_Loop [2018-11-18 14:06:31,644 INFO L132 ssoRankerPreferences]: MapElimAlgo: Frank [2018-11-18 14:06:31,644 INFO L282 LassoAnalysis]: Starting lasso preprocessing... [2018-11-18 14:06:31,661 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:31,668 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:31,670 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:31,676 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:31,679 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:31,681 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:31,683 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:31,690 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:31,693 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:31,696 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:31,699 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:31,704 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:31,707 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:31,709 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:31,714 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:31,717 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:31,721 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:31,725 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:31,727 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:31,729 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:31,738 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:31,742 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:31,743 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:31,755 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:31,759 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:31,762 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:31,768 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:31,770 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:31,777 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:31,780 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:31,783 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:31,786 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:31,789 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:31,791 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:31,794 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:31,801 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:31,804 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:31,810 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:31,813 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:31,821 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:31,823 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:32,082 INFO L300 LassoAnalysis]: Preprocessing complete. [2018-11-18 14:06:32,082 INFO L412 LassoAnalysis]: Checking for nontermination... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9edd41f0-bb38-47c2-83e2-42ee9941d34f/bin-2019/uautomizer/z3 Starting monitored process 2 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 14:06:32,091 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-18 14:06:32,091 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-18 14:06:32,097 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-18 14:06:32,097 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_~tmp___1~0=0} Honda state: {ULTIMATE.start_activate_threads_~tmp___1~0=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9edd41f0-bb38-47c2-83e2-42ee9941d34f/bin-2019/uautomizer/z3 Starting monitored process 3 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 14:06:32,131 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-18 14:06:32,131 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-18 14:06:32,134 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-18 14:06:32,134 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t2_st~0=7} Honda state: {~t2_st~0=7} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9edd41f0-bb38-47c2-83e2-42ee9941d34f/bin-2019/uautomizer/z3 Starting monitored process 4 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 14:06:32,160 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-18 14:06:32,161 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-18 14:06:32,164 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-18 14:06:32,164 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_stop_simulation_~__retres2~0=0, ULTIMATE.start_start_simulation_~tmp___0~1=0, ULTIMATE.start_stop_simulation_#res=0} Honda state: {ULTIMATE.start_stop_simulation_~__retres2~0=0, ULTIMATE.start_start_simulation_~tmp___0~1=0, ULTIMATE.start_stop_simulation_#res=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9edd41f0-bb38-47c2-83e2-42ee9941d34f/bin-2019/uautomizer/z3 Starting monitored process 5 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 14:06:32,186 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-18 14:06:32,187 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-18 14:06:32,189 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-18 14:06:32,189 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret5=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret5=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9edd41f0-bb38-47c2-83e2-42ee9941d34f/bin-2019/uautomizer/z3 Starting monitored process 6 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 14:06:32,210 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-18 14:06:32,211 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-18 14:06:32,213 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-18 14:06:32,213 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_3~0=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_3~0=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9edd41f0-bb38-47c2-83e2-42ee9941d34f/bin-2019/uautomizer/z3 Starting monitored process 7 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 14:06:32,234 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-18 14:06:32,234 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-18 14:06:32,236 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-18 14:06:32,237 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_#t~ret10=0} Honda state: {ULTIMATE.start_start_simulation_#t~ret10=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9edd41f0-bb38-47c2-83e2-42ee9941d34f/bin-2019/uautomizer/z3 Starting monitored process 8 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 14:06:32,260 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-18 14:06:32,260 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-18 14:06:32,274 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-18 14:06:32,274 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit3_triggered_#res=0, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=0, ULTIMATE.start_activate_threads_~tmp___2~0=0} Honda state: {ULTIMATE.start_is_transmit3_triggered_#res=0, ULTIMATE.start_is_transmit3_triggered_~__retres1~3=0, ULTIMATE.start_activate_threads_~tmp___2~0=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9edd41f0-bb38-47c2-83e2-42ee9941d34f/bin-2019/uautomizer/z3 Starting monitored process 9 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 14:06:32,311 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-18 14:06:32,311 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-18 14:06:32,313 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-18 14:06:32,313 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t1_pc~0=4} Honda state: {~t1_pc~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9edd41f0-bb38-47c2-83e2-42ee9941d34f/bin-2019/uautomizer/z3 Starting monitored process 10 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 14:06:32,338 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-18 14:06:32,338 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-18 14:06:32,340 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-18 14:06:32,340 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_#t~ret11=0} Honda state: {ULTIMATE.start_start_simulation_#t~ret11=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9edd41f0-bb38-47c2-83e2-42ee9941d34f/bin-2019/uautomizer/z3 Starting monitored process 11 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 14:06:32,357 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-18 14:06:32,357 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-18 14:06:32,360 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-18 14:06:32,360 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t3_pc~0=4} Honda state: {~t3_pc~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9edd41f0-bb38-47c2-83e2-42ee9941d34f/bin-2019/uautomizer/z3 Starting monitored process 12 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 14:06:32,376 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-18 14:06:32,376 INFO L163 nArgumentSynthesizer]: Using integer mode. No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9edd41f0-bb38-47c2-83e2-42ee9941d34f/bin-2019/uautomizer/z3 Starting monitored process 13 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 14:06:32,396 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2018-11-18 14:06:32,396 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-18 14:06:32,399 INFO L452 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2018-11-18 14:06:32,413 INFO L216 LassoAnalysis]: Preferences: [2018-11-18 14:06:32,413 INFO L124 ssoRankerPreferences]: Compute integeral hull: false [2018-11-18 14:06:32,413 INFO L125 ssoRankerPreferences]: Enable LassoPartitioneer: true [2018-11-18 14:06:32,413 INFO L126 ssoRankerPreferences]: Term annotations enabled: false [2018-11-18 14:06:32,413 INFO L127 ssoRankerPreferences]: Use exernal solver: false [2018-11-18 14:06:32,413 INFO L128 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 14:06:32,413 INFO L129 ssoRankerPreferences]: Dump SMT script to file: false [2018-11-18 14:06:32,413 INFO L130 ssoRankerPreferences]: Path of dumped script: [2018-11-18 14:06:32,413 INFO L131 ssoRankerPreferences]: Filename of dumped script: transmitter.03_false-unreach-call_false-termination.cil.c_Iteration16_Loop [2018-11-18 14:06:32,413 INFO L132 ssoRankerPreferences]: MapElimAlgo: Frank [2018-11-18 14:06:32,414 INFO L282 LassoAnalysis]: Starting lasso preprocessing... [2018-11-18 14:06:32,416 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:32,431 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:32,434 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:32,436 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:32,438 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:32,441 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:32,444 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:32,446 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:32,449 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:32,457 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:32,466 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:32,468 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:32,472 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:32,473 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:32,476 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:32,478 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:32,479 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:32,480 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:32,481 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:32,485 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:32,487 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:32,492 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:32,494 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:32,499 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:32,501 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:32,505 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:32,506 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:32,509 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:32,513 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:32,514 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:32,515 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:32,519 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:32,534 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:32,537 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:32,540 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:32,542 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:32,544 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:32,549 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:32,551 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:32,562 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:32,565 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:32,855 INFO L300 LassoAnalysis]: Preprocessing complete. [2018-11-18 14:06:32,860 INFO L497 LassoAnalysis]: Using template 'affine'. [2018-11-18 14:06:32,862 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-18 14:06:32,863 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-18 14:06:32,863 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-18 14:06:32,864 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-18 14:06:32,864 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-18 14:06:32,864 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-18 14:06:32,866 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-18 14:06:32,866 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-18 14:06:32,868 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-18 14:06:32,868 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-18 14:06:32,869 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-18 14:06:32,869 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-18 14:06:32,869 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-18 14:06:32,869 INFO L206 nArgumentSynthesizer]: 2 loop disjuncts [2018-11-18 14:06:32,869 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-18 14:06:32,870 INFO L402 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2018-11-18 14:06:32,870 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-18 14:06:32,871 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-18 14:06:32,871 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-18 14:06:32,871 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-18 14:06:32,872 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-18 14:06:32,872 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-18 14:06:32,872 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-18 14:06:32,872 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-18 14:06:32,872 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-18 14:06:32,872 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-18 14:06:32,873 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-18 14:06:32,873 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-18 14:06:32,874 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-18 14:06:32,874 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-18 14:06:32,874 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-18 14:06:32,874 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-18 14:06:32,874 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-18 14:06:32,874 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-18 14:06:32,874 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-18 14:06:32,875 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-18 14:06:32,875 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-18 14:06:32,875 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-18 14:06:32,875 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-18 14:06:32,876 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-18 14:06:32,876 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-18 14:06:32,876 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-18 14:06:32,876 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-18 14:06:32,876 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-18 14:06:32,877 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-18 14:06:32,877 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-18 14:06:32,877 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-18 14:06:32,877 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-18 14:06:32,877 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-18 14:06:32,877 INFO L206 nArgumentSynthesizer]: 2 loop disjuncts [2018-11-18 14:06:32,878 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-18 14:06:32,878 INFO L402 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2018-11-18 14:06:32,878 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-18 14:06:32,879 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-18 14:06:32,879 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-18 14:06:32,879 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-18 14:06:32,879 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-18 14:06:32,880 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-18 14:06:32,880 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-18 14:06:32,880 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-18 14:06:32,880 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-18 14:06:32,880 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-18 14:06:32,881 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-18 14:06:32,881 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-18 14:06:32,881 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-18 14:06:32,881 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-18 14:06:32,881 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-18 14:06:32,881 INFO L206 nArgumentSynthesizer]: 2 loop disjuncts [2018-11-18 14:06:32,882 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-18 14:06:32,882 INFO L402 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2018-11-18 14:06:32,882 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-18 14:06:32,883 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-18 14:06:32,883 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-18 14:06:32,883 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-18 14:06:32,883 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-18 14:06:32,883 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-18 14:06:32,883 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-18 14:06:32,883 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-18 14:06:32,884 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-18 14:06:32,884 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-18 14:06:32,886 INFO L421 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2018-11-18 14:06:32,887 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2018-11-18 14:06:32,887 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2018-11-18 14:06:32,889 INFO L437 nArgumentSynthesizer]: Simplifying supporting invariants... [2018-11-18 14:06:32,889 INFO L440 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2018-11-18 14:06:32,889 INFO L518 LassoAnalysis]: Proved termination. [2018-11-18 14:06:32,890 INFO L520 LassoAnalysis]: Termination argument consisting of: Ranking function f(~E_3~0) = -1*~E_3~0 + 1 Supporting invariants [] [2018-11-18 14:06:32,890 INFO L297 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2018-11-18 14:06:32,974 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:06:32,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:06:32,999 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 14:06:33,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:06:33,029 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 14:06:33,058 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:06:33,061 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2018-11-18 14:06:33,061 INFO L72 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 1050 states and 1358 transitions. cyclomatic complexity: 312 Second operand 5 states. [2018-11-18 14:06:33,171 INFO L76 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 1050 states and 1358 transitions. cyclomatic complexity: 312. Second operand 5 states. Result 2796 states and 3643 transitions. Complement of second has 5 states. [2018-11-18 14:06:33,173 INFO L142 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2018-11-18 14:06:33,173 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5 states. [2018-11-18 14:06:33,174 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 359 transitions. [2018-11-18 14:06:33,175 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 359 transitions. Stem has 49 letters. Loop has 67 letters. [2018-11-18 14:06:33,177 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2018-11-18 14:06:33,177 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 359 transitions. Stem has 116 letters. Loop has 67 letters. [2018-11-18 14:06:33,182 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2018-11-18 14:06:33,182 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 359 transitions. Stem has 49 letters. Loop has 134 letters. [2018-11-18 14:06:33,182 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2018-11-18 14:06:33,183 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2796 states and 3643 transitions. [2018-11-18 14:06:33,192 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 1844 [2018-11-18 14:06:33,202 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2796 states to 2792 states and 3639 transitions. [2018-11-18 14:06:33,202 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1911 [2018-11-18 14:06:33,204 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1924 [2018-11-18 14:06:33,204 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2792 states and 3639 transitions. [2018-11-18 14:06:33,205 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-18 14:06:33,205 INFO L705 BuchiCegarLoop]: Abstraction has 2792 states and 3639 transitions. [2018-11-18 14:06:33,207 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2792 states and 3639 transitions. [2018-11-18 14:06:33,235 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2792 to 2775. [2018-11-18 14:06:33,235 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2775 states. [2018-11-18 14:06:33,241 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2775 states to 2775 states and 3614 transitions. [2018-11-18 14:06:33,241 INFO L728 BuchiCegarLoop]: Abstraction has 2775 states and 3614 transitions. [2018-11-18 14:06:33,241 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 14:06:33,241 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 14:06:33,241 INFO L87 Difference]: Start difference. First operand 2775 states and 3614 transitions. Second operand 3 states. [2018-11-18 14:06:33,316 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:06:33,316 INFO L93 Difference]: Finished difference Result 4891 states and 6219 transitions. [2018-11-18 14:06:33,316 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 14:06:33,317 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4891 states and 6219 transitions. [2018-11-18 14:06:33,359 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3288 [2018-11-18 14:06:33,374 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4891 states to 4891 states and 6219 transitions. [2018-11-18 14:06:33,374 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3359 [2018-11-18 14:06:33,376 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3359 [2018-11-18 14:06:33,376 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4891 states and 6219 transitions. [2018-11-18 14:06:33,377 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-18 14:06:33,377 INFO L705 BuchiCegarLoop]: Abstraction has 4891 states and 6219 transitions. [2018-11-18 14:06:33,379 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4891 states and 6219 transitions. [2018-11-18 14:06:33,424 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4891 to 4555. [2018-11-18 14:06:33,424 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4555 states. [2018-11-18 14:06:33,433 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4555 states to 4555 states and 5835 transitions. [2018-11-18 14:06:33,433 INFO L728 BuchiCegarLoop]: Abstraction has 4555 states and 5835 transitions. [2018-11-18 14:06:33,433 INFO L608 BuchiCegarLoop]: Abstraction has 4555 states and 5835 transitions. [2018-11-18 14:06:33,433 INFO L442 BuchiCegarLoop]: ======== Iteration 17============ [2018-11-18 14:06:33,433 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4555 states and 5835 transitions. [2018-11-18 14:06:33,443 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3064 [2018-11-18 14:06:33,443 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:06:33,443 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:06:33,444 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:06:33,444 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:06:33,445 INFO L794 eck$LassoCheckResult]: Stem: 42088#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 41792#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 41793#L605 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 42072#L264 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 42073#L271 assume 1 == ~m_i~0;~m_st~0 := 0; 42249#L271-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 42263#L276-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 42017#L281-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 42018#L286-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 42071#L408 assume !(0 == ~M_E~0); 42301#L408-2 assume !(0 == ~T1_E~0); 41997#L413-1 assume !(0 == ~T2_E~0); 41998#L418-1 assume !(0 == ~T3_E~0); 42128#L423-1 assume !(0 == ~E_1~0); 41854#L428-1 assume !(0 == ~E_2~0); 41855#L433-1 assume !(0 == ~E_3~0); 41872#L438-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 42053#L187 assume !(1 == ~m_pc~0); 42054#L187-2 is_master_triggered_~__retres1~0 := 0; 42110#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 42438#L199 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 42175#L500 assume !(0 != activate_threads_~tmp~1); 42176#L500-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 42180#L206 assume !(1 == ~t1_pc~0); 42406#L206-2 is_transmit1_triggered_~__retres1~1 := 0; 42407#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 41875#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 41876#L508 assume !(0 != activate_threads_~tmp___0~0); 42244#L508-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 42181#L225 assume !(1 == ~t2_pc~0); 42000#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 42177#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 42007#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 41842#L516 assume !(0 != activate_threads_~tmp___1~0); 41843#L516-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 41847#L244 assume !(1 == ~t3_pc~0); 42422#L244-2 is_transmit3_triggered_~__retres1~3 := 0; 42225#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 42226#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 42283#L524 assume !(0 != activate_threads_~tmp___2~0); 42284#L524-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 42117#L451 assume !(1 == ~M_E~0); 42118#L451-2 assume !(1 == ~T1_E~0); 42129#L456-1 assume !(1 == ~T2_E~0); 41848#L461-1 assume !(1 == ~T3_E~0); 41849#L466-1 assume !(1 == ~E_1~0); 41871#L471-1 assume !(1 == ~E_2~0); 42336#L476-1 assume !(1 == ~E_3~0); 42392#L481-1 assume { :end_inline_reset_delta_events } true; 42426#L642-3 assume true; 43069#L642-1 [2018-11-18 14:06:33,445 INFO L796 eck$LassoCheckResult]: Loop: 43069#L642-1 assume !false; 44626#L643 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 44625#L383 assume true; 44624#L331-1 assume !false; 44623#L332 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 44622#L299 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 44378#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 44621#L322 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 44620#L336 assume 0 != eval_~tmp~0; 44619#L336-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 43781#L344 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1;assume { :begin_inline_master } true; 41808#L43 assume !(0 == ~m_pc~0); 41810#L46 assume 1 == ~m_pc~0; 42239#L47 assume true; 42311#L62-1 assume !false; 43788#L63 ~m_pc~0 := 1;~m_st~0 := 2; 43782#L73 assume { :end_inline_master } true; 43780#L341 assume !(0 == ~t1_st~0); 43731#L355 assume !(0 == ~t2_st~0); 44353#L369 assume !(0 == ~t3_st~0); 44381#L383 assume true; 44380#L331-1 assume !false; 44379#L332 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 44377#L299 assume !(0 == ~m_st~0); 44375#L303 assume !(0 == ~t1_st~0); 44376#L307 assume !(0 == ~t2_st~0); 44373#L311 assume !(0 == ~t3_st~0);exists_runnable_thread_~__retres1~4 := 0; 44374#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 44736#L322 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 44735#L336 assume !(0 != eval_~tmp~0); 44734#L398 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 44733#L264-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 44731#L408-3 assume 0 == ~M_E~0;~M_E~0 := 1; 44728#L408-5 assume !(0 == ~T1_E~0); 44726#L413-3 assume !(0 == ~T2_E~0); 44724#L418-3 assume !(0 == ~T3_E~0); 44723#L423-3 assume 0 == ~E_1~0;~E_1~0 := 1; 44722#L428-3 assume !(0 == ~E_2~0); 44720#L433-3 assume !(0 == ~E_3~0); 44719#L438-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 44718#L187-12 assume 1 == ~m_pc~0; 44716#L188-4 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 44715#L198-4 is_master_triggered_#res := is_master_triggered_~__retres1~0; 44714#L199-4 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 44710#L500-12 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 44708#L500-14 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 44706#L206-12 assume !(1 == ~t1_pc~0); 44704#L206-14 is_transmit1_triggered_~__retres1~1 := 0; 44700#L217-4 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 44698#L218-4 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 44696#L508-12 assume !(0 != activate_threads_~tmp___0~0); 44694#L508-14 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 44692#L225-12 assume !(1 == ~t2_pc~0); 44689#L225-14 is_transmit2_triggered_~__retres1~2 := 0; 44687#L236-4 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 44685#L237-4 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 44682#L516-12 assume !(0 != activate_threads_~tmp___1~0); 44680#L516-14 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 44678#L244-12 assume !(1 == ~t3_pc~0); 44676#L244-14 is_transmit3_triggered_~__retres1~3 := 0; 44674#L255-4 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 44672#L256-4 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 44670#L524-12 assume !(0 != activate_threads_~tmp___2~0); 44668#L524-14 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44666#L451-3 assume 1 == ~M_E~0;~M_E~0 := 2; 44664#L451-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 44662#L456-3 assume !(1 == ~T2_E~0); 44660#L461-3 assume !(1 == ~T3_E~0); 44658#L466-3 assume 1 == ~E_1~0;~E_1~0 := 2; 44656#L471-3 assume !(1 == ~E_2~0); 44654#L476-3 assume !(1 == ~E_3~0); 44650#L481-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 44648#L299-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 44418#L321-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 44647#L322-1 start_simulation_#t~ret10 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret10;havoc start_simulation_#t~ret10; 44645#L661 assume !(0 == start_simulation_~tmp~3); 44643#L661-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret9, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 44642#L299-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 44403#L321-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 44641#L322-2 stop_simulation_#t~ret9 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret9;havoc stop_simulation_#t~ret9; 44640#L616 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 44639#L623 stop_simulation_#res := stop_simulation_~__retres2~0; 44638#L624 start_simulation_#t~ret11 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret11;havoc start_simulation_#t~ret11; 44637#L674 assume !(0 != start_simulation_~tmp___0~1); 44635#L642-3 assume true; 43069#L642-1 [2018-11-18 14:06:33,446 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:06:33,446 INFO L82 PathProgramCache]: Analyzing trace with hash -1276375257, now seen corresponding path program 1 times [2018-11-18 14:06:33,446 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:06:33,446 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:06:33,446 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:33,447 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:06:33,447 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:33,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:06:33,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:06:33,456 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:06:33,456 INFO L82 PathProgramCache]: Analyzing trace with hash -1047158819, now seen corresponding path program 1 times [2018-11-18 14:06:33,456 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:06:33,456 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:06:33,457 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:33,457 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:06:33,457 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:33,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:06:33,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:06:33,473 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:06:33,473 INFO L82 PathProgramCache]: Analyzing trace with hash 570479735, now seen corresponding path program 1 times [2018-11-18 14:06:33,473 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:06:33,473 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:06:33,474 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:33,474 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:06:33,474 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:33,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:06:33,535 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:06:33,535 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:06:33,535 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 14:06:33,854 WARN L180 SmtUtils]: Spent 315.00 ms on a formula simplification. DAG size of input: 155 DAG size of output: 136 [2018-11-18 14:06:33,923 INFO L216 LassoAnalysis]: Preferences: [2018-11-18 14:06:33,923 INFO L124 ssoRankerPreferences]: Compute integeral hull: false [2018-11-18 14:06:33,923 INFO L125 ssoRankerPreferences]: Enable LassoPartitioneer: true [2018-11-18 14:06:33,923 INFO L126 ssoRankerPreferences]: Term annotations enabled: false [2018-11-18 14:06:33,923 INFO L127 ssoRankerPreferences]: Use exernal solver: true [2018-11-18 14:06:33,923 INFO L128 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 14:06:33,923 INFO L129 ssoRankerPreferences]: Dump SMT script to file: false [2018-11-18 14:06:33,923 INFO L130 ssoRankerPreferences]: Path of dumped script: [2018-11-18 14:06:33,923 INFO L131 ssoRankerPreferences]: Filename of dumped script: transmitter.03_false-unreach-call_false-termination.cil.c_Iteration17_Loop [2018-11-18 14:06:33,923 INFO L132 ssoRankerPreferences]: MapElimAlgo: Frank [2018-11-18 14:06:33,923 INFO L282 LassoAnalysis]: Starting lasso preprocessing... [2018-11-18 14:06:33,925 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:33,927 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:33,932 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:33,933 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:33,935 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:33,936 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:33,937 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:33,938 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:33,939 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:33,946 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:33,948 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:33,950 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:33,951 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:33,954 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:33,957 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:33,961 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:33,965 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:33,967 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:33,969 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:33,970 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:33,971 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:33,973 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:33,974 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:33,977 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:33,979 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:33,980 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:33,982 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:33,984 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:33,987 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:33,989 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:33,996 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:33,999 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:34,001 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:34,003 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:34,004 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:34,008 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:34,010 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:34,011 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:34,014 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:34,018 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:34,027 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:34,031 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:34,239 INFO L300 LassoAnalysis]: Preprocessing complete. [2018-11-18 14:06:34,240 INFO L412 LassoAnalysis]: Checking for nontermination... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9edd41f0-bb38-47c2-83e2-42ee9941d34f/bin-2019/uautomizer/z3 Starting monitored process 14 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 14:06:34,244 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-18 14:06:34,244 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-18 14:06:34,247 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-18 14:06:34,247 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_#t~ret11=0} Honda state: {ULTIMATE.start_start_simulation_#t~ret11=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9edd41f0-bb38-47c2-83e2-42ee9941d34f/bin-2019/uautomizer/z3 Starting monitored process 15 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 14:06:34,262 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-18 14:06:34,262 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-18 14:06:34,265 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-18 14:06:34,265 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~E_3~0=-5} Honda state: {~E_3~0=-5} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9edd41f0-bb38-47c2-83e2-42ee9941d34f/bin-2019/uautomizer/z3 Starting monitored process 16 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 14:06:34,282 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-18 14:06:34,282 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-18 14:06:34,284 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-18 14:06:34,284 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t2_st~0=7} Honda state: {~t2_st~0=7} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9edd41f0-bb38-47c2-83e2-42ee9941d34f/bin-2019/uautomizer/z3 Starting monitored process 17 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 14:06:34,301 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-18 14:06:34,301 INFO L163 nArgumentSynthesizer]: Using integer mode. No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_9edd41f0-bb38-47c2-83e2-42ee9941d34f/bin-2019/uautomizer/z3 Starting monitored process 18 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 14:06:34,318 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2018-11-18 14:06:34,318 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-18 14:06:34,321 INFO L452 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2018-11-18 14:06:34,335 INFO L216 LassoAnalysis]: Preferences: [2018-11-18 14:06:34,335 INFO L124 ssoRankerPreferences]: Compute integeral hull: false [2018-11-18 14:06:34,335 INFO L125 ssoRankerPreferences]: Enable LassoPartitioneer: true [2018-11-18 14:06:34,335 INFO L126 ssoRankerPreferences]: Term annotations enabled: false [2018-11-18 14:06:34,335 INFO L127 ssoRankerPreferences]: Use exernal solver: false [2018-11-18 14:06:34,335 INFO L128 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 14:06:34,335 INFO L129 ssoRankerPreferences]: Dump SMT script to file: false [2018-11-18 14:06:34,335 INFO L130 ssoRankerPreferences]: Path of dumped script: [2018-11-18 14:06:34,335 INFO L131 ssoRankerPreferences]: Filename of dumped script: transmitter.03_false-unreach-call_false-termination.cil.c_Iteration17_Loop [2018-11-18 14:06:34,335 INFO L132 ssoRankerPreferences]: MapElimAlgo: Frank [2018-11-18 14:06:34,335 INFO L282 LassoAnalysis]: Starting lasso preprocessing... [2018-11-18 14:06:34,338 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:34,347 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:34,364 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:34,365 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:34,367 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:34,377 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:34,378 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:34,381 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:34,382 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:34,384 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:34,385 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:34,388 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:34,389 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:34,392 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:34,393 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:34,395 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:34,398 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:34,399 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:34,403 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:34,405 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:34,406 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:34,407 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:34,408 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:34,410 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:34,413 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:34,416 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:34,418 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:34,422 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:34,424 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:34,427 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:34,429 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:34,432 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:34,433 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:34,435 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:34,437 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:34,450 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:34,453 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:34,455 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:34,460 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:34,464 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:34,465 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:34,467 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:06:34,707 INFO L300 LassoAnalysis]: Preprocessing complete. [2018-11-18 14:06:34,707 INFO L497 LassoAnalysis]: Using template 'affine'. [2018-11-18 14:06:34,707 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-18 14:06:34,708 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-18 14:06:34,708 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-18 14:06:34,708 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-18 14:06:34,708 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-18 14:06:34,708 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-18 14:06:34,708 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-18 14:06:34,708 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-18 14:06:34,709 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-18 14:06:34,709 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-18 14:06:34,709 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-18 14:06:34,710 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-18 14:06:34,710 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-18 14:06:34,710 INFO L206 nArgumentSynthesizer]: 2 loop disjuncts [2018-11-18 14:06:34,710 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-18 14:06:34,710 INFO L402 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2018-11-18 14:06:34,710 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-18 14:06:34,711 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-18 14:06:34,711 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-18 14:06:34,711 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-18 14:06:34,711 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-18 14:06:34,711 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-18 14:06:34,711 INFO L206 nArgumentSynthesizer]: 2 loop disjuncts [2018-11-18 14:06:34,711 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-18 14:06:34,712 INFO L402 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2018-11-18 14:06:34,712 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-18 14:06:34,712 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-18 14:06:34,712 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-18 14:06:34,712 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-18 14:06:34,712 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-18 14:06:34,713 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-18 14:06:34,713 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-18 14:06:34,713 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-18 14:06:34,713 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-18 14:06:34,713 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-18 14:06:34,713 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-18 14:06:34,713 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-18 14:06:34,713 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-18 14:06:34,714 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-18 14:06:34,714 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-18 14:06:34,714 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-18 14:06:34,714 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-18 14:06:34,714 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-18 14:06:34,714 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-18 14:06:34,716 INFO L421 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2018-11-18 14:06:34,717 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2018-11-18 14:06:34,717 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2018-11-18 14:06:34,717 INFO L437 nArgumentSynthesizer]: Simplifying supporting invariants... [2018-11-18 14:06:34,717 INFO L440 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2018-11-18 14:06:34,717 INFO L518 LassoAnalysis]: Proved termination. [2018-11-18 14:06:34,717 INFO L520 LassoAnalysis]: Termination argument consisting of: Ranking function f(~T1_E~0) = -2*~T1_E~0 + 3 Supporting invariants [] [2018-11-18 14:06:34,717 INFO L297 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2018-11-18 14:06:34,788 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:06:34,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:06:34,807 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 14:06:34,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:06:34,829 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 14:06:34,869 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-11-18 14:06:34,869 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2018-11-18 14:06:34,869 INFO L72 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 4555 states and 5835 transitions. cyclomatic complexity: 1292 Second operand 4 states. [2018-11-18 14:06:34,937 INFO L76 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 4555 states and 5835 transitions. cyclomatic complexity: 1292. Second operand 4 states. Result 9178 states and 11734 transitions. Complement of second has 4 states. [2018-11-18 14:06:34,938 INFO L142 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2018-11-18 14:06:34,938 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4 states. [2018-11-18 14:06:34,940 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 400 transitions. [2018-11-18 14:06:34,940 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 400 transitions. Stem has 50 letters. Loop has 85 letters. [2018-11-18 14:06:34,941 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2018-11-18 14:06:34,941 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 400 transitions. Stem has 135 letters. Loop has 85 letters. [2018-11-18 14:06:34,941 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2018-11-18 14:06:34,941 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 400 transitions. Stem has 50 letters. Loop has 170 letters. [2018-11-18 14:06:34,942 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2018-11-18 14:06:34,942 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9178 states and 11734 transitions. [2018-11-18 14:06:34,971 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3064 [2018-11-18 14:06:34,994 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9178 states to 9178 states and 11734 transitions. [2018-11-18 14:06:34,994 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3156 [2018-11-18 14:06:34,996 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3197 [2018-11-18 14:06:34,996 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9178 states and 11734 transitions. [2018-11-18 14:06:34,997 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-18 14:06:34,997 INFO L705 BuchiCegarLoop]: Abstraction has 9178 states and 11734 transitions. [2018-11-18 14:06:35,002 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9178 states and 11734 transitions. [2018-11-18 14:06:35,083 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9178 to 9137. [2018-11-18 14:06:35,083 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9137 states. [2018-11-18 14:06:35,098 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9137 states to 9137 states and 11693 transitions. [2018-11-18 14:06:35,098 INFO L728 BuchiCegarLoop]: Abstraction has 9137 states and 11693 transitions. [2018-11-18 14:06:35,098 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 14:06:35,098 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 14:06:35,098 INFO L87 Difference]: Start difference. First operand 9137 states and 11693 transitions. Second operand 3 states. [2018-11-18 14:06:35,162 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:06:35,163 INFO L93 Difference]: Finished difference Result 11377 states and 14392 transitions. [2018-11-18 14:06:35,164 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 14:06:35,164 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11377 states and 14392 transitions. [2018-11-18 14:06:35,197 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 3836 [2018-11-18 14:06:35,223 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11377 states to 11377 states and 14392 transitions. [2018-11-18 14:06:35,223 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3941 [2018-11-18 14:06:35,227 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3941 [2018-11-18 14:06:35,227 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11377 states and 14392 transitions. [2018-11-18 14:06:35,229 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-18 14:06:35,229 INFO L705 BuchiCegarLoop]: Abstraction has 11377 states and 14392 transitions. [2018-11-18 14:06:35,235 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11377 states and 14392 transitions. [2018-11-18 14:06:35,317 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11377 to 10609. [2018-11-18 14:06:35,317 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10609 states. [2018-11-18 14:06:35,333 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10609 states to 10609 states and 13528 transitions. [2018-11-18 14:06:35,333 INFO L728 BuchiCegarLoop]: Abstraction has 10609 states and 13528 transitions. [2018-11-18 14:06:35,333 INFO L608 BuchiCegarLoop]: Abstraction has 10609 states and 13528 transitions. [2018-11-18 14:06:35,333 INFO L442 BuchiCegarLoop]: ======== Iteration 18============ [2018-11-18 14:06:35,333 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10609 states and 13528 transitions. [2018-11-18 14:06:35,355 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 3580 [2018-11-18 14:06:35,355 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:06:35,355 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:06:35,356 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:06:35,356 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:06:35,356 INFO L794 eck$LassoCheckResult]: Stem: 76773#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 76468#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 76469#L605 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 76759#L264 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 76760#L271 assume 1 == ~m_i~0;~m_st~0 := 0; 76945#L271-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 76960#L276-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 76703#L281-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 76704#L286-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 76758#L408 assume !(0 == ~M_E~0); 77004#L408-2 assume !(0 == ~T1_E~0); 76684#L413-1 assume !(0 == ~T2_E~0); 76685#L418-1 assume !(0 == ~T3_E~0); 76806#L423-1 assume !(0 == ~E_1~0); 76528#L428-1 assume !(0 == ~E_2~0); 76529#L433-1 assume !(0 == ~E_3~0); 76543#L438-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 76741#L187 assume !(1 == ~m_pc~0); 76742#L187-2 is_master_triggered_~__retres1~0 := 0; 76743#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 76744#L199 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 76862#L500 assume !(0 != activate_threads_~tmp~1); 76863#L500-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 76868#L206 assume !(1 == ~t1_pc~0); 77125#L206-2 is_transmit1_triggered_~__retres1~1 := 0; 77126#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 76548#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 76549#L508 assume !(0 != activate_threads_~tmp___0~0); 76936#L508-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 76869#L225 assume !(1 == ~t2_pc~0); 76690#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 76864#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 76702#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 76518#L516 assume !(0 != activate_threads_~tmp___1~0); 76519#L516-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 76521#L244 assume !(1 == ~t3_pc~0); 77144#L244-2 is_transmit3_triggered_~__retres1~3 := 0; 76915#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 76916#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 76972#L524 assume !(0 != activate_threads_~tmp___2~0); 76973#L524-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 76796#L451 assume !(1 == ~M_E~0); 76797#L451-2 assume !(1 == ~T1_E~0); 76807#L456-1 assume !(1 == ~T2_E~0); 76522#L461-1 assume !(1 == ~T3_E~0); 76523#L466-1 assume !(1 == ~E_1~0); 76542#L471-1 assume !(1 == ~E_2~0); 77046#L476-1 assume !(1 == ~E_3~0); 77103#L481-1 assume { :end_inline_reset_delta_events } true; 77149#L642-3 assume true; 77614#L642-1 assume !false; 77613#L643 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 77516#L383 [2018-11-18 14:06:35,356 INFO L796 eck$LassoCheckResult]: Loop: 77516#L383 assume true; 77612#L331-1 assume !false; 80418#L332 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 80416#L299 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 77607#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 77606#L322 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 77575#L336 assume 0 != eval_~tmp~0; 77576#L336-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 80398#L344 assume !(0 != eval_~tmp_ndt_1~0); 77561#L341 assume !(0 == ~t1_st~0); 77554#L355 assume !(0 == ~t2_st~0); 77525#L369 assume !(0 == ~t3_st~0); 77516#L383 [2018-11-18 14:06:35,357 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:06:35,357 INFO L82 PathProgramCache]: Analyzing trace with hash 1764031817, now seen corresponding path program 1 times [2018-11-18 14:06:35,357 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:06:35,357 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:06:35,357 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:35,357 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:06:35,358 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:35,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:06:35,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:06:35,366 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:06:35,366 INFO L82 PathProgramCache]: Analyzing trace with hash -2144534838, now seen corresponding path program 1 times [2018-11-18 14:06:35,367 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:06:35,367 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:06:35,367 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:35,367 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:06:35,367 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:35,369 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:06:35,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:06:35,371 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:06:35,371 INFO L82 PathProgramCache]: Analyzing trace with hash -443002862, now seen corresponding path program 1 times [2018-11-18 14:06:35,371 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:06:35,371 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:06:35,371 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:35,371 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:06:35,371 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:35,374 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:06:35,401 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:06:35,401 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:06:35,402 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:06:35,442 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 14:06:35,442 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 14:06:35,442 INFO L87 Difference]: Start difference. First operand 10609 states and 13528 transitions. cyclomatic complexity: 2967 Second operand 3 states. [2018-11-18 14:06:35,530 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:06:35,530 INFO L93 Difference]: Finished difference Result 18344 states and 23023 transitions. [2018-11-18 14:06:35,532 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 14:06:35,532 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18344 states and 23023 transitions. [2018-11-18 14:06:35,592 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 5860 [2018-11-18 14:06:35,635 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18344 states to 18344 states and 23023 transitions. [2018-11-18 14:06:35,635 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6416 [2018-11-18 14:06:35,643 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6416 [2018-11-18 14:06:35,643 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18344 states and 23023 transitions. [2018-11-18 14:06:35,643 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-18 14:06:35,643 INFO L705 BuchiCegarLoop]: Abstraction has 18344 states and 23023 transitions. [2018-11-18 14:06:35,652 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18344 states and 23023 transitions. [2018-11-18 14:06:35,832 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18344 to 17516. [2018-11-18 14:06:35,832 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17516 states. [2018-11-18 14:06:35,857 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17516 states to 17516 states and 22069 transitions. [2018-11-18 14:06:35,857 INFO L728 BuchiCegarLoop]: Abstraction has 17516 states and 22069 transitions. [2018-11-18 14:06:35,857 INFO L608 BuchiCegarLoop]: Abstraction has 17516 states and 22069 transitions. [2018-11-18 14:06:35,857 INFO L442 BuchiCegarLoop]: ======== Iteration 19============ [2018-11-18 14:06:35,858 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17516 states and 22069 transitions. [2018-11-18 14:06:35,891 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 5584 [2018-11-18 14:06:35,891 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:06:35,891 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:06:35,891 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:06:35,892 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:06:35,892 INFO L794 eck$LassoCheckResult]: Stem: 105733#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 105428#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 105429#L605 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 105719#L264 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 105720#L271 assume 1 == ~m_i~0;~m_st~0 := 0; 105907#L271-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 105924#L276-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 105663#L281-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 105664#L286-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 105718#L408 assume !(0 == ~M_E~0); 105968#L408-2 assume !(0 == ~T1_E~0); 105640#L413-1 assume !(0 == ~T2_E~0); 105641#L418-1 assume !(0 == ~T3_E~0); 105769#L423-1 assume !(0 == ~E_1~0); 105486#L428-1 assume !(0 == ~E_2~0); 105487#L433-1 assume !(0 == ~E_3~0); 105501#L438-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 105701#L187 assume !(1 == ~m_pc~0); 105702#L187-2 is_master_triggered_~__retres1~0 := 0; 105703#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 105704#L199 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 105825#L500 assume !(0 != activate_threads_~tmp~1); 105826#L500-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 105832#L206 assume !(1 == ~t1_pc~0); 106072#L206-2 is_transmit1_triggered_~__retres1~1 := 0; 106073#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 105504#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 105505#L508 assume !(0 != activate_threads_~tmp___0~0); 105896#L508-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 105903#L225 assume !(1 == ~t2_pc~0); 109855#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 109854#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 109853#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 109852#L516 assume !(0 != activate_threads_~tmp___1~0); 109851#L516-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 109850#L244 assume !(1 == ~t3_pc~0); 109849#L244-2 is_transmit3_triggered_~__retres1~3 := 0; 109848#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 109847#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 109846#L524 assume !(0 != activate_threads_~tmp___2~0); 109845#L524-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 109844#L451 assume !(1 == ~M_E~0); 109843#L451-2 assume !(1 == ~T1_E~0); 109842#L456-1 assume !(1 == ~T2_E~0); 109841#L461-1 assume !(1 == ~T3_E~0); 109840#L466-1 assume !(1 == ~E_1~0); 109839#L471-1 assume !(1 == ~E_2~0); 109838#L476-1 assume !(1 == ~E_3~0); 109836#L481-1 assume { :end_inline_reset_delta_events } true; 109833#L642-3 assume true; 109830#L642-1 assume !false; 109254#L643 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 109252#L383 [2018-11-18 14:06:35,892 INFO L796 eck$LassoCheckResult]: Loop: 109252#L383 assume true; 109250#L331-1 assume !false; 109248#L332 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 109246#L299 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 109244#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 109242#L322 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 109240#L336 assume 0 != eval_~tmp~0; 109237#L336-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 109234#L344 assume !(0 != eval_~tmp_ndt_1~0); 109231#L341 assume !(0 == ~t1_st~0); 109229#L355 assume !(0 == ~t2_st~0); 109227#L369 assume !(0 == ~t3_st~0); 109252#L383 [2018-11-18 14:06:35,892 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:06:35,892 INFO L82 PathProgramCache]: Analyzing trace with hash 1410943435, now seen corresponding path program 1 times [2018-11-18 14:06:35,892 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:06:35,892 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:06:35,893 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:35,893 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:06:35,893 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:35,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:06:35,919 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:06:35,920 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:06:35,920 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:06:35,920 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 14:06:35,920 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:06:35,920 INFO L82 PathProgramCache]: Analyzing trace with hash -2144534838, now seen corresponding path program 2 times [2018-11-18 14:06:35,920 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:06:35,920 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:06:35,921 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:35,921 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:06:35,921 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:35,926 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:06:35,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:06:35,996 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 14:06:35,996 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 14:06:35,996 INFO L87 Difference]: Start difference. First operand 17516 states and 22069 transitions. cyclomatic complexity: 4625 Second operand 3 states. [2018-11-18 14:06:36,025 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:06:36,025 INFO L93 Difference]: Finished difference Result 12033 states and 15255 transitions. [2018-11-18 14:06:36,027 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 14:06:36,028 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12033 states and 15255 transitions. [2018-11-18 14:06:36,058 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4126 [2018-11-18 14:06:36,086 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12033 states to 12033 states and 15255 transitions. [2018-11-18 14:06:36,086 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4233 [2018-11-18 14:06:36,089 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4233 [2018-11-18 14:06:36,089 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12033 states and 15255 transitions. [2018-11-18 14:06:36,089 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-18 14:06:36,089 INFO L705 BuchiCegarLoop]: Abstraction has 12033 states and 15255 transitions. [2018-11-18 14:06:36,099 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12033 states and 15255 transitions. [2018-11-18 14:06:36,163 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12033 to 12033. [2018-11-18 14:06:36,163 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12033 states. [2018-11-18 14:06:36,178 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12033 states to 12033 states and 15255 transitions. [2018-11-18 14:06:36,178 INFO L728 BuchiCegarLoop]: Abstraction has 12033 states and 15255 transitions. [2018-11-18 14:06:36,178 INFO L608 BuchiCegarLoop]: Abstraction has 12033 states and 15255 transitions. [2018-11-18 14:06:36,178 INFO L442 BuchiCegarLoop]: ======== Iteration 20============ [2018-11-18 14:06:36,178 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12033 states and 15255 transitions. [2018-11-18 14:06:36,197 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 4126 [2018-11-18 14:06:36,197 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:06:36,197 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:06:36,198 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:06:36,198 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:06:36,198 INFO L794 eck$LassoCheckResult]: Stem: 135290#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 134983#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 134984#L605 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 135277#L264 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 135278#L271 assume 1 == ~m_i~0;~m_st~0 := 0; 135451#L271-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 135467#L276-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 135221#L281-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 135222#L286-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 135276#L408 assume !(0 == ~M_E~0); 135502#L408-2 assume !(0 == ~T1_E~0); 135199#L413-1 assume !(0 == ~T2_E~0); 135200#L418-1 assume !(0 == ~T3_E~0); 135323#L423-1 assume !(0 == ~E_1~0); 135041#L428-1 assume !(0 == ~E_2~0); 135042#L433-1 assume !(0 == ~E_3~0); 135057#L438-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 135260#L187 assume !(1 == ~m_pc~0); 135261#L187-2 is_master_triggered_~__retres1~0 := 0; 135262#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 135263#L199 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 135376#L500 assume !(0 != activate_threads_~tmp~1); 135377#L500-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 135382#L206 assume !(1 == ~t1_pc~0); 135602#L206-2 is_transmit1_triggered_~__retres1~1 := 0; 135603#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 135060#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 135061#L508 assume !(0 != activate_threads_~tmp___0~0); 135443#L508-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 135383#L225 assume !(1 == ~t2_pc~0); 135202#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 135378#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 135214#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 135031#L516 assume !(0 != activate_threads_~tmp___1~0); 135032#L516-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 135034#L244 assume !(1 == ~t3_pc~0); 135616#L244-2 is_transmit3_triggered_~__retres1~3 := 0; 135425#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 135426#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 135484#L524 assume !(0 != activate_threads_~tmp___2~0); 135485#L524-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 135313#L451 assume !(1 == ~M_E~0); 135314#L451-2 assume !(1 == ~T1_E~0); 135324#L456-1 assume !(1 == ~T2_E~0); 135035#L461-1 assume !(1 == ~T3_E~0); 135036#L466-1 assume !(1 == ~E_1~0); 135056#L471-1 assume !(1 == ~E_2~0); 135536#L476-1 assume !(1 == ~E_3~0); 135584#L481-1 assume { :end_inline_reset_delta_events } true; 135619#L642-3 assume true; 137187#L642-1 assume !false; 137188#L643 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 144015#L383 [2018-11-18 14:06:36,198 INFO L796 eck$LassoCheckResult]: Loop: 144015#L383 assume true; 144014#L331-1 assume !false; 144012#L332 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 144010#L299 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 144008#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 144006#L322 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 144004#L336 assume 0 != eval_~tmp~0; 144002#L336-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 143998#L344 assume !(0 != eval_~tmp_ndt_1~0); 143999#L341 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 144025#L358 assume !(0 != eval_~tmp_ndt_2~0); 144020#L355 assume !(0 == ~t2_st~0); 144018#L369 assume !(0 == ~t3_st~0); 144015#L383 [2018-11-18 14:06:36,198 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:06:36,198 INFO L82 PathProgramCache]: Analyzing trace with hash 1764031817, now seen corresponding path program 2 times [2018-11-18 14:06:36,198 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:06:36,198 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:06:36,199 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:36,199 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 14:06:36,199 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:36,200 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:06:36,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:06:36,204 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:06:36,204 INFO L82 PathProgramCache]: Analyzing trace with hash -2060137191, now seen corresponding path program 1 times [2018-11-18 14:06:36,204 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:06:36,204 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:06:36,205 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:36,205 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 14:06:36,205 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:36,206 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:06:36,207 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:06:36,208 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:06:36,208 INFO L82 PathProgramCache]: Analyzing trace with hash -852253487, now seen corresponding path program 1 times [2018-11-18 14:06:36,208 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:06:36,208 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:06:36,208 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:36,209 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:06:36,209 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:36,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:06:36,237 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:06:36,237 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:06:36,237 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:06:36,334 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 14:06:36,334 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 14:06:36,334 INFO L87 Difference]: Start difference. First operand 12033 states and 15255 transitions. cyclomatic complexity: 3270 Second operand 3 states. [2018-11-18 14:06:36,384 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:06:36,384 INFO L93 Difference]: Finished difference Result 19437 states and 24417 transitions. [2018-11-18 14:06:36,386 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 14:06:36,386 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19437 states and 24417 transitions. [2018-11-18 14:06:36,434 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 6542 [2018-11-18 14:06:36,476 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19437 states to 19437 states and 24417 transitions. [2018-11-18 14:06:36,476 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6693 [2018-11-18 14:06:36,480 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6693 [2018-11-18 14:06:36,480 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19437 states and 24417 transitions. [2018-11-18 14:06:36,481 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-18 14:06:36,481 INFO L705 BuchiCegarLoop]: Abstraction has 19437 states and 24417 transitions. [2018-11-18 14:06:36,489 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19437 states and 24417 transitions. [2018-11-18 14:06:36,592 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19437 to 19437. [2018-11-18 14:06:36,592 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19437 states. [2018-11-18 14:06:36,615 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19437 states to 19437 states and 24417 transitions. [2018-11-18 14:06:36,615 INFO L728 BuchiCegarLoop]: Abstraction has 19437 states and 24417 transitions. [2018-11-18 14:06:36,615 INFO L608 BuchiCegarLoop]: Abstraction has 19437 states and 24417 transitions. [2018-11-18 14:06:36,615 INFO L442 BuchiCegarLoop]: ======== Iteration 21============ [2018-11-18 14:06:36,615 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19437 states and 24417 transitions. [2018-11-18 14:06:36,648 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 6542 [2018-11-18 14:06:36,648 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:06:36,649 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:06:36,649 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:06:36,649 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:06:36,649 INFO L794 eck$LassoCheckResult]: Stem: 166767#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 166461#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 166462#L605 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 166753#L264 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 166754#L271 assume 1 == ~m_i~0;~m_st~0 := 0; 166930#L271-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 166948#L276-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 166696#L281-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 166697#L286-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 166752#L408 assume !(0 == ~M_E~0); 166986#L408-2 assume !(0 == ~T1_E~0); 166672#L413-1 assume !(0 == ~T2_E~0); 166673#L418-1 assume !(0 == ~T3_E~0); 166800#L423-1 assume !(0 == ~E_1~0); 166516#L428-1 assume !(0 == ~E_2~0); 166517#L433-1 assume !(0 == ~E_3~0); 166531#L438-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 166736#L187 assume !(1 == ~m_pc~0); 166737#L187-2 is_master_triggered_~__retres1~0 := 0; 166738#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 166739#L199 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 166854#L500 assume !(0 != activate_threads_~tmp~1); 166855#L500-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 166862#L206 assume !(1 == ~t1_pc~0); 167098#L206-2 is_transmit1_triggered_~__retres1~1 := 0; 167099#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 166534#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 166535#L508 assume !(0 != activate_threads_~tmp___0~0); 166921#L508-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 166863#L225 assume !(1 == ~t2_pc~0); 166675#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 166856#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 166685#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 166506#L516 assume !(0 != activate_threads_~tmp___1~0); 166507#L516-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 166509#L244 assume !(1 == ~t3_pc~0); 167114#L244-2 is_transmit3_triggered_~__retres1~3 := 0; 166906#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 166907#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 166966#L524 assume !(0 != activate_threads_~tmp___2~0); 166967#L524-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 166790#L451 assume !(1 == ~M_E~0); 166791#L451-2 assume !(1 == ~T1_E~0); 166801#L456-1 assume !(1 == ~T2_E~0); 166510#L461-1 assume !(1 == ~T3_E~0); 166511#L466-1 assume !(1 == ~E_1~0); 166530#L471-1 assume !(1 == ~E_2~0); 167023#L476-1 assume !(1 == ~E_3~0); 167082#L481-1 assume { :end_inline_reset_delta_events } true; 167118#L642-3 assume true; 172397#L642-1 assume !false; 172398#L643 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 179701#L383 [2018-11-18 14:06:36,650 INFO L796 eck$LassoCheckResult]: Loop: 179701#L383 assume true; 179699#L331-1 assume !false; 179652#L332 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 179638#L299 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 179634#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 179629#L322 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 179622#L336 assume 0 != eval_~tmp~0; 179616#L336-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 179610#L344 assume !(0 != eval_~tmp_ndt_1~0); 179606#L341 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 179601#L358 assume !(0 != eval_~tmp_ndt_2~0); 179599#L355 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 178936#L372 assume !(0 != eval_~tmp_ndt_3~0); 179249#L369 assume !(0 == ~t3_st~0); 179701#L383 [2018-11-18 14:06:36,650 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:06:36,650 INFO L82 PathProgramCache]: Analyzing trace with hash 1764031817, now seen corresponding path program 3 times [2018-11-18 14:06:36,650 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:06:36,650 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:06:36,651 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:36,651 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:06:36,651 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:36,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:06:36,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:06:36,661 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:06:36,661 INFO L82 PathProgramCache]: Analyzing trace with hash 560128912, now seen corresponding path program 1 times [2018-11-18 14:06:36,661 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:06:36,662 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:06:36,662 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:36,662 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 14:06:36,662 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:36,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:06:36,665 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:06:36,666 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:06:36,666 INFO L82 PathProgramCache]: Analyzing trace with hash -650181928, now seen corresponding path program 1 times [2018-11-18 14:06:36,666 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:06:36,667 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:06:36,667 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:36,667 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:06:36,667 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:36,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:06:36,698 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:06:36,698 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:06:36,698 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 14:06:36,753 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 14:06:36,754 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 14:06:36,754 INFO L87 Difference]: Start difference. First operand 19437 states and 24417 transitions. cyclomatic complexity: 5028 Second operand 3 states. [2018-11-18 14:06:36,830 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:06:36,830 INFO L93 Difference]: Finished difference Result 24999 states and 31358 transitions. [2018-11-18 14:06:36,832 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 14:06:36,832 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 24999 states and 31358 transitions. [2018-11-18 14:06:36,956 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8471 [2018-11-18 14:06:36,983 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 24999 states to 24999 states and 31358 transitions. [2018-11-18 14:06:36,983 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8657 [2018-11-18 14:06:36,986 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8657 [2018-11-18 14:06:36,987 INFO L73 IsDeterministic]: Start isDeterministic. Operand 24999 states and 31358 transitions. [2018-11-18 14:06:36,987 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-18 14:06:36,987 INFO L705 BuchiCegarLoop]: Abstraction has 24999 states and 31358 transitions. [2018-11-18 14:06:36,995 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24999 states and 31358 transitions. [2018-11-18 14:06:37,096 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24999 to 24999. [2018-11-18 14:06:37,096 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24999 states. [2018-11-18 14:06:37,117 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24999 states to 24999 states and 31358 transitions. [2018-11-18 14:06:37,117 INFO L728 BuchiCegarLoop]: Abstraction has 24999 states and 31358 transitions. [2018-11-18 14:06:37,117 INFO L608 BuchiCegarLoop]: Abstraction has 24999 states and 31358 transitions. [2018-11-18 14:06:37,117 INFO L442 BuchiCegarLoop]: ======== Iteration 22============ [2018-11-18 14:06:37,117 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24999 states and 31358 transitions. [2018-11-18 14:06:37,150 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8471 [2018-11-18 14:06:37,150 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:06:37,150 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:06:37,151 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:06:37,151 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:06:37,151 INFO L794 eck$LassoCheckResult]: Stem: 211205#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2; 210905#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~5;havoc main_~__retres1~5;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1; 210906#L605 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10, start_simulation_#t~ret11, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 211191#L264 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 211192#L271 assume 1 == ~m_i~0;~m_st~0 := 0; 211368#L271-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 211388#L276-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 211133#L281-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 211134#L286-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 211190#L408 assume !(0 == ~M_E~0); 211428#L408-2 assume !(0 == ~T1_E~0); 211111#L413-1 assume !(0 == ~T2_E~0); 211112#L418-1 assume !(0 == ~T3_E~0); 211236#L423-1 assume !(0 == ~E_1~0); 210959#L428-1 assume !(0 == ~E_2~0); 210960#L433-1 assume !(0 == ~E_3~0); 210973#L438-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret5, activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 211174#L187 assume !(1 == ~m_pc~0); 211175#L187-2 is_master_triggered_~__retres1~0 := 0; 211176#L198 is_master_triggered_#res := is_master_triggered_~__retres1~0; 211177#L199 activate_threads_#t~ret5 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret5;havoc activate_threads_#t~ret5; 211289#L500 assume !(0 != activate_threads_~tmp~1); 211290#L500-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 211294#L206 assume !(1 == ~t1_pc~0); 211547#L206-2 is_transmit1_triggered_~__retres1~1 := 0; 211548#L217 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 210976#L218 activate_threads_#t~ret6 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 210977#L508 assume !(0 != activate_threads_~tmp___0~0); 211359#L508-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 211295#L225 assume !(1 == ~t2_pc~0); 211118#L225-2 is_transmit2_triggered_~__retres1~2 := 0; 211291#L236 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 211132#L237 activate_threads_#t~ret7 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 210950#L516 assume !(0 != activate_threads_~tmp___1~0); 210951#L516-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 210952#L244 assume !(1 == ~t3_pc~0); 211572#L244-2 is_transmit3_triggered_~__retres1~3 := 0; 211341#L255 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 211342#L256 activate_threads_#t~ret8 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 211404#L524 assume !(0 != activate_threads_~tmp___2~0); 211405#L524-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 211226#L451 assume !(1 == ~M_E~0); 211227#L451-2 assume !(1 == ~T1_E~0); 211237#L456-1 assume !(1 == ~T2_E~0); 210953#L461-1 assume !(1 == ~T3_E~0); 210954#L466-1 assume !(1 == ~E_1~0); 210972#L471-1 assume !(1 == ~E_2~0); 211474#L476-1 assume !(1 == ~E_3~0); 211527#L481-1 assume { :end_inline_reset_delta_events } true; 211576#L642-3 assume true; 216132#L642-1 assume !false; 216133#L643 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_~tmp~0;havoc eval_~tmp~0; 217894#L383 [2018-11-18 14:06:37,151 INFO L796 eck$LassoCheckResult]: Loop: 217894#L383 assume true; 219599#L331-1 assume !false; 219598#L332 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~4;havoc exists_runnable_thread_~__retres1~4; 219597#L299 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~4 := 1; 219596#L321 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~4; 219595#L322 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 219594#L336 assume 0 != eval_~tmp~0; 219593#L336-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 219591#L344 assume !(0 != eval_~tmp_ndt_1~0); 219590#L341 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 219588#L358 assume !(0 != eval_~tmp_ndt_2~0); 219568#L355 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 219566#L372 assume !(0 != eval_~tmp_ndt_3~0); 219567#L369 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 219600#L386 assume !(0 != eval_~tmp_ndt_4~0); 217894#L383 [2018-11-18 14:06:37,151 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:06:37,151 INFO L82 PathProgramCache]: Analyzing trace with hash 1764031817, now seen corresponding path program 4 times [2018-11-18 14:06:37,151 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:06:37,151 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:06:37,152 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:37,152 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:06:37,152 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:37,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:06:37,157 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:06:37,160 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:06:37,160 INFO L82 PathProgramCache]: Analyzing trace with hash 184126547, now seen corresponding path program 1 times [2018-11-18 14:06:37,160 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:06:37,160 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:06:37,161 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:37,161 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 14:06:37,161 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:37,162 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:06:37,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:06:37,165 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:06:37,165 INFO L82 PathProgramCache]: Analyzing trace with hash 1319196171, now seen corresponding path program 1 times [2018-11-18 14:06:37,165 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:06:37,165 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:06:37,165 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:37,166 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:06:37,166 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:06:37,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:06:37,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:06:37,413 WARN L180 SmtUtils]: Spent 168.00 ms on a formula simplification. DAG size of input: 126 DAG size of output: 86 [2018-11-18 14:06:37,477 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 18.11 02:06:37 BoogieIcfgContainer [2018-11-18 14:06:37,477 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2018-11-18 14:06:37,477 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-18 14:06:37,479 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-18 14:06:37,479 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-18 14:06:37,480 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 02:06:28" (3/4) ... [2018-11-18 14:06:37,482 INFO L141 WitnessPrinter]: Generating witness for non-termination counterexample [2018-11-18 14:06:37,528 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_9edd41f0-bb38-47c2-83e2-42ee9941d34f/bin-2019/uautomizer/witness.graphml [2018-11-18 14:06:37,528 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-18 14:06:37,529 INFO L168 Benchmark]: Toolchain (without parser) took 9540.39 ms. Allocated memory was 1.0 GB in the beginning and 1.4 GB in the end (delta: 361.2 MB). Free memory was 961.9 MB in the beginning and 958.1 MB in the end (delta: 3.8 MB). Peak memory consumption was 365.0 MB. Max. memory is 11.5 GB. [2018-11-18 14:06:37,529 INFO L168 Benchmark]: CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 982.9 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-18 14:06:37,529 INFO L168 Benchmark]: CACSL2BoogieTranslator took 213.93 ms. Allocated memory is still 1.0 GB. Free memory was 961.9 MB in the beginning and 945.8 MB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. [2018-11-18 14:06:37,530 INFO L168 Benchmark]: Boogie Procedure Inliner took 67.57 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 131.1 MB). Free memory was 945.8 MB in the beginning and 1.1 GB in the end (delta: -179.7 MB). Peak memory consumption was 20.4 MB. Max. memory is 11.5 GB. [2018-11-18 14:06:37,530 INFO L168 Benchmark]: Boogie Preprocessor took 32.69 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-18 14:06:37,530 INFO L168 Benchmark]: RCFGBuilder took 599.09 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 71.8 MB). Peak memory consumption was 71.8 MB. Max. memory is 11.5 GB. [2018-11-18 14:06:37,530 INFO L168 Benchmark]: BuchiAutomizer took 8573.10 ms. Allocated memory was 1.2 GB in the beginning and 1.4 GB in the end (delta: 230.2 MB). Free memory was 1.1 GB in the beginning and 958.4 MB in the end (delta: 95.3 MB). Peak memory consumption was 325.5 MB. Max. memory is 11.5 GB. [2018-11-18 14:06:37,530 INFO L168 Benchmark]: Witness Printer took 50.56 ms. Allocated memory is still 1.4 GB. Free memory was 958.4 MB in the beginning and 958.1 MB in the end (delta: 244.8 kB). Peak memory consumption was 244.8 kB. Max. memory is 11.5 GB. [2018-11-18 14:06:37,532 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 982.9 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 213.93 ms. Allocated memory is still 1.0 GB. Free memory was 961.9 MB in the beginning and 945.8 MB in the end (delta: 16.1 MB). Peak memory consumption was 16.1 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 67.57 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 131.1 MB). Free memory was 945.8 MB in the beginning and 1.1 GB in the end (delta: -179.7 MB). Peak memory consumption was 20.4 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 32.69 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 599.09 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 71.8 MB). Peak memory consumption was 71.8 MB. Max. memory is 11.5 GB. * BuchiAutomizer took 8573.10 ms. Allocated memory was 1.2 GB in the beginning and 1.4 GB in the end (delta: 230.2 MB). Free memory was 1.1 GB in the beginning and 958.4 MB in the end (delta: 95.3 MB). Peak memory consumption was 325.5 MB. Max. memory is 11.5 GB. * Witness Printer took 50.56 ms. Allocated memory is still 1.4 GB. Free memory was 958.4 MB in the beginning and 958.1 MB in the end (delta: 244.8 kB). Peak memory consumption was 244.8 kB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 23 terminating modules (21 trivial, 2 deterministic, 0 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function -1 * E_3 + 1 and consists of 3 locations. One deterministic module has affine ranking function -2 * T1_E + 3 and consists of 3 locations. 21 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 24999 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 8.5s and 22 iterations. TraceHistogramMax:2. Analysis of lassos took 4.7s. Construction of modules took 0.6s. Büchi inclusion checks took 1.0s. Highest rank in rank-based complementation 3. Minimization of det autom 15. Minimization of nondet autom 8. Automata minimization 1.0s AutomataMinimizationTime, 23 MinimizatonAttempts, 8259 StatesRemovedByMinimization, 14 NontrivialMinimizations. Non-live state removal took 0.6s Buchi closure took 0.0s. Biggest automaton had 24999 states and ocurred in iteration 21. Nontrivial modules had stage [2, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 7/7 HoareTripleCheckerStatistics: 10320 SDtfs, 11655 SDslu, 11716 SDs, 0 SdLazy, 581 SolverSat, 231 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.6s Time LassoAnalysisResults: nont1 unkn0 SFLI6 SFLT0 conc3 concLT2 SILN1 SILU0 SILI9 SILT0 lasso0 LassoPreprocessingBenchmarks: Lassos: inital151 mio100 ax100 hnf100 lsp7 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq209 hnf86 smp100 dnf189 smp57 tf109 neg96 sie108 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 2ms VariablesStem: 0 VariablesLoop: 1 DisjunctsStem: 1 DisjunctsLoop: 2 SupportingInvariants: 0 MotzkinApplications: 4 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 13 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 2 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.1s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 331]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {__retres1=0, t3_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2abe81a5=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5de43a62=0, tmp=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7287765d=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@668c134f=0, __retres1=0, kernel_st=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@73fb78d0=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@71afbd4c=0, t2_st=0, E_3=2, \result=0, E_1=2, tmp_ndt_2=0, \result=0, \result=0, tmp_ndt_4=0, m_st=0, tmp___2=0, tmp___0=0, t3_pc=0, tmp=0, __retres1=0, m_pc=0, \result=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2c9c8cdb=0, \result=0, T2_E=2, tmp___0=0, t1_pc=0, E_2=2, T1_E=2, __retres1=1, tmp_ndt_1=0, M_E=2, tmp=0, tmp_ndt_3=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@30368243=0, __retres1=0, t2_i=1, t3_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@462c1c53=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@70d87fda=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5e8cd29f=0, t1_st=0, t2_pc=0, tmp___1=0, T3_E=2, t1_i=1, \result=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 331]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int m_st ; [L20] int t1_st ; [L21] int t2_st ; [L22] int t3_st ; [L23] int m_i ; [L24] int t1_i ; [L25] int t2_i ; [L26] int t3_i ; [L27] int M_E = 2; [L28] int T1_E = 2; [L29] int T2_E = 2; [L30] int T3_E = 2; [L31] int E_1 = 2; [L32] int E_2 = 2; [L33] int E_3 = 2; [L687] int __retres1 ; [L691] CALL init_model() [L600] m_i = 1 [L601] t1_i = 1 [L602] t2_i = 1 [L603] RET t3_i = 1 [L691] init_model() [L692] CALL start_simulation() [L628] int kernel_st ; [L629] int tmp ; [L630] int tmp___0 ; [L634] kernel_st = 0 [L635] FCALL update_channels() [L636] CALL init_threads() [L271] COND TRUE m_i == 1 [L272] m_st = 0 [L276] COND TRUE t1_i == 1 [L277] t1_st = 0 [L281] COND TRUE t2_i == 1 [L282] t2_st = 0 [L286] COND TRUE t3_i == 1 [L287] RET t3_st = 0 [L636] init_threads() [L637] CALL fire_delta_events() [L408] COND FALSE !(M_E == 0) [L413] COND FALSE !(T1_E == 0) [L418] COND FALSE !(T2_E == 0) [L423] COND FALSE !(T3_E == 0) [L428] COND FALSE !(E_1 == 0) [L433] COND FALSE !(E_2 == 0) [L438] COND FALSE, RET !(E_3 == 0) [L637] fire_delta_events() [L638] CALL activate_threads() [L491] int tmp ; [L492] int tmp___0 ; [L493] int tmp___1 ; [L494] int tmp___2 ; [L498] CALL, EXPR is_master_triggered() [L184] int __retres1 ; [L187] COND FALSE !(m_pc == 1) [L197] __retres1 = 0 [L199] RET return (__retres1); [L498] EXPR is_master_triggered() [L498] tmp = is_master_triggered() [L500] COND FALSE !(\read(tmp)) [L506] CALL, EXPR is_transmit1_triggered() [L203] int __retres1 ; [L206] COND FALSE !(t1_pc == 1) [L216] __retres1 = 0 [L218] RET return (__retres1); [L506] EXPR is_transmit1_triggered() [L506] tmp___0 = is_transmit1_triggered() [L508] COND FALSE !(\read(tmp___0)) [L514] CALL, EXPR is_transmit2_triggered() [L222] int __retres1 ; [L225] COND FALSE !(t2_pc == 1) [L235] __retres1 = 0 [L237] RET return (__retres1); [L514] EXPR is_transmit2_triggered() [L514] tmp___1 = is_transmit2_triggered() [L516] COND FALSE !(\read(tmp___1)) [L522] CALL, EXPR is_transmit3_triggered() [L241] int __retres1 ; [L244] COND FALSE !(t3_pc == 1) [L254] __retres1 = 0 [L256] RET return (__retres1); [L522] EXPR is_transmit3_triggered() [L522] tmp___2 = is_transmit3_triggered() [L524] COND FALSE, RET !(\read(tmp___2)) [L638] activate_threads() [L639] CALL reset_delta_events() [L451] COND FALSE !(M_E == 1) [L456] COND FALSE !(T1_E == 1) [L461] COND FALSE !(T2_E == 1) [L466] COND FALSE !(T3_E == 1) [L471] COND FALSE !(E_1 == 1) [L476] COND FALSE !(E_2 == 1) [L481] COND FALSE, RET !(E_3 == 1) [L639] reset_delta_events() [L642] COND TRUE 1 [L645] kernel_st = 1 [L646] CALL eval() [L327] int tmp ; Loop: [L331] COND TRUE 1 [L334] CALL, EXPR exists_runnable_thread() [L296] int __retres1 ; [L299] COND TRUE m_st == 0 [L300] __retres1 = 1 [L322] RET return (__retres1); [L334] EXPR exists_runnable_thread() [L334] tmp = exists_runnable_thread() [L336] COND TRUE \read(tmp) [L341] COND TRUE m_st == 0 [L342] int tmp_ndt_1; [L343] tmp_ndt_1 = __VERIFIER_nondet_int() [L344] COND FALSE !(\read(tmp_ndt_1)) [L355] COND TRUE t1_st == 0 [L356] int tmp_ndt_2; [L357] tmp_ndt_2 = __VERIFIER_nondet_int() [L358] COND FALSE !(\read(tmp_ndt_2)) [L369] COND TRUE t2_st == 0 [L370] int tmp_ndt_3; [L371] tmp_ndt_3 = __VERIFIER_nondet_int() [L372] COND FALSE !(\read(tmp_ndt_3)) [L383] COND TRUE t3_st == 0 [L384] int tmp_ndt_4; [L385] tmp_ndt_4 = __VERIFIER_nondet_int() [L386] COND FALSE !(\read(tmp_ndt_4)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...