./Ultimate.py --spec ../../sv-benchmarks/c/Termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.04_false-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 5842f4b8 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_a9952978-50ee-4e47-ad28-4acf357c8425/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_a9952978-50ee-4e47-ad28-4acf357c8425/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_a9952978-50ee-4e47-ad28-4acf357c8425/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_a9952978-50ee-4e47-ad28-4acf357c8425/bin-2019/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.04_false-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_a9952978-50ee-4e47-ad28-4acf357c8425/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_a9952978-50ee-4e47-ad28-4acf357c8425/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash bcbeb24241e70d50816527d1472e428919d63db5 ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.1.23-5842f4b [2018-11-18 09:11:29,267 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-18 09:11:29,268 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-18 09:11:29,274 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-18 09:11:29,274 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-18 09:11:29,274 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-18 09:11:29,275 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-18 09:11:29,276 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-18 09:11:29,278 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-18 09:11:29,278 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-18 09:11:29,279 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-18 09:11:29,279 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-18 09:11:29,279 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-18 09:11:29,280 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-18 09:11:29,281 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-18 09:11:29,281 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-18 09:11:29,281 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-18 09:11:29,283 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-18 09:11:29,284 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-18 09:11:29,285 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-18 09:11:29,286 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-18 09:11:29,286 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-18 09:11:29,288 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-18 09:11:29,288 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-18 09:11:29,288 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-18 09:11:29,289 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-18 09:11:29,289 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-18 09:11:29,289 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-18 09:11:29,290 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-18 09:11:29,291 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-18 09:11:29,291 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-18 09:11:29,291 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-18 09:11:29,292 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-18 09:11:29,292 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-18 09:11:29,292 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-18 09:11:29,293 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-18 09:11:29,293 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_a9952978-50ee-4e47-ad28-4acf357c8425/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2018-11-18 09:11:29,301 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-18 09:11:29,301 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-18 09:11:29,302 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-18 09:11:29,302 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-18 09:11:29,302 INFO L133 SettingsManager]: * Use SBE=true [2018-11-18 09:11:29,302 INFO L131 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2018-11-18 09:11:29,302 INFO L133 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2018-11-18 09:11:29,303 INFO L133 SettingsManager]: * Use old map elimination=false [2018-11-18 09:11:29,303 INFO L133 SettingsManager]: * Use external solver (rank synthesis)=false [2018-11-18 09:11:29,303 INFO L133 SettingsManager]: * Use only trivial implications for array writes=true [2018-11-18 09:11:29,303 INFO L133 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2018-11-18 09:11:29,303 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-18 09:11:29,303 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-18 09:11:29,303 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-11-18 09:11:29,304 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-18 09:11:29,304 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-18 09:11:29,304 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-18 09:11:29,304 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2018-11-18 09:11:29,304 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2018-11-18 09:11:29,304 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2018-11-18 09:11:29,304 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-18 09:11:29,304 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-18 09:11:29,305 INFO L133 SettingsManager]: * Assume nondeterminstic values are in range=false [2018-11-18 09:11:29,305 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-18 09:11:29,305 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2018-11-18 09:11:29,305 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-18 09:11:29,305 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-18 09:11:29,305 INFO L133 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2018-11-18 09:11:29,305 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-18 09:11:29,306 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-18 09:11:29,306 INFO L133 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2018-11-18 09:11:29,306 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-11-18 09:11:29,306 INFO L133 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_a9952978-50ee-4e47-ad28-4acf357c8425/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> bcbeb24241e70d50816527d1472e428919d63db5 [2018-11-18 09:11:29,331 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-18 09:11:29,340 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-18 09:11:29,342 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-18 09:11:29,344 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-18 09:11:29,344 INFO L276 PluginConnector]: CDTParser initialized [2018-11-18 09:11:29,344 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_a9952978-50ee-4e47-ad28-4acf357c8425/bin-2019/uautomizer/../../sv-benchmarks/c/systemc/transmitter.04_false-unreach-call_false-termination.cil.c [2018-11-18 09:11:29,388 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_a9952978-50ee-4e47-ad28-4acf357c8425/bin-2019/uautomizer/data/92d389263/7e0243496da4487eb49cfea6486a326d/FLAG99f6cd4bc [2018-11-18 09:11:29,817 INFO L307 CDTParser]: Found 1 translation units. [2018-11-18 09:11:29,818 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_a9952978-50ee-4e47-ad28-4acf357c8425/sv-benchmarks/c/systemc/transmitter.04_false-unreach-call_false-termination.cil.c [2018-11-18 09:11:29,825 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_a9952978-50ee-4e47-ad28-4acf357c8425/bin-2019/uautomizer/data/92d389263/7e0243496da4487eb49cfea6486a326d/FLAG99f6cd4bc [2018-11-18 09:11:29,836 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_a9952978-50ee-4e47-ad28-4acf357c8425/bin-2019/uautomizer/data/92d389263/7e0243496da4487eb49cfea6486a326d [2018-11-18 09:11:29,839 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-18 09:11:29,840 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-18 09:11:29,840 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-18 09:11:29,841 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-18 09:11:29,844 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-18 09:11:29,844 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 09:11:29" (1/1) ... [2018-11-18 09:11:29,847 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@44c74022 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:11:29, skipping insertion in model container [2018-11-18 09:11:29,847 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 09:11:29" (1/1) ... [2018-11-18 09:11:29,855 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-18 09:11:29,881 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-18 09:11:30,024 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 09:11:30,029 INFO L191 MainTranslator]: Completed pre-run [2018-11-18 09:11:30,055 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 09:11:30,067 INFO L195 MainTranslator]: Completed translation [2018-11-18 09:11:30,067 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:11:30 WrapperNode [2018-11-18 09:11:30,067 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-18 09:11:30,068 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-18 09:11:30,068 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-18 09:11:30,068 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-18 09:11:30,073 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:11:30" (1/1) ... [2018-11-18 09:11:30,077 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:11:30" (1/1) ... [2018-11-18 09:11:30,147 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-18 09:11:30,148 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-18 09:11:30,148 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-18 09:11:30,148 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-18 09:11:30,156 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:11:30" (1/1) ... [2018-11-18 09:11:30,156 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:11:30" (1/1) ... [2018-11-18 09:11:30,159 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:11:30" (1/1) ... [2018-11-18 09:11:30,160 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:11:30" (1/1) ... [2018-11-18 09:11:30,168 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:11:30" (1/1) ... [2018-11-18 09:11:30,179 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:11:30" (1/1) ... [2018-11-18 09:11:30,181 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:11:30" (1/1) ... [2018-11-18 09:11:30,188 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-18 09:11:30,188 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-18 09:11:30,188 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-18 09:11:30,188 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-18 09:11:30,189 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:11:30" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a9952978-50ee-4e47-ad28-4acf357c8425/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 09:11:30,237 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-18 09:11:30,237 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-18 09:11:31,010 INFO L278 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-18 09:11:31,011 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 09:11:31 BoogieIcfgContainer [2018-11-18 09:11:31,011 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-18 09:11:31,011 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2018-11-18 09:11:31,011 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2018-11-18 09:11:31,016 INFO L276 PluginConnector]: BuchiAutomizer initialized [2018-11-18 09:11:31,016 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-18 09:11:31,017 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 18.11 09:11:29" (1/3) ... [2018-11-18 09:11:31,018 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@37ca3684 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 18.11 09:11:31, skipping insertion in model container [2018-11-18 09:11:31,018 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-18 09:11:31,018 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 09:11:30" (2/3) ... [2018-11-18 09:11:31,018 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@37ca3684 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 18.11 09:11:31, skipping insertion in model container [2018-11-18 09:11:31,018 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-18 09:11:31,018 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 09:11:31" (3/3) ... [2018-11-18 09:11:31,020 INFO L375 chiAutomizerObserver]: Analyzing ICFG transmitter.04_false-unreach-call_false-termination.cil.c [2018-11-18 09:11:31,067 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-18 09:11:31,067 INFO L374 BuchiCegarLoop]: Interprodecural is true [2018-11-18 09:11:31,068 INFO L375 BuchiCegarLoop]: Hoare is false [2018-11-18 09:11:31,068 INFO L376 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2018-11-18 09:11:31,068 INFO L377 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-18 09:11:31,068 INFO L378 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-18 09:11:31,068 INFO L379 BuchiCegarLoop]: Difference is false [2018-11-18 09:11:31,068 INFO L380 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-18 09:11:31,068 INFO L383 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2018-11-18 09:11:31,088 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 399 states. [2018-11-18 09:11:31,119 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 330 [2018-11-18 09:11:31,119 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:11:31,119 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:11:31,128 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:11:31,128 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:11:31,128 INFO L442 BuchiCegarLoop]: ======== Iteration 1============ [2018-11-18 09:11:31,128 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 399 states. [2018-11-18 09:11:31,135 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 330 [2018-11-18 09:11:31,135 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:11:31,135 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:11:31,137 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:11:31,137 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:11:31,144 INFO L794 eck$LassoCheckResult]: Stem: 261#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 191#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 148#L729true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 75#L324true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 125#L331true assume !(1 == ~m_i~0);~m_st~0 := 2; 121#L331-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 46#L336-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 259#L341-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 77#L346-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 193#L351-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 392#L492true assume !(0 == ~M_E~0); 396#L492-2true assume 0 == ~T1_E~0;~T1_E~0 := 1; 113#L497-1true assume !(0 == ~T2_E~0); 318#L502-1true assume !(0 == ~T3_E~0); 128#L507-1true assume !(0 == ~T4_E~0); 52#L512-1true assume !(0 == ~E_1~0); 270#L517-1true assume !(0 == ~E_2~0); 84#L522-1true assume !(0 == ~E_3~0); 205#L527-1true assume !(0 == ~E_4~0); 17#L532-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 387#L228true assume 1 == ~m_pc~0; 224#L229true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 351#L239true is_master_triggered_#res := is_master_triggered_~__retres1~0; 225#L240true activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 277#L605true assume !(0 != activate_threads_~tmp~1); 278#L605-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 94#L247true assume 1 == ~t1_pc~0; 41#L248true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 95#L258true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 43#L259true activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 401#L613true assume !(0 != activate_threads_~tmp___0~0); 389#L613-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 107#L266true assume !(1 == ~t2_pc~0); 169#L266-2true is_transmit2_triggered_~__retres1~2 := 0; 108#L277true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 145#L278true activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 4#L621true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 7#L621-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 188#L285true assume 1 == ~t3_pc~0; 257#L286true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 189#L296true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 258#L297true activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 119#L629true assume !(0 != activate_threads_~tmp___2~0); 109#L629-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 316#L304true assume !(1 == ~t4_pc~0); 299#L304-2true is_transmit4_triggered_~__retres1~4 := 0; 315#L315true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 373#L316true activate_threads_#t~ret10 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 216#L637true assume !(0 != activate_threads_~tmp___3~0); 218#L637-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49#L545true assume !(1 == ~M_E~0); 53#L545-2true assume !(1 == ~T1_E~0); 279#L550-1true assume !(1 == ~T2_E~0); 9#L555-1true assume !(1 == ~T3_E~0); 220#L560-1true assume !(1 == ~T4_E~0); 16#L565-1true assume !(1 == ~E_1~0); 330#L570-1true assume !(1 == ~E_2~0); 142#L575-1true assume 1 == ~E_3~0;~E_3~0 := 2; 390#L580-1true assume !(1 == ~E_4~0); 110#L585-1true assume { :end_inline_reset_delta_events } true; 320#L766-3true [2018-11-18 09:11:31,145 INFO L796 eck$LassoCheckResult]: Loop: 320#L766-3true assume true; 319#L766-1true assume !false; 293#L767true start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 86#L467true assume !true; 332#L482true assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 79#L324-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 364#L492-3true assume 0 == ~M_E~0;~M_E~0 := 1; 370#L492-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 100#L497-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 309#L502-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 123#L507-3true assume !(0 == ~T4_E~0); 31#L512-3true assume 0 == ~E_1~0;~E_1~0 := 1; 273#L517-3true assume 0 == ~E_2~0;~E_2~0 := 1; 92#L522-3true assume 0 == ~E_3~0;~E_3~0 := 1; 211#L527-3true assume 0 == ~E_4~0;~E_4~0 := 1; 19#L532-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 345#L228-15true assume 1 == ~m_pc~0; 230#L229-5true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 365#L239-5true is_master_triggered_#res := is_master_triggered_~__retres1~0; 232#L240-5true activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 246#L605-15true assume !(0 != activate_threads_~tmp~1); 252#L605-17true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 50#L247-15true assume !(1 == ~t1_pc~0); 48#L247-17true is_transmit1_triggered_~__retres1~1 := 0; 65#L258-5true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 327#L259-5true activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 360#L613-15true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 344#L613-17true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 149#L266-15true assume 1 == ~t2_pc~0; 133#L267-5true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 163#L277-5true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 134#L278-5true activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 69#L621-15true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 72#L621-17true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 289#L285-15true assume !(1 == ~t3_pc~0); 288#L285-17true is_transmit3_triggered_~__retres1~3 := 0; 201#L296-5true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 269#L297-5true activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 177#L629-15true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 158#L629-17true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 292#L304-15true assume !(1 == ~t4_pc~0); 294#L304-17true is_transmit4_triggered_~__retres1~4 := 0; 303#L315-5true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 358#L316-5true activate_threads_#t~ret10 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 183#L637-15true assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 187#L637-17true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27#L545-3true assume 1 == ~M_E~0;~M_E~0 := 2; 38#L545-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 271#L550-3true assume !(1 == ~T2_E~0); 90#L555-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 207#L560-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 18#L565-3true assume 1 == ~E_1~0;~E_1~0 := 2; 333#L570-3true assume 1 == ~E_2~0;~E_2~0 := 2; 146#L575-3true assume 1 == ~E_3~0;~E_3~0 := 2; 393#L580-3true assume 1 == ~E_4~0;~E_4~0 := 2; 112#L585-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 126#L364-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 40#L391-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 313#L392-1true start_simulation_#t~ret12 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 22#L785true assume !(0 == start_simulation_~tmp~3); 23#L785-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 127#L364-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 44#L391-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 314#L392-2true stop_simulation_#t~ret11 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 147#L740true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 221#L747true stop_simulation_#res := stop_simulation_~__retres2~0; 283#L748true start_simulation_#t~ret13 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 54#L798true assume !(0 != start_simulation_~tmp___0~1); 320#L766-3true [2018-11-18 09:11:31,150 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:11:31,150 INFO L82 PathProgramCache]: Analyzing trace with hash 1110077256, now seen corresponding path program 1 times [2018-11-18 09:11:31,152 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:11:31,152 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:11:31,191 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:31,191 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:11:31,191 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:31,217 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:11:31,266 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:11:31,269 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:11:31,269 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 09:11:31,273 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 09:11:31,274 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:11:31,274 INFO L82 PathProgramCache]: Analyzing trace with hash -599230231, now seen corresponding path program 1 times [2018-11-18 09:11:31,274 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:11:31,274 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:11:31,275 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:31,275 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:11:31,275 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:31,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:11:31,291 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:11:31,291 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:11:31,291 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 09:11:31,293 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 09:11:31,309 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 09:11:31,310 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 09:11:31,312 INFO L87 Difference]: Start difference. First operand 399 states. Second operand 3 states. [2018-11-18 09:11:31,357 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:11:31,357 INFO L93 Difference]: Finished difference Result 398 states and 589 transitions. [2018-11-18 09:11:31,358 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 09:11:31,360 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 398 states and 589 transitions. [2018-11-18 09:11:31,364 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 327 [2018-11-18 09:11:31,370 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 398 states to 392 states and 583 transitions. [2018-11-18 09:11:31,371 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 392 [2018-11-18 09:11:31,372 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 392 [2018-11-18 09:11:31,373 INFO L73 IsDeterministic]: Start isDeterministic. Operand 392 states and 583 transitions. [2018-11-18 09:11:31,376 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:11:31,376 INFO L705 BuchiCegarLoop]: Abstraction has 392 states and 583 transitions. [2018-11-18 09:11:31,394 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 392 states and 583 transitions. [2018-11-18 09:11:31,411 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 392 to 392. [2018-11-18 09:11:31,412 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 392 states. [2018-11-18 09:11:31,413 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 392 states to 392 states and 583 transitions. [2018-11-18 09:11:31,415 INFO L728 BuchiCegarLoop]: Abstraction has 392 states and 583 transitions. [2018-11-18 09:11:31,415 INFO L608 BuchiCegarLoop]: Abstraction has 392 states and 583 transitions. [2018-11-18 09:11:31,415 INFO L442 BuchiCegarLoop]: ======== Iteration 2============ [2018-11-18 09:11:31,415 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 392 states and 583 transitions. [2018-11-18 09:11:31,418 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 327 [2018-11-18 09:11:31,418 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:11:31,418 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:11:31,420 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:11:31,420 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:11:31,421 INFO L794 eck$LassoCheckResult]: Stem: 1141#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 1065#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 1027#L729 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 927#L324 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 928#L331 assume 1 == ~m_i~0;~m_st~0 := 0; 991#L331-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 887#L336-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 888#L341-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 931#L346-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 932#L351-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1068#L492 assume !(0 == ~M_E~0); 1197#L492-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 982#L497-1 assume !(0 == ~T2_E~0); 983#L502-1 assume !(0 == ~T3_E~0); 993#L507-1 assume !(0 == ~T4_E~0); 900#L512-1 assume !(0 == ~E_1~0); 901#L517-1 assume !(0 == ~E_2~0); 941#L522-1 assume !(0 == ~E_3~0); 942#L527-1 assume !(0 == ~E_4~0); 829#L532-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 830#L228 assume 1 == ~m_pc~0; 1098#L229 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 1099#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1101#L240 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 1102#L605 assume !(0 != activate_threads_~tmp~1); 1149#L605-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 954#L247 assume 1 == ~t1_pc~0; 878#L248 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 879#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 882#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 883#L613 assume !(0 != activate_threads_~tmp___0~0); 1195#L613-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 970#L266 assume !(1 == ~t2_pc~0); 971#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 973#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 974#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 808#L621 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 809#L621-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 814#L285 assume 1 == ~t3_pc~0; 1061#L286 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1056#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1062#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 990#L629 assume !(0 != activate_threads_~tmp___2~0); 975#L629-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 976#L304 assume !(1 == ~t4_pc~0); 1163#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 1164#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1176#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1090#L637 assume !(0 != activate_threads_~tmp___3~0); 1091#L637-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 894#L545 assume !(1 == ~M_E~0); 895#L545-2 assume !(1 == ~T1_E~0); 902#L550-1 assume !(1 == ~T2_E~0); 817#L555-1 assume !(1 == ~T3_E~0); 818#L560-1 assume !(1 == ~T4_E~0); 827#L565-1 assume !(1 == ~E_1~0); 828#L570-1 assume !(1 == ~E_2~0); 1020#L575-1 assume 1 == ~E_3~0;~E_3~0 := 2; 1021#L580-1 assume !(1 == ~E_4~0); 977#L585-1 assume { :end_inline_reset_delta_events } true; 904#L766-3 [2018-11-18 09:11:31,421 INFO L796 eck$LassoCheckResult]: Loop: 904#L766-3 assume true; 1179#L766-1 assume !false; 1155#L767 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 943#L467 assume true; 944#L401-1 assume !false; 863#L402 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 864#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 867#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 868#L392 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 1084#L406 assume !(0 != eval_~tmp~0); 1086#L482 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 935#L324-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 936#L492-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1190#L492-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 960#L497-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 961#L502-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 992#L507-3 assume !(0 == ~T4_E~0); 858#L512-3 assume 0 == ~E_1~0;~E_1~0 := 1; 859#L517-3 assume 0 == ~E_2~0;~E_2~0 := 1; 950#L522-3 assume 0 == ~E_3~0;~E_3~0 := 1; 951#L527-3 assume 0 == ~E_4~0;~E_4~0 := 1; 833#L532-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 834#L228-15 assume 1 == ~m_pc~0; 1108#L229-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 1109#L239-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1111#L240-5 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 1112#L605-15 assume !(0 != activate_threads_~tmp~1); 1135#L605-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 896#L247-15 assume 1 == ~t1_pc~0; 897#L248-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 893#L258-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 918#L259-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1183#L613-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1185#L613-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1028#L266-15 assume 1 == ~t2_pc~0; 1001#L267-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1003#L277-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1004#L278-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 920#L621-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 921#L621-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 924#L285-15 assume 1 == ~t3_pc~0; 1145#L286-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1075#L296-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1076#L297-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1046#L629-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1034#L629-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1035#L304-15 assume !(1 == ~t4_pc~0); 1153#L304-17 is_transmit4_triggered_~__retres1~4 := 0; 1156#L315-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1169#L316-5 activate_threads_#t~ret10 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1053#L637-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1054#L637-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 850#L545-3 assume 1 == ~M_E~0;~M_E~0 := 2; 851#L545-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 873#L550-3 assume !(1 == ~T2_E~0); 948#L555-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 949#L560-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 831#L565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 832#L570-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1023#L575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1024#L580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 980#L585-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 981#L364-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 876#L391-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 877#L392-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 839#L785 assume !(0 == start_simulation_~tmp~3); 841#L785-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 842#L364-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 884#L391-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 885#L392-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 1025#L740 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1026#L747 stop_simulation_#res := stop_simulation_~__retres2~0; 1093#L748 start_simulation_#t~ret13 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 903#L798 assume !(0 != start_simulation_~tmp___0~1); 904#L766-3 [2018-11-18 09:11:31,422 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:11:31,422 INFO L82 PathProgramCache]: Analyzing trace with hash 1069402506, now seen corresponding path program 1 times [2018-11-18 09:11:31,422 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:11:31,422 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:11:31,423 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:31,423 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:11:31,423 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:31,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:11:31,473 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:11:31,473 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:11:31,473 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 09:11:31,473 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 09:11:31,474 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:11:31,474 INFO L82 PathProgramCache]: Analyzing trace with hash -1523718106, now seen corresponding path program 1 times [2018-11-18 09:11:31,474 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:11:31,474 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:11:31,475 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:31,475 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:11:31,475 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:31,491 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:11:31,535 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:11:31,536 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:11:31,536 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 09:11:31,536 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 09:11:31,537 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 09:11:31,537 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 09:11:31,537 INFO L87 Difference]: Start difference. First operand 392 states and 583 transitions. cyclomatic complexity: 192 Second operand 3 states. [2018-11-18 09:11:31,553 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:11:31,553 INFO L93 Difference]: Finished difference Result 392 states and 582 transitions. [2018-11-18 09:11:31,554 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 09:11:31,554 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 392 states and 582 transitions. [2018-11-18 09:11:31,558 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 327 [2018-11-18 09:11:31,561 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 392 states to 392 states and 582 transitions. [2018-11-18 09:11:31,562 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 392 [2018-11-18 09:11:31,562 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 392 [2018-11-18 09:11:31,563 INFO L73 IsDeterministic]: Start isDeterministic. Operand 392 states and 582 transitions. [2018-11-18 09:11:31,564 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:11:31,564 INFO L705 BuchiCegarLoop]: Abstraction has 392 states and 582 transitions. [2018-11-18 09:11:31,565 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 392 states and 582 transitions. [2018-11-18 09:11:31,576 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 392 to 392. [2018-11-18 09:11:31,576 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 392 states. [2018-11-18 09:11:31,578 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 392 states to 392 states and 582 transitions. [2018-11-18 09:11:31,578 INFO L728 BuchiCegarLoop]: Abstraction has 392 states and 582 transitions. [2018-11-18 09:11:31,578 INFO L608 BuchiCegarLoop]: Abstraction has 392 states and 582 transitions. [2018-11-18 09:11:31,578 INFO L442 BuchiCegarLoop]: ======== Iteration 3============ [2018-11-18 09:11:31,579 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 392 states and 582 transitions. [2018-11-18 09:11:31,582 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 327 [2018-11-18 09:11:31,582 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:11:31,582 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:11:31,584 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:11:31,584 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:11:31,584 INFO L794 eck$LassoCheckResult]: Stem: 1932#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 1856#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 1818#L729 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 1718#L324 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1719#L331 assume 1 == ~m_i~0;~m_st~0 := 0; 1782#L331-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1678#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1679#L341-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1722#L346-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1723#L351-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1859#L492 assume !(0 == ~M_E~0); 1988#L492-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1773#L497-1 assume !(0 == ~T2_E~0); 1774#L502-1 assume !(0 == ~T3_E~0); 1784#L507-1 assume !(0 == ~T4_E~0); 1691#L512-1 assume !(0 == ~E_1~0); 1692#L517-1 assume !(0 == ~E_2~0); 1732#L522-1 assume !(0 == ~E_3~0); 1733#L527-1 assume !(0 == ~E_4~0); 1620#L532-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1621#L228 assume 1 == ~m_pc~0; 1889#L229 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 1890#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1892#L240 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 1893#L605 assume !(0 != activate_threads_~tmp~1); 1940#L605-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1745#L247 assume 1 == ~t1_pc~0; 1669#L248 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1670#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1673#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1674#L613 assume !(0 != activate_threads_~tmp___0~0); 1986#L613-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1761#L266 assume !(1 == ~t2_pc~0); 1762#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 1764#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1765#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 1599#L621 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1600#L621-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1605#L285 assume 1 == ~t3_pc~0; 1852#L286 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1847#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1853#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1781#L629 assume !(0 != activate_threads_~tmp___2~0); 1766#L629-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1767#L304 assume !(1 == ~t4_pc~0); 1954#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 1955#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1967#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1881#L637 assume !(0 != activate_threads_~tmp___3~0); 1882#L637-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1685#L545 assume !(1 == ~M_E~0); 1686#L545-2 assume !(1 == ~T1_E~0); 1693#L550-1 assume !(1 == ~T2_E~0); 1608#L555-1 assume !(1 == ~T3_E~0); 1609#L560-1 assume !(1 == ~T4_E~0); 1618#L565-1 assume !(1 == ~E_1~0); 1619#L570-1 assume !(1 == ~E_2~0); 1811#L575-1 assume 1 == ~E_3~0;~E_3~0 := 2; 1812#L580-1 assume !(1 == ~E_4~0); 1768#L585-1 assume { :end_inline_reset_delta_events } true; 1695#L766-3 [2018-11-18 09:11:31,585 INFO L796 eck$LassoCheckResult]: Loop: 1695#L766-3 assume true; 1970#L766-1 assume !false; 1946#L767 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 1734#L467 assume true; 1735#L401-1 assume !false; 1654#L402 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1655#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 1658#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 1659#L392 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 1875#L406 assume !(0 != eval_~tmp~0); 1877#L482 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 1726#L324-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 1727#L492-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1981#L492-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1751#L497-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1752#L502-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1783#L507-3 assume !(0 == ~T4_E~0); 1649#L512-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1650#L517-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1741#L522-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1742#L527-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1624#L532-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1625#L228-15 assume 1 == ~m_pc~0; 1899#L229-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 1900#L239-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1902#L240-5 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 1903#L605-15 assume !(0 != activate_threads_~tmp~1); 1926#L605-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1687#L247-15 assume !(1 == ~t1_pc~0); 1683#L247-17 is_transmit1_triggered_~__retres1~1 := 0; 1684#L258-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1709#L259-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1974#L613-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1976#L613-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1819#L266-15 assume 1 == ~t2_pc~0; 1792#L267-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1794#L277-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1795#L278-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 1711#L621-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1712#L621-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1715#L285-15 assume 1 == ~t3_pc~0; 1936#L286-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1866#L296-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1867#L297-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1837#L629-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1825#L629-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1826#L304-15 assume !(1 == ~t4_pc~0); 1944#L304-17 is_transmit4_triggered_~__retres1~4 := 0; 1947#L315-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1960#L316-5 activate_threads_#t~ret10 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1844#L637-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1845#L637-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1641#L545-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1642#L545-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1664#L550-3 assume !(1 == ~T2_E~0); 1739#L555-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1740#L560-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1622#L565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1623#L570-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1814#L575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1815#L580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1771#L585-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1772#L364-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 1667#L391-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 1668#L392-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 1630#L785 assume !(0 == start_simulation_~tmp~3); 1632#L785-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 1633#L364-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 1675#L391-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 1676#L392-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 1816#L740 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1817#L747 stop_simulation_#res := stop_simulation_~__retres2~0; 1884#L748 start_simulation_#t~ret13 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 1694#L798 assume !(0 != start_simulation_~tmp___0~1); 1695#L766-3 [2018-11-18 09:11:31,585 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:11:31,585 INFO L82 PathProgramCache]: Analyzing trace with hash 193383500, now seen corresponding path program 1 times [2018-11-18 09:11:31,585 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:11:31,586 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:11:31,586 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:31,587 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:11:31,587 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:31,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:11:31,621 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:11:31,621 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:11:31,622 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 09:11:31,622 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 09:11:31,622 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:11:31,622 INFO L82 PathProgramCache]: Analyzing trace with hash 1463244421, now seen corresponding path program 1 times [2018-11-18 09:11:31,623 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:11:31,623 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:11:31,623 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:31,624 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:11:31,624 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:31,631 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:11:31,666 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:11:31,667 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:11:31,667 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 09:11:31,667 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 09:11:31,667 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 09:11:31,667 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 09:11:31,668 INFO L87 Difference]: Start difference. First operand 392 states and 582 transitions. cyclomatic complexity: 191 Second operand 3 states. [2018-11-18 09:11:31,680 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:11:31,680 INFO L93 Difference]: Finished difference Result 392 states and 581 transitions. [2018-11-18 09:11:31,681 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 09:11:31,681 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 392 states and 581 transitions. [2018-11-18 09:11:31,685 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 327 [2018-11-18 09:11:31,687 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 392 states to 392 states and 581 transitions. [2018-11-18 09:11:31,688 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 392 [2018-11-18 09:11:31,688 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 392 [2018-11-18 09:11:31,688 INFO L73 IsDeterministic]: Start isDeterministic. Operand 392 states and 581 transitions. [2018-11-18 09:11:31,689 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:11:31,689 INFO L705 BuchiCegarLoop]: Abstraction has 392 states and 581 transitions. [2018-11-18 09:11:31,690 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 392 states and 581 transitions. [2018-11-18 09:11:31,698 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 392 to 392. [2018-11-18 09:11:31,698 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 392 states. [2018-11-18 09:11:31,700 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 392 states to 392 states and 581 transitions. [2018-11-18 09:11:31,700 INFO L728 BuchiCegarLoop]: Abstraction has 392 states and 581 transitions. [2018-11-18 09:11:31,700 INFO L608 BuchiCegarLoop]: Abstraction has 392 states and 581 transitions. [2018-11-18 09:11:31,700 INFO L442 BuchiCegarLoop]: ======== Iteration 4============ [2018-11-18 09:11:31,700 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 392 states and 581 transitions. [2018-11-18 09:11:31,704 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 327 [2018-11-18 09:11:31,705 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:11:31,705 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:11:31,706 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:11:31,706 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:11:31,707 INFO L794 eck$LassoCheckResult]: Stem: 2723#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 2649#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 2609#L729 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 2511#L324 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2512#L331 assume 1 == ~m_i~0;~m_st~0 := 0; 2573#L331-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2469#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2470#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2513#L346-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2514#L351-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2651#L492 assume !(0 == ~M_E~0); 2779#L492-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2565#L497-1 assume !(0 == ~T2_E~0); 2566#L502-1 assume !(0 == ~T3_E~0); 2575#L507-1 assume !(0 == ~T4_E~0); 2483#L512-1 assume !(0 == ~E_1~0); 2484#L517-1 assume !(0 == ~E_2~0); 2523#L522-1 assume !(0 == ~E_3~0); 2524#L527-1 assume !(0 == ~E_4~0); 2411#L532-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2412#L228 assume 1 == ~m_pc~0; 2680#L229 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 2681#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2683#L240 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 2684#L605 assume !(0 != activate_threads_~tmp~1); 2731#L605-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2536#L247 assume 1 == ~t1_pc~0; 2461#L248 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2462#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2464#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 2465#L613 assume !(0 != activate_threads_~tmp___0~0); 2777#L613-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2552#L266 assume !(1 == ~t2_pc~0); 2553#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 2555#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2556#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2392#L621 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2393#L621-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2398#L285 assume 1 == ~t3_pc~0; 2643#L286 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2638#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2646#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2572#L629 assume !(0 != activate_threads_~tmp___2~0); 2557#L629-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2558#L304 assume !(1 == ~t4_pc~0); 2745#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 2746#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2758#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2672#L637 assume !(0 != activate_threads_~tmp___3~0); 2673#L637-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2476#L545 assume !(1 == ~M_E~0); 2477#L545-2 assume !(1 == ~T1_E~0); 2482#L550-1 assume !(1 == ~T2_E~0); 2399#L555-1 assume !(1 == ~T3_E~0); 2400#L560-1 assume !(1 == ~T4_E~0); 2409#L565-1 assume !(1 == ~E_1~0); 2410#L570-1 assume !(1 == ~E_2~0); 2602#L575-1 assume 1 == ~E_3~0;~E_3~0 := 2; 2603#L580-1 assume !(1 == ~E_4~0); 2559#L585-1 assume { :end_inline_reset_delta_events } true; 2486#L766-3 [2018-11-18 09:11:31,707 INFO L796 eck$LassoCheckResult]: Loop: 2486#L766-3 assume true; 2761#L766-1 assume !false; 2737#L767 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 2525#L467 assume true; 2526#L401-1 assume !false; 2445#L402 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 2446#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 2449#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 2450#L392 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 2666#L406 assume !(0 != eval_~tmp~0); 2668#L482 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 2517#L324-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 2518#L492-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2772#L492-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2542#L497-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2543#L502-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2574#L507-3 assume !(0 == ~T4_E~0); 2440#L512-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2441#L517-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2532#L522-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2533#L527-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2415#L532-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2416#L228-15 assume 1 == ~m_pc~0; 2690#L229-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 2691#L239-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2693#L240-5 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 2694#L605-15 assume !(0 != activate_threads_~tmp~1); 2717#L605-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2478#L247-15 assume !(1 == ~t1_pc~0); 2474#L247-17 is_transmit1_triggered_~__retres1~1 := 0; 2475#L258-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2500#L259-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 2765#L613-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2767#L613-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2610#L266-15 assume 1 == ~t2_pc~0; 2583#L267-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2585#L277-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2586#L278-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2502#L621-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2503#L621-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2506#L285-15 assume 1 == ~t3_pc~0; 2727#L286-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2657#L296-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2658#L297-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2628#L629-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2616#L629-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2617#L304-15 assume 1 == ~t4_pc~0; 2736#L305-5 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2738#L315-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2751#L316-5 activate_threads_#t~ret10 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2635#L637-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 2636#L637-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2432#L545-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2433#L545-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2455#L550-3 assume !(1 == ~T2_E~0); 2530#L555-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2531#L560-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2413#L565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2414#L570-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2605#L575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2606#L580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2562#L585-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 2563#L364-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 2458#L391-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 2459#L392-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 2421#L785 assume !(0 == start_simulation_~tmp~3); 2423#L785-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 2424#L364-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 2466#L391-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 2467#L392-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 2607#L740 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2608#L747 stop_simulation_#res := stop_simulation_~__retres2~0; 2675#L748 start_simulation_#t~ret13 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 2485#L798 assume !(0 != start_simulation_~tmp___0~1); 2486#L766-3 [2018-11-18 09:11:31,707 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:11:31,707 INFO L82 PathProgramCache]: Analyzing trace with hash -250517174, now seen corresponding path program 1 times [2018-11-18 09:11:31,708 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:11:31,708 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:11:31,709 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:31,709 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:11:31,709 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:31,715 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:11:31,730 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:11:31,730 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:11:31,730 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 09:11:31,731 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 09:11:31,731 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:11:31,731 INFO L82 PathProgramCache]: Analyzing trace with hash 1771683430, now seen corresponding path program 1 times [2018-11-18 09:11:31,731 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:11:31,731 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:11:31,732 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:31,732 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:11:31,733 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:31,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:11:31,777 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:11:31,778 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:11:31,778 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 09:11:31,778 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 09:11:31,778 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 09:11:31,778 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 09:11:31,779 INFO L87 Difference]: Start difference. First operand 392 states and 581 transitions. cyclomatic complexity: 190 Second operand 3 states. [2018-11-18 09:11:31,792 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:11:31,792 INFO L93 Difference]: Finished difference Result 392 states and 580 transitions. [2018-11-18 09:11:31,793 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 09:11:31,793 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 392 states and 580 transitions. [2018-11-18 09:11:31,796 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 327 [2018-11-18 09:11:31,799 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 392 states to 392 states and 580 transitions. [2018-11-18 09:11:31,799 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 392 [2018-11-18 09:11:31,799 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 392 [2018-11-18 09:11:31,800 INFO L73 IsDeterministic]: Start isDeterministic. Operand 392 states and 580 transitions. [2018-11-18 09:11:31,801 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:11:31,801 INFO L705 BuchiCegarLoop]: Abstraction has 392 states and 580 transitions. [2018-11-18 09:11:31,802 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 392 states and 580 transitions. [2018-11-18 09:11:31,808 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 392 to 392. [2018-11-18 09:11:31,808 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 392 states. [2018-11-18 09:11:31,810 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 392 states to 392 states and 580 transitions. [2018-11-18 09:11:31,810 INFO L728 BuchiCegarLoop]: Abstraction has 392 states and 580 transitions. [2018-11-18 09:11:31,810 INFO L608 BuchiCegarLoop]: Abstraction has 392 states and 580 transitions. [2018-11-18 09:11:31,810 INFO L442 BuchiCegarLoop]: ======== Iteration 5============ [2018-11-18 09:11:31,810 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 392 states and 580 transitions. [2018-11-18 09:11:31,813 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 327 [2018-11-18 09:11:31,813 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:11:31,813 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:11:31,814 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:11:31,814 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:11:31,815 INFO L794 eck$LassoCheckResult]: Stem: 3514#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 3440#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 3400#L729 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 3300#L324 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3301#L331 assume 1 == ~m_i~0;~m_st~0 := 0; 3364#L331-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3260#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3261#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3304#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3305#L351-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3441#L492 assume !(0 == ~M_E~0); 3570#L492-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3355#L497-1 assume !(0 == ~T2_E~0); 3356#L502-1 assume !(0 == ~T3_E~0); 3366#L507-1 assume !(0 == ~T4_E~0); 3273#L512-1 assume !(0 == ~E_1~0); 3274#L517-1 assume !(0 == ~E_2~0); 3314#L522-1 assume !(0 == ~E_3~0); 3315#L527-1 assume !(0 == ~E_4~0); 3202#L532-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3203#L228 assume 1 == ~m_pc~0; 3471#L229 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 3472#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3474#L240 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 3475#L605 assume !(0 != activate_threads_~tmp~1); 3522#L605-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3327#L247 assume 1 == ~t1_pc~0; 3252#L248 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 3253#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3255#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 3256#L613 assume !(0 != activate_threads_~tmp___0~0); 3568#L613-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3343#L266 assume !(1 == ~t2_pc~0); 3344#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 3346#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3347#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 3183#L621 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3184#L621-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3189#L285 assume 1 == ~t3_pc~0; 3434#L286 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3429#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3437#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 3363#L629 assume !(0 != activate_threads_~tmp___2~0); 3348#L629-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3349#L304 assume !(1 == ~t4_pc~0); 3536#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 3537#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3549#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3463#L637 assume !(0 != activate_threads_~tmp___3~0); 3464#L637-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3267#L545 assume !(1 == ~M_E~0); 3268#L545-2 assume !(1 == ~T1_E~0); 3275#L550-1 assume !(1 == ~T2_E~0); 3190#L555-1 assume !(1 == ~T3_E~0); 3191#L560-1 assume !(1 == ~T4_E~0); 3200#L565-1 assume !(1 == ~E_1~0); 3201#L570-1 assume !(1 == ~E_2~0); 3393#L575-1 assume 1 == ~E_3~0;~E_3~0 := 2; 3394#L580-1 assume !(1 == ~E_4~0); 3350#L585-1 assume { :end_inline_reset_delta_events } true; 3277#L766-3 [2018-11-18 09:11:31,815 INFO L796 eck$LassoCheckResult]: Loop: 3277#L766-3 assume true; 3552#L766-1 assume !false; 3529#L767 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 3316#L467 assume true; 3317#L401-1 assume !false; 3236#L402 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 3237#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 3240#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3241#L392 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 3457#L406 assume !(0 != eval_~tmp~0); 3459#L482 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 3308#L324-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 3309#L492-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3563#L492-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3333#L497-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3334#L502-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3365#L507-3 assume !(0 == ~T4_E~0); 3231#L512-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3232#L517-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3323#L522-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3324#L527-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3206#L532-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3207#L228-15 assume 1 == ~m_pc~0; 3481#L229-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 3482#L239-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3484#L240-5 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 3485#L605-15 assume !(0 != activate_threads_~tmp~1); 3508#L605-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3269#L247-15 assume !(1 == ~t1_pc~0); 3265#L247-17 is_transmit1_triggered_~__retres1~1 := 0; 3266#L258-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3291#L259-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 3556#L613-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3558#L613-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3401#L266-15 assume 1 == ~t2_pc~0; 3374#L267-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3376#L277-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3377#L278-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 3293#L621-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3294#L621-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3297#L285-15 assume 1 == ~t3_pc~0; 3518#L286-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3448#L296-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3449#L297-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 3419#L629-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 3407#L629-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3408#L304-15 assume !(1 == ~t4_pc~0); 3526#L304-17 is_transmit4_triggered_~__retres1~4 := 0; 3528#L315-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3542#L316-5 activate_threads_#t~ret10 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3424#L637-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 3425#L637-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3218#L545-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3219#L545-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3242#L550-3 assume !(1 == ~T2_E~0); 3318#L555-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3319#L560-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3204#L565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3205#L570-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3396#L575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3397#L580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3353#L585-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 3354#L364-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 3249#L391-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3250#L392-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 3212#L785 assume !(0 == start_simulation_~tmp~3); 3214#L785-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 3215#L364-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 3257#L391-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 3258#L392-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 3398#L740 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 3399#L747 stop_simulation_#res := stop_simulation_~__retres2~0; 3466#L748 start_simulation_#t~ret13 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 3276#L798 assume !(0 != start_simulation_~tmp___0~1); 3277#L766-3 [2018-11-18 09:11:31,815 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:11:31,816 INFO L82 PathProgramCache]: Analyzing trace with hash -1788857204, now seen corresponding path program 1 times [2018-11-18 09:11:31,816 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:11:31,816 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:11:31,817 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:31,817 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:11:31,817 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:31,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:11:31,854 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:11:31,854 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:11:31,854 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 09:11:31,855 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 09:11:31,855 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:11:31,855 INFO L82 PathProgramCache]: Analyzing trace with hash 1463244421, now seen corresponding path program 2 times [2018-11-18 09:11:31,855 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:11:31,855 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:11:31,856 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:31,856 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:11:31,857 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:31,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:11:31,905 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:11:31,905 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:11:31,905 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 09:11:31,906 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 09:11:31,906 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 09:11:31,906 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 09:11:31,906 INFO L87 Difference]: Start difference. First operand 392 states and 580 transitions. cyclomatic complexity: 189 Second operand 3 states. [2018-11-18 09:11:31,937 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:11:31,937 INFO L93 Difference]: Finished difference Result 392 states and 575 transitions. [2018-11-18 09:11:31,938 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 09:11:31,938 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 392 states and 575 transitions. [2018-11-18 09:11:31,941 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 327 [2018-11-18 09:11:31,943 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 392 states to 392 states and 575 transitions. [2018-11-18 09:11:31,943 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 392 [2018-11-18 09:11:31,944 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 392 [2018-11-18 09:11:31,944 INFO L73 IsDeterministic]: Start isDeterministic. Operand 392 states and 575 transitions. [2018-11-18 09:11:31,945 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:11:31,945 INFO L705 BuchiCegarLoop]: Abstraction has 392 states and 575 transitions. [2018-11-18 09:11:31,946 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 392 states and 575 transitions. [2018-11-18 09:11:31,952 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 392 to 392. [2018-11-18 09:11:31,952 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 392 states. [2018-11-18 09:11:31,953 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 392 states to 392 states and 575 transitions. [2018-11-18 09:11:31,954 INFO L728 BuchiCegarLoop]: Abstraction has 392 states and 575 transitions. [2018-11-18 09:11:31,954 INFO L608 BuchiCegarLoop]: Abstraction has 392 states and 575 transitions. [2018-11-18 09:11:31,954 INFO L442 BuchiCegarLoop]: ======== Iteration 6============ [2018-11-18 09:11:31,954 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 392 states and 575 transitions. [2018-11-18 09:11:31,956 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 327 [2018-11-18 09:11:31,956 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:11:31,957 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:11:31,958 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:11:31,958 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:11:31,958 INFO L794 eck$LassoCheckResult]: Stem: 4305#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 4229#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 4191#L729 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 4091#L324 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4092#L331 assume 1 == ~m_i~0;~m_st~0 := 0; 4155#L331-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4051#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4052#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4095#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4096#L351-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4232#L492 assume !(0 == ~M_E~0); 4361#L492-2 assume !(0 == ~T1_E~0); 4146#L497-1 assume !(0 == ~T2_E~0); 4147#L502-1 assume !(0 == ~T3_E~0); 4157#L507-1 assume !(0 == ~T4_E~0); 4064#L512-1 assume !(0 == ~E_1~0); 4065#L517-1 assume !(0 == ~E_2~0); 4105#L522-1 assume !(0 == ~E_3~0); 4106#L527-1 assume !(0 == ~E_4~0); 3993#L532-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3994#L228 assume 1 == ~m_pc~0; 4262#L229 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 4263#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4265#L240 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 4266#L605 assume !(0 != activate_threads_~tmp~1); 4313#L605-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4118#L247 assume 1 == ~t1_pc~0; 4042#L248 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 4043#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4046#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 4047#L613 assume !(0 != activate_threads_~tmp___0~0); 4359#L613-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4134#L266 assume !(1 == ~t2_pc~0); 4135#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 4137#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4138#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 3972#L621 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3973#L621-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3978#L285 assume 1 == ~t3_pc~0; 4225#L286 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 4220#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4226#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 4154#L629 assume !(0 != activate_threads_~tmp___2~0); 4139#L629-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4140#L304 assume !(1 == ~t4_pc~0); 4327#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 4328#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4340#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 4254#L637 assume !(0 != activate_threads_~tmp___3~0); 4255#L637-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4058#L545 assume !(1 == ~M_E~0); 4059#L545-2 assume !(1 == ~T1_E~0); 4066#L550-1 assume !(1 == ~T2_E~0); 3981#L555-1 assume !(1 == ~T3_E~0); 3982#L560-1 assume !(1 == ~T4_E~0); 3991#L565-1 assume !(1 == ~E_1~0); 3992#L570-1 assume !(1 == ~E_2~0); 4184#L575-1 assume 1 == ~E_3~0;~E_3~0 := 2; 4185#L580-1 assume !(1 == ~E_4~0); 4141#L585-1 assume { :end_inline_reset_delta_events } true; 4068#L766-3 [2018-11-18 09:11:31,959 INFO L796 eck$LassoCheckResult]: Loop: 4068#L766-3 assume true; 4343#L766-1 assume !false; 4319#L767 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 4107#L467 assume true; 4108#L401-1 assume !false; 4027#L402 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 4028#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 4031#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 4032#L392 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 4248#L406 assume !(0 != eval_~tmp~0); 4250#L482 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 4099#L324-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 4100#L492-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4354#L492-5 assume !(0 == ~T1_E~0); 4124#L497-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4125#L502-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4156#L507-3 assume !(0 == ~T4_E~0); 4022#L512-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4023#L517-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4114#L522-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4115#L527-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3997#L532-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3998#L228-15 assume 1 == ~m_pc~0; 4272#L229-5 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 4273#L239-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4275#L240-5 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 4276#L605-15 assume !(0 != activate_threads_~tmp~1); 4299#L605-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4060#L247-15 assume !(1 == ~t1_pc~0); 4056#L247-17 is_transmit1_triggered_~__retres1~1 := 0; 4057#L258-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4082#L259-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 4347#L613-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4349#L613-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4192#L266-15 assume 1 == ~t2_pc~0; 4165#L267-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4167#L277-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4168#L278-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 4084#L621-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4085#L621-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4088#L285-15 assume 1 == ~t3_pc~0; 4309#L286-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 4239#L296-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4240#L297-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 4210#L629-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 4198#L629-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4199#L304-15 assume !(1 == ~t4_pc~0); 4317#L304-17 is_transmit4_triggered_~__retres1~4 := 0; 4320#L315-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4333#L316-5 activate_threads_#t~ret10 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 4217#L637-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 4218#L637-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4014#L545-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4015#L545-5 assume !(1 == ~T1_E~0); 4037#L550-3 assume !(1 == ~T2_E~0); 4112#L555-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4113#L560-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3995#L565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3996#L570-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4187#L575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4188#L580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4144#L585-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 4145#L364-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 4040#L391-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 4041#L392-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 4003#L785 assume !(0 == start_simulation_~tmp~3); 4005#L785-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 4006#L364-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 4048#L391-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 4049#L392-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 4189#L740 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 4190#L747 stop_simulation_#res := stop_simulation_~__retres2~0; 4257#L748 start_simulation_#t~ret13 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 4067#L798 assume !(0 != start_simulation_~tmp___0~1); 4068#L766-3 [2018-11-18 09:11:31,959 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:11:31,959 INFO L82 PathProgramCache]: Analyzing trace with hash -1804375922, now seen corresponding path program 1 times [2018-11-18 09:11:31,959 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:11:31,959 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:11:31,960 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:31,960 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 09:11:31,961 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:31,965 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:11:31,996 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:11:31,997 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:11:31,997 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 09:11:31,997 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 09:11:31,997 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:11:31,998 INFO L82 PathProgramCache]: Analyzing trace with hash -447446391, now seen corresponding path program 1 times [2018-11-18 09:11:31,998 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:11:31,998 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:11:31,999 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:31,999 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:11:31,999 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:32,005 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:11:32,042 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:11:32,042 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:11:32,042 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 09:11:32,043 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 09:11:32,043 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 09:11:32,043 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 09:11:32,043 INFO L87 Difference]: Start difference. First operand 392 states and 575 transitions. cyclomatic complexity: 184 Second operand 3 states. [2018-11-18 09:11:32,110 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:11:32,111 INFO L93 Difference]: Finished difference Result 711 states and 1030 transitions. [2018-11-18 09:11:32,111 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 09:11:32,111 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 711 states and 1030 transitions. [2018-11-18 09:11:32,116 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 645 [2018-11-18 09:11:32,120 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 711 states to 711 states and 1030 transitions. [2018-11-18 09:11:32,120 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 711 [2018-11-18 09:11:32,121 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 711 [2018-11-18 09:11:32,121 INFO L73 IsDeterministic]: Start isDeterministic. Operand 711 states and 1030 transitions. [2018-11-18 09:11:32,123 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:11:32,123 INFO L705 BuchiCegarLoop]: Abstraction has 711 states and 1030 transitions. [2018-11-18 09:11:32,124 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states and 1030 transitions. [2018-11-18 09:11:32,134 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 674. [2018-11-18 09:11:32,134 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 674 states. [2018-11-18 09:11:32,136 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 674 states to 674 states and 980 transitions. [2018-11-18 09:11:32,137 INFO L728 BuchiCegarLoop]: Abstraction has 674 states and 980 transitions. [2018-11-18 09:11:32,137 INFO L608 BuchiCegarLoop]: Abstraction has 674 states and 980 transitions. [2018-11-18 09:11:32,137 INFO L442 BuchiCegarLoop]: ======== Iteration 7============ [2018-11-18 09:11:32,137 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 674 states and 980 transitions. [2018-11-18 09:11:32,140 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 608 [2018-11-18 09:11:32,140 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:11:32,141 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:11:32,142 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:11:32,142 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:11:32,143 INFO L794 eck$LassoCheckResult]: Stem: 5415#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 5342#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 5303#L729 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 5201#L324 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5202#L331 assume 1 == ~m_i~0;~m_st~0 := 0; 5266#L331-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5161#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5162#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5205#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5206#L351-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5345#L492 assume !(0 == ~M_E~0); 5483#L492-2 assume !(0 == ~T1_E~0); 5257#L497-1 assume !(0 == ~T2_E~0); 5258#L502-1 assume !(0 == ~T3_E~0); 5268#L507-1 assume !(0 == ~T4_E~0); 5174#L512-1 assume !(0 == ~E_1~0); 5175#L517-1 assume !(0 == ~E_2~0); 5215#L522-1 assume !(0 == ~E_3~0); 5216#L527-1 assume !(0 == ~E_4~0); 5103#L532-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5104#L228 assume !(1 == ~m_pc~0); 5478#L228-2 is_master_triggered_~__retres1~0 := 0; 5470#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5375#L240 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 5376#L605 assume !(0 != activate_threads_~tmp~1); 5423#L605-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5229#L247 assume 1 == ~t1_pc~0; 5152#L248 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 5153#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5156#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 5157#L613 assume !(0 != activate_threads_~tmp___0~0); 5481#L613-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5245#L266 assume !(1 == ~t2_pc~0); 5246#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 5248#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5249#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 5082#L621 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 5083#L621-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5088#L285 assume 1 == ~t3_pc~0; 5338#L286 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 5333#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5339#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 5265#L629 assume !(0 != activate_threads_~tmp___2~0); 5250#L629-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5251#L304 assume !(1 == ~t4_pc~0); 5437#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 5438#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5450#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 5367#L637 assume !(0 != activate_threads_~tmp___3~0); 5368#L637-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5168#L545 assume !(1 == ~M_E~0); 5169#L545-2 assume !(1 == ~T1_E~0); 5176#L550-1 assume !(1 == ~T2_E~0); 5091#L555-1 assume !(1 == ~T3_E~0); 5092#L560-1 assume !(1 == ~T4_E~0); 5101#L565-1 assume !(1 == ~E_1~0); 5102#L570-1 assume !(1 == ~E_2~0); 5296#L575-1 assume 1 == ~E_3~0;~E_3~0 := 2; 5297#L580-1 assume !(1 == ~E_4~0); 5252#L585-1 assume { :end_inline_reset_delta_events } true; 5178#L766-3 [2018-11-18 09:11:32,143 INFO L796 eck$LassoCheckResult]: Loop: 5178#L766-3 assume true; 5453#L766-1 assume !false; 5429#L767 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 5217#L467 assume true; 5218#L401-1 assume !false; 5137#L402 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 5138#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 5141#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 5142#L392 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 5361#L406 assume !(0 != eval_~tmp~0); 5363#L482 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 5209#L324-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 5210#L492-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5474#L492-5 assume !(0 == ~T1_E~0); 5235#L497-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5236#L502-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5267#L507-3 assume !(0 == ~T4_E~0); 5132#L512-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5133#L517-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5225#L522-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5226#L527-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5107#L532-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5108#L228-15 assume !(1 == ~m_pc~0); 5461#L228-17 is_master_triggered_~__retres1~0 := 0; 5462#L239-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5385#L240-5 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 5386#L605-15 assume !(0 != activate_threads_~tmp~1); 5409#L605-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5170#L247-15 assume 1 == ~t1_pc~0; 5171#L248-5 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 5167#L258-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5192#L259-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 5458#L613-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5465#L613-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5304#L266-15 assume 1 == ~t2_pc~0; 5276#L267-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5278#L277-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5279#L278-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 5194#L621-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 5195#L621-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5198#L285-15 assume 1 == ~t3_pc~0; 5419#L286-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 5352#L296-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5353#L297-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 5323#L629-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 5310#L629-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5311#L304-15 assume !(1 == ~t4_pc~0); 5427#L304-17 is_transmit4_triggered_~__retres1~4 := 0; 5430#L315-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5443#L316-5 activate_threads_#t~ret10 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 5330#L637-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 5331#L637-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5124#L545-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5125#L545-5 assume !(1 == ~T1_E~0); 5147#L550-3 assume !(1 == ~T2_E~0); 5223#L555-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5224#L560-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5105#L565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5106#L570-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5299#L575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5300#L580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5255#L585-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 5256#L364-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 5150#L391-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 5151#L392-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 5113#L785 assume !(0 == start_simulation_~tmp~3); 5115#L785-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 5116#L364-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 5158#L391-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 5159#L392-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 5301#L740 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5302#L747 stop_simulation_#res := stop_simulation_~__retres2~0; 5370#L748 start_simulation_#t~ret13 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 5177#L798 assume !(0 != start_simulation_~tmp___0~1); 5178#L766-3 [2018-11-18 09:11:32,143 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:11:32,144 INFO L82 PathProgramCache]: Analyzing trace with hash -1404384723, now seen corresponding path program 1 times [2018-11-18 09:11:32,144 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:11:32,144 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:11:32,145 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:32,145 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:11:32,145 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:32,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:11:32,169 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:11:32,170 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:11:32,170 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 09:11:32,170 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 09:11:32,170 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:11:32,171 INFO L82 PathProgramCache]: Analyzing trace with hash 158990153, now seen corresponding path program 1 times [2018-11-18 09:11:32,171 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:11:32,171 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:11:32,172 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:32,172 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:11:32,172 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:32,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:11:32,202 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:11:32,202 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:11:32,202 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 09:11:32,202 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 09:11:32,203 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 09:11:32,203 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 09:11:32,203 INFO L87 Difference]: Start difference. First operand 674 states and 980 transitions. cyclomatic complexity: 308 Second operand 3 states. [2018-11-18 09:11:32,289 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:11:32,289 INFO L93 Difference]: Finished difference Result 1199 states and 1731 transitions. [2018-11-18 09:11:32,289 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 09:11:32,290 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1199 states and 1731 transitions. [2018-11-18 09:11:32,297 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1128 [2018-11-18 09:11:32,303 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1199 states to 1199 states and 1731 transitions. [2018-11-18 09:11:32,303 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1199 [2018-11-18 09:11:32,304 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1199 [2018-11-18 09:11:32,305 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1199 states and 1731 transitions. [2018-11-18 09:11:32,307 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:11:32,307 INFO L705 BuchiCegarLoop]: Abstraction has 1199 states and 1731 transitions. [2018-11-18 09:11:32,309 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1199 states and 1731 transitions. [2018-11-18 09:11:32,327 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1199 to 1193. [2018-11-18 09:11:32,327 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1193 states. [2018-11-18 09:11:32,331 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1193 states to 1193 states and 1725 transitions. [2018-11-18 09:11:32,331 INFO L728 BuchiCegarLoop]: Abstraction has 1193 states and 1725 transitions. [2018-11-18 09:11:32,331 INFO L608 BuchiCegarLoop]: Abstraction has 1193 states and 1725 transitions. [2018-11-18 09:11:32,331 INFO L442 BuchiCegarLoop]: ======== Iteration 8============ [2018-11-18 09:11:32,332 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1193 states and 1725 transitions. [2018-11-18 09:11:32,350 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1122 [2018-11-18 09:11:32,351 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:11:32,351 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:11:32,352 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:11:32,352 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:11:32,352 INFO L794 eck$LassoCheckResult]: Stem: 7309#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 7233#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 7189#L729 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 7084#L324 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7085#L331 assume 1 == ~m_i~0;~m_st~0 := 0; 7151#L331-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7042#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7043#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7086#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7087#L351-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7235#L492 assume !(0 == ~M_E~0); 7405#L492-2 assume !(0 == ~T1_E~0); 7141#L497-1 assume !(0 == ~T2_E~0); 7142#L502-1 assume !(0 == ~T3_E~0); 7153#L507-1 assume !(0 == ~T4_E~0); 7053#L512-1 assume !(0 == ~E_1~0); 7054#L517-1 assume !(0 == ~E_2~0); 7096#L522-1 assume !(0 == ~E_3~0); 7097#L527-1 assume !(0 == ~E_4~0); 6985#L532-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6986#L228 assume !(1 == ~m_pc~0); 7399#L228-2 is_master_triggered_~__retres1~0 := 0; 7386#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7268#L240 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 7269#L605 assume !(0 != activate_threads_~tmp~1); 7321#L605-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7112#L247 assume !(1 == ~t1_pc~0); 7098#L247-2 is_transmit1_triggered_~__retres1~1 := 0; 7099#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7037#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 7038#L613 assume !(0 != activate_threads_~tmp___0~0); 7402#L613-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7128#L266 assume !(1 == ~t2_pc~0); 7129#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 7131#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7132#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 6964#L621 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 6965#L621-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6970#L285 assume 1 == ~t3_pc~0; 7227#L286 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 7222#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7230#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 7150#L629 assume !(0 != activate_threads_~tmp___2~0); 7133#L629-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7134#L304 assume !(1 == ~t4_pc~0); 7337#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 7338#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7353#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 7260#L637 assume !(0 != activate_threads_~tmp___3~0); 7261#L637-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7048#L545 assume !(1 == ~M_E~0); 7049#L545-2 assume !(1 == ~T1_E~0); 7055#L550-1 assume !(1 == ~T2_E~0); 6973#L555-1 assume !(1 == ~T3_E~0); 6974#L560-1 assume !(1 == ~T4_E~0); 6983#L565-1 assume !(1 == ~E_1~0); 6984#L570-1 assume !(1 == ~E_2~0); 7183#L575-1 assume 1 == ~E_3~0;~E_3~0 := 2; 7184#L580-1 assume !(1 == ~E_4~0); 7135#L585-1 assume { :end_inline_reset_delta_events } true; 7057#L766-3 [2018-11-18 09:11:32,352 INFO L796 eck$LassoCheckResult]: Loop: 7057#L766-3 assume true; 7356#L766-1 assume !false; 7357#L767 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 7100#L467 assume true; 7101#L401-1 assume !false; 7021#L402 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 7022#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 7025#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 7026#L392 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 7253#L406 assume !(0 != eval_~tmp~0); 7255#L482 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 8080#L324-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 8079#L492-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8078#L492-5 assume !(0 == ~T1_E~0); 8077#L497-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8076#L502-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8075#L507-3 assume !(0 == ~T4_E~0); 8074#L512-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8073#L517-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8072#L522-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8071#L527-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8070#L532-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8069#L228-15 assume !(1 == ~m_pc~0); 8068#L228-17 is_master_triggered_~__retres1~0 := 0; 8067#L239-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8066#L240-5 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 8065#L605-15 assume !(0 != activate_threads_~tmp~1); 8064#L605-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8063#L247-15 assume !(1 == ~t1_pc~0); 8062#L247-17 is_transmit1_triggered_~__retres1~1 := 0; 8061#L258-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8059#L259-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 8057#L613-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 8044#L613-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8043#L266-15 assume !(1 == ~t2_pc~0); 8040#L266-17 is_transmit2_triggered_~__retres1~2 := 0; 8038#L277-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8036#L278-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 8033#L621-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 8032#L621-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8031#L285-15 assume 1 == ~t3_pc~0; 8029#L286-5 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 8028#L296-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 8027#L297-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 7975#L629-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 7974#L629-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7973#L304-15 assume !(1 == ~t4_pc~0); 7970#L304-17 is_transmit4_triggered_~__retres1~4 := 0; 7968#L315-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7966#L316-5 activate_threads_#t~ret10 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 7964#L637-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 7962#L637-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7960#L545-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7958#L545-5 assume !(1 == ~T1_E~0); 7956#L550-3 assume !(1 == ~T2_E~0); 7954#L555-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7952#L560-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7950#L565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7948#L570-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7946#L575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7945#L580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7943#L585-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 7940#L364-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 7936#L391-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 7935#L392-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 7934#L785 assume !(0 == start_simulation_~tmp~3); 7932#L785-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 7875#L364-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 7866#L391-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 7352#L392-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 7187#L740 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 7188#L747 stop_simulation_#res := stop_simulation_~__retres2~0; 7263#L748 start_simulation_#t~ret13 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 7056#L798 assume !(0 != start_simulation_~tmp___0~1); 7057#L766-3 [2018-11-18 09:11:32,353 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:11:32,353 INFO L82 PathProgramCache]: Analyzing trace with hash 1261932300, now seen corresponding path program 1 times [2018-11-18 09:11:32,353 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:11:32,353 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:11:32,354 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:32,354 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:11:32,354 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:32,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:11:32,390 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:11:32,390 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:11:32,390 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 09:11:32,390 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 09:11:32,391 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:11:32,391 INFO L82 PathProgramCache]: Analyzing trace with hash -749023417, now seen corresponding path program 1 times [2018-11-18 09:11:32,391 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:11:32,391 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:11:32,392 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:32,392 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:11:32,392 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:32,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:11:32,445 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:11:32,445 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:11:32,445 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 09:11:32,445 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 09:11:32,446 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 09:11:32,446 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 09:11:32,446 INFO L87 Difference]: Start difference. First operand 1193 states and 1725 transitions. cyclomatic complexity: 536 Second operand 3 states. [2018-11-18 09:11:32,518 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:11:32,518 INFO L93 Difference]: Finished difference Result 2158 states and 3104 transitions. [2018-11-18 09:11:32,519 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 09:11:32,519 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2158 states and 3104 transitions. [2018-11-18 09:11:32,530 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2072 [2018-11-18 09:11:32,540 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2158 states to 2158 states and 3104 transitions. [2018-11-18 09:11:32,540 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2158 [2018-11-18 09:11:32,542 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2158 [2018-11-18 09:11:32,542 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2158 states and 3104 transitions. [2018-11-18 09:11:32,545 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:11:32,546 INFO L705 BuchiCegarLoop]: Abstraction has 2158 states and 3104 transitions. [2018-11-18 09:11:32,547 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2158 states and 3104 transitions. [2018-11-18 09:11:32,573 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2158 to 2146. [2018-11-18 09:11:32,573 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2146 states. [2018-11-18 09:11:32,579 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2146 states to 2146 states and 3092 transitions. [2018-11-18 09:11:32,579 INFO L728 BuchiCegarLoop]: Abstraction has 2146 states and 3092 transitions. [2018-11-18 09:11:32,579 INFO L608 BuchiCegarLoop]: Abstraction has 2146 states and 3092 transitions. [2018-11-18 09:11:32,579 INFO L442 BuchiCegarLoop]: ======== Iteration 9============ [2018-11-18 09:11:32,579 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2146 states and 3092 transitions. [2018-11-18 09:11:32,587 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2060 [2018-11-18 09:11:32,587 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:11:32,588 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:11:32,588 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:11:32,589 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:11:32,589 INFO L794 eck$LassoCheckResult]: Stem: 10660#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 10582#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 10542#L729 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 10439#L324 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10440#L331 assume 1 == ~m_i~0;~m_st~0 := 0; 10505#L331-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10397#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10398#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10441#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10442#L351-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10584#L492 assume !(0 == ~M_E~0); 10745#L492-2 assume !(0 == ~T1_E~0); 10497#L497-1 assume !(0 == ~T2_E~0); 10498#L502-1 assume !(0 == ~T3_E~0); 10508#L507-1 assume !(0 == ~T4_E~0); 10411#L512-1 assume !(0 == ~E_1~0); 10412#L517-1 assume !(0 == ~E_2~0); 10451#L522-1 assume !(0 == ~E_3~0); 10452#L527-1 assume !(0 == ~E_4~0); 10341#L532-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10342#L228 assume !(1 == ~m_pc~0); 10738#L228-2 is_master_triggered_~__retres1~0 := 0; 10730#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10613#L240 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 10614#L605 assume !(0 != activate_threads_~tmp~1); 10676#L605-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10467#L247 assume !(1 == ~t1_pc~0); 10453#L247-2 is_transmit1_triggered_~__retres1~1 := 0; 10454#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10392#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 10393#L613 assume !(0 != activate_threads_~tmp___0~0); 10743#L613-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10483#L266 assume !(1 == ~t2_pc~0); 10484#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 10486#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10487#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 10320#L621 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 10321#L621-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 10326#L285 assume !(1 == ~t3_pc~0); 10571#L285-2 is_transmit3_triggered_~__retres1~3 := 0; 10572#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 10577#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 10504#L629 assume !(0 != activate_threads_~tmp___2~0); 10488#L629-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 10489#L304 assume !(1 == ~t4_pc~0); 10692#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 10693#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 10706#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 10605#L637 assume !(0 != activate_threads_~tmp___3~0); 10606#L637-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10404#L545 assume !(1 == ~M_E~0); 10405#L545-2 assume !(1 == ~T1_E~0); 10410#L550-1 assume !(1 == ~T2_E~0); 10329#L555-1 assume !(1 == ~T3_E~0); 10330#L560-1 assume !(1 == ~T4_E~0); 10339#L565-1 assume !(1 == ~E_1~0); 10340#L570-1 assume !(1 == ~E_2~0); 10535#L575-1 assume 1 == ~E_3~0;~E_3~0 := 2; 10536#L580-1 assume !(1 == ~E_4~0); 10490#L585-1 assume { :end_inline_reset_delta_events } true; 10491#L766-3 [2018-11-18 09:11:32,589 INFO L796 eck$LassoCheckResult]: Loop: 10491#L766-3 assume true; 11297#L766-1 assume !false; 11271#L767 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 11270#L467 assume true; 11269#L401-1 assume !false; 11268#L402 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 11262#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 11259#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 11256#L392 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 11253#L406 assume !(0 != eval_~tmp~0); 11254#L482 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 12063#L324-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 12061#L492-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12059#L492-5 assume !(0 == ~T1_E~0); 12057#L497-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12055#L502-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12053#L507-3 assume !(0 == ~T4_E~0); 12050#L512-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12048#L517-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12046#L522-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12044#L527-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12042#L532-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12040#L228-15 assume !(1 == ~m_pc~0); 12039#L228-17 is_master_triggered_~__retres1~0 := 0; 12038#L239-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12036#L240-5 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 12034#L605-15 assume !(0 != activate_threads_~tmp~1); 12032#L605-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12030#L247-15 assume !(1 == ~t1_pc~0); 12027#L247-17 is_transmit1_triggered_~__retres1~1 := 0; 12025#L258-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12023#L259-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 12021#L613-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 12019#L613-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12017#L266-15 assume !(1 == ~t2_pc~0); 12014#L266-17 is_transmit2_triggered_~__retres1~2 := 0; 12012#L277-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12010#L278-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 12009#L621-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 12008#L621-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 12007#L285-15 assume !(1 == ~t3_pc~0); 12006#L285-17 is_transmit3_triggered_~__retres1~3 := 0; 12004#L296-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 12002#L297-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 12000#L629-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 11998#L629-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 11996#L304-15 assume !(1 == ~t4_pc~0); 11993#L304-17 is_transmit4_triggered_~__retres1~4 := 0; 11991#L315-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 11989#L316-5 activate_threads_#t~ret10 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 11987#L637-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 11984#L637-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11982#L545-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11980#L545-5 assume !(1 == ~T1_E~0); 11978#L550-3 assume !(1 == ~T2_E~0); 11976#L555-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11974#L560-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11968#L565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11960#L570-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11945#L575-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11941#L580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11937#L585-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 11332#L364-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 11327#L391-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 11325#L392-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 11322#L785 assume !(0 == start_simulation_~tmp~3); 11319#L785-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 11317#L364-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 11311#L391-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 11309#L392-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 11307#L740 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 11305#L747 stop_simulation_#res := stop_simulation_~__retres2~0; 11303#L748 start_simulation_#t~ret13 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 11300#L798 assume !(0 != start_simulation_~tmp___0~1); 10491#L766-3 [2018-11-18 09:11:32,589 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:11:32,589 INFO L82 PathProgramCache]: Analyzing trace with hash 1148545643, now seen corresponding path program 1 times [2018-11-18 09:11:32,589 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:11:32,590 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:11:32,590 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:32,590 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:11:32,590 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:32,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:11:32,625 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:11:32,625 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:11:32,625 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 09:11:32,625 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 09:11:32,625 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:11:32,625 INFO L82 PathProgramCache]: Analyzing trace with hash 1917293606, now seen corresponding path program 1 times [2018-11-18 09:11:32,626 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:11:32,626 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:11:32,626 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:32,626 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:11:32,626 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:32,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:11:32,649 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:11:32,650 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:11:32,650 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 09:11:32,650 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 09:11:32,650 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 09:11:32,650 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 09:11:32,650 INFO L87 Difference]: Start difference. First operand 2146 states and 3092 transitions. cyclomatic complexity: 954 Second operand 3 states. [2018-11-18 09:11:32,694 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:11:32,694 INFO L93 Difference]: Finished difference Result 2146 states and 3050 transitions. [2018-11-18 09:11:32,694 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 09:11:32,694 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2146 states and 3050 transitions. [2018-11-18 09:11:32,703 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2060 [2018-11-18 09:11:32,711 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2146 states to 2146 states and 3050 transitions. [2018-11-18 09:11:32,711 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2146 [2018-11-18 09:11:32,713 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2146 [2018-11-18 09:11:32,713 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2146 states and 3050 transitions. [2018-11-18 09:11:32,716 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:11:32,716 INFO L705 BuchiCegarLoop]: Abstraction has 2146 states and 3050 transitions. [2018-11-18 09:11:32,718 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2146 states and 3050 transitions. [2018-11-18 09:11:32,737 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2146 to 2146. [2018-11-18 09:11:32,737 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2146 states. [2018-11-18 09:11:32,741 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2146 states to 2146 states and 3050 transitions. [2018-11-18 09:11:32,741 INFO L728 BuchiCegarLoop]: Abstraction has 2146 states and 3050 transitions. [2018-11-18 09:11:32,741 INFO L608 BuchiCegarLoop]: Abstraction has 2146 states and 3050 transitions. [2018-11-18 09:11:32,741 INFO L442 BuchiCegarLoop]: ======== Iteration 10============ [2018-11-18 09:11:32,742 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2146 states and 3050 transitions. [2018-11-18 09:11:32,748 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2060 [2018-11-18 09:11:32,748 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:11:32,749 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:11:32,749 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:11:32,749 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:11:32,750 INFO L794 eck$LassoCheckResult]: Stem: 14966#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 14885#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 14848#L729 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 14738#L324 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14739#L331 assume 1 == ~m_i~0;~m_st~0 := 0; 14809#L331-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14697#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14698#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14742#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14743#L351-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14888#L492 assume !(0 == ~M_E~0); 15047#L492-2 assume !(0 == ~T1_E~0); 14799#L497-1 assume !(0 == ~T2_E~0); 14800#L502-1 assume !(0 == ~T3_E~0); 14814#L507-1 assume !(0 == ~T4_E~0); 14710#L512-1 assume !(0 == ~E_1~0); 14711#L517-1 assume !(0 == ~E_2~0); 14754#L522-1 assume !(0 == ~E_3~0); 14755#L527-1 assume !(0 == ~E_4~0); 14642#L532-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 14643#L228 assume !(1 == ~m_pc~0); 15041#L228-2 is_master_triggered_~__retres1~0 := 0; 15028#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 14921#L240 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 14922#L605 assume !(0 != activate_threads_~tmp~1); 14977#L605-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 14769#L247 assume !(1 == ~t1_pc~0); 14756#L247-2 is_transmit1_triggered_~__retres1~1 := 0; 14757#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14692#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 14693#L613 assume !(0 != activate_threads_~tmp___0~0); 15045#L613-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 14786#L266 assume !(1 == ~t2_pc~0); 14787#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 14789#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 14790#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 14619#L621 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 14620#L621-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 14625#L285 assume !(1 == ~t3_pc~0); 14876#L285-2 is_transmit3_triggered_~__retres1~3 := 0; 14877#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 14882#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 14808#L629 assume !(0 != activate_threads_~tmp___2~0); 14791#L629-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 14792#L304 assume !(1 == ~t4_pc~0); 14993#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 14994#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 15008#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 14913#L637 assume !(0 != activate_threads_~tmp___3~0); 14914#L637-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14704#L545 assume !(1 == ~M_E~0); 14705#L545-2 assume !(1 == ~T1_E~0); 14712#L550-1 assume !(1 == ~T2_E~0); 14628#L555-1 assume !(1 == ~T3_E~0); 14629#L560-1 assume !(1 == ~T4_E~0); 14640#L565-1 assume !(1 == ~E_1~0); 14641#L570-1 assume !(1 == ~E_2~0); 14841#L575-1 assume !(1 == ~E_3~0); 14842#L580-1 assume !(1 == ~E_4~0); 14793#L585-1 assume { :end_inline_reset_delta_events } true; 14794#L766-3 [2018-11-18 09:11:32,750 INFO L796 eck$LassoCheckResult]: Loop: 14794#L766-3 assume true; 16027#L766-1 assume !false; 15961#L767 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 15959#L467 assume true; 15957#L401-1 assume !false; 15955#L402 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 15853#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 15822#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 15819#L392 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 15813#L406 assume !(0 != eval_~tmp~0); 15814#L482 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 16150#L324-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 16149#L492-3 assume 0 == ~M_E~0;~M_E~0 := 1; 16148#L492-5 assume !(0 == ~T1_E~0); 16147#L497-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16146#L502-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16145#L507-3 assume !(0 == ~T4_E~0); 16144#L512-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16143#L517-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16142#L522-3 assume !(0 == ~E_3~0); 16141#L527-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16140#L532-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 16139#L228-15 assume !(1 == ~m_pc~0); 16138#L228-17 is_master_triggered_~__retres1~0 := 0; 16137#L239-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 16136#L240-5 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 16134#L605-15 assume !(0 != activate_threads_~tmp~1); 16132#L605-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 16130#L247-15 assume !(1 == ~t1_pc~0); 16128#L247-17 is_transmit1_triggered_~__retres1~1 := 0; 16126#L258-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 16124#L259-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 16122#L613-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 16120#L613-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 16118#L266-15 assume !(1 == ~t2_pc~0); 16115#L266-17 is_transmit2_triggered_~__retres1~2 := 0; 16113#L277-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 16111#L278-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 16109#L621-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 16108#L621-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 16105#L285-15 assume !(1 == ~t3_pc~0); 16103#L285-17 is_transmit3_triggered_~__retres1~3 := 0; 16101#L296-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 16099#L297-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 16097#L629-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 16095#L629-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 16093#L304-15 assume !(1 == ~t4_pc~0); 16090#L304-17 is_transmit4_triggered_~__retres1~4 := 0; 16088#L315-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 16086#L316-5 activate_threads_#t~ret10 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 16084#L637-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 16082#L637-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16079#L545-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16077#L545-5 assume !(1 == ~T1_E~0); 16075#L550-3 assume !(1 == ~T2_E~0); 16073#L555-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16071#L560-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16069#L565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16067#L570-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16065#L575-3 assume !(1 == ~E_3~0); 16063#L580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16061#L585-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 16057#L364-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 16052#L391-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 16050#L392-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 16048#L785 assume !(0 == start_simulation_~tmp~3); 16046#L785-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 16045#L364-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 16040#L391-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 16038#L392-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 16036#L740 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 16034#L747 stop_simulation_#res := stop_simulation_~__retres2~0; 16032#L748 start_simulation_#t~ret13 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 16030#L798 assume !(0 != start_simulation_~tmp___0~1); 14794#L766-3 [2018-11-18 09:11:32,750 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:11:32,750 INFO L82 PathProgramCache]: Analyzing trace with hash 1148547565, now seen corresponding path program 1 times [2018-11-18 09:11:32,750 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:11:32,750 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:11:32,751 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:32,751 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:11:32,751 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:32,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:11:32,808 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:11:32,808 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:11:32,808 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 09:11:32,808 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 09:11:32,809 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:11:32,809 INFO L82 PathProgramCache]: Analyzing trace with hash 2024215338, now seen corresponding path program 1 times [2018-11-18 09:11:32,809 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:11:32,809 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:11:32,809 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:32,809 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:11:32,810 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:32,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:11:32,835 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:11:32,835 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:11:32,835 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 09:11:32,835 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 09:11:32,835 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 09:11:32,836 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 09:11:32,836 INFO L87 Difference]: Start difference. First operand 2146 states and 3050 transitions. cyclomatic complexity: 912 Second operand 5 states. [2018-11-18 09:11:32,984 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:11:32,984 INFO L93 Difference]: Finished difference Result 5565 states and 7883 transitions. [2018-11-18 09:11:32,985 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 09:11:32,985 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5565 states and 7883 transitions. [2018-11-18 09:11:33,006 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5380 [2018-11-18 09:11:33,027 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5565 states to 5565 states and 7883 transitions. [2018-11-18 09:11:33,027 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5565 [2018-11-18 09:11:33,031 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5565 [2018-11-18 09:11:33,032 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5565 states and 7883 transitions. [2018-11-18 09:11:33,039 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:11:33,039 INFO L705 BuchiCegarLoop]: Abstraction has 5565 states and 7883 transitions. [2018-11-18 09:11:33,043 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5565 states and 7883 transitions. [2018-11-18 09:11:33,077 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5565 to 2257. [2018-11-18 09:11:33,077 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2257 states. [2018-11-18 09:11:33,082 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2257 states to 2257 states and 3161 transitions. [2018-11-18 09:11:33,082 INFO L728 BuchiCegarLoop]: Abstraction has 2257 states and 3161 transitions. [2018-11-18 09:11:33,082 INFO L608 BuchiCegarLoop]: Abstraction has 2257 states and 3161 transitions. [2018-11-18 09:11:33,082 INFO L442 BuchiCegarLoop]: ======== Iteration 11============ [2018-11-18 09:11:33,082 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2257 states and 3161 transitions. [2018-11-18 09:11:33,089 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2168 [2018-11-18 09:11:33,089 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:11:33,089 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:11:33,090 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:11:33,090 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:11:33,090 INFO L794 eck$LassoCheckResult]: Stem: 22717#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 22636#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 22578#L729 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 22464#L324 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22465#L331 assume 1 == ~m_i~0;~m_st~0 := 0; 22534#L331-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22421#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22422#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 22468#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22469#L351-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22639#L492 assume !(0 == ~M_E~0); 22811#L492-2 assume !(0 == ~T1_E~0); 22524#L497-1 assume !(0 == ~T2_E~0); 22525#L502-1 assume !(0 == ~T3_E~0); 22537#L507-1 assume !(0 == ~T4_E~0); 22432#L512-1 assume !(0 == ~E_1~0); 22433#L517-1 assume !(0 == ~E_2~0); 22478#L522-1 assume !(0 == ~E_3~0); 22479#L527-1 assume !(0 == ~E_4~0); 22364#L532-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 22365#L228 assume !(1 == ~m_pc~0); 22805#L228-2 is_master_triggered_~__retres1~0 := 0; 22790#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 22674#L240 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 22675#L605 assume !(0 != activate_threads_~tmp~1); 22728#L605-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 22496#L247 assume !(1 == ~t1_pc~0); 22480#L247-2 is_transmit1_triggered_~__retres1~1 := 0; 22481#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 22416#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 22417#L613 assume !(0 != activate_threads_~tmp___0~0); 22809#L613-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 22512#L266 assume !(1 == ~t2_pc~0); 22513#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 22515#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 22516#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 22343#L621 assume !(0 != activate_threads_~tmp___1~0); 22344#L621-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 22349#L285 assume !(1 == ~t3_pc~0); 22627#L285-2 is_transmit3_triggered_~__retres1~3 := 0; 22628#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 22633#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 22533#L629 assume !(0 != activate_threads_~tmp___2~0); 22517#L629-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 22518#L304 assume !(1 == ~t4_pc~0); 22744#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 22745#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 22759#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 22666#L637 assume !(0 != activate_threads_~tmp___3~0); 22667#L637-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22427#L545 assume !(1 == ~M_E~0); 22428#L545-2 assume !(1 == ~T1_E~0); 22434#L550-1 assume !(1 == ~T2_E~0); 22352#L555-1 assume !(1 == ~T3_E~0); 22353#L560-1 assume !(1 == ~T4_E~0); 22362#L565-1 assume !(1 == ~E_1~0); 22363#L570-1 assume !(1 == ~E_2~0); 22567#L575-1 assume !(1 == ~E_3~0); 22568#L580-1 assume !(1 == ~E_4~0); 22519#L585-1 assume { :end_inline_reset_delta_events } true; 22436#L766-3 [2018-11-18 09:11:33,090 INFO L796 eck$LassoCheckResult]: Loop: 22436#L766-3 assume true; 22763#L766-1 assume !false; 22735#L767 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 22482#L467 assume true; 22483#L401-1 assume !false; 22399#L402 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 22400#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 22406#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 22757#L392 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 22660#L406 assume !(0 != eval_~tmp~0); 22662#L482 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 24564#L324-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 24562#L492-3 assume 0 == ~M_E~0;~M_E~0 := 1; 24560#L492-5 assume !(0 == ~T1_E~0); 24558#L497-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 24556#L502-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 24554#L507-3 assume !(0 == ~T4_E~0); 24552#L512-3 assume 0 == ~E_1~0;~E_1~0 := 1; 24550#L517-3 assume 0 == ~E_2~0;~E_2~0 := 1; 24548#L522-3 assume !(0 == ~E_3~0); 24546#L527-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22368#L532-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 22369#L228-15 assume !(1 == ~m_pc~0); 22778#L228-17 is_master_triggered_~__retres1~0 := 0; 22779#L239-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 22684#L240-5 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 22685#L605-15 assume !(0 != activate_threads_~tmp~1); 22708#L605-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 22429#L247-15 assume !(1 == ~t1_pc~0); 22425#L247-17 is_transmit1_triggered_~__retres1~1 := 0; 22426#L258-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 22450#L259-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 22771#L613-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 22785#L613-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 22579#L266-15 assume !(1 == ~t2_pc~0); 22580#L266-17 is_transmit2_triggered_~__retres1~2 := 0; 24534#L277-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 24532#L278-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 24530#L621-15 assume !(0 != activate_threads_~tmp___1~0); 22459#L621-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 22460#L285-15 assume !(1 == ~t3_pc~0); 22729#L285-17 is_transmit3_triggered_~__retres1~3 := 0; 22647#L296-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 22648#L297-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 22617#L629-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 22594#L629-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 22595#L304-15 assume !(1 == ~t4_pc~0); 22733#L304-17 is_transmit4_triggered_~__retres1~4 := 0; 22736#L315-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 22750#L316-5 activate_threads_#t~ret10 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 22625#L637-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 22626#L637-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22386#L545-3 assume 1 == ~M_E~0;~M_E~0 := 2; 22387#L545-5 assume !(1 == ~T1_E~0); 22410#L550-3 assume !(1 == ~T2_E~0); 22488#L555-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22489#L560-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22366#L565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 22367#L570-3 assume 1 == ~E_2~0;~E_2~0 := 2; 22574#L575-3 assume !(1 == ~E_3~0); 22575#L580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 22522#L585-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 22523#L364-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 22413#L391-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 22414#L392-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 22375#L785 assume !(0 == start_simulation_~tmp~3); 22377#L785-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 22378#L364-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 22418#L391-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 22419#L392-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 22576#L740 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 22577#L747 stop_simulation_#res := stop_simulation_~__retres2~0; 22669#L748 start_simulation_#t~ret13 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 22435#L798 assume !(0 != start_simulation_~tmp___0~1); 22436#L766-3 [2018-11-18 09:11:33,090 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:11:33,090 INFO L82 PathProgramCache]: Analyzing trace with hash 1014534059, now seen corresponding path program 1 times [2018-11-18 09:11:33,091 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:11:33,091 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:11:33,091 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:33,091 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:11:33,091 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:33,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:11:33,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:11:33,120 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:11:33,120 INFO L82 PathProgramCache]: Analyzing trace with hash 1629848552, now seen corresponding path program 1 times [2018-11-18 09:11:33,120 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:11:33,120 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:11:33,120 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:33,121 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:11:33,121 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:33,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:11:33,157 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:11:33,157 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:11:33,157 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 09:11:33,157 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 09:11:33,157 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 09:11:33,158 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 09:11:33,158 INFO L87 Difference]: Start difference. First operand 2257 states and 3161 transitions. cyclomatic complexity: 912 Second operand 3 states. [2018-11-18 09:11:33,191 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:11:33,191 INFO L93 Difference]: Finished difference Result 2674 states and 3733 transitions. [2018-11-18 09:11:33,192 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 09:11:33,193 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2674 states and 3733 transitions. [2018-11-18 09:11:33,203 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2540 [2018-11-18 09:11:33,212 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2674 states to 2674 states and 3733 transitions. [2018-11-18 09:11:33,213 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2674 [2018-11-18 09:11:33,215 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2674 [2018-11-18 09:11:33,215 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2674 states and 3733 transitions. [2018-11-18 09:11:33,218 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:11:33,218 INFO L705 BuchiCegarLoop]: Abstraction has 2674 states and 3733 transitions. [2018-11-18 09:11:33,220 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2674 states and 3733 transitions. [2018-11-18 09:11:33,245 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2674 to 2674. [2018-11-18 09:11:33,245 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2674 states. [2018-11-18 09:11:33,250 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2674 states to 2674 states and 3733 transitions. [2018-11-18 09:11:33,250 INFO L728 BuchiCegarLoop]: Abstraction has 2674 states and 3733 transitions. [2018-11-18 09:11:33,250 INFO L608 BuchiCegarLoop]: Abstraction has 2674 states and 3733 transitions. [2018-11-18 09:11:33,250 INFO L442 BuchiCegarLoop]: ======== Iteration 12============ [2018-11-18 09:11:33,250 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2674 states and 3733 transitions. [2018-11-18 09:11:33,258 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2540 [2018-11-18 09:11:33,258 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:11:33,258 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:11:33,259 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:11:33,259 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:11:33,259 INFO L794 eck$LassoCheckResult]: Stem: 27645#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 27568#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 27518#L729 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 27401#L324 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27402#L331 assume 1 == ~m_i~0;~m_st~0 := 0; 27474#L331-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 27358#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27359#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27405#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 27406#L351-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27571#L492 assume !(0 == ~M_E~0); 27732#L492-2 assume !(0 == ~T1_E~0); 27463#L497-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 27464#L502-1 assume !(0 == ~T3_E~0); 27768#L507-1 assume !(0 == ~T4_E~0); 27767#L512-1 assume !(0 == ~E_1~0); 27651#L517-1 assume !(0 == ~E_2~0); 27415#L522-1 assume !(0 == ~E_3~0); 27416#L527-1 assume !(0 == ~E_4~0); 27301#L532-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 27302#L228 assume !(1 == ~m_pc~0); 27729#L228-2 is_master_triggered_~__retres1~0 := 0; 27714#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 27602#L240 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 27603#L605 assume !(0 != activate_threads_~tmp~1); 27657#L605-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 27658#L247 assume !(1 == ~t1_pc~0); 27417#L247-2 is_transmit1_triggered_~__retres1~1 := 0; 27418#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 27353#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 27354#L613 assume !(0 != activate_threads_~tmp___0~0); 27730#L613-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 27450#L266 assume !(1 == ~t2_pc~0); 27451#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 27756#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 27754#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 27751#L621 assume !(0 != activate_threads_~tmp___1~0); 27750#L621-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 27562#L285 assume !(1 == ~t3_pc~0); 27563#L285-2 is_transmit3_triggered_~__retres1~3 := 0; 27564#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 27565#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 27473#L629 assume !(0 != activate_threads_~tmp___2~0); 27455#L629-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 27456#L304 assume !(1 == ~t4_pc~0); 27674#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 27675#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 27688#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 27594#L637 assume !(0 != activate_threads_~tmp___3~0); 27595#L637-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27365#L545 assume !(1 == ~M_E~0); 27366#L545-2 assume !(1 == ~T1_E~0); 27373#L550-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27289#L555-1 assume !(1 == ~T3_E~0); 27290#L560-1 assume !(1 == ~T4_E~0); 27299#L565-1 assume !(1 == ~E_1~0); 27300#L570-1 assume !(1 == ~E_2~0); 27507#L575-1 assume !(1 == ~E_3~0); 27508#L580-1 assume !(1 == ~E_4~0); 27457#L585-1 assume { :end_inline_reset_delta_events } true; 27458#L766-3 [2018-11-18 09:11:33,260 INFO L796 eck$LassoCheckResult]: Loop: 27458#L766-3 assume true; 29606#L766-1 assume !false; 29598#L767 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 29594#L467 assume true; 29482#L401-1 assume !false; 29478#L402 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 27476#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 27341#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 27342#L392 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 27588#L406 assume !(0 != eval_~tmp~0); 27590#L482 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 29798#L324-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 29797#L492-3 assume 0 == ~M_E~0;~M_E~0 := 1; 29795#L492-5 assume !(0 == ~T1_E~0); 29610#L497-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 29604#L502-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 29590#L507-3 assume !(0 == ~T4_E~0); 29587#L512-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29585#L517-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29583#L522-3 assume !(0 == ~E_3~0); 29581#L527-3 assume 0 == ~E_4~0;~E_4~0 := 1; 29579#L532-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 29577#L228-15 assume !(1 == ~m_pc~0); 29575#L228-17 is_master_triggered_~__retres1~0 := 0; 29573#L239-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 29571#L240-5 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 29569#L605-15 assume !(0 != activate_threads_~tmp~1); 29567#L605-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 29563#L247-15 assume !(1 == ~t1_pc~0); 29561#L247-17 is_transmit1_triggered_~__retres1~1 := 0; 29559#L258-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 29557#L259-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 29554#L613-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 29552#L613-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 29541#L266-15 assume !(1 == ~t2_pc~0); 29537#L266-17 is_transmit2_triggered_~__retres1~2 := 0; 29535#L277-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 29533#L278-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 29531#L621-15 assume !(0 != activate_threads_~tmp___1~0); 29527#L621-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 29525#L285-15 assume !(1 == ~t3_pc~0); 29523#L285-17 is_transmit3_triggered_~__retres1~3 := 0; 29521#L296-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 29519#L297-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 29517#L629-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 29515#L629-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 29514#L304-15 assume !(1 == ~t4_pc~0); 29511#L304-17 is_transmit4_triggered_~__retres1~4 := 0; 29508#L315-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 29506#L316-5 activate_threads_#t~ret10 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 29504#L637-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 29502#L637-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 29500#L545-3 assume 1 == ~M_E~0;~M_E~0 := 2; 29498#L545-5 assume !(1 == ~T1_E~0); 29496#L550-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29494#L555-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29493#L560-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29491#L565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 29489#L570-3 assume 1 == ~E_2~0;~E_2~0 := 2; 29486#L575-3 assume !(1 == ~E_3~0); 29484#L580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 29480#L585-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 27477#L364-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 27350#L391-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 27351#L392-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 27312#L785 assume !(0 == start_simulation_~tmp~3); 27314#L785-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 29630#L364-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 29624#L391-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 29621#L392-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 29620#L740 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 29619#L747 stop_simulation_#res := stop_simulation_~__retres2~0; 29617#L748 start_simulation_#t~ret13 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 29615#L798 assume !(0 != start_simulation_~tmp___0~1); 27458#L766-3 [2018-11-18 09:11:33,260 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:11:33,260 INFO L82 PathProgramCache]: Analyzing trace with hash -115281361, now seen corresponding path program 1 times [2018-11-18 09:11:33,260 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:11:33,260 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:11:33,261 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:33,261 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:11:33,261 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:33,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:11:33,281 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:11:33,281 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:11:33,281 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 09:11:33,281 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 09:11:33,282 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:11:33,282 INFO L82 PathProgramCache]: Analyzing trace with hash -1847470294, now seen corresponding path program 1 times [2018-11-18 09:11:33,282 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:11:33,282 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:11:33,282 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:33,282 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:11:33,283 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:33,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:11:33,334 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:11:33,334 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:11:33,334 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 09:11:33,334 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 09:11:33,334 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 09:11:33,334 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 09:11:33,335 INFO L87 Difference]: Start difference. First operand 2674 states and 3733 transitions. cyclomatic complexity: 1067 Second operand 3 states. [2018-11-18 09:11:33,351 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:11:33,351 INFO L93 Difference]: Finished difference Result 2257 states and 3135 transitions. [2018-11-18 09:11:33,352 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 09:11:33,352 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2257 states and 3135 transitions. [2018-11-18 09:11:33,359 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2168 [2018-11-18 09:11:33,367 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2257 states to 2257 states and 3135 transitions. [2018-11-18 09:11:33,367 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2257 [2018-11-18 09:11:33,369 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2257 [2018-11-18 09:11:33,369 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2257 states and 3135 transitions. [2018-11-18 09:11:33,371 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:11:33,371 INFO L705 BuchiCegarLoop]: Abstraction has 2257 states and 3135 transitions. [2018-11-18 09:11:33,373 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2257 states and 3135 transitions. [2018-11-18 09:11:33,394 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2257 to 2257. [2018-11-18 09:11:33,394 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2257 states. [2018-11-18 09:11:33,398 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2257 states to 2257 states and 3135 transitions. [2018-11-18 09:11:33,398 INFO L728 BuchiCegarLoop]: Abstraction has 2257 states and 3135 transitions. [2018-11-18 09:11:33,398 INFO L608 BuchiCegarLoop]: Abstraction has 2257 states and 3135 transitions. [2018-11-18 09:11:33,398 INFO L442 BuchiCegarLoop]: ======== Iteration 13============ [2018-11-18 09:11:33,398 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2257 states and 3135 transitions. [2018-11-18 09:11:33,404 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2168 [2018-11-18 09:11:33,404 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:11:33,404 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:11:33,405 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:11:33,405 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:11:33,406 INFO L794 eck$LassoCheckResult]: Stem: 32572#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 32494#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 32447#L729 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 32336#L324 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 32337#L331 assume 1 == ~m_i~0;~m_st~0 := 0; 32406#L331-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 32296#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 32297#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 32340#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 32341#L351-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 32497#L492 assume !(0 == ~M_E~0); 32650#L492-2 assume !(0 == ~T1_E~0); 32396#L497-1 assume !(0 == ~T2_E~0); 32397#L502-1 assume !(0 == ~T3_E~0); 32408#L507-1 assume !(0 == ~T4_E~0); 32309#L512-1 assume !(0 == ~E_1~0); 32310#L517-1 assume !(0 == ~E_2~0); 32352#L522-1 assume !(0 == ~E_3~0); 32353#L527-1 assume !(0 == ~E_4~0); 32241#L532-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 32242#L228 assume !(1 == ~m_pc~0); 32645#L228-2 is_master_triggered_~__retres1~0 := 0; 32636#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 32527#L240 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 32528#L605 assume !(0 != activate_threads_~tmp~1); 32585#L605-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 32367#L247 assume !(1 == ~t1_pc~0); 32354#L247-2 is_transmit1_triggered_~__retres1~1 := 0; 32355#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 32291#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 32292#L613 assume !(0 != activate_threads_~tmp___0~0); 32648#L613-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 32383#L266 assume !(1 == ~t2_pc~0); 32384#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 32386#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 32387#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 32220#L621 assume !(0 != activate_threads_~tmp___1~0); 32221#L621-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 32226#L285 assume !(1 == ~t3_pc~0); 32485#L285-2 is_transmit3_triggered_~__retres1~3 := 0; 32486#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 32491#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 32405#L629 assume !(0 != activate_threads_~tmp___2~0); 32388#L629-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 32389#L304 assume !(1 == ~t4_pc~0); 32601#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 32602#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 32615#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 32519#L637 assume !(0 != activate_threads_~tmp___3~0); 32520#L637-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 32303#L545 assume !(1 == ~M_E~0); 32304#L545-2 assume !(1 == ~T1_E~0); 32311#L550-1 assume !(1 == ~T2_E~0); 32229#L555-1 assume !(1 == ~T3_E~0); 32230#L560-1 assume !(1 == ~T4_E~0); 32239#L565-1 assume !(1 == ~E_1~0); 32240#L570-1 assume !(1 == ~E_2~0); 32437#L575-1 assume !(1 == ~E_3~0); 32438#L580-1 assume !(1 == ~E_4~0); 32390#L585-1 assume { :end_inline_reset_delta_events } true; 32391#L766-3 [2018-11-18 09:11:33,406 INFO L796 eck$LassoCheckResult]: Loop: 32391#L766-3 assume true; 33423#L766-1 assume !false; 33418#L767 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 33416#L467 assume true; 33414#L401-1 assume !false; 33412#L402 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 33395#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 33391#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 33389#L392 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 33386#L406 assume !(0 != eval_~tmp~0); 33387#L482 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 33569#L324-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 33567#L492-3 assume 0 == ~M_E~0;~M_E~0 := 1; 33565#L492-5 assume !(0 == ~T1_E~0); 33563#L497-3 assume !(0 == ~T2_E~0); 33560#L502-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 33558#L507-3 assume !(0 == ~T4_E~0); 33556#L512-3 assume 0 == ~E_1~0;~E_1~0 := 1; 33554#L517-3 assume 0 == ~E_2~0;~E_2~0 := 1; 33552#L522-3 assume !(0 == ~E_3~0); 33550#L527-3 assume 0 == ~E_4~0;~E_4~0 := 1; 33548#L532-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 33546#L228-15 assume !(1 == ~m_pc~0); 33544#L228-17 is_master_triggered_~__retres1~0 := 0; 33542#L239-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 33540#L240-5 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 33538#L605-15 assume !(0 != activate_threads_~tmp~1); 33536#L605-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 33534#L247-15 assume !(1 == ~t1_pc~0); 33533#L247-17 is_transmit1_triggered_~__retres1~1 := 0; 33532#L258-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 33531#L259-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 33530#L613-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 33529#L613-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 33528#L266-15 assume !(1 == ~t2_pc~0); 33525#L266-17 is_transmit2_triggered_~__retres1~2 := 0; 33523#L277-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 33522#L278-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 33521#L621-15 assume !(0 != activate_threads_~tmp___1~0); 33518#L621-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 33517#L285-15 assume !(1 == ~t3_pc~0); 33516#L285-17 is_transmit3_triggered_~__retres1~3 := 0; 33515#L296-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 33514#L297-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 33512#L629-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 33510#L629-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 33508#L304-15 assume !(1 == ~t4_pc~0); 33505#L304-17 is_transmit4_triggered_~__retres1~4 := 0; 33503#L315-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 33501#L316-5 activate_threads_#t~ret10 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 33499#L637-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 33497#L637-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33495#L545-3 assume 1 == ~M_E~0;~M_E~0 := 2; 33493#L545-5 assume !(1 == ~T1_E~0); 33491#L550-3 assume !(1 == ~T2_E~0); 33489#L555-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33485#L560-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33483#L565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 33481#L570-3 assume 1 == ~E_2~0;~E_2~0 := 2; 33479#L575-3 assume !(1 == ~E_3~0); 33476#L580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 33474#L585-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 33453#L364-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 33449#L391-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 33445#L392-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 33442#L785 assume !(0 == start_simulation_~tmp~3); 33439#L785-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 33437#L364-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 33432#L391-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 33431#L392-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 33430#L740 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 33429#L747 stop_simulation_#res := stop_simulation_~__retres2~0; 33428#L748 start_simulation_#t~ret13 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 33426#L798 assume !(0 != start_simulation_~tmp___0~1); 32391#L766-3 [2018-11-18 09:11:33,406 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:11:33,406 INFO L82 PathProgramCache]: Analyzing trace with hash 1014534059, now seen corresponding path program 2 times [2018-11-18 09:11:33,406 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:11:33,406 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:11:33,407 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:33,407 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:11:33,407 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:33,410 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:11:33,414 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:11:33,423 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:11:33,423 INFO L82 PathProgramCache]: Analyzing trace with hash 1831672486, now seen corresponding path program 1 times [2018-11-18 09:11:33,423 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:11:33,423 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:11:33,424 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:33,424 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 09:11:33,424 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:33,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:11:33,451 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:11:33,451 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:11:33,451 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 09:11:33,451 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 09:11:33,451 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 09:11:33,452 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 09:11:33,452 INFO L87 Difference]: Start difference. First operand 2257 states and 3135 transitions. cyclomatic complexity: 886 Second operand 5 states. [2018-11-18 09:11:33,551 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:11:33,551 INFO L93 Difference]: Finished difference Result 3957 states and 5415 transitions. [2018-11-18 09:11:33,552 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-18 09:11:33,552 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3957 states and 5415 transitions. [2018-11-18 09:11:33,565 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3844 [2018-11-18 09:11:33,576 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3957 states to 3957 states and 5415 transitions. [2018-11-18 09:11:33,577 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3957 [2018-11-18 09:11:33,579 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3957 [2018-11-18 09:11:33,579 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3957 states and 5415 transitions. [2018-11-18 09:11:33,582 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:11:33,582 INFO L705 BuchiCegarLoop]: Abstraction has 3957 states and 5415 transitions. [2018-11-18 09:11:33,585 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3957 states and 5415 transitions. [2018-11-18 09:11:33,617 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3957 to 2281. [2018-11-18 09:11:33,618 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2281 states. [2018-11-18 09:11:33,622 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2281 states to 2281 states and 3159 transitions. [2018-11-18 09:11:33,622 INFO L728 BuchiCegarLoop]: Abstraction has 2281 states and 3159 transitions. [2018-11-18 09:11:33,623 INFO L608 BuchiCegarLoop]: Abstraction has 2281 states and 3159 transitions. [2018-11-18 09:11:33,623 INFO L442 BuchiCegarLoop]: ======== Iteration 14============ [2018-11-18 09:11:33,623 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2281 states and 3159 transitions. [2018-11-18 09:11:33,629 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2192 [2018-11-18 09:11:33,629 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:11:33,629 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:11:33,630 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:11:33,630 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:11:33,631 INFO L794 eck$LassoCheckResult]: Stem: 38803#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 38724#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 38677#L729 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 38569#L324 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 38570#L331 assume 1 == ~m_i~0;~m_st~0 := 0; 38636#L331-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 38529#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 38530#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 38573#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 38574#L351-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 38727#L492 assume !(0 == ~M_E~0); 38890#L492-2 assume !(0 == ~T1_E~0); 38627#L497-1 assume !(0 == ~T2_E~0); 38628#L502-1 assume !(0 == ~T3_E~0); 38639#L507-1 assume !(0 == ~T4_E~0); 38540#L512-1 assume !(0 == ~E_1~0); 38541#L517-1 assume !(0 == ~E_2~0); 38583#L522-1 assume !(0 == ~E_3~0); 38584#L527-1 assume !(0 == ~E_4~0); 38471#L532-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 38472#L228 assume !(1 == ~m_pc~0); 38885#L228-2 is_master_triggered_~__retres1~0 := 0; 38874#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 38756#L240 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 38757#L605 assume !(0 != activate_threads_~tmp~1); 38815#L605-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 38598#L247 assume !(1 == ~t1_pc~0); 38585#L247-2 is_transmit1_triggered_~__retres1~1 := 0; 38586#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 38524#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 38525#L613 assume !(0 != activate_threads_~tmp___0~0); 38888#L613-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 38614#L266 assume !(1 == ~t2_pc~0); 38615#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 38617#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 38618#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 38450#L621 assume !(0 != activate_threads_~tmp___1~0); 38451#L621-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 38456#L285 assume !(1 == ~t3_pc~0); 38715#L285-2 is_transmit3_triggered_~__retres1~3 := 0; 38716#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 38721#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 38635#L629 assume !(0 != activate_threads_~tmp___2~0); 38619#L629-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 38620#L304 assume !(1 == ~t4_pc~0); 38831#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 38832#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 38845#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 38748#L637 assume !(0 != activate_threads_~tmp___3~0); 38749#L637-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38535#L545 assume !(1 == ~M_E~0); 38536#L545-2 assume !(1 == ~T1_E~0); 38542#L550-1 assume !(1 == ~T2_E~0); 38459#L555-1 assume !(1 == ~T3_E~0); 38460#L560-1 assume !(1 == ~T4_E~0); 38469#L565-1 assume !(1 == ~E_1~0); 38470#L570-1 assume !(1 == ~E_2~0); 38667#L575-1 assume !(1 == ~E_3~0); 38668#L580-1 assume !(1 == ~E_4~0); 38621#L585-1 assume { :end_inline_reset_delta_events } true; 38622#L766-3 [2018-11-18 09:11:33,631 INFO L796 eck$LassoCheckResult]: Loop: 38622#L766-3 assume true; 40234#L766-1 assume !false; 40229#L767 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 40206#L467 assume true; 40143#L401-1 assume !false; 39882#L402 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 39881#L364 assume !(0 == ~m_st~0); 39880#L368 assume !(0 == ~t1_st~0); 39878#L372 assume !(0 == ~t2_st~0); 39877#L376 assume !(0 == ~t3_st~0); 39876#L380 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5 := 0; 39875#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 39863#L392 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 39861#L406 assume !(0 != eval_~tmp~0); 38862#L482 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 38577#L324-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 38578#L492-3 assume 0 == ~M_E~0;~M_E~0 := 1; 38883#L492-5 assume !(0 == ~T1_E~0); 38604#L497-3 assume !(0 == ~T2_E~0); 38605#L502-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 38843#L507-3 assume !(0 == ~T4_E~0); 40041#L512-3 assume 0 == ~E_1~0;~E_1~0 := 1; 40040#L517-3 assume 0 == ~E_2~0;~E_2~0 := 1; 38594#L522-3 assume !(0 == ~E_3~0); 38595#L527-3 assume 0 == ~E_4~0;~E_4~0 := 1; 38475#L532-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 38476#L228-15 assume !(1 == ~m_pc~0); 38869#L228-17 is_master_triggered_~__retres1~0 := 0; 40682#L239-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 40681#L240-5 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 40680#L605-15 assume !(0 != activate_threads_~tmp~1); 40137#L605-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 40138#L247-15 assume !(1 == ~t1_pc~0); 40367#L247-17 is_transmit1_triggered_~__retres1~1 := 0; 40366#L258-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 40365#L259-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 40364#L613-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 40363#L613-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 40362#L266-15 assume 1 == ~t2_pc~0; 40360#L267-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 40358#L277-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 40356#L278-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 40354#L621-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 40353#L621-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 40352#L285-15 assume !(1 == ~t3_pc~0); 40351#L285-17 is_transmit3_triggered_~__retres1~3 := 0; 40350#L296-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 40349#L297-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 40348#L629-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 40347#L629-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 40346#L304-15 assume !(1 == ~t4_pc~0); 40344#L304-17 is_transmit4_triggered_~__retres1~4 := 0; 40343#L315-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 40342#L316-5 activate_threads_#t~ret10 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 40341#L637-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 40340#L637-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40339#L545-3 assume 1 == ~M_E~0;~M_E~0 := 2; 40338#L545-5 assume !(1 == ~T1_E~0); 40337#L550-3 assume !(1 == ~T2_E~0); 40336#L555-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 40335#L560-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 40334#L565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 40333#L570-3 assume 1 == ~E_2~0;~E_2~0 := 2; 40332#L575-3 assume !(1 == ~E_3~0); 40331#L580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 40330#L585-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 40328#L364-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 40323#L391-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 40321#L392-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 40318#L785 assume !(0 == start_simulation_~tmp~3); 40280#L785-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 40249#L364-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 40244#L391-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 40243#L392-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 40242#L740 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 40241#L747 stop_simulation_#res := stop_simulation_~__retres2~0; 40239#L748 start_simulation_#t~ret13 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 40237#L798 assume !(0 != start_simulation_~tmp___0~1); 38622#L766-3 [2018-11-18 09:11:33,631 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:11:33,631 INFO L82 PathProgramCache]: Analyzing trace with hash 1014534059, now seen corresponding path program 3 times [2018-11-18 09:11:33,631 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:11:33,631 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:11:33,632 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:33,632 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:11:33,632 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:33,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:11:33,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:11:33,649 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:11:33,649 INFO L82 PathProgramCache]: Analyzing trace with hash -1565070659, now seen corresponding path program 1 times [2018-11-18 09:11:33,649 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:11:33,649 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:11:33,650 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:33,650 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 09:11:33,650 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:33,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:11:33,677 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:11:33,678 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:11:33,678 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 09:11:33,678 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 09:11:33,678 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 09:11:33,678 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 09:11:33,679 INFO L87 Difference]: Start difference. First operand 2281 states and 3159 transitions. cyclomatic complexity: 886 Second operand 3 states. [2018-11-18 09:11:33,722 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:11:33,723 INFO L93 Difference]: Finished difference Result 4157 states and 5659 transitions. [2018-11-18 09:11:33,724 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 09:11:33,724 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4157 states and 5659 transitions. [2018-11-18 09:11:33,740 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4052 [2018-11-18 09:11:33,754 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4157 states to 4157 states and 5659 transitions. [2018-11-18 09:11:33,754 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4157 [2018-11-18 09:11:33,757 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4157 [2018-11-18 09:11:33,757 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4157 states and 5659 transitions. [2018-11-18 09:11:33,761 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:11:33,761 INFO L705 BuchiCegarLoop]: Abstraction has 4157 states and 5659 transitions. [2018-11-18 09:11:33,764 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4157 states and 5659 transitions. [2018-11-18 09:11:33,804 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4157 to 4017. [2018-11-18 09:11:33,804 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4017 states. [2018-11-18 09:11:33,835 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4017 states to 4017 states and 5481 transitions. [2018-11-18 09:11:33,835 INFO L728 BuchiCegarLoop]: Abstraction has 4017 states and 5481 transitions. [2018-11-18 09:11:33,835 INFO L608 BuchiCegarLoop]: Abstraction has 4017 states and 5481 transitions. [2018-11-18 09:11:33,835 INFO L442 BuchiCegarLoop]: ======== Iteration 15============ [2018-11-18 09:11:33,836 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4017 states and 5481 transitions. [2018-11-18 09:11:33,844 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3912 [2018-11-18 09:11:33,844 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:11:33,844 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:11:33,845 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:11:33,845 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:11:33,845 INFO L794 eck$LassoCheckResult]: Stem: 45263#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 45184#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 45131#L729 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 45018#L324 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 45019#L331 assume 1 == ~m_i~0;~m_st~0 := 0; 45090#L331-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 44974#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 44975#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 45020#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 45021#L351-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 45186#L492 assume !(0 == ~M_E~0); 45362#L492-2 assume !(0 == ~T1_E~0); 45080#L497-1 assume !(0 == ~T2_E~0); 45081#L502-1 assume !(0 == ~T3_E~0); 45092#L507-1 assume !(0 == ~T4_E~0); 44986#L512-1 assume !(0 == ~E_1~0); 44987#L517-1 assume !(0 == ~E_2~0); 45030#L522-1 assume !(0 == ~E_3~0); 45031#L527-1 assume !(0 == ~E_4~0); 44916#L532-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 44917#L228 assume !(1 == ~m_pc~0); 45354#L228-2 is_master_triggered_~__retres1~0 := 0; 45340#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 45217#L240 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 45218#L605 assume !(0 != activate_threads_~tmp~1); 45275#L605-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 45047#L247 assume !(1 == ~t1_pc~0); 45032#L247-2 is_transmit1_triggered_~__retres1~1 := 0; 45033#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 44969#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 44970#L613 assume !(0 != activate_threads_~tmp___0~0); 45359#L613-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 45066#L266 assume !(1 == ~t2_pc~0); 45067#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 45157#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 45126#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 44896#L621 assume !(0 != activate_threads_~tmp___1~0); 44897#L621-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 44902#L285 assume !(1 == ~t3_pc~0); 45173#L285-2 is_transmit3_triggered_~__retres1~3 := 0; 45174#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 45181#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 45089#L629 assume !(0 != activate_threads_~tmp___2~0); 45071#L629-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 45072#L304 assume !(1 == ~t4_pc~0); 45290#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 45291#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 45307#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 45209#L637 assume !(0 != activate_threads_~tmp___3~0); 45210#L637-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44980#L545 assume !(1 == ~M_E~0); 44981#L545-2 assume !(1 == ~T1_E~0); 44988#L550-1 assume !(1 == ~T2_E~0); 44905#L555-1 assume !(1 == ~T3_E~0); 44906#L560-1 assume !(1 == ~T4_E~0); 44914#L565-1 assume !(1 == ~E_1~0); 44915#L570-1 assume !(1 == ~E_2~0); 45124#L575-1 assume !(1 == ~E_3~0); 45125#L580-1 assume !(1 == ~E_4~0); 45073#L585-1 assume { :end_inline_reset_delta_events } true; 45074#L766-3 [2018-11-18 09:11:33,846 INFO L796 eck$LassoCheckResult]: Loop: 45074#L766-3 assume true; 48021#L766-1 assume !false; 47710#L767 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 47708#L467 assume true; 47707#L401-1 assume !false; 47706#L402 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 47704#L364 assume !(0 == ~m_st~0); 47705#L368 assume !(0 == ~t1_st~0); 48300#L372 assume !(0 == ~t2_st~0); 48297#L376 assume !(0 == ~t3_st~0); 48294#L380 assume !(0 == ~t4_st~0);exists_runnable_thread_~__retres1~5 := 0; 48292#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 48290#L392 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 48287#L406 assume !(0 != eval_~tmp~0); 48283#L482 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 48281#L324-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 48279#L492-3 assume 0 == ~M_E~0;~M_E~0 := 1; 48277#L492-5 assume !(0 == ~T1_E~0); 48274#L497-3 assume !(0 == ~T2_E~0); 48272#L502-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 48270#L507-3 assume !(0 == ~T4_E~0); 48268#L512-3 assume 0 == ~E_1~0;~E_1~0 := 1; 48266#L517-3 assume 0 == ~E_2~0;~E_2~0 := 1; 48264#L522-3 assume !(0 == ~E_3~0); 48262#L527-3 assume 0 == ~E_4~0;~E_4~0 := 1; 48260#L532-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 48258#L228-15 assume !(1 == ~m_pc~0); 48255#L228-17 is_master_triggered_~__retres1~0 := 0; 48253#L239-5 is_master_triggered_#res := is_master_triggered_~__retres1~0; 48251#L240-5 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 48249#L605-15 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 48248#L605-17 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 48247#L247-15 assume !(1 == ~t1_pc~0); 48246#L247-17 is_transmit1_triggered_~__retres1~1 := 0; 48242#L258-5 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 48240#L259-5 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 48238#L613-15 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 48235#L613-17 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 48225#L266-15 assume 1 == ~t2_pc~0; 48220#L267-5 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 48206#L277-5 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 48198#L278-5 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 48194#L621-15 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 48189#L621-17 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 48182#L285-15 assume !(1 == ~t3_pc~0); 48178#L285-17 is_transmit3_triggered_~__retres1~3 := 0; 48173#L296-5 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 48168#L297-5 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 48165#L629-15 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 48163#L629-17 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 48161#L304-15 assume !(1 == ~t4_pc~0); 48158#L304-17 is_transmit4_triggered_~__retres1~4 := 0; 48153#L315-5 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 48148#L316-5 activate_threads_#t~ret10 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 48142#L637-15 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 48137#L637-17 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 48134#L545-3 assume 1 == ~M_E~0;~M_E~0 := 2; 48129#L545-5 assume !(1 == ~T1_E~0); 48124#L550-3 assume !(1 == ~T2_E~0); 48119#L555-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 48114#L560-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 48108#L565-3 assume 1 == ~E_1~0;~E_1~0 := 2; 48103#L570-3 assume 1 == ~E_2~0;~E_2~0 := 2; 48098#L575-3 assume !(1 == ~E_3~0); 48093#L580-3 assume 1 == ~E_4~0;~E_4~0 := 2; 48088#L585-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 48081#L364-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 48074#L391-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 48067#L392-1 start_simulation_#t~ret12 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret12;havoc start_simulation_#t~ret12; 48059#L785 assume !(0 == start_simulation_~tmp~3); 48053#L785-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret11, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 48048#L364-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 48045#L391-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 48041#L392-2 stop_simulation_#t~ret11 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret11;havoc stop_simulation_#t~ret11; 48037#L740 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 48034#L747 stop_simulation_#res := stop_simulation_~__retres2~0; 48030#L748 start_simulation_#t~ret13 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret13;havoc start_simulation_#t~ret13; 48026#L798 assume !(0 != start_simulation_~tmp___0~1); 45074#L766-3 [2018-11-18 09:11:33,846 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:11:33,846 INFO L82 PathProgramCache]: Analyzing trace with hash 1014534059, now seen corresponding path program 4 times [2018-11-18 09:11:33,846 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:11:33,846 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:11:33,847 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:33,847 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:11:33,847 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:33,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:11:33,856 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:11:33,864 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:11:33,864 INFO L82 PathProgramCache]: Analyzing trace with hash 790734591, now seen corresponding path program 1 times [2018-11-18 09:11:33,864 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:11:33,865 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:11:33,866 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:33,866 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 09:11:33,866 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:33,871 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:11:33,934 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:11:33,934 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:11:33,934 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 09:11:33,935 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 09:11:33,935 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 09:11:33,935 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 09:11:33,935 INFO L87 Difference]: Start difference. First operand 4017 states and 5481 transitions. cyclomatic complexity: 1472 Second operand 5 states. [2018-11-18 09:11:34,116 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:11:34,116 INFO L93 Difference]: Finished difference Result 6530 states and 8840 transitions. [2018-11-18 09:11:34,118 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 09:11:34,118 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6530 states and 8840 transitions. [2018-11-18 09:11:34,140 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 6390 [2018-11-18 09:11:34,156 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6530 states to 6530 states and 8840 transitions. [2018-11-18 09:11:34,157 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6530 [2018-11-18 09:11:34,160 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6530 [2018-11-18 09:11:34,160 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6530 states and 8840 transitions. [2018-11-18 09:11:34,165 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:11:34,165 INFO L705 BuchiCegarLoop]: Abstraction has 6530 states and 8840 transitions. [2018-11-18 09:11:34,170 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6530 states and 8840 transitions. [2018-11-18 09:11:34,210 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6530 to 3704. [2018-11-18 09:11:34,210 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3704 states. [2018-11-18 09:11:34,216 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3704 states to 3704 states and 4999 transitions. [2018-11-18 09:11:34,216 INFO L728 BuchiCegarLoop]: Abstraction has 3704 states and 4999 transitions. [2018-11-18 09:11:34,216 INFO L608 BuchiCegarLoop]: Abstraction has 3704 states and 4999 transitions. [2018-11-18 09:11:34,216 INFO L442 BuchiCegarLoop]: ======== Iteration 16============ [2018-11-18 09:11:34,217 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3704 states and 4999 transitions. [2018-11-18 09:11:34,225 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 3596 [2018-11-18 09:11:34,225 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:11:34,225 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:11:34,225 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:11:34,226 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:11:34,226 INFO L794 eck$LassoCheckResult]: Stem: 55805#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 55729#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 55683#L729 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 55576#L324 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 55577#L331 assume 1 == ~m_i~0;~m_st~0 := 0; 55645#L331-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 55534#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 55535#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 55578#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 55579#L351-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 55731#L492 assume !(0 == ~M_E~0); 55903#L492-2 assume !(0 == ~T1_E~0); 55636#L497-1 assume !(0 == ~T2_E~0); 55637#L502-1 assume !(0 == ~T3_E~0); 55647#L507-1 assume !(0 == ~T4_E~0); 55547#L512-1 assume !(0 == ~E_1~0); 55548#L517-1 assume !(0 == ~E_2~0); 55588#L522-1 assume !(0 == ~E_3~0); 55589#L527-1 assume !(0 == ~E_4~0); 55476#L532-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 55477#L228 assume !(1 == ~m_pc~0); 55898#L228-2 is_master_triggered_~__retres1~0 := 0; 55882#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 55762#L240 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 55763#L605 assume !(0 != activate_threads_~tmp~1); 55813#L605-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 55606#L247 assume !(1 == ~t1_pc~0); 55590#L247-2 is_transmit1_triggered_~__retres1~1 := 0; 55591#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 55528#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 55529#L613 assume !(0 != activate_threads_~tmp___0~0); 55901#L613-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 55622#L266 assume !(1 == ~t2_pc~0); 55623#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 55704#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 55678#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 55456#L621 assume !(0 != activate_threads_~tmp___1~0); 55457#L621-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 55462#L285 assume !(1 == ~t3_pc~0); 55718#L285-2 is_transmit3_triggered_~__retres1~3 := 0; 55719#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 55726#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 55644#L629 assume !(0 != activate_threads_~tmp___2~0); 55627#L629-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 55628#L304 assume !(1 == ~t4_pc~0); 55828#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 55829#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 55846#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 55754#L637 assume !(0 != activate_threads_~tmp___3~0); 55755#L637-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 55541#L545 assume !(1 == ~M_E~0); 55542#L545-2 assume !(1 == ~T1_E~0); 55549#L550-1 assume !(1 == ~T2_E~0); 55465#L555-1 assume !(1 == ~T3_E~0); 55466#L560-1 assume !(1 == ~T4_E~0); 55474#L565-1 assume !(1 == ~E_1~0); 55475#L570-1 assume !(1 == ~E_2~0); 55676#L575-1 assume !(1 == ~E_3~0); 55677#L580-1 assume !(1 == ~E_4~0); 55629#L585-1 assume { :end_inline_reset_delta_events } true; 55630#L766-3 assume true; 56317#L766-1 assume !false; 56308#L767 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 56306#L467 [2018-11-18 09:11:34,226 INFO L796 eck$LassoCheckResult]: Loop: 56306#L467 assume true; 56303#L401-1 assume !false; 56300#L402 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 56294#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 56290#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 56286#L392 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 56281#L406 assume 0 != eval_~tmp~0; 56274#L406-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 56268#L414 assume !(0 != eval_~tmp_ndt_1~0); 56262#L411 assume !(0 == ~t1_st~0); 56255#L425 assume !(0 == ~t2_st~0); 56321#L439 assume !(0 == ~t3_st~0); 56312#L453 assume !(0 == ~t4_st~0); 56306#L467 [2018-11-18 09:11:34,226 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:11:34,226 INFO L82 PathProgramCache]: Analyzing trace with hash 299558021, now seen corresponding path program 1 times [2018-11-18 09:11:34,226 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:11:34,226 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:11:34,227 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:34,227 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:11:34,227 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:34,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:11:34,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:11:34,241 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:11:34,242 INFO L82 PathProgramCache]: Analyzing trace with hash 1765171976, now seen corresponding path program 1 times [2018-11-18 09:11:34,242 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:11:34,242 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:11:34,242 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:34,242 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:11:34,243 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:34,244 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:11:34,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:11:34,247 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:11:34,247 INFO L82 PathProgramCache]: Analyzing trace with hash -1484131068, now seen corresponding path program 1 times [2018-11-18 09:11:34,247 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:11:34,247 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:11:34,248 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:34,248 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:11:34,248 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:34,252 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:11:34,278 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:11:34,279 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:11:34,279 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 09:11:34,335 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 09:11:34,335 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 09:11:34,336 INFO L87 Difference]: Start difference. First operand 3704 states and 4999 transitions. cyclomatic complexity: 1307 Second operand 3 states. [2018-11-18 09:11:34,463 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:11:34,464 INFO L93 Difference]: Finished difference Result 6900 states and 9209 transitions. [2018-11-18 09:11:34,465 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 09:11:34,465 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6900 states and 9209 transitions. [2018-11-18 09:11:34,489 INFO L131 ngComponentsAnalysis]: Automaton has 18 accepting balls. 6106 [2018-11-18 09:11:34,507 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6900 states to 6900 states and 9209 transitions. [2018-11-18 09:11:34,507 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6900 [2018-11-18 09:11:34,511 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6900 [2018-11-18 09:11:34,512 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6900 states and 9209 transitions. [2018-11-18 09:11:34,518 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:11:34,518 INFO L705 BuchiCegarLoop]: Abstraction has 6900 states and 9209 transitions. [2018-11-18 09:11:34,524 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6900 states and 9209 transitions. [2018-11-18 09:11:34,577 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6900 to 6672. [2018-11-18 09:11:34,577 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6672 states. [2018-11-18 09:11:34,590 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6672 states to 6672 states and 8921 transitions. [2018-11-18 09:11:34,591 INFO L728 BuchiCegarLoop]: Abstraction has 6672 states and 8921 transitions. [2018-11-18 09:11:34,591 INFO L608 BuchiCegarLoop]: Abstraction has 6672 states and 8921 transitions. [2018-11-18 09:11:34,591 INFO L442 BuchiCegarLoop]: ======== Iteration 17============ [2018-11-18 09:11:34,591 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6672 states and 8921 transitions. [2018-11-18 09:11:34,610 INFO L131 ngComponentsAnalysis]: Automaton has 18 accepting balls. 5878 [2018-11-18 09:11:34,610 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:11:34,610 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:11:34,611 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:11:34,611 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:11:34,611 INFO L794 eck$LassoCheckResult]: Stem: 66467#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 66371#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 66314#L729 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 66192#L324 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 66193#L331 assume 1 == ~m_i~0;~m_st~0 := 0; 66264#L331-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 66147#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 66148#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 66196#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 66197#L351-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 66611#L492 assume !(0 == ~M_E~0); 66612#L492-2 assume !(0 == ~T1_E~0); 66253#L497-1 assume !(0 == ~T2_E~0); 66254#L502-1 assume !(0 == ~T3_E~0); 66270#L507-1 assume !(0 == ~T4_E~0); 66271#L512-1 assume !(0 == ~E_1~0); 66474#L517-1 assume !(0 == ~E_2~0); 66475#L522-1 assume !(0 == ~E_3~0); 66391#L527-1 assume !(0 == ~E_4~0); 66392#L532-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 66604#L228 assume !(1 == ~m_pc~0); 66605#L228-2 is_master_triggered_~__retres1~0 := 0; 66577#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 66578#L240 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 66480#L605 assume !(0 != activate_threads_~tmp~1); 66481#L605-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 66223#L247 assume !(1 == ~t1_pc~0); 66224#L247-2 is_transmit1_triggered_~__retres1~1 := 0; 66225#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 66226#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 66619#L613 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 66606#L613-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 66607#L266 assume !(1 == ~t2_pc~0); 66307#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 66340#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 66622#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 66623#L621 assume !(0 != activate_threads_~tmp___1~0); 66072#L621-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 66073#L285 assume !(1 == ~t3_pc~0); 66359#L285-2 is_transmit3_triggered_~__retres1~3 := 0; 66360#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 66462#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 66463#L629 assume !(0 != activate_threads_~tmp___2~0); 66245#L629-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 66246#L304 assume !(1 == ~t4_pc~0); 66509#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 66510#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 66592#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 66593#L637 assume !(0 != activate_threads_~tmp___3~0); 66405#L637-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 66406#L545 assume !(1 == ~M_E~0); 66160#L545-2 assume !(1 == ~T1_E~0); 66161#L550-1 assume !(1 == ~T2_E~0); 66076#L555-1 assume !(1 == ~T3_E~0); 66077#L560-1 assume !(1 == ~T4_E~0); 66086#L565-1 assume !(1 == ~E_1~0); 66087#L570-1 assume !(1 == ~E_2~0); 66302#L575-1 assume !(1 == ~E_3~0); 66303#L580-1 assume !(1 == ~E_4~0); 66247#L585-1 assume { :end_inline_reset_delta_events } true; 66248#L766-3 assume true; 68875#L766-1 assume !false; 68782#L767 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 68783#L467 [2018-11-18 09:11:34,611 INFO L796 eck$LassoCheckResult]: Loop: 68783#L467 assume true; 68776#L401-1 assume !false; 68777#L402 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 68770#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 68771#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 67239#L392 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 67240#L406 assume 0 != eval_~tmp~0; 67232#L406-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 67233#L414 assume !(0 != eval_~tmp_ndt_1~0); 67190#L411 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 67187#L428 assume !(0 != eval_~tmp_ndt_2~0); 67189#L425 assume !(0 == ~t2_st~0); 68794#L439 assume !(0 == ~t3_st~0); 68787#L453 assume !(0 == ~t4_st~0); 68783#L467 [2018-11-18 09:11:34,612 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:11:34,612 INFO L82 PathProgramCache]: Analyzing trace with hash 805673665, now seen corresponding path program 1 times [2018-11-18 09:11:34,612 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:11:34,612 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:11:34,612 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:34,621 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:11:34,621 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:34,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:11:34,644 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:11:34,644 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:11:34,644 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 09:11:34,644 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 09:11:34,644 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:11:34,645 INFO L82 PathProgramCache]: Analyzing trace with hash -1262368664, now seen corresponding path program 1 times [2018-11-18 09:11:34,645 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:11:34,645 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:11:34,645 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:34,645 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:11:34,645 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:34,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:11:34,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:11:34,757 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 09:11:34,757 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 09:11:34,758 INFO L87 Difference]: Start difference. First operand 6672 states and 8921 transitions. cyclomatic complexity: 2267 Second operand 3 states. [2018-11-18 09:11:34,773 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:11:34,773 INFO L93 Difference]: Finished difference Result 4407 states and 5896 transitions. [2018-11-18 09:11:34,775 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 09:11:34,775 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4407 states and 5896 transitions. [2018-11-18 09:11:34,787 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 4287 [2018-11-18 09:11:34,797 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4407 states to 4407 states and 5896 transitions. [2018-11-18 09:11:34,798 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4407 [2018-11-18 09:11:34,800 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4407 [2018-11-18 09:11:34,800 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4407 states and 5896 transitions. [2018-11-18 09:11:34,803 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:11:34,803 INFO L705 BuchiCegarLoop]: Abstraction has 4407 states and 5896 transitions. [2018-11-18 09:11:34,806 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4407 states and 5896 transitions. [2018-11-18 09:11:34,836 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4407 to 4407. [2018-11-18 09:11:34,836 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4407 states. [2018-11-18 09:11:34,843 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4407 states to 4407 states and 5896 transitions. [2018-11-18 09:11:34,844 INFO L728 BuchiCegarLoop]: Abstraction has 4407 states and 5896 transitions. [2018-11-18 09:11:34,844 INFO L608 BuchiCegarLoop]: Abstraction has 4407 states and 5896 transitions. [2018-11-18 09:11:34,844 INFO L442 BuchiCegarLoop]: ======== Iteration 18============ [2018-11-18 09:11:34,844 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4407 states and 5896 transitions. [2018-11-18 09:11:34,853 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 4287 [2018-11-18 09:11:34,854 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:11:34,854 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:11:34,854 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:11:34,854 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:11:34,854 INFO L794 eck$LassoCheckResult]: Stem: 77520#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 77435#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 77382#L729 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 77276#L324 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 77277#L331 assume 1 == ~m_i~0;~m_st~0 := 0; 77342#L331-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 77231#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 77232#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 77278#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 77279#L351-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 77437#L492 assume !(0 == ~M_E~0); 77635#L492-2 assume !(0 == ~T1_E~0); 77333#L497-1 assume !(0 == ~T2_E~0); 77334#L502-1 assume !(0 == ~T3_E~0); 77345#L507-1 assume !(0 == ~T4_E~0); 77245#L512-1 assume !(0 == ~E_1~0); 77246#L517-1 assume !(0 == ~E_2~0); 77288#L522-1 assume !(0 == ~E_3~0); 77289#L527-1 assume !(0 == ~E_4~0); 77173#L532-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 77174#L228 assume !(1 == ~m_pc~0); 77628#L228-2 is_master_triggered_~__retres1~0 := 0; 77609#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 77470#L240 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 77471#L605 assume !(0 != activate_threads_~tmp~1); 77537#L605-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 77303#L247 assume !(1 == ~t1_pc~0); 77290#L247-2 is_transmit1_triggered_~__retres1~1 := 0; 77291#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 77226#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 77227#L613 assume !(0 != activate_threads_~tmp___0~0); 77632#L613-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 77319#L266 assume !(1 == ~t2_pc~0); 77320#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 77406#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 77377#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 77153#L621 assume !(0 != activate_threads_~tmp___1~0); 77154#L621-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 77159#L285 assume !(1 == ~t3_pc~0); 77423#L285-2 is_transmit3_triggered_~__retres1~3 := 0; 77424#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 77432#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 77341#L629 assume !(0 != activate_threads_~tmp___2~0); 77324#L629-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 77325#L304 assume !(1 == ~t4_pc~0); 77558#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 77559#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 77576#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 77462#L637 assume !(0 != activate_threads_~tmp___3~0); 77463#L637-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 77238#L545 assume !(1 == ~M_E~0); 77239#L545-2 assume !(1 == ~T1_E~0); 77247#L550-1 assume !(1 == ~T2_E~0); 77162#L555-1 assume !(1 == ~T3_E~0); 77163#L560-1 assume !(1 == ~T4_E~0); 77171#L565-1 assume !(1 == ~E_1~0); 77172#L570-1 assume !(1 == ~E_2~0); 77375#L575-1 assume !(1 == ~E_3~0); 77376#L580-1 assume !(1 == ~E_4~0); 77326#L585-1 assume { :end_inline_reset_delta_events } true; 77327#L766-3 assume true; 77764#L766-1 assume !false; 77760#L767 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 77759#L467 [2018-11-18 09:11:34,855 INFO L796 eck$LassoCheckResult]: Loop: 77759#L467 assume true; 77905#L401-1 assume !false; 77904#L402 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 77746#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 77747#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 77740#L392 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 77741#L406 assume 0 != eval_~tmp~0; 77732#L406-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 77726#L414 assume !(0 != eval_~tmp_ndt_1~0); 77727#L411 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 77839#L428 assume !(0 != eval_~tmp_ndt_2~0); 77829#L425 assume !(0 == ~t2_st~0); 77826#L439 assume !(0 == ~t3_st~0); 77763#L453 assume !(0 == ~t4_st~0); 77759#L467 [2018-11-18 09:11:34,855 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:11:34,855 INFO L82 PathProgramCache]: Analyzing trace with hash 299558021, now seen corresponding path program 2 times [2018-11-18 09:11:34,855 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:11:34,855 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:11:34,856 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:34,856 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:11:34,856 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:34,859 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:11:34,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:11:34,870 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:11:34,870 INFO L82 PathProgramCache]: Analyzing trace with hash -1262368664, now seen corresponding path program 2 times [2018-11-18 09:11:34,870 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:11:34,870 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:11:34,871 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:34,871 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 09:11:34,871 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:34,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:11:34,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:11:34,875 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:11:34,875 INFO L82 PathProgramCache]: Analyzing trace with hash 1088452076, now seen corresponding path program 1 times [2018-11-18 09:11:34,875 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:11:34,875 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:11:34,876 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:34,876 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 09:11:34,876 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:34,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:11:34,905 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:11:34,905 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:11:34,906 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 09:11:34,991 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 09:11:34,991 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 09:11:34,991 INFO L87 Difference]: Start difference. First operand 4407 states and 5896 transitions. cyclomatic complexity: 1501 Second operand 3 states. [2018-11-18 09:11:35,074 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:11:35,074 INFO L93 Difference]: Finished difference Result 7784 states and 10358 transitions. [2018-11-18 09:11:35,076 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 09:11:35,076 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7784 states and 10358 transitions. [2018-11-18 09:11:35,100 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 7612 [2018-11-18 09:11:35,120 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7784 states to 7784 states and 10358 transitions. [2018-11-18 09:11:35,121 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7784 [2018-11-18 09:11:35,127 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7784 [2018-11-18 09:11:35,127 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7784 states and 10358 transitions. [2018-11-18 09:11:35,132 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:11:35,132 INFO L705 BuchiCegarLoop]: Abstraction has 7784 states and 10358 transitions. [2018-11-18 09:11:35,138 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7784 states and 10358 transitions. [2018-11-18 09:11:35,189 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7784 to 7340. [2018-11-18 09:11:35,189 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7340 states. [2018-11-18 09:11:35,200 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7340 states to 7340 states and 9794 transitions. [2018-11-18 09:11:35,201 INFO L728 BuchiCegarLoop]: Abstraction has 7340 states and 9794 transitions. [2018-11-18 09:11:35,201 INFO L608 BuchiCegarLoop]: Abstraction has 7340 states and 9794 transitions. [2018-11-18 09:11:35,201 INFO L442 BuchiCegarLoop]: ======== Iteration 19============ [2018-11-18 09:11:35,201 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7340 states and 9794 transitions. [2018-11-18 09:11:35,217 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 7168 [2018-11-18 09:11:35,217 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:11:35,217 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:11:35,218 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:11:35,218 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:11:35,218 INFO L794 eck$LassoCheckResult]: Stem: 89722#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 89635#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 89583#L729 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 89476#L324 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 89477#L331 assume 1 == ~m_i~0;~m_st~0 := 0; 89542#L331-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 89430#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 89431#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 89478#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 89479#L351-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 89637#L492 assume !(0 == ~M_E~0); 89829#L492-2 assume !(0 == ~T1_E~0); 89532#L497-1 assume !(0 == ~T2_E~0); 89533#L502-1 assume !(0 == ~T3_E~0); 89546#L507-1 assume !(0 == ~T4_E~0); 89443#L512-1 assume !(0 == ~E_1~0); 89444#L517-1 assume !(0 == ~E_2~0); 89487#L522-1 assume !(0 == ~E_3~0); 89488#L527-1 assume !(0 == ~E_4~0); 89371#L532-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 89372#L228 assume !(1 == ~m_pc~0); 89819#L228-2 is_master_triggered_~__retres1~0 := 0; 89803#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 89669#L240 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 89670#L605 assume !(0 != activate_threads_~tmp~1); 89734#L605-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 89502#L247 assume !(1 == ~t1_pc~0); 89489#L247-2 is_transmit1_triggered_~__retres1~1 := 0; 89490#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 89424#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 89425#L613 assume !(0 != activate_threads_~tmp___0~0); 89827#L613-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 89518#L266 assume !(1 == ~t2_pc~0); 89519#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 89609#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 89578#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 89352#L621 assume !(0 != activate_threads_~tmp___1~0); 89353#L621-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 89358#L285 assume !(1 == ~t3_pc~0); 89623#L285-2 is_transmit3_triggered_~__retres1~3 := 0; 89624#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 89632#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 89541#L629 assume !(0 != activate_threads_~tmp___2~0); 89523#L629-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 89524#L304 assume !(1 == ~t4_pc~0); 89752#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 89753#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 89773#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 89661#L637 assume !(0 != activate_threads_~tmp___3~0); 89662#L637-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 89437#L545 assume !(1 == ~M_E~0); 89438#L545-2 assume !(1 == ~T1_E~0); 89445#L550-1 assume !(1 == ~T2_E~0); 89361#L555-1 assume !(1 == ~T3_E~0); 89362#L560-1 assume !(1 == ~T4_E~0); 89369#L565-1 assume !(1 == ~E_1~0); 89370#L570-1 assume !(1 == ~E_2~0); 89576#L575-1 assume !(1 == ~E_3~0); 89577#L580-1 assume !(1 == ~E_4~0); 89525#L585-1 assume { :end_inline_reset_delta_events } true; 89526#L766-3 assume true; 90671#L766-1 assume !false; 90595#L767 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 90499#L467 [2018-11-18 09:11:35,218 INFO L796 eck$LassoCheckResult]: Loop: 90499#L467 assume true; 90493#L401-1 assume !false; 90460#L402 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 90453#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 90449#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 90444#L392 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 90439#L406 assume 0 != eval_~tmp~0; 90434#L406-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 90430#L414 assume !(0 != eval_~tmp_ndt_1~0); 90424#L411 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 90415#L428 assume !(0 != eval_~tmp_ndt_2~0); 90416#L425 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 90476#L442 assume !(0 != eval_~tmp_ndt_3~0); 90682#L439 assume !(0 == ~t3_st~0); 90599#L453 assume !(0 == ~t4_st~0); 90499#L467 [2018-11-18 09:11:35,218 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:11:35,218 INFO L82 PathProgramCache]: Analyzing trace with hash 299558021, now seen corresponding path program 3 times [2018-11-18 09:11:35,218 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:11:35,218 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:11:35,219 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:35,219 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:11:35,219 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:35,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:11:35,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:11:35,233 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:11:35,233 INFO L82 PathProgramCache]: Analyzing trace with hash -483496583, now seen corresponding path program 1 times [2018-11-18 09:11:35,233 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:11:35,234 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:11:35,234 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:35,234 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 09:11:35,234 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:35,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:11:35,237 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:11:35,238 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:11:35,239 INFO L82 PathProgramCache]: Analyzing trace with hash -622497675, now seen corresponding path program 1 times [2018-11-18 09:11:35,239 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:11:35,239 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:11:35,239 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:35,240 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:11:35,240 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:35,244 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:11:35,270 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:11:35,271 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:11:35,271 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 09:11:35,367 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 09:11:35,367 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 09:11:35,367 INFO L87 Difference]: Start difference. First operand 7340 states and 9794 transitions. cyclomatic complexity: 2466 Second operand 3 states. [2018-11-18 09:11:35,441 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:11:35,441 INFO L93 Difference]: Finished difference Result 9243 states and 12251 transitions. [2018-11-18 09:11:35,443 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 09:11:35,443 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9243 states and 12251 transitions. [2018-11-18 09:11:35,474 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 9043 [2018-11-18 09:11:35,498 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9243 states to 9243 states and 12251 transitions. [2018-11-18 09:11:35,498 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9243 [2018-11-18 09:11:35,503 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9243 [2018-11-18 09:11:35,503 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9243 states and 12251 transitions. [2018-11-18 09:11:35,509 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:11:35,509 INFO L705 BuchiCegarLoop]: Abstraction has 9243 states and 12251 transitions. [2018-11-18 09:11:35,514 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9243 states and 12251 transitions. [2018-11-18 09:11:35,605 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9243 to 8955. [2018-11-18 09:11:35,605 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8955 states. [2018-11-18 09:11:35,613 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8955 states to 8955 states and 11891 transitions. [2018-11-18 09:11:35,614 INFO L728 BuchiCegarLoop]: Abstraction has 8955 states and 11891 transitions. [2018-11-18 09:11:35,614 INFO L608 BuchiCegarLoop]: Abstraction has 8955 states and 11891 transitions. [2018-11-18 09:11:35,614 INFO L442 BuchiCegarLoop]: ======== Iteration 20============ [2018-11-18 09:11:35,614 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8955 states and 11891 transitions. [2018-11-18 09:11:35,628 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 8755 [2018-11-18 09:11:35,628 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:11:35,628 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:11:35,629 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:11:35,629 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:11:35,629 INFO L794 eck$LassoCheckResult]: Stem: 106321#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 106233#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 106179#L729 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 106070#L324 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 106071#L331 assume 1 == ~m_i~0;~m_st~0 := 0; 106140#L331-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 106022#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 106023#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 106072#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 106073#L351-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 106235#L492 assume !(0 == ~M_E~0); 106430#L492-2 assume !(0 == ~T1_E~0); 106129#L497-1 assume !(0 == ~T2_E~0); 106130#L502-1 assume !(0 == ~T3_E~0); 106143#L507-1 assume !(0 == ~T4_E~0); 106035#L512-1 assume !(0 == ~E_1~0); 106036#L517-1 assume !(0 == ~E_2~0); 106082#L522-1 assume !(0 == ~E_3~0); 106083#L527-1 assume !(0 == ~E_4~0); 105962#L532-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 105963#L228 assume !(1 == ~m_pc~0); 106423#L228-2 is_master_triggered_~__retres1~0 := 0; 106408#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 106269#L240 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 106270#L605 assume !(0 != activate_threads_~tmp~1); 106331#L605-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 106097#L247 assume !(1 == ~t1_pc~0); 106084#L247-2 is_transmit1_triggered_~__retres1~1 := 0; 106085#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 106016#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 106017#L613 assume !(0 != activate_threads_~tmp___0~0); 106427#L613-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 106115#L266 assume !(1 == ~t2_pc~0); 106116#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 106118#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 106119#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 105943#L621 assume !(0 != activate_threads_~tmp___1~0); 105944#L621-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 105949#L285 assume !(1 == ~t3_pc~0); 106222#L285-2 is_transmit3_triggered_~__retres1~3 := 0; 106223#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 106230#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 106139#L629 assume !(0 != activate_threads_~tmp___2~0); 106120#L629-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 106121#L304 assume !(1 == ~t4_pc~0); 106352#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 106353#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 106373#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 106260#L637 assume !(0 != activate_threads_~tmp___3~0); 106261#L637-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 106029#L545 assume !(1 == ~M_E~0); 106030#L545-2 assume !(1 == ~T1_E~0); 106037#L550-1 assume !(1 == ~T2_E~0); 105952#L555-1 assume !(1 == ~T3_E~0); 105953#L560-1 assume !(1 == ~T4_E~0); 105960#L565-1 assume !(1 == ~E_1~0); 105961#L570-1 assume !(1 == ~E_2~0); 106172#L575-1 assume !(1 == ~E_3~0); 106173#L580-1 assume !(1 == ~E_4~0); 106122#L585-1 assume { :end_inline_reset_delta_events } true; 106123#L766-3 assume true; 113973#L766-1 assume !false; 113961#L767 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 113958#L467 [2018-11-18 09:11:35,629 INFO L796 eck$LassoCheckResult]: Loop: 113958#L467 assume true; 113956#L401-1 assume !false; 113954#L402 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 113952#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 113950#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 113948#L392 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 113946#L406 assume 0 != eval_~tmp~0; 113942#L406-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 113943#L414 assume !(0 != eval_~tmp_ndt_1~0); 113984#L411 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 113832#L428 assume !(0 != eval_~tmp_ndt_2~0); 106363#L425 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 106133#L442 assume !(0 != eval_~tmp_ndt_3~0); 106135#L439 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 113967#L456 assume !(0 != eval_~tmp_ndt_4~0); 113965#L453 assume !(0 == ~t4_st~0); 113958#L467 [2018-11-18 09:11:35,629 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:11:35,629 INFO L82 PathProgramCache]: Analyzing trace with hash 299558021, now seen corresponding path program 4 times [2018-11-18 09:11:35,630 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:11:35,630 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:11:35,630 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:35,630 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:11:35,630 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:35,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:11:35,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:11:35,643 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:11:35,643 INFO L82 PathProgramCache]: Analyzing trace with hash -2103641609, now seen corresponding path program 1 times [2018-11-18 09:11:35,644 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:11:35,644 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:11:35,644 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:35,644 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 09:11:35,644 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:35,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:11:35,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:11:35,649 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:11:35,649 INFO L82 PathProgramCache]: Analyzing trace with hash -2117708165, now seen corresponding path program 1 times [2018-11-18 09:11:35,649 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:11:35,649 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:11:35,649 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:35,650 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:11:35,650 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:35,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 09:11:35,671 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 09:11:35,671 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 09:11:35,671 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 09:11:35,756 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 09:11:35,756 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 09:11:35,756 INFO L87 Difference]: Start difference. First operand 8955 states and 11891 transitions. cyclomatic complexity: 2948 Second operand 3 states. [2018-11-18 09:11:35,798 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 09:11:35,798 INFO L93 Difference]: Finished difference Result 16955 states and 22445 transitions. [2018-11-18 09:11:35,800 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 09:11:35,800 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16955 states and 22445 transitions. [2018-11-18 09:11:35,834 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 16623 [2018-11-18 09:11:35,859 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16955 states to 16955 states and 22445 transitions. [2018-11-18 09:11:35,859 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16955 [2018-11-18 09:11:35,867 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16955 [2018-11-18 09:11:35,867 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16955 states and 22445 transitions. [2018-11-18 09:11:35,874 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 09:11:35,874 INFO L705 BuchiCegarLoop]: Abstraction has 16955 states and 22445 transitions. [2018-11-18 09:11:35,881 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16955 states and 22445 transitions. [2018-11-18 09:11:35,956 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16955 to 16955. [2018-11-18 09:11:35,956 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16955 states. [2018-11-18 09:11:35,971 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16955 states to 16955 states and 22445 transitions. [2018-11-18 09:11:35,971 INFO L728 BuchiCegarLoop]: Abstraction has 16955 states and 22445 transitions. [2018-11-18 09:11:35,972 INFO L608 BuchiCegarLoop]: Abstraction has 16955 states and 22445 transitions. [2018-11-18 09:11:35,972 INFO L442 BuchiCegarLoop]: ======== Iteration 21============ [2018-11-18 09:11:35,972 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16955 states and 22445 transitions. [2018-11-18 09:11:36,002 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 16623 [2018-11-18 09:11:36,002 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 09:11:36,002 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 09:11:36,003 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:11:36,003 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 09:11:36,003 INFO L794 eck$LassoCheckResult]: Stem: 132250#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2; 132155#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~6;havoc main_~__retres1~6;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1; 132098#L729 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret12, start_simulation_#t~ret13, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 131981#L324 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 131982#L331 assume 1 == ~m_i~0;~m_st~0 := 0; 132054#L331-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 131940#L336-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 131941#L341-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 131985#L346-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 131986#L351-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 132158#L492 assume !(0 == ~M_E~0); 132350#L492-2 assume !(0 == ~T1_E~0); 132043#L497-1 assume !(0 == ~T2_E~0); 132044#L502-1 assume !(0 == ~T3_E~0); 132058#L507-1 assume !(0 == ~T4_E~0); 131953#L512-1 assume !(0 == ~E_1~0); 131954#L517-1 assume !(0 == ~E_2~0); 131994#L522-1 assume !(0 == ~E_3~0); 131995#L527-1 assume !(0 == ~E_4~0); 131881#L532-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6, activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 131882#L228 assume !(1 == ~m_pc~0); 132343#L228-2 is_master_triggered_~__retres1~0 := 0; 132329#L239 is_master_triggered_#res := is_master_triggered_~__retres1~0; 132197#L240 activate_threads_#t~ret6 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret6;havoc activate_threads_#t~ret6; 132198#L605 assume !(0 != activate_threads_~tmp~1); 132260#L605-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 132010#L247 assume !(1 == ~t1_pc~0); 131996#L247-2 is_transmit1_triggered_~__retres1~1 := 0; 131997#L258 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 131934#L259 activate_threads_#t~ret7 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 131935#L613 assume !(0 != activate_threads_~tmp___0~0); 132348#L613-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 132030#L266 assume !(1 == ~t2_pc~0); 132031#L266-2 is_transmit2_triggered_~__retres1~2 := 0; 132127#L277 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 132353#L278 activate_threads_#t~ret8 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 131859#L621 assume !(0 != activate_threads_~tmp___1~0); 131860#L621-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 131865#L285 assume !(1 == ~t3_pc~0); 132146#L285-2 is_transmit3_triggered_~__retres1~3 := 0; 132147#L296 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 132154#L297 activate_threads_#t~ret9 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 132053#L629 assume !(0 != activate_threads_~tmp___2~0); 132035#L629-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 132036#L304 assume !(1 == ~t4_pc~0); 132277#L304-2 is_transmit4_triggered_~__retres1~4 := 0; 132278#L315 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 132298#L316 activate_threads_#t~ret10 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 132187#L637 assume !(0 != activate_threads_~tmp___3~0); 132188#L637-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 131947#L545 assume !(1 == ~M_E~0); 131948#L545-2 assume !(1 == ~T1_E~0); 131955#L550-1 assume !(1 == ~T2_E~0); 131868#L555-1 assume !(1 == ~T3_E~0); 131869#L560-1 assume !(1 == ~T4_E~0); 131879#L565-1 assume !(1 == ~E_1~0); 131880#L570-1 assume !(1 == ~E_2~0); 132090#L575-1 assume !(1 == ~E_3~0); 132091#L580-1 assume !(1 == ~E_4~0); 132037#L585-1 assume { :end_inline_reset_delta_events } true; 132038#L766-3 assume true; 142901#L766-1 assume !false; 142898#L767 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_~tmp~0;havoc eval_~tmp~0; 142358#L467 [2018-11-18 09:11:36,003 INFO L796 eck$LassoCheckResult]: Loop: 142358#L467 assume true; 142895#L401-1 assume !false; 142893#L402 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~5;havoc exists_runnable_thread_~__retres1~5; 142891#L364 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~5 := 1; 142890#L391 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~5; 142886#L392 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 142884#L406 assume 0 != eval_~tmp~0; 142881#L406-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 142878#L414 assume !(0 != eval_~tmp_ndt_1~0); 142873#L411 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 142870#L428 assume !(0 != eval_~tmp_ndt_2~0); 140397#L425 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 140395#L442 assume !(0 != eval_~tmp_ndt_3~0); 140394#L439 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 140391#L456 assume !(0 != eval_~tmp_ndt_4~0); 140392#L453 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 142320#L470 assume !(0 != eval_~tmp_ndt_5~0); 142358#L467 [2018-11-18 09:11:36,004 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:11:36,004 INFO L82 PathProgramCache]: Analyzing trace with hash 299558021, now seen corresponding path program 5 times [2018-11-18 09:11:36,004 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:11:36,004 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:11:36,004 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:36,005 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:11:36,005 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:36,008 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:11:36,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:11:36,018 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:11:36,019 INFO L82 PathProgramCache]: Analyzing trace with hash -788380694, now seen corresponding path program 1 times [2018-11-18 09:11:36,019 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:11:36,019 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:11:36,019 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:36,019 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 09:11:36,020 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:36,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:11:36,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:11:36,024 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 09:11:36,024 INFO L82 PathProgramCache]: Analyzing trace with hash -1224443930, now seen corresponding path program 1 times [2018-11-18 09:11:36,024 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 09:11:36,024 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 09:11:36,025 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:36,025 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 09:11:36,025 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 09:11:36,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:11:36,033 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 09:11:36,486 WARN L180 SmtUtils]: Spent 296.00 ms on a formula simplification. DAG size of input: 157 DAG size of output: 106 [2018-11-18 09:11:36,584 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 18.11 09:11:36 BoogieIcfgContainer [2018-11-18 09:11:36,584 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2018-11-18 09:11:36,584 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-18 09:11:36,584 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-18 09:11:36,584 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-18 09:11:36,588 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 09:11:31" (3/4) ... [2018-11-18 09:11:36,590 INFO L141 WitnessPrinter]: Generating witness for non-termination counterexample [2018-11-18 09:11:36,639 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_a9952978-50ee-4e47-ad28-4acf357c8425/bin-2019/uautomizer/witness.graphml [2018-11-18 09:11:36,639 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-18 09:11:36,640 INFO L168 Benchmark]: Toolchain (without parser) took 6800.59 ms. Allocated memory was 1.0 GB in the beginning and 1.4 GB in the end (delta: 324.0 MB). Free memory was 959.2 MB in the beginning and 862.5 MB in the end (delta: 96.7 MB). Peak memory consumption was 420.7 MB. Max. memory is 11.5 GB. [2018-11-18 09:11:36,640 INFO L168 Benchmark]: CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 985.5 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-18 09:11:36,640 INFO L168 Benchmark]: CACSL2BoogieTranslator took 227.22 ms. Allocated memory is still 1.0 GB. Free memory was 959.2 MB in the beginning and 940.4 MB in the end (delta: 18.8 MB). Peak memory consumption was 18.8 MB. Max. memory is 11.5 GB. [2018-11-18 09:11:36,641 INFO L168 Benchmark]: Boogie Procedure Inliner took 79.83 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 138.9 MB). Free memory was 940.4 MB in the beginning and 1.1 GB in the end (delta: -192.9 MB). Peak memory consumption was 14.8 MB. Max. memory is 11.5 GB. [2018-11-18 09:11:36,641 INFO L168 Benchmark]: Boogie Preprocessor took 40.16 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 3.4 MB). Peak memory consumption was 3.4 MB. Max. memory is 11.5 GB. [2018-11-18 09:11:36,641 INFO L168 Benchmark]: RCFGBuilder took 822.68 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 94.4 MB). Peak memory consumption was 94.4 MB. Max. memory is 11.5 GB. [2018-11-18 09:11:36,641 INFO L168 Benchmark]: BuchiAutomizer took 5572.36 ms. Allocated memory was 1.2 GB in the beginning and 1.4 GB in the end (delta: 185.1 MB). Free memory was 1.0 GB in the beginning and 870.9 MB in the end (delta: 164.7 MB). Peak memory consumption was 349.8 MB. Max. memory is 11.5 GB. [2018-11-18 09:11:36,642 INFO L168 Benchmark]: Witness Printer took 54.90 ms. Allocated memory is still 1.4 GB. Free memory was 870.9 MB in the beginning and 862.5 MB in the end (delta: 8.4 MB). Peak memory consumption was 8.4 MB. Max. memory is 11.5 GB. [2018-11-18 09:11:36,643 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 985.5 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 227.22 ms. Allocated memory is still 1.0 GB. Free memory was 959.2 MB in the beginning and 940.4 MB in the end (delta: 18.8 MB). Peak memory consumption was 18.8 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 79.83 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 138.9 MB). Free memory was 940.4 MB in the beginning and 1.1 GB in the end (delta: -192.9 MB). Peak memory consumption was 14.8 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 40.16 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 3.4 MB). Peak memory consumption was 3.4 MB. Max. memory is 11.5 GB. * RCFGBuilder took 822.68 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 94.4 MB). Peak memory consumption was 94.4 MB. Max. memory is 11.5 GB. * BuchiAutomizer took 5572.36 ms. Allocated memory was 1.2 GB in the beginning and 1.4 GB in the end (delta: 185.1 MB). Free memory was 1.0 GB in the beginning and 870.9 MB in the end (delta: 164.7 MB). Peak memory consumption was 349.8 MB. Max. memory is 11.5 GB. * Witness Printer took 54.90 ms. Allocated memory is still 1.4 GB. Free memory was 870.9 MB in the beginning and 862.5 MB in the end (delta: 8.4 MB). Peak memory consumption was 8.4 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 20 terminating modules (20 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.20 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 16955 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 5.5s and 21 iterations. TraceHistogramMax:1. Analysis of lassos took 2.4s. Construction of modules took 0.7s. Büchi inclusion checks took 0.5s. Highest rank in rank-based complementation 0. Minimization of det autom 20. Minimization of nondet autom 0. Automata minimization 0.8s AutomataMinimizationTime, 20 MinimizatonAttempts, 8965 StatesRemovedByMinimization, 10 NontrivialMinimizations. Non-live state removal took 0.4s Buchi closure took 0.0s. Biggest automaton had 16955 states and ocurred in iteration 20. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 11799 SDtfs, 12165 SDslu, 9995 SDs, 0 SdLazy, 402 SolverSat, 201 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.7s Time LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc4 concLT0 SILN1 SILU0 SILI11 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 401]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {__retres1=0, t3_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2ff2e521=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@307dd2f5=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1249450d=0, tmp=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@ced86cb=0, __retres1=0, kernel_st=1, t2_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6c41a02d=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@45f03f1b=0, t4_i=1, E_3=2, t4_pc=0, \result=0, E_1=2, tmp_ndt_2=0, \result=0, __retres1=0, \result=0, tmp_ndt_4=0, m_st=0, tmp___2=0, tmp___0=0, t3_pc=0, tmp=0, \result=0, __retres1=0, m_pc=0, \result=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@472bfd95=0, \result=0, T2_E=2, tmp___0=0, t1_pc=0, E_2=2, E_4=2, __retres1=1, T1_E=2, tmp_ndt_1=0, M_E=2, tmp=0, tmp_ndt_3=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3a24d186=0, __retres1=0, t2_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4d67c33c=0, T4_E=2, t3_i=1, t4_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@51539071=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@332a22ce=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@dfc3794=0, t1_st=0, tmp_ndt_5=0, t2_pc=0, tmp___3=0, tmp___1=0, T3_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@47816d87=0, t1_i=1, \result=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 401]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int t4_pc = 0; [L20] int m_st ; [L21] int t1_st ; [L22] int t2_st ; [L23] int t3_st ; [L24] int t4_st ; [L25] int m_i ; [L26] int t1_i ; [L27] int t2_i ; [L28] int t3_i ; [L29] int t4_i ; [L30] int M_E = 2; [L31] int T1_E = 2; [L32] int T2_E = 2; [L33] int T3_E = 2; [L34] int T4_E = 2; [L35] int E_1 = 2; [L36] int E_2 = 2; [L37] int E_3 = 2; [L38] int E_4 = 2; [L811] int __retres1 ; [L815] CALL init_model() [L723] m_i = 1 [L724] t1_i = 1 [L725] t2_i = 1 [L726] t3_i = 1 [L727] RET t4_i = 1 [L815] init_model() [L816] CALL start_simulation() [L752] int kernel_st ; [L753] int tmp ; [L754] int tmp___0 ; [L758] kernel_st = 0 [L759] FCALL update_channels() [L760] CALL init_threads() [L331] COND TRUE m_i == 1 [L332] m_st = 0 [L336] COND TRUE t1_i == 1 [L337] t1_st = 0 [L341] COND TRUE t2_i == 1 [L342] t2_st = 0 [L346] COND TRUE t3_i == 1 [L347] t3_st = 0 [L351] COND TRUE t4_i == 1 [L352] RET t4_st = 0 [L760] init_threads() [L761] CALL fire_delta_events() [L492] COND FALSE !(M_E == 0) [L497] COND FALSE !(T1_E == 0) [L502] COND FALSE !(T2_E == 0) [L507] COND FALSE !(T3_E == 0) [L512] COND FALSE !(T4_E == 0) [L517] COND FALSE !(E_1 == 0) [L522] COND FALSE !(E_2 == 0) [L527] COND FALSE !(E_3 == 0) [L532] COND FALSE, RET !(E_4 == 0) [L761] fire_delta_events() [L762] CALL activate_threads() [L595] int tmp ; [L596] int tmp___0 ; [L597] int tmp___1 ; [L598] int tmp___2 ; [L599] int tmp___3 ; [L603] CALL, EXPR is_master_triggered() [L225] int __retres1 ; [L228] COND FALSE !(m_pc == 1) [L238] __retres1 = 0 [L240] RET return (__retres1); [L603] EXPR is_master_triggered() [L603] tmp = is_master_triggered() [L605] COND FALSE !(\read(tmp)) [L611] CALL, EXPR is_transmit1_triggered() [L244] int __retres1 ; [L247] COND FALSE !(t1_pc == 1) [L257] __retres1 = 0 [L259] RET return (__retres1); [L611] EXPR is_transmit1_triggered() [L611] tmp___0 = is_transmit1_triggered() [L613] COND FALSE !(\read(tmp___0)) [L619] CALL, EXPR is_transmit2_triggered() [L263] int __retres1 ; [L266] COND FALSE !(t2_pc == 1) [L276] __retres1 = 0 [L278] RET return (__retres1); [L619] EXPR is_transmit2_triggered() [L619] tmp___1 = is_transmit2_triggered() [L621] COND FALSE !(\read(tmp___1)) [L627] CALL, EXPR is_transmit3_triggered() [L282] int __retres1 ; [L285] COND FALSE !(t3_pc == 1) [L295] __retres1 = 0 [L297] RET return (__retres1); [L627] EXPR is_transmit3_triggered() [L627] tmp___2 = is_transmit3_triggered() [L629] COND FALSE !(\read(tmp___2)) [L635] CALL, EXPR is_transmit4_triggered() [L301] int __retres1 ; [L304] COND FALSE !(t4_pc == 1) [L314] __retres1 = 0 [L316] RET return (__retres1); [L635] EXPR is_transmit4_triggered() [L635] tmp___3 = is_transmit4_triggered() [L637] COND FALSE, RET !(\read(tmp___3)) [L762] activate_threads() [L763] CALL reset_delta_events() [L545] COND FALSE !(M_E == 1) [L550] COND FALSE !(T1_E == 1) [L555] COND FALSE !(T2_E == 1) [L560] COND FALSE !(T3_E == 1) [L565] COND FALSE !(T4_E == 1) [L570] COND FALSE !(E_1 == 1) [L575] COND FALSE !(E_2 == 1) [L580] COND FALSE !(E_3 == 1) [L585] COND FALSE, RET !(E_4 == 1) [L763] reset_delta_events() [L766] COND TRUE 1 [L769] kernel_st = 1 [L770] CALL eval() [L397] int tmp ; Loop: [L401] COND TRUE 1 [L404] CALL, EXPR exists_runnable_thread() [L361] int __retres1 ; [L364] COND TRUE m_st == 0 [L365] __retres1 = 1 [L392] RET return (__retres1); [L404] EXPR exists_runnable_thread() [L404] tmp = exists_runnable_thread() [L406] COND TRUE \read(tmp) [L411] COND TRUE m_st == 0 [L412] int tmp_ndt_1; [L413] tmp_ndt_1 = __VERIFIER_nondet_int() [L414] COND FALSE !(\read(tmp_ndt_1)) [L425] COND TRUE t1_st == 0 [L426] int tmp_ndt_2; [L427] tmp_ndt_2 = __VERIFIER_nondet_int() [L428] COND FALSE !(\read(tmp_ndt_2)) [L439] COND TRUE t2_st == 0 [L440] int tmp_ndt_3; [L441] tmp_ndt_3 = __VERIFIER_nondet_int() [L442] COND FALSE !(\read(tmp_ndt_3)) [L453] COND TRUE t3_st == 0 [L454] int tmp_ndt_4; [L455] tmp_ndt_4 = __VERIFIER_nondet_int() [L456] COND FALSE !(\read(tmp_ndt_4)) [L467] COND TRUE t4_st == 0 [L468] int tmp_ndt_5; [L469] tmp_ndt_5 = __VERIFIER_nondet_int() [L470] COND FALSE !(\read(tmp_ndt_5)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...