./Ultimate.py --spec ../../sv-benchmarks/c/Termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.05_false-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 5842f4b8 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_dbb4afbb-caeb-472f-b19b-2b0b4ce518c7/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_dbb4afbb-caeb-472f-b19b-2b0b4ce518c7/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_dbb4afbb-caeb-472f-b19b-2b0b4ce518c7/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_dbb4afbb-caeb-472f-b19b-2b0b4ce518c7/bin-2019/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.05_false-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_dbb4afbb-caeb-472f-b19b-2b0b4ce518c7/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_dbb4afbb-caeb-472f-b19b-2b0b4ce518c7/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 8ef5d3a30c95e1a42cc229ca801f47c5cf92951a ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.1.23-5842f4b [2018-11-18 16:15:49,661 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-18 16:15:49,662 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-18 16:15:49,671 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-18 16:15:49,671 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-18 16:15:49,672 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-18 16:15:49,673 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-18 16:15:49,674 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-18 16:15:49,675 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-18 16:15:49,676 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-18 16:15:49,676 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-18 16:15:49,677 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-18 16:15:49,677 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-18 16:15:49,678 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-18 16:15:49,678 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-18 16:15:49,679 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-18 16:15:49,679 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-18 16:15:49,680 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-18 16:15:49,683 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-18 16:15:49,684 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-18 16:15:49,684 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-18 16:15:49,686 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-18 16:15:49,687 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-18 16:15:49,687 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-18 16:15:49,687 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-18 16:15:49,688 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-18 16:15:49,689 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-18 16:15:49,689 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-18 16:15:49,690 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-18 16:15:49,690 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-18 16:15:49,690 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-18 16:15:49,691 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-18 16:15:49,691 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-18 16:15:49,691 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-18 16:15:49,692 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-18 16:15:49,692 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-18 16:15:49,692 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_dbb4afbb-caeb-472f-b19b-2b0b4ce518c7/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2018-11-18 16:15:49,701 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-18 16:15:49,701 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-18 16:15:49,702 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-18 16:15:49,702 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-18 16:15:49,702 INFO L133 SettingsManager]: * Use SBE=true [2018-11-18 16:15:49,702 INFO L131 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2018-11-18 16:15:49,702 INFO L133 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2018-11-18 16:15:49,702 INFO L133 SettingsManager]: * Use old map elimination=false [2018-11-18 16:15:49,703 INFO L133 SettingsManager]: * Use external solver (rank synthesis)=false [2018-11-18 16:15:49,703 INFO L133 SettingsManager]: * Use only trivial implications for array writes=true [2018-11-18 16:15:49,703 INFO L133 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2018-11-18 16:15:49,703 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-18 16:15:49,703 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-18 16:15:49,703 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-11-18 16:15:49,703 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-18 16:15:49,704 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-18 16:15:49,704 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-18 16:15:49,704 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2018-11-18 16:15:49,704 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2018-11-18 16:15:49,704 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2018-11-18 16:15:49,706 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-18 16:15:49,706 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-18 16:15:49,706 INFO L133 SettingsManager]: * Assume nondeterminstic values are in range=false [2018-11-18 16:15:49,706 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-18 16:15:49,706 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2018-11-18 16:15:49,706 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-18 16:15:49,707 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-18 16:15:49,707 INFO L133 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2018-11-18 16:15:49,707 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-18 16:15:49,707 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-18 16:15:49,707 INFO L133 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2018-11-18 16:15:49,708 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-11-18 16:15:49,708 INFO L133 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_dbb4afbb-caeb-472f-b19b-2b0b4ce518c7/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 8ef5d3a30c95e1a42cc229ca801f47c5cf92951a [2018-11-18 16:15:49,733 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-18 16:15:49,742 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-18 16:15:49,744 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-18 16:15:49,745 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-18 16:15:49,746 INFO L276 PluginConnector]: CDTParser initialized [2018-11-18 16:15:49,746 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_dbb4afbb-caeb-472f-b19b-2b0b4ce518c7/bin-2019/uautomizer/../../sv-benchmarks/c/systemc/transmitter.05_false-unreach-call_false-termination.cil.c [2018-11-18 16:15:49,791 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_dbb4afbb-caeb-472f-b19b-2b0b4ce518c7/bin-2019/uautomizer/data/167fdb55c/c80f261f392240dfbd3bc6531d23c4fb/FLAG79709b757 [2018-11-18 16:15:50,152 INFO L307 CDTParser]: Found 1 translation units. [2018-11-18 16:15:50,153 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_dbb4afbb-caeb-472f-b19b-2b0b4ce518c7/sv-benchmarks/c/systemc/transmitter.05_false-unreach-call_false-termination.cil.c [2018-11-18 16:15:50,162 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_dbb4afbb-caeb-472f-b19b-2b0b4ce518c7/bin-2019/uautomizer/data/167fdb55c/c80f261f392240dfbd3bc6531d23c4fb/FLAG79709b757 [2018-11-18 16:15:50,548 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_dbb4afbb-caeb-472f-b19b-2b0b4ce518c7/bin-2019/uautomizer/data/167fdb55c/c80f261f392240dfbd3bc6531d23c4fb [2018-11-18 16:15:50,551 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-18 16:15:50,552 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-18 16:15:50,553 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-18 16:15:50,553 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-18 16:15:50,556 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-18 16:15:50,556 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 04:15:50" (1/1) ... [2018-11-18 16:15:50,558 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4c44aa5a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 04:15:50, skipping insertion in model container [2018-11-18 16:15:50,558 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 04:15:50" (1/1) ... [2018-11-18 16:15:50,564 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-18 16:15:50,590 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-18 16:15:50,730 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 16:15:50,734 INFO L191 MainTranslator]: Completed pre-run [2018-11-18 16:15:50,763 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 16:15:50,779 INFO L195 MainTranslator]: Completed translation [2018-11-18 16:15:50,779 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 04:15:50 WrapperNode [2018-11-18 16:15:50,779 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-18 16:15:50,780 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-18 16:15:50,780 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-18 16:15:50,780 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-18 16:15:50,785 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 04:15:50" (1/1) ... [2018-11-18 16:15:50,790 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 04:15:50" (1/1) ... [2018-11-18 16:15:50,864 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-18 16:15:50,865 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-18 16:15:50,865 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-18 16:15:50,865 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-18 16:15:50,873 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 04:15:50" (1/1) ... [2018-11-18 16:15:50,874 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 04:15:50" (1/1) ... [2018-11-18 16:15:50,878 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 04:15:50" (1/1) ... [2018-11-18 16:15:50,878 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 04:15:50" (1/1) ... [2018-11-18 16:15:50,890 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 04:15:50" (1/1) ... [2018-11-18 16:15:50,905 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 04:15:50" (1/1) ... [2018-11-18 16:15:50,911 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 04:15:50" (1/1) ... [2018-11-18 16:15:50,915 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-18 16:15:50,916 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-18 16:15:50,916 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-18 16:15:50,916 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-18 16:15:50,917 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 04:15:50" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_dbb4afbb-caeb-472f-b19b-2b0b4ce518c7/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 16:15:50,981 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-18 16:15:50,981 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-18 16:15:51,750 INFO L278 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-18 16:15:51,750 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 04:15:51 BoogieIcfgContainer [2018-11-18 16:15:51,750 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-18 16:15:51,751 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2018-11-18 16:15:51,751 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2018-11-18 16:15:51,753 INFO L276 PluginConnector]: BuchiAutomizer initialized [2018-11-18 16:15:51,753 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-18 16:15:51,754 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 18.11 04:15:50" (1/3) ... [2018-11-18 16:15:51,754 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@15f2badc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 18.11 04:15:51, skipping insertion in model container [2018-11-18 16:15:51,754 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-18 16:15:51,754 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 04:15:50" (2/3) ... [2018-11-18 16:15:51,755 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@15f2badc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 18.11 04:15:51, skipping insertion in model container [2018-11-18 16:15:51,755 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-18 16:15:51,755 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 04:15:51" (3/3) ... [2018-11-18 16:15:51,756 INFO L375 chiAutomizerObserver]: Analyzing ICFG transmitter.05_false-unreach-call_false-termination.cil.c [2018-11-18 16:15:51,799 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-18 16:15:51,800 INFO L374 BuchiCegarLoop]: Interprodecural is true [2018-11-18 16:15:51,800 INFO L375 BuchiCegarLoop]: Hoare is false [2018-11-18 16:15:51,800 INFO L376 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2018-11-18 16:15:51,800 INFO L377 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-18 16:15:51,801 INFO L378 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-18 16:15:51,801 INFO L379 BuchiCegarLoop]: Difference is false [2018-11-18 16:15:51,801 INFO L380 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-18 16:15:51,801 INFO L383 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2018-11-18 16:15:51,817 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 514 states. [2018-11-18 16:15:51,842 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 433 [2018-11-18 16:15:51,842 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 16:15:51,842 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 16:15:51,849 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:51,849 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:51,849 INFO L442 BuchiCegarLoop]: ======== Iteration 1============ [2018-11-18 16:15:51,849 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 514 states. [2018-11-18 16:15:51,856 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 433 [2018-11-18 16:15:51,856 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 16:15:51,856 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 16:15:51,858 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:51,858 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:51,865 INFO L794 eck$LassoCheckResult]: Stem: 356#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 313#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 101#L853true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 330#L384true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 62#L391true assume !(1 == ~m_i~0);~m_st~0 := 2; 70#L391-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 381#L396-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 147#L401-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 331#L406-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 46#L411-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 455#L416-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49#L576true assume 0 == ~M_E~0;~M_E~0 := 1; 40#L576-2true assume !(0 == ~T1_E~0); 448#L581-1true assume !(0 == ~T2_E~0); 249#L586-1true assume !(0 == ~T3_E~0); 498#L591-1true assume !(0 == ~T4_E~0); 166#L596-1true assume !(0 == ~T5_E~0); 432#L601-1true assume !(0 == ~E_1~0); 214#L606-1true assume !(0 == ~E_2~0); 78#L611-1true assume 0 == ~E_3~0;~E_3~0 := 1; 390#L616-1true assume !(0 == ~E_4~0); 8#L621-1true assume !(0 == ~E_5~0); 334#L626-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 143#L269true assume 1 == ~m_pc~0; 71#L270true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 144#L280true is_master_triggered_#res := is_master_triggered_~__retres1~0; 72#L281true activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 90#L710true assume !(0 != activate_threads_~tmp~1); 74#L710-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 167#L288true assume !(1 == ~t1_pc~0); 289#L288-2true is_transmit1_triggered_~__retres1~1 := 0; 168#L299true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 258#L300true activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 265#L718true assume !(0 != activate_threads_~tmp___0~0); 267#L718-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 315#L307true assume 1 == ~t2_pc~0; 354#L308true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 314#L318true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 385#L319true activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 401#L726true assume !(0 != activate_threads_~tmp___1~0); 386#L726-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 427#L326true assume 1 == ~t3_pc~0; 488#L327true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 426#L337true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 486#L338true activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 506#L734true assume !(0 != activate_threads_~tmp___2~0); 510#L734-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 32#L345true assume !(1 == ~t4_pc~0); 35#L345-2true is_transmit4_triggered_~__retres1~4 := 0; 31#L356true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 148#L357true activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 17#L742true assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 3#L742-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 210#L364true assume 1 == ~t5_pc~0; 153#L365true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 208#L375true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 152#L376true activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 173#L750true assume !(0 != activate_threads_~tmp___4~0); 177#L750-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 344#L639true assume 1 == ~M_E~0;~M_E~0 := 2; 215#L639-2true assume !(1 == ~T1_E~0); 75#L644-1true assume !(1 == ~T2_E~0); 389#L649-1true assume !(1 == ~T3_E~0); 6#L654-1true assume !(1 == ~T4_E~0); 333#L659-1true assume !(1 == ~T5_E~0); 48#L664-1true assume !(1 == ~E_1~0); 457#L669-1true assume !(1 == ~E_2~0); 268#L674-1true assume 1 == ~E_3~0;~E_3~0 := 2; 513#L679-1true assume !(1 == ~E_4~0); 178#L684-1true assume !(1 == ~E_5~0); 435#L689-1true assume { :end_inline_reset_delta_events } true; 338#L890-3true [2018-11-18 16:15:51,867 INFO L796 eck$LassoCheckResult]: Loop: 338#L890-3true assume true; 337#L890-1true assume !false; 405#L891true start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 216#L551true assume !true; 10#L566true assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 332#L384-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 42#L576-3true assume 0 == ~M_E~0;~M_E~0 := 1; 44#L576-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 451#L581-3true assume !(0 == ~T2_E~0); 259#L586-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 500#L591-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 170#L596-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 433#L601-3true assume 0 == ~E_1~0;~E_1~0 := 1; 219#L606-3true assume 0 == ~E_2~0;~E_2~0 := 1; 84#L611-3true assume 0 == ~E_3~0;~E_3~0 := 1; 395#L616-3true assume 0 == ~E_4~0;~E_4~0 := 1; 13#L621-3true assume !(0 == ~E_5~0); 336#L626-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 77#L269-18true assume 1 == ~m_pc~0; 439#L270-6true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 97#L280-6true is_master_triggered_#res := is_master_triggered_~__retres1~0; 441#L281-6true activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 444#L710-18true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 445#L710-20true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 277#L288-18true assume 1 == ~t1_pc~0; 225#L289-6true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 280#L299-6true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 226#L300-6true activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 241#L718-18true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 242#L718-20true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 400#L307-18true assume !(1 == ~t2_pc~0); 402#L307-20true is_transmit2_triggered_~__retres1~2 := 0; 308#L318-6true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 347#L319-6true activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 346#L726-18true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 351#L726-20true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 505#L326-18true assume 1 == ~t3_pc~0; 476#L327-6true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 423#L337-6true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 474#L338-6true activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 475#L734-18true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 479#L734-20true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 15#L345-18true assume !(1 == ~t4_pc~0); 18#L345-20true is_transmit4_triggered_~__retres1~4 := 0; 26#L356-6true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 127#L357-6true activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 105#L742-18true assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 109#L742-20true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 185#L364-18true assume 1 == ~t5_pc~0; 298#L365-6true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 201#L375-6true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 297#L376-6true activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 300#L750-18true assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 304#L750-20true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 218#L639-3true assume 1 == ~M_E~0;~M_E~0 := 2; 220#L639-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 81#L644-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 393#L649-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 11#L654-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 335#L659-3true assume !(1 == ~T5_E~0); 50#L664-3true assume 1 == ~E_1~0;~E_1~0 := 2; 460#L669-3true assume 1 == ~E_2~0;~E_2~0 := 2; 272#L674-3true assume 1 == ~E_3~0;~E_3~0 := 2; 496#L679-3true assume 1 == ~E_4~0;~E_4~0 := 2; 165#L684-3true assume 1 == ~E_5~0;~E_5~0 := 2; 431#L689-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 379#L429-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 328#L461-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 378#L462-1true start_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 436#L909true assume !(0 == start_simulation_~tmp~3); 440#L909-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 383#L429-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 329#L461-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 380#L462-2true stop_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 100#L864true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 183#L871true stop_simulation_#res := stop_simulation_~__retres2~0; 273#L872true start_simulation_#t~ret15 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 466#L922true assume !(0 != start_simulation_~tmp___0~1); 338#L890-3true [2018-11-18 16:15:51,872 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:51,872 INFO L82 PathProgramCache]: Analyzing trace with hash -777385748, now seen corresponding path program 1 times [2018-11-18 16:15:51,874 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:15:51,875 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:15:51,910 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:51,910 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:15:51,910 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:51,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:15:51,985 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:15:51,987 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 16:15:51,987 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 16:15:51,991 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 16:15:51,991 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:51,991 INFO L82 PathProgramCache]: Analyzing trace with hash 29941730, now seen corresponding path program 1 times [2018-11-18 16:15:51,991 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:15:51,992 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:15:51,992 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:51,992 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:15:51,992 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:51,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:15:52,010 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:15:52,011 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 16:15:52,011 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 16:15:52,012 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 16:15:52,026 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 16:15:52,026 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 16:15:52,028 INFO L87 Difference]: Start difference. First operand 514 states. Second operand 3 states. [2018-11-18 16:15:52,068 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:15:52,068 INFO L93 Difference]: Finished difference Result 513 states and 761 transitions. [2018-11-18 16:15:52,068 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 16:15:52,070 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 513 states and 761 transitions. [2018-11-18 16:15:52,074 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 430 [2018-11-18 16:15:52,081 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 513 states to 507 states and 755 transitions. [2018-11-18 16:15:52,082 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 507 [2018-11-18 16:15:52,083 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 507 [2018-11-18 16:15:52,084 INFO L73 IsDeterministic]: Start isDeterministic. Operand 507 states and 755 transitions. [2018-11-18 16:15:52,086 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 16:15:52,087 INFO L705 BuchiCegarLoop]: Abstraction has 507 states and 755 transitions. [2018-11-18 16:15:52,099 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 507 states and 755 transitions. [2018-11-18 16:15:52,121 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 507 to 507. [2018-11-18 16:15:52,121 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 507 states. [2018-11-18 16:15:52,123 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 507 states to 507 states and 755 transitions. [2018-11-18 16:15:52,124 INFO L728 BuchiCegarLoop]: Abstraction has 507 states and 755 transitions. [2018-11-18 16:15:52,124 INFO L608 BuchiCegarLoop]: Abstraction has 507 states and 755 transitions. [2018-11-18 16:15:52,124 INFO L442 BuchiCegarLoop]: ======== Iteration 2============ [2018-11-18 16:15:52,124 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 507 states and 755 transitions. [2018-11-18 16:15:52,126 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 430 [2018-11-18 16:15:52,126 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 16:15:52,126 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 16:15:52,128 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:52,128 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:52,129 INFO L794 eck$LassoCheckResult]: Stem: 1461#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 1423#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1212#L853 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 1213#L384 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1147#L391 assume 1 == ~m_i~0;~m_st~0 := 0; 1148#L391-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1165#L396-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1243#L401-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1244#L406-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1114#L411-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1115#L416-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1121#L576 assume 0 == ~M_E~0;~M_E~0 := 1; 1101#L576-2 assume !(0 == ~T1_E~0); 1102#L581-1 assume !(0 == ~T2_E~0); 1370#L586-1 assume !(0 == ~T3_E~0); 1371#L591-1 assume !(0 == ~T4_E~0); 1278#L596-1 assume !(0 == ~T5_E~0); 1279#L601-1 assume !(0 == ~E_1~0); 1321#L606-1 assume !(0 == ~E_2~0); 1179#L611-1 assume 0 == ~E_3~0;~E_3~0 := 1; 1180#L616-1 assume !(0 == ~E_4~0); 1046#L621-1 assume !(0 == ~E_5~0); 1047#L626-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1239#L269 assume 1 == ~m_pc~0; 1166#L270 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 1167#L280 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1169#L281 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1170#L710 assume !(0 != activate_threads_~tmp~1); 1171#L710-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1172#L288 assume !(1 == ~t1_pc~0); 1280#L288-2 is_transmit1_triggered_~__retres1~1 := 0; 1282#L299 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1283#L300 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 1384#L718 assume !(0 != activate_threads_~tmp___0~0); 1392#L718-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1393#L307 assume 1 == ~t2_pc~0; 1426#L308 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1424#L318 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1425#L319 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1484#L726 assume !(0 != activate_threads_~tmp___1~0); 1485#L726-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1486#L326 assume 1 == ~t3_pc~0; 1515#L327 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1502#L337 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1514#L338 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1535#L734 assume !(0 != activate_threads_~tmp___2~0); 1542#L734-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1091#L345 assume !(1 == ~t4_pc~0); 1092#L345-2 is_transmit4_triggered_~__retres1~4 := 0; 1089#L356 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1090#L357 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1064#L742 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1036#L742-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1037#L364 assume 1 == ~t5_pc~0; 1249#L365 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 1250#L375 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1247#L376 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1248#L750 assume !(0 != activate_threads_~tmp___4~0); 1288#L750-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1295#L639 assume 1 == ~M_E~0;~M_E~0 := 2; 1322#L639-2 assume !(1 == ~T1_E~0); 1173#L644-1 assume !(1 == ~T2_E~0); 1174#L649-1 assume !(1 == ~T3_E~0); 1043#L654-1 assume !(1 == ~T4_E~0); 1044#L659-1 assume !(1 == ~T5_E~0); 1119#L664-1 assume !(1 == ~E_1~0); 1120#L669-1 assume !(1 == ~E_2~0); 1394#L674-1 assume 1 == ~E_3~0;~E_3~0 := 2; 1395#L679-1 assume !(1 == ~E_4~0); 1296#L684-1 assume !(1 == ~E_5~0); 1297#L689-1 assume { :end_inline_reset_delta_events } true; 1445#L890-3 [2018-11-18 16:15:52,129 INFO L796 eck$LassoCheckResult]: Loop: 1445#L890-3 assume true; 1443#L890-1 assume !false; 1444#L891 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 1126#L551 assume true; 1323#L471-1 assume !false; 1438#L472 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1439#L429 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 1109#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1440#L462 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 1387#L476 assume !(0 != eval_~tmp~0); 1049#L566 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 1050#L384-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 1105#L576-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1106#L576-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1110#L581-3 assume !(0 == ~T2_E~0); 1385#L586-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1386#L591-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1285#L596-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1286#L601-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1327#L606-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1192#L611-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1193#L616-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1055#L621-3 assume !(0 == ~E_5~0); 1056#L626-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1176#L269-18 assume 1 == ~m_pc~0; 1177#L270-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 1203#L280-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1208#L281-6 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 1519#L710-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1520#L710-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1402#L288-18 assume 1 == ~t1_pc~0; 1335#L289-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1336#L299-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1338#L300-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 1339#L718-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1361#L718-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1362#L307-18 assume 1 == ~t2_pc~0; 1452#L308-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1414#L318-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1415#L319-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1450#L726-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1451#L726-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1457#L326-18 assume 1 == ~t3_pc~0; 1530#L327-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1509#L337-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1510#L338-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1528#L734-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1529#L734-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1061#L345-18 assume 1 == ~t4_pc~0; 1062#L346-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1065#L356-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1081#L357-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1214#L742-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1215#L742-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1218#L364-18 assume !(1 == ~t5_pc~0); 1289#L364-20 is_transmit5_triggered_~__retres1~5 := 0; 1290#L375-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1314#L376-6 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1408#L750-18 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 1409#L750-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1325#L639-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1326#L639-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1184#L644-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1185#L649-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1051#L654-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1052#L659-3 assume !(1 == ~T5_E~0); 1122#L664-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1123#L669-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1396#L674-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1397#L679-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1276#L684-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1277#L689-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1481#L429-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 1112#L461-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1441#L462-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 1480#L909 assume !(0 == start_simulation_~tmp~3); 1493#L909-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 1483#L429-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 1117#L461-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 1442#L462-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 1210#L864 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1211#L871 stop_simulation_#res := stop_simulation_~__retres2~0; 1303#L872 start_simulation_#t~ret15 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 1398#L922 assume !(0 != start_simulation_~tmp___0~1); 1445#L890-3 [2018-11-18 16:15:52,130 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:52,130 INFO L82 PathProgramCache]: Analyzing trace with hash 438767978, now seen corresponding path program 1 times [2018-11-18 16:15:52,130 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:15:52,130 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:15:52,131 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:52,131 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:15:52,131 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:52,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:15:52,172 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:15:52,172 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 16:15:52,172 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 16:15:52,172 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 16:15:52,173 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:52,173 INFO L82 PathProgramCache]: Analyzing trace with hash 1049592300, now seen corresponding path program 1 times [2018-11-18 16:15:52,173 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:15:52,173 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:15:52,173 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:52,173 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:15:52,174 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:52,190 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:15:52,235 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:15:52,235 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 16:15:52,235 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 16:15:52,235 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 16:15:52,236 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 16:15:52,236 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 16:15:52,236 INFO L87 Difference]: Start difference. First operand 507 states and 755 transitions. cyclomatic complexity: 249 Second operand 3 states. [2018-11-18 16:15:52,250 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:15:52,250 INFO L93 Difference]: Finished difference Result 507 states and 754 transitions. [2018-11-18 16:15:52,251 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 16:15:52,251 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 507 states and 754 transitions. [2018-11-18 16:15:52,254 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 430 [2018-11-18 16:15:52,256 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 507 states to 507 states and 754 transitions. [2018-11-18 16:15:52,256 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 507 [2018-11-18 16:15:52,257 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 507 [2018-11-18 16:15:52,257 INFO L73 IsDeterministic]: Start isDeterministic. Operand 507 states and 754 transitions. [2018-11-18 16:15:52,259 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 16:15:52,259 INFO L705 BuchiCegarLoop]: Abstraction has 507 states and 754 transitions. [2018-11-18 16:15:52,260 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 507 states and 754 transitions. [2018-11-18 16:15:52,269 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 507 to 507. [2018-11-18 16:15:52,269 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 507 states. [2018-11-18 16:15:52,271 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 507 states to 507 states and 754 transitions. [2018-11-18 16:15:52,271 INFO L728 BuchiCegarLoop]: Abstraction has 507 states and 754 transitions. [2018-11-18 16:15:52,271 INFO L608 BuchiCegarLoop]: Abstraction has 507 states and 754 transitions. [2018-11-18 16:15:52,271 INFO L442 BuchiCegarLoop]: ======== Iteration 3============ [2018-11-18 16:15:52,272 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 507 states and 754 transitions. [2018-11-18 16:15:52,274 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 430 [2018-11-18 16:15:52,274 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 16:15:52,275 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 16:15:52,276 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:52,276 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:52,277 INFO L794 eck$LassoCheckResult]: Stem: 2482#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 2444#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 2233#L853 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 2234#L384 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2168#L391 assume 1 == ~m_i~0;~m_st~0 := 0; 2169#L391-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2186#L396-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2264#L401-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2265#L406-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2135#L411-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2136#L416-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2142#L576 assume 0 == ~M_E~0;~M_E~0 := 1; 2122#L576-2 assume !(0 == ~T1_E~0); 2123#L581-1 assume !(0 == ~T2_E~0); 2391#L586-1 assume !(0 == ~T3_E~0); 2392#L591-1 assume !(0 == ~T4_E~0); 2299#L596-1 assume !(0 == ~T5_E~0); 2300#L601-1 assume !(0 == ~E_1~0); 2342#L606-1 assume !(0 == ~E_2~0); 2200#L611-1 assume 0 == ~E_3~0;~E_3~0 := 1; 2201#L616-1 assume !(0 == ~E_4~0); 2067#L621-1 assume !(0 == ~E_5~0); 2068#L626-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2260#L269 assume 1 == ~m_pc~0; 2187#L270 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 2188#L280 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2190#L281 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 2191#L710 assume !(0 != activate_threads_~tmp~1); 2192#L710-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2193#L288 assume !(1 == ~t1_pc~0); 2301#L288-2 is_transmit1_triggered_~__retres1~1 := 0; 2303#L299 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2304#L300 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2405#L718 assume !(0 != activate_threads_~tmp___0~0); 2413#L718-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2414#L307 assume 1 == ~t2_pc~0; 2447#L308 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2445#L318 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2446#L319 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2505#L726 assume !(0 != activate_threads_~tmp___1~0); 2506#L726-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2507#L326 assume 1 == ~t3_pc~0; 2536#L327 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2523#L337 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2535#L338 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2556#L734 assume !(0 != activate_threads_~tmp___2~0); 2563#L734-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2112#L345 assume !(1 == ~t4_pc~0); 2113#L345-2 is_transmit4_triggered_~__retres1~4 := 0; 2110#L356 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2111#L357 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2085#L742 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 2057#L742-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2058#L364 assume 1 == ~t5_pc~0; 2270#L365 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 2271#L375 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2268#L376 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2269#L750 assume !(0 != activate_threads_~tmp___4~0); 2309#L750-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2316#L639 assume 1 == ~M_E~0;~M_E~0 := 2; 2343#L639-2 assume !(1 == ~T1_E~0); 2194#L644-1 assume !(1 == ~T2_E~0); 2195#L649-1 assume !(1 == ~T3_E~0); 2064#L654-1 assume !(1 == ~T4_E~0); 2065#L659-1 assume !(1 == ~T5_E~0); 2140#L664-1 assume !(1 == ~E_1~0); 2141#L669-1 assume !(1 == ~E_2~0); 2415#L674-1 assume 1 == ~E_3~0;~E_3~0 := 2; 2416#L679-1 assume !(1 == ~E_4~0); 2317#L684-1 assume !(1 == ~E_5~0); 2318#L689-1 assume { :end_inline_reset_delta_events } true; 2466#L890-3 [2018-11-18 16:15:52,277 INFO L796 eck$LassoCheckResult]: Loop: 2466#L890-3 assume true; 2464#L890-1 assume !false; 2465#L891 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 2147#L551 assume true; 2344#L471-1 assume !false; 2459#L472 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 2460#L429 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 2130#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 2461#L462 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 2408#L476 assume !(0 != eval_~tmp~0); 2070#L566 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 2071#L384-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 2126#L576-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2127#L576-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2131#L581-3 assume !(0 == ~T2_E~0); 2406#L586-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2407#L591-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2306#L596-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2307#L601-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2348#L606-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2213#L611-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2214#L616-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2076#L621-3 assume !(0 == ~E_5~0); 2077#L626-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2197#L269-18 assume 1 == ~m_pc~0; 2198#L270-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 2224#L280-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2229#L281-6 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 2540#L710-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2541#L710-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2423#L288-18 assume 1 == ~t1_pc~0; 2356#L289-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2357#L299-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2359#L300-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2360#L718-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2382#L718-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2383#L307-18 assume 1 == ~t2_pc~0; 2473#L308-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2435#L318-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2436#L319-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2471#L726-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2472#L726-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2478#L326-18 assume 1 == ~t3_pc~0; 2551#L327-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2530#L337-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2531#L338-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2549#L734-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2550#L734-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2082#L345-18 assume 1 == ~t4_pc~0; 2083#L346-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2086#L356-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2102#L357-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2235#L742-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 2236#L742-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2239#L364-18 assume !(1 == ~t5_pc~0); 2310#L364-20 is_transmit5_triggered_~__retres1~5 := 0; 2311#L375-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2335#L376-6 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2429#L750-18 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 2430#L750-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2346#L639-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2347#L639-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2205#L644-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2206#L649-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2072#L654-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2073#L659-3 assume !(1 == ~T5_E~0); 2143#L664-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2144#L669-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2417#L674-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2418#L679-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2297#L684-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2298#L689-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 2502#L429-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 2133#L461-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 2462#L462-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 2501#L909 assume !(0 == start_simulation_~tmp~3); 2514#L909-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 2504#L429-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 2138#L461-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 2463#L462-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 2231#L864 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2232#L871 stop_simulation_#res := stop_simulation_~__retres2~0; 2324#L872 start_simulation_#t~ret15 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 2419#L922 assume !(0 != start_simulation_~tmp___0~1); 2466#L890-3 [2018-11-18 16:15:52,277 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:52,277 INFO L82 PathProgramCache]: Analyzing trace with hash 2124947816, now seen corresponding path program 1 times [2018-11-18 16:15:52,278 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:15:52,278 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:15:52,278 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:52,279 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:15:52,279 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:52,285 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:15:52,308 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:15:52,308 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 16:15:52,308 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 16:15:52,308 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 16:15:52,309 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:52,309 INFO L82 PathProgramCache]: Analyzing trace with hash 1049592300, now seen corresponding path program 2 times [2018-11-18 16:15:52,309 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:15:52,309 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:15:52,309 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:52,310 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:15:52,310 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:52,320 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:15:52,355 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:15:52,355 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 16:15:52,355 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 16:15:52,355 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 16:15:52,356 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 16:15:52,356 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 16:15:52,356 INFO L87 Difference]: Start difference. First operand 507 states and 754 transitions. cyclomatic complexity: 248 Second operand 3 states. [2018-11-18 16:15:52,381 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:15:52,381 INFO L93 Difference]: Finished difference Result 507 states and 753 transitions. [2018-11-18 16:15:52,382 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 16:15:52,382 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 507 states and 753 transitions. [2018-11-18 16:15:52,384 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 430 [2018-11-18 16:15:52,386 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 507 states to 507 states and 753 transitions. [2018-11-18 16:15:52,386 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 507 [2018-11-18 16:15:52,386 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 507 [2018-11-18 16:15:52,387 INFO L73 IsDeterministic]: Start isDeterministic. Operand 507 states and 753 transitions. [2018-11-18 16:15:52,387 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 16:15:52,387 INFO L705 BuchiCegarLoop]: Abstraction has 507 states and 753 transitions. [2018-11-18 16:15:52,388 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 507 states and 753 transitions. [2018-11-18 16:15:52,392 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 507 to 507. [2018-11-18 16:15:52,392 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 507 states. [2018-11-18 16:15:52,394 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 507 states to 507 states and 753 transitions. [2018-11-18 16:15:52,394 INFO L728 BuchiCegarLoop]: Abstraction has 507 states and 753 transitions. [2018-11-18 16:15:52,394 INFO L608 BuchiCegarLoop]: Abstraction has 507 states and 753 transitions. [2018-11-18 16:15:52,394 INFO L442 BuchiCegarLoop]: ======== Iteration 4============ [2018-11-18 16:15:52,394 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 507 states and 753 transitions. [2018-11-18 16:15:52,396 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 430 [2018-11-18 16:15:52,396 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 16:15:52,396 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 16:15:52,397 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:52,397 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:52,398 INFO L794 eck$LassoCheckResult]: Stem: 3503#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 3465#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 3254#L853 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 3255#L384 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3189#L391 assume 1 == ~m_i~0;~m_st~0 := 0; 3190#L391-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3207#L396-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3285#L401-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3286#L406-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3156#L411-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3157#L416-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3163#L576 assume 0 == ~M_E~0;~M_E~0 := 1; 3143#L576-2 assume !(0 == ~T1_E~0); 3144#L581-1 assume !(0 == ~T2_E~0); 3412#L586-1 assume !(0 == ~T3_E~0); 3413#L591-1 assume !(0 == ~T4_E~0); 3320#L596-1 assume !(0 == ~T5_E~0); 3321#L601-1 assume !(0 == ~E_1~0); 3363#L606-1 assume !(0 == ~E_2~0); 3221#L611-1 assume 0 == ~E_3~0;~E_3~0 := 1; 3222#L616-1 assume !(0 == ~E_4~0); 3088#L621-1 assume !(0 == ~E_5~0); 3089#L626-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3281#L269 assume 1 == ~m_pc~0; 3208#L270 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 3209#L280 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3211#L281 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 3212#L710 assume !(0 != activate_threads_~tmp~1); 3213#L710-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3214#L288 assume !(1 == ~t1_pc~0); 3322#L288-2 is_transmit1_triggered_~__retres1~1 := 0; 3324#L299 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3325#L300 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 3426#L718 assume !(0 != activate_threads_~tmp___0~0); 3434#L718-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3435#L307 assume 1 == ~t2_pc~0; 3468#L308 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3466#L318 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3467#L319 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 3526#L726 assume !(0 != activate_threads_~tmp___1~0); 3527#L726-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3528#L326 assume 1 == ~t3_pc~0; 3557#L327 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3544#L337 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3556#L338 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3577#L734 assume !(0 != activate_threads_~tmp___2~0); 3584#L734-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3133#L345 assume !(1 == ~t4_pc~0); 3134#L345-2 is_transmit4_triggered_~__retres1~4 := 0; 3131#L356 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3132#L357 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3106#L742 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 3078#L742-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3079#L364 assume 1 == ~t5_pc~0; 3291#L365 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 3292#L375 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3289#L376 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3290#L750 assume !(0 != activate_threads_~tmp___4~0); 3330#L750-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3337#L639 assume 1 == ~M_E~0;~M_E~0 := 2; 3364#L639-2 assume !(1 == ~T1_E~0); 3215#L644-1 assume !(1 == ~T2_E~0); 3216#L649-1 assume !(1 == ~T3_E~0); 3085#L654-1 assume !(1 == ~T4_E~0); 3086#L659-1 assume !(1 == ~T5_E~0); 3161#L664-1 assume !(1 == ~E_1~0); 3162#L669-1 assume !(1 == ~E_2~0); 3436#L674-1 assume 1 == ~E_3~0;~E_3~0 := 2; 3437#L679-1 assume !(1 == ~E_4~0); 3338#L684-1 assume !(1 == ~E_5~0); 3339#L689-1 assume { :end_inline_reset_delta_events } true; 3487#L890-3 [2018-11-18 16:15:52,398 INFO L796 eck$LassoCheckResult]: Loop: 3487#L890-3 assume true; 3485#L890-1 assume !false; 3486#L891 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 3168#L551 assume true; 3365#L471-1 assume !false; 3480#L472 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 3481#L429 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 3151#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 3482#L462 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 3429#L476 assume !(0 != eval_~tmp~0); 3091#L566 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 3092#L384-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 3147#L576-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3148#L576-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3152#L581-3 assume !(0 == ~T2_E~0); 3427#L586-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3428#L591-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3327#L596-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3328#L601-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3369#L606-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3234#L611-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3235#L616-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3097#L621-3 assume !(0 == ~E_5~0); 3098#L626-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3218#L269-18 assume 1 == ~m_pc~0; 3219#L270-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 3245#L280-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3250#L281-6 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 3561#L710-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3562#L710-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3444#L288-18 assume 1 == ~t1_pc~0; 3377#L289-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 3378#L299-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3380#L300-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 3381#L718-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3403#L718-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3404#L307-18 assume 1 == ~t2_pc~0; 3494#L308-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3456#L318-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3457#L319-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 3492#L726-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3493#L726-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3499#L326-18 assume 1 == ~t3_pc~0; 3572#L327-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3551#L337-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3552#L338-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3570#L734-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 3571#L734-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3103#L345-18 assume 1 == ~t4_pc~0; 3104#L346-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3107#L356-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3123#L357-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3256#L742-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 3257#L742-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3260#L364-18 assume !(1 == ~t5_pc~0); 3331#L364-20 is_transmit5_triggered_~__retres1~5 := 0; 3332#L375-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3356#L376-6 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3450#L750-18 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 3451#L750-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3367#L639-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3368#L639-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3226#L644-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3227#L649-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3093#L654-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3094#L659-3 assume !(1 == ~T5_E~0); 3164#L664-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3165#L669-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3438#L674-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3439#L679-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3318#L684-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3319#L689-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 3523#L429-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 3154#L461-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 3483#L462-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 3522#L909 assume !(0 == start_simulation_~tmp~3); 3535#L909-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 3525#L429-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 3159#L461-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 3484#L462-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 3252#L864 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 3253#L871 stop_simulation_#res := stop_simulation_~__retres2~0; 3345#L872 start_simulation_#t~ret15 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 3440#L922 assume !(0 != start_simulation_~tmp___0~1); 3487#L890-3 [2018-11-18 16:15:52,398 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:52,398 INFO L82 PathProgramCache]: Analyzing trace with hash -2115626582, now seen corresponding path program 1 times [2018-11-18 16:15:52,399 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:15:52,399 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:15:52,399 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:52,400 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:15:52,400 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:52,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:15:52,433 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:15:52,433 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 16:15:52,434 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 16:15:52,434 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 16:15:52,434 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:52,434 INFO L82 PathProgramCache]: Analyzing trace with hash 1049592300, now seen corresponding path program 3 times [2018-11-18 16:15:52,434 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:15:52,435 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:15:52,435 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:52,435 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:15:52,435 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:52,442 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:15:52,492 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:15:52,492 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 16:15:52,492 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 16:15:52,493 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 16:15:52,493 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 16:15:52,493 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 16:15:52,493 INFO L87 Difference]: Start difference. First operand 507 states and 753 transitions. cyclomatic complexity: 247 Second operand 3 states. [2018-11-18 16:15:52,500 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:15:52,500 INFO L93 Difference]: Finished difference Result 507 states and 752 transitions. [2018-11-18 16:15:52,501 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 16:15:52,501 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 507 states and 752 transitions. [2018-11-18 16:15:52,503 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 430 [2018-11-18 16:15:52,505 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 507 states to 507 states and 752 transitions. [2018-11-18 16:15:52,505 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 507 [2018-11-18 16:15:52,505 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 507 [2018-11-18 16:15:52,505 INFO L73 IsDeterministic]: Start isDeterministic. Operand 507 states and 752 transitions. [2018-11-18 16:15:52,506 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 16:15:52,506 INFO L705 BuchiCegarLoop]: Abstraction has 507 states and 752 transitions. [2018-11-18 16:15:52,507 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 507 states and 752 transitions. [2018-11-18 16:15:52,511 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 507 to 507. [2018-11-18 16:15:52,511 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 507 states. [2018-11-18 16:15:52,512 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 507 states to 507 states and 752 transitions. [2018-11-18 16:15:52,512 INFO L728 BuchiCegarLoop]: Abstraction has 507 states and 752 transitions. [2018-11-18 16:15:52,512 INFO L608 BuchiCegarLoop]: Abstraction has 507 states and 752 transitions. [2018-11-18 16:15:52,512 INFO L442 BuchiCegarLoop]: ======== Iteration 5============ [2018-11-18 16:15:52,512 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 507 states and 752 transitions. [2018-11-18 16:15:52,514 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 430 [2018-11-18 16:15:52,514 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 16:15:52,514 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 16:15:52,515 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:52,515 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:52,516 INFO L794 eck$LassoCheckResult]: Stem: 4524#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 4486#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 4275#L853 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 4276#L384 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4210#L391 assume 1 == ~m_i~0;~m_st~0 := 0; 4211#L391-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4228#L396-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4306#L401-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4307#L406-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4177#L411-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4178#L416-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4184#L576 assume 0 == ~M_E~0;~M_E~0 := 1; 4164#L576-2 assume !(0 == ~T1_E~0); 4165#L581-1 assume !(0 == ~T2_E~0); 4433#L586-1 assume !(0 == ~T3_E~0); 4434#L591-1 assume !(0 == ~T4_E~0); 4341#L596-1 assume !(0 == ~T5_E~0); 4342#L601-1 assume !(0 == ~E_1~0); 4384#L606-1 assume !(0 == ~E_2~0); 4242#L611-1 assume 0 == ~E_3~0;~E_3~0 := 1; 4243#L616-1 assume !(0 == ~E_4~0); 4109#L621-1 assume !(0 == ~E_5~0); 4110#L626-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4302#L269 assume 1 == ~m_pc~0; 4229#L270 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 4230#L280 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4232#L281 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 4233#L710 assume !(0 != activate_threads_~tmp~1); 4234#L710-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4235#L288 assume !(1 == ~t1_pc~0); 4343#L288-2 is_transmit1_triggered_~__retres1~1 := 0; 4345#L299 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4346#L300 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 4447#L718 assume !(0 != activate_threads_~tmp___0~0); 4455#L718-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4456#L307 assume 1 == ~t2_pc~0; 4489#L308 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4487#L318 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4488#L319 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 4547#L726 assume !(0 != activate_threads_~tmp___1~0); 4548#L726-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4549#L326 assume 1 == ~t3_pc~0; 4578#L327 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 4565#L337 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4577#L338 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 4598#L734 assume !(0 != activate_threads_~tmp___2~0); 4605#L734-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4154#L345 assume !(1 == ~t4_pc~0); 4155#L345-2 is_transmit4_triggered_~__retres1~4 := 0; 4152#L356 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4153#L357 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 4127#L742 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 4099#L742-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4100#L364 assume 1 == ~t5_pc~0; 4312#L365 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 4313#L375 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4310#L376 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4311#L750 assume !(0 != activate_threads_~tmp___4~0); 4351#L750-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4358#L639 assume 1 == ~M_E~0;~M_E~0 := 2; 4385#L639-2 assume !(1 == ~T1_E~0); 4236#L644-1 assume !(1 == ~T2_E~0); 4237#L649-1 assume !(1 == ~T3_E~0); 4106#L654-1 assume !(1 == ~T4_E~0); 4107#L659-1 assume !(1 == ~T5_E~0); 4182#L664-1 assume !(1 == ~E_1~0); 4183#L669-1 assume !(1 == ~E_2~0); 4457#L674-1 assume 1 == ~E_3~0;~E_3~0 := 2; 4458#L679-1 assume !(1 == ~E_4~0); 4359#L684-1 assume !(1 == ~E_5~0); 4360#L689-1 assume { :end_inline_reset_delta_events } true; 4508#L890-3 [2018-11-18 16:15:52,516 INFO L796 eck$LassoCheckResult]: Loop: 4508#L890-3 assume true; 4506#L890-1 assume !false; 4507#L891 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 4189#L551 assume true; 4386#L471-1 assume !false; 4501#L472 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 4502#L429 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 4172#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 4503#L462 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 4450#L476 assume !(0 != eval_~tmp~0); 4112#L566 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 4113#L384-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 4168#L576-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4169#L576-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4173#L581-3 assume !(0 == ~T2_E~0); 4448#L586-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4449#L591-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4348#L596-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4349#L601-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4390#L606-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4255#L611-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4256#L616-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4118#L621-3 assume !(0 == ~E_5~0); 4119#L626-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4239#L269-18 assume 1 == ~m_pc~0; 4240#L270-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 4266#L280-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4271#L281-6 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 4582#L710-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4583#L710-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4465#L288-18 assume !(1 == ~t1_pc~0); 4400#L288-20 is_transmit1_triggered_~__retres1~1 := 0; 4399#L299-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4401#L300-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 4402#L718-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4424#L718-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4425#L307-18 assume 1 == ~t2_pc~0; 4515#L308-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4477#L318-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4478#L319-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 4513#L726-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4514#L726-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4520#L326-18 assume 1 == ~t3_pc~0; 4593#L327-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 4572#L337-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4573#L338-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 4591#L734-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 4592#L734-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4122#L345-18 assume 1 == ~t4_pc~0; 4123#L346-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4128#L356-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4144#L357-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 4277#L742-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 4278#L742-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4281#L364-18 assume !(1 == ~t5_pc~0); 4352#L364-20 is_transmit5_triggered_~__retres1~5 := 0; 4353#L375-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4377#L376-6 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4471#L750-18 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 4472#L750-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4388#L639-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4389#L639-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4247#L644-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4248#L649-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4114#L654-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4115#L659-3 assume !(1 == ~T5_E~0); 4185#L664-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4186#L669-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4459#L674-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4460#L679-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4339#L684-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4340#L689-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 4544#L429-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 4175#L461-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 4504#L462-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 4543#L909 assume !(0 == start_simulation_~tmp~3); 4556#L909-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 4546#L429-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 4180#L461-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 4505#L462-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 4273#L864 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 4274#L871 stop_simulation_#res := stop_simulation_~__retres2~0; 4366#L872 start_simulation_#t~ret15 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 4461#L922 assume !(0 != start_simulation_~tmp___0~1); 4508#L890-3 [2018-11-18 16:15:52,516 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:52,516 INFO L82 PathProgramCache]: Analyzing trace with hash -1698229976, now seen corresponding path program 1 times [2018-11-18 16:15:52,516 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:15:52,516 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:15:52,517 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:52,517 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:15:52,517 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:52,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:15:52,539 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:15:52,539 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 16:15:52,539 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 16:15:52,540 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 16:15:52,540 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:52,540 INFO L82 PathProgramCache]: Analyzing trace with hash 1152393547, now seen corresponding path program 1 times [2018-11-18 16:15:52,540 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:15:52,540 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:15:52,541 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:52,541 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:15:52,541 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:52,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:15:52,583 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:15:52,583 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 16:15:52,583 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 16:15:52,584 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 16:15:52,584 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 16:15:52,584 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 16:15:52,584 INFO L87 Difference]: Start difference. First operand 507 states and 752 transitions. cyclomatic complexity: 246 Second operand 3 states. [2018-11-18 16:15:52,590 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:15:52,590 INFO L93 Difference]: Finished difference Result 507 states and 751 transitions. [2018-11-18 16:15:52,591 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 16:15:52,591 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 507 states and 751 transitions. [2018-11-18 16:15:52,592 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 430 [2018-11-18 16:15:52,594 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 507 states to 507 states and 751 transitions. [2018-11-18 16:15:52,594 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 507 [2018-11-18 16:15:52,594 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 507 [2018-11-18 16:15:52,594 INFO L73 IsDeterministic]: Start isDeterministic. Operand 507 states and 751 transitions. [2018-11-18 16:15:52,595 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 16:15:52,595 INFO L705 BuchiCegarLoop]: Abstraction has 507 states and 751 transitions. [2018-11-18 16:15:52,595 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 507 states and 751 transitions. [2018-11-18 16:15:52,598 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 507 to 507. [2018-11-18 16:15:52,598 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 507 states. [2018-11-18 16:15:52,599 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 507 states to 507 states and 751 transitions. [2018-11-18 16:15:52,600 INFO L728 BuchiCegarLoop]: Abstraction has 507 states and 751 transitions. [2018-11-18 16:15:52,600 INFO L608 BuchiCegarLoop]: Abstraction has 507 states and 751 transitions. [2018-11-18 16:15:52,600 INFO L442 BuchiCegarLoop]: ======== Iteration 6============ [2018-11-18 16:15:52,600 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 507 states and 751 transitions. [2018-11-18 16:15:52,601 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 430 [2018-11-18 16:15:52,601 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 16:15:52,601 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 16:15:52,602 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:52,603 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:52,603 INFO L794 eck$LassoCheckResult]: Stem: 5545#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 5507#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 5296#L853 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 5297#L384 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5231#L391 assume 1 == ~m_i~0;~m_st~0 := 0; 5232#L391-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5249#L396-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5327#L401-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5328#L406-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5198#L411-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 5199#L416-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5205#L576 assume 0 == ~M_E~0;~M_E~0 := 1; 5185#L576-2 assume !(0 == ~T1_E~0); 5186#L581-1 assume !(0 == ~T2_E~0); 5454#L586-1 assume !(0 == ~T3_E~0); 5455#L591-1 assume !(0 == ~T4_E~0); 5362#L596-1 assume !(0 == ~T5_E~0); 5363#L601-1 assume !(0 == ~E_1~0); 5405#L606-1 assume !(0 == ~E_2~0); 5263#L611-1 assume 0 == ~E_3~0;~E_3~0 := 1; 5264#L616-1 assume !(0 == ~E_4~0); 5130#L621-1 assume !(0 == ~E_5~0); 5131#L626-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5323#L269 assume 1 == ~m_pc~0; 5250#L270 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 5251#L280 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5253#L281 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 5254#L710 assume !(0 != activate_threads_~tmp~1); 5255#L710-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5256#L288 assume !(1 == ~t1_pc~0); 5364#L288-2 is_transmit1_triggered_~__retres1~1 := 0; 5366#L299 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5367#L300 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 5468#L718 assume !(0 != activate_threads_~tmp___0~0); 5476#L718-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5477#L307 assume 1 == ~t2_pc~0; 5510#L308 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5508#L318 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5509#L319 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 5568#L726 assume !(0 != activate_threads_~tmp___1~0); 5569#L726-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5570#L326 assume 1 == ~t3_pc~0; 5599#L327 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 5586#L337 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5598#L338 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 5619#L734 assume !(0 != activate_threads_~tmp___2~0); 5626#L734-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5175#L345 assume !(1 == ~t4_pc~0); 5176#L345-2 is_transmit4_triggered_~__retres1~4 := 0; 5173#L356 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5174#L357 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 5148#L742 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 5120#L742-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5121#L364 assume 1 == ~t5_pc~0; 5333#L365 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 5334#L375 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5331#L376 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 5332#L750 assume !(0 != activate_threads_~tmp___4~0); 5372#L750-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5379#L639 assume 1 == ~M_E~0;~M_E~0 := 2; 5406#L639-2 assume !(1 == ~T1_E~0); 5257#L644-1 assume !(1 == ~T2_E~0); 5258#L649-1 assume !(1 == ~T3_E~0); 5127#L654-1 assume !(1 == ~T4_E~0); 5128#L659-1 assume !(1 == ~T5_E~0); 5203#L664-1 assume !(1 == ~E_1~0); 5204#L669-1 assume !(1 == ~E_2~0); 5478#L674-1 assume 1 == ~E_3~0;~E_3~0 := 2; 5479#L679-1 assume !(1 == ~E_4~0); 5380#L684-1 assume !(1 == ~E_5~0); 5381#L689-1 assume { :end_inline_reset_delta_events } true; 5529#L890-3 [2018-11-18 16:15:52,603 INFO L796 eck$LassoCheckResult]: Loop: 5529#L890-3 assume true; 5527#L890-1 assume !false; 5528#L891 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 5210#L551 assume true; 5407#L471-1 assume !false; 5522#L472 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 5523#L429 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 5193#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 5524#L462 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 5471#L476 assume !(0 != eval_~tmp~0); 5133#L566 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 5134#L384-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 5189#L576-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5190#L576-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5194#L581-3 assume !(0 == ~T2_E~0); 5469#L586-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5470#L591-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5369#L596-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5370#L601-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5411#L606-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5276#L611-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5277#L616-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5139#L621-3 assume !(0 == ~E_5~0); 5140#L626-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5260#L269-18 assume 1 == ~m_pc~0; 5261#L270-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 5287#L280-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5292#L281-6 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 5603#L710-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 5604#L710-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5486#L288-18 assume 1 == ~t1_pc~0; 5419#L289-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 5420#L299-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5422#L300-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 5423#L718-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5445#L718-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5446#L307-18 assume 1 == ~t2_pc~0; 5536#L308-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5498#L318-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5499#L319-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 5534#L726-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 5535#L726-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5541#L326-18 assume 1 == ~t3_pc~0; 5614#L327-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 5593#L337-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5594#L338-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 5612#L734-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 5613#L734-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5143#L345-18 assume 1 == ~t4_pc~0; 5144#L346-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5149#L356-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5165#L357-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 5298#L742-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 5299#L742-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5302#L364-18 assume !(1 == ~t5_pc~0); 5373#L364-20 is_transmit5_triggered_~__retres1~5 := 0; 5374#L375-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5398#L376-6 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 5492#L750-18 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 5493#L750-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5409#L639-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5410#L639-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5268#L644-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5269#L649-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5135#L654-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5136#L659-3 assume !(1 == ~T5_E~0); 5206#L664-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5207#L669-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5480#L674-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5481#L679-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5360#L684-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5361#L689-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 5565#L429-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 5196#L461-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 5525#L462-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 5564#L909 assume !(0 == start_simulation_~tmp~3); 5577#L909-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 5567#L429-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 5201#L461-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 5526#L462-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 5294#L864 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5295#L871 stop_simulation_#res := stop_simulation_~__retres2~0; 5387#L872 start_simulation_#t~ret15 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 5482#L922 assume !(0 != start_simulation_~tmp___0~1); 5529#L890-3 [2018-11-18 16:15:52,603 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:52,603 INFO L82 PathProgramCache]: Analyzing trace with hash 1917465066, now seen corresponding path program 1 times [2018-11-18 16:15:52,603 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:15:52,604 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:15:52,604 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:52,604 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:15:52,604 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:52,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:15:52,630 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:15:52,630 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 16:15:52,631 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 16:15:52,631 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 16:15:52,631 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:52,631 INFO L82 PathProgramCache]: Analyzing trace with hash 1049592300, now seen corresponding path program 4 times [2018-11-18 16:15:52,631 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:15:52,631 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:15:52,632 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:52,632 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:15:52,632 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:52,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:15:52,655 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:15:52,656 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 16:15:52,656 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 16:15:52,656 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 16:15:52,656 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 16:15:52,656 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 16:15:52,656 INFO L87 Difference]: Start difference. First operand 507 states and 751 transitions. cyclomatic complexity: 245 Second operand 3 states. [2018-11-18 16:15:52,720 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:15:52,720 INFO L93 Difference]: Finished difference Result 893 states and 1310 transitions. [2018-11-18 16:15:52,721 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 16:15:52,721 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 893 states and 1310 transitions. [2018-11-18 16:15:52,723 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 816 [2018-11-18 16:15:52,725 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 893 states to 893 states and 1310 transitions. [2018-11-18 16:15:52,726 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 893 [2018-11-18 16:15:52,726 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 893 [2018-11-18 16:15:52,726 INFO L73 IsDeterministic]: Start isDeterministic. Operand 893 states and 1310 transitions. [2018-11-18 16:15:52,727 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 16:15:52,727 INFO L705 BuchiCegarLoop]: Abstraction has 893 states and 1310 transitions. [2018-11-18 16:15:52,728 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 893 states and 1310 transitions. [2018-11-18 16:15:52,735 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 893 to 893. [2018-11-18 16:15:52,735 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 893 states. [2018-11-18 16:15:52,737 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 893 states to 893 states and 1310 transitions. [2018-11-18 16:15:52,737 INFO L728 BuchiCegarLoop]: Abstraction has 893 states and 1310 transitions. [2018-11-18 16:15:52,737 INFO L608 BuchiCegarLoop]: Abstraction has 893 states and 1310 transitions. [2018-11-18 16:15:52,737 INFO L442 BuchiCegarLoop]: ======== Iteration 7============ [2018-11-18 16:15:52,737 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 893 states and 1310 transitions. [2018-11-18 16:15:52,740 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 816 [2018-11-18 16:15:52,740 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 16:15:52,740 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 16:15:52,741 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:52,741 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:52,741 INFO L794 eck$LassoCheckResult]: Stem: 6984#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 6944#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 6702#L853 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 6703#L384 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6641#L391 assume 1 == ~m_i~0;~m_st~0 := 0; 6642#L391-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6652#L396-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6740#L401-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6741#L406-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6605#L411-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6606#L416-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6612#L576 assume !(0 == ~M_E~0); 6594#L576-2 assume !(0 == ~T1_E~0); 6595#L581-1 assume !(0 == ~T2_E~0); 6882#L586-1 assume !(0 == ~T3_E~0); 6883#L591-1 assume !(0 == ~T4_E~0); 6775#L596-1 assume !(0 == ~T5_E~0); 6776#L601-1 assume !(0 == ~E_1~0); 6826#L606-1 assume !(0 == ~E_2~0); 6665#L611-1 assume 0 == ~E_3~0;~E_3~0 := 1; 6666#L616-1 assume !(0 == ~E_4~0); 6537#L621-1 assume !(0 == ~E_5~0); 6538#L626-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6736#L269 assume !(1 == ~m_pc~0); 6654#L269-2 is_master_triggered_~__retres1~0 := 0; 6729#L280 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6655#L281 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 6656#L710 assume !(0 != activate_threads_~tmp~1); 6657#L710-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6658#L288 assume !(1 == ~t1_pc~0); 6777#L288-2 is_transmit1_triggered_~__retres1~1 := 0; 6780#L299 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6781#L300 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 6894#L718 assume !(0 != activate_threads_~tmp___0~0); 6901#L718-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6902#L307 assume 1 == ~t2_pc~0; 6947#L308 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 6945#L318 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6946#L319 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 7013#L726 assume !(0 != activate_threads_~tmp___1~0); 7014#L726-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7015#L326 assume 1 == ~t3_pc~0; 7044#L327 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 7031#L337 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7043#L338 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 7068#L734 assume !(0 != activate_threads_~tmp___2~0); 7074#L734-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6582#L345 assume !(1 == ~t4_pc~0); 6583#L345-2 is_transmit4_triggered_~__retres1~4 := 0; 6580#L356 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6581#L357 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 6555#L742 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 6527#L742-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 6528#L364 assume 1 == ~t5_pc~0; 6746#L365 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 6747#L375 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 6744#L376 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 6745#L750 assume !(0 != activate_threads_~tmp___4~0); 6787#L750-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6794#L639 assume !(1 == ~M_E~0); 6827#L639-2 assume !(1 == ~T1_E~0); 6660#L644-1 assume !(1 == ~T2_E~0); 6661#L649-1 assume !(1 == ~T3_E~0); 6534#L654-1 assume !(1 == ~T4_E~0); 6535#L659-1 assume !(1 == ~T5_E~0); 6610#L664-1 assume !(1 == ~E_1~0); 6611#L669-1 assume !(1 == ~E_2~0); 6903#L674-1 assume 1 == ~E_3~0;~E_3~0 := 2; 6904#L679-1 assume !(1 == ~E_4~0); 6795#L684-1 assume !(1 == ~E_5~0); 6796#L689-1 assume { :end_inline_reset_delta_events } true; 6967#L890-3 [2018-11-18 16:15:52,741 INFO L796 eck$LassoCheckResult]: Loop: 6967#L890-3 assume true; 6965#L890-1 assume !false; 6966#L891 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 6617#L551 assume true; 6828#L471-1 assume !false; 6960#L472 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 6961#L429 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 6600#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 6962#L462 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 6895#L476 assume !(0 != eval_~tmp~0); 6540#L566 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 6541#L384-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 6596#L576-3 assume !(0 == ~M_E~0); 6597#L576-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6601#L581-3 assume !(0 == ~T2_E~0); 6892#L586-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6893#L591-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6782#L596-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6783#L601-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6832#L606-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6678#L611-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6679#L616-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6546#L621-3 assume !(0 == ~E_5~0); 6547#L626-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6662#L269-18 assume !(1 == ~m_pc~0); 6664#L269-20 is_master_triggered_~__retres1~0 := 0; 6689#L280-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6696#L281-6 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 7048#L710-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 7049#L710-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6913#L288-18 assume 1 == ~t1_pc~0; 6841#L289-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 6842#L299-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6844#L300-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 6845#L718-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 6869#L718-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6870#L307-18 assume !(1 == ~t2_pc~0); 6976#L307-20 is_transmit2_triggered_~__retres1~2 := 0; 6935#L318-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6936#L319-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 6973#L726-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 6974#L726-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6980#L326-18 assume 1 == ~t3_pc~0; 7061#L327-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 7038#L337-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7039#L338-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 7059#L734-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 7060#L734-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6550#L345-18 assume 1 == ~t4_pc~0; 6551#L346-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 6556#L356-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6572#L357-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 6706#L742-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 6707#L742-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 6711#L364-18 assume !(1 == ~t5_pc~0); 6805#L364-20 is_transmit5_triggered_~__retres1~5 := 0; 7111#L375-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 6922#L376-6 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 6923#L750-18 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 6930#L750-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6830#L639-3 assume !(1 == ~M_E~0); 6831#L639-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7375#L644-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7374#L649-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7373#L654-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7372#L659-3 assume !(1 == ~T5_E~0); 7362#L664-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7052#L669-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6907#L674-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6908#L679-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6773#L684-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6774#L689-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 7008#L429-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 6603#L461-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 6963#L462-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 7007#L909 assume !(0 == start_simulation_~tmp~3); 7022#L909-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 7009#L429-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 6608#L461-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 6964#L462-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 6699#L864 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 6700#L871 stop_simulation_#res := stop_simulation_~__retres2~0; 6802#L872 start_simulation_#t~ret15 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 6909#L922 assume !(0 != start_simulation_~tmp___0~1); 6967#L890-3 [2018-11-18 16:15:52,741 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:52,742 INFO L82 PathProgramCache]: Analyzing trace with hash -484678139, now seen corresponding path program 1 times [2018-11-18 16:15:52,742 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:15:52,742 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:15:52,742 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:52,742 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:15:52,743 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:52,746 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:15:52,770 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:15:52,771 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 16:15:52,771 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 16:15:52,771 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 16:15:52,771 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:52,771 INFO L82 PathProgramCache]: Analyzing trace with hash 518830118, now seen corresponding path program 1 times [2018-11-18 16:15:52,771 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:15:52,771 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:15:52,772 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:52,772 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:15:52,772 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:52,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:15:52,805 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:15:52,805 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 16:15:52,805 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 16:15:52,805 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 16:15:52,806 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 16:15:52,806 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 16:15:52,806 INFO L87 Difference]: Start difference. First operand 893 states and 1310 transitions. cyclomatic complexity: 418 Second operand 3 states. [2018-11-18 16:15:52,836 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:15:52,836 INFO L93 Difference]: Finished difference Result 893 states and 1290 transitions. [2018-11-18 16:15:52,837 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 16:15:52,837 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 893 states and 1290 transitions. [2018-11-18 16:15:52,840 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 816 [2018-11-18 16:15:52,842 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 893 states to 893 states and 1290 transitions. [2018-11-18 16:15:52,842 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 893 [2018-11-18 16:15:52,842 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 893 [2018-11-18 16:15:52,843 INFO L73 IsDeterministic]: Start isDeterministic. Operand 893 states and 1290 transitions. [2018-11-18 16:15:52,844 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 16:15:52,844 INFO L705 BuchiCegarLoop]: Abstraction has 893 states and 1290 transitions. [2018-11-18 16:15:52,845 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 893 states and 1290 transitions. [2018-11-18 16:15:52,852 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 893 to 893. [2018-11-18 16:15:52,852 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 893 states. [2018-11-18 16:15:52,854 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 893 states to 893 states and 1290 transitions. [2018-11-18 16:15:52,854 INFO L728 BuchiCegarLoop]: Abstraction has 893 states and 1290 transitions. [2018-11-18 16:15:52,854 INFO L608 BuchiCegarLoop]: Abstraction has 893 states and 1290 transitions. [2018-11-18 16:15:52,854 INFO L442 BuchiCegarLoop]: ======== Iteration 8============ [2018-11-18 16:15:52,855 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 893 states and 1290 transitions. [2018-11-18 16:15:52,857 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 816 [2018-11-18 16:15:52,857 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 16:15:52,857 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 16:15:52,858 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:52,858 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:52,858 INFO L794 eck$LassoCheckResult]: Stem: 8794#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 8749#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 8498#L853 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 8499#L384 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8430#L391 assume 1 == ~m_i~0;~m_st~0 := 0; 8431#L391-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8446#L396-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8541#L401-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8542#L406-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8399#L411-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8400#L416-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8406#L576 assume !(0 == ~M_E~0); 8386#L576-2 assume !(0 == ~T1_E~0); 8387#L581-1 assume !(0 == ~T2_E~0); 8676#L586-1 assume !(0 == ~T3_E~0); 8677#L591-1 assume !(0 == ~T4_E~0); 8576#L596-1 assume !(0 == ~T5_E~0); 8577#L601-1 assume !(0 == ~E_1~0); 8623#L606-1 assume !(0 == ~E_2~0); 8459#L611-1 assume !(0 == ~E_3~0); 8460#L616-1 assume !(0 == ~E_4~0); 8330#L621-1 assume !(0 == ~E_5~0); 8331#L626-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8537#L269 assume !(1 == ~m_pc~0); 8448#L269-2 is_master_triggered_~__retres1~0 := 0; 8526#L280 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8449#L281 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 8450#L710 assume !(0 != activate_threads_~tmp~1); 8451#L710-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8452#L288 assume !(1 == ~t1_pc~0); 8578#L288-2 is_transmit1_triggered_~__retres1~1 := 0; 8581#L299 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8582#L300 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 8692#L718 assume !(0 != activate_threads_~tmp___0~0); 8701#L718-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8702#L307 assume 1 == ~t2_pc~0; 8752#L308 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 8750#L318 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8751#L319 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 8818#L726 assume !(0 != activate_threads_~tmp___1~0); 8819#L726-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8820#L326 assume !(1 == ~t3_pc~0); 8837#L326-2 is_transmit3_triggered_~__retres1~3 := 0; 8838#L337 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 8851#L338 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 8879#L734 assume !(0 != activate_threads_~tmp___2~0); 8885#L734-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 8375#L345 assume !(1 == ~t4_pc~0); 8376#L345-2 is_transmit4_triggered_~__retres1~4 := 0; 8373#L356 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 8374#L357 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 8348#L742 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 8320#L742-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 8321#L364 assume 1 == ~t5_pc~0; 8547#L365 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 8548#L375 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 8545#L376 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 8546#L750 assume !(0 != activate_threads_~tmp___4~0); 8586#L750-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8593#L639 assume !(1 == ~M_E~0); 8624#L639-2 assume !(1 == ~T1_E~0); 8453#L644-1 assume !(1 == ~T2_E~0); 8454#L649-1 assume !(1 == ~T3_E~0); 8327#L654-1 assume !(1 == ~T4_E~0); 8328#L659-1 assume !(1 == ~T5_E~0); 8404#L664-1 assume !(1 == ~E_1~0); 8405#L669-1 assume !(1 == ~E_2~0); 8703#L674-1 assume !(1 == ~E_3~0); 8704#L679-1 assume !(1 == ~E_4~0); 8594#L684-1 assume !(1 == ~E_5~0); 8595#L689-1 assume { :end_inline_reset_delta_events } true; 8774#L890-3 [2018-11-18 16:15:52,858 INFO L796 eck$LassoCheckResult]: Loop: 8774#L890-3 assume true; 8775#L890-1 assume !false; 8824#L891 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 8411#L551 assume true; 8625#L471-1 assume !false; 8767#L472 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 8768#L429 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 8394#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 8769#L462 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 8695#L476 assume !(0 != eval_~tmp~0); 8333#L566 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 8334#L384-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 8390#L576-3 assume !(0 == ~M_E~0); 8391#L576-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8395#L581-3 assume !(0 == ~T2_E~0); 8693#L586-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8694#L591-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8583#L596-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8584#L601-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8629#L606-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8472#L611-3 assume !(0 == ~E_3~0); 8473#L616-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8339#L621-3 assume !(0 == ~E_5~0); 8340#L626-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8456#L269-18 assume !(1 == ~m_pc~0); 8458#L269-20 is_master_triggered_~__retres1~0 := 0; 8491#L280-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8492#L281-6 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 8856#L710-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 8857#L710-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8858#L288-18 assume !(1 == ~t1_pc~0); 8640#L288-20 is_transmit1_triggered_~__retres1~1 := 0; 8639#L299-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8641#L300-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 8642#L718-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 8667#L718-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8668#L307-18 assume 1 == ~t2_pc~0; 8784#L308-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 8738#L318-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8739#L319-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 8781#L726-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 8782#L726-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8934#L326-18 assume !(1 == ~t3_pc~0); 8932#L326-20 is_transmit3_triggered_~__retres1~3 := 0; 8931#L337-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 8930#L338-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 8929#L734-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 8928#L734-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 8927#L345-18 assume 1 == ~t4_pc~0; 8925#L346-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 8924#L356-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 8923#L357-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 8922#L742-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 8921#L742-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 8920#L364-18 assume !(1 == ~t5_pc~0); 8918#L364-20 is_transmit5_triggered_~__retres1~5 := 0; 8917#L375-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 8729#L376-6 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 8730#L750-18 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 8733#L750-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8626#L639-3 assume !(1 == ~M_E~0); 8627#L639-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8463#L644-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8464#L649-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8335#L654-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8336#L659-3 assume !(1 == ~T5_E~0); 8407#L664-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8408#L669-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8705#L674-3 assume !(1 == ~E_3~0); 8706#L679-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8572#L684-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8573#L689-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 8815#L429-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 8397#L461-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 8770#L462-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 8813#L909 assume !(0 == start_simulation_~tmp~3); 8829#L909-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 8817#L429-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 8402#L461-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 8771#L462-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 8496#L864 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 8497#L871 stop_simulation_#res := stop_simulation_~__retres2~0; 8601#L872 start_simulation_#t~ret15 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 9131#L922 assume !(0 != start_simulation_~tmp___0~1); 8774#L890-3 [2018-11-18 16:15:52,859 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:52,859 INFO L82 PathProgramCache]: Analyzing trace with hash 996577248, now seen corresponding path program 1 times [2018-11-18 16:15:52,859 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:15:52,859 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:15:52,859 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:52,859 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:15:52,860 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:52,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:15:52,897 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:15:52,897 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 16:15:52,897 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 16:15:52,897 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 16:15:52,897 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:52,898 INFO L82 PathProgramCache]: Analyzing trace with hash 252788289, now seen corresponding path program 1 times [2018-11-18 16:15:52,898 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:15:52,898 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:15:52,898 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:52,898 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:15:52,899 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:52,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:15:52,932 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:15:52,932 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 16:15:52,932 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 16:15:52,933 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 16:15:52,933 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 16:15:52,933 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 16:15:52,933 INFO L87 Difference]: Start difference. First operand 893 states and 1290 transitions. cyclomatic complexity: 398 Second operand 3 states. [2018-11-18 16:15:52,967 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:15:52,967 INFO L93 Difference]: Finished difference Result 1607 states and 2305 transitions. [2018-11-18 16:15:52,968 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 16:15:52,968 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1607 states and 2305 transitions. [2018-11-18 16:15:52,972 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1527 [2018-11-18 16:15:52,975 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1607 states to 1607 states and 2305 transitions. [2018-11-18 16:15:52,976 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1607 [2018-11-18 16:15:52,976 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1607 [2018-11-18 16:15:52,977 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1607 states and 2305 transitions. [2018-11-18 16:15:52,978 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 16:15:52,978 INFO L705 BuchiCegarLoop]: Abstraction has 1607 states and 2305 transitions. [2018-11-18 16:15:52,979 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1607 states and 2305 transitions. [2018-11-18 16:15:52,990 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1607 to 1601. [2018-11-18 16:15:52,990 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1601 states. [2018-11-18 16:15:52,992 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1601 states to 1601 states and 2299 transitions. [2018-11-18 16:15:52,992 INFO L728 BuchiCegarLoop]: Abstraction has 1601 states and 2299 transitions. [2018-11-18 16:15:52,993 INFO L608 BuchiCegarLoop]: Abstraction has 1601 states and 2299 transitions. [2018-11-18 16:15:52,993 INFO L442 BuchiCegarLoop]: ======== Iteration 9============ [2018-11-18 16:15:52,993 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1601 states and 2299 transitions. [2018-11-18 16:15:52,996 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1521 [2018-11-18 16:15:52,996 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 16:15:52,997 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 16:15:52,998 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:52,998 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:52,998 INFO L794 eck$LassoCheckResult]: Stem: 11298#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 11250#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 11001#L853 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 11002#L384 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10936#L391 assume 1 == ~m_i~0;~m_st~0 := 0; 10937#L391-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10953#L396-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11045#L401-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11046#L406-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10905#L411-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10906#L416-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10912#L576 assume !(0 == ~M_E~0); 10892#L576-2 assume !(0 == ~T1_E~0); 10893#L581-1 assume !(0 == ~T2_E~0); 11187#L586-1 assume !(0 == ~T3_E~0); 11188#L591-1 assume !(0 == ~T4_E~0); 11080#L596-1 assume !(0 == ~T5_E~0); 11081#L601-1 assume !(0 == ~E_1~0); 11133#L606-1 assume !(0 == ~E_2~0); 10966#L611-1 assume !(0 == ~E_3~0); 10967#L616-1 assume !(0 == ~E_4~0); 10837#L621-1 assume !(0 == ~E_5~0); 10838#L626-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 11041#L269 assume !(1 == ~m_pc~0); 10955#L269-2 is_master_triggered_~__retres1~0 := 0; 11033#L280 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10956#L281 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 10957#L710 assume !(0 != activate_threads_~tmp~1); 10958#L710-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10959#L288 assume !(1 == ~t1_pc~0); 11082#L288-2 is_transmit1_triggered_~__retres1~1 := 0; 11084#L299 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 11085#L300 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 11202#L718 assume !(0 != activate_threads_~tmp___0~0); 11212#L718-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 11213#L307 assume !(1 == ~t2_pc~0); 11253#L307-2 is_transmit2_triggered_~__retres1~2 := 0; 11251#L318 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 11252#L319 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 11338#L726 assume !(0 != activate_threads_~tmp___1~0); 11339#L726-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 11340#L326 assume !(1 == ~t3_pc~0); 11369#L326-2 is_transmit3_triggered_~__retres1~3 := 0; 11370#L337 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 11382#L338 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 11417#L734 assume !(0 != activate_threads_~tmp___2~0); 11427#L734-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 10882#L345 assume !(1 == ~t4_pc~0); 10883#L345-2 is_transmit4_triggered_~__retres1~4 := 0; 10880#L356 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 10881#L357 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 10855#L742 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 10827#L742-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 10828#L364 assume 1 == ~t5_pc~0; 11051#L365 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 11052#L375 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 11049#L376 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 11050#L750 assume !(0 != activate_threads_~tmp___4~0); 11091#L750-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11098#L639 assume !(1 == ~M_E~0); 11134#L639-2 assume !(1 == ~T1_E~0); 10960#L644-1 assume !(1 == ~T2_E~0); 10961#L649-1 assume !(1 == ~T3_E~0); 10834#L654-1 assume !(1 == ~T4_E~0); 10835#L659-1 assume !(1 == ~T5_E~0); 10910#L664-1 assume !(1 == ~E_1~0); 10911#L669-1 assume !(1 == ~E_2~0); 11214#L674-1 assume !(1 == ~E_3~0); 11215#L679-1 assume !(1 == ~E_4~0); 11099#L684-1 assume !(1 == ~E_5~0); 11100#L689-1 assume { :end_inline_reset_delta_events } true; 11275#L890-3 [2018-11-18 16:15:52,998 INFO L796 eck$LassoCheckResult]: Loop: 11275#L890-3 assume true; 11276#L890-1 assume !false; 11355#L891 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 10917#L551 assume true; 11135#L471-1 assume !false; 11397#L472 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 11331#L429 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 10900#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 11327#L462 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 11328#L476 assume !(0 != eval_~tmp~0); 10840#L566 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 10841#L384-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 12155#L576-3 assume !(0 == ~M_E~0); 12154#L576-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12153#L581-3 assume !(0 == ~T2_E~0); 11203#L586-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11204#L591-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11425#L596-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12148#L601-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12146#L606-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12145#L611-3 assume !(0 == ~E_3~0); 11345#L616-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11346#L621-3 assume !(0 == ~E_5~0); 11271#L626-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 11272#L269-18 assume !(1 == ~m_pc~0); 11389#L269-20 is_master_triggered_~__retres1~0 := 0; 10995#L280-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10996#L281-6 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 11390#L710-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 11391#L710-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 11222#L288-18 assume !(1 == ~t1_pc~0); 11152#L288-20 is_transmit1_triggered_~__retres1~1 := 0; 11151#L299-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 12149#L300-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 11177#L718-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 11178#L718-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 11179#L307-18 assume !(1 == ~t2_pc~0); 11352#L307-20 is_transmit2_triggered_~__retres1~2 := 0; 11353#L318-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 11285#L319-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 11286#L726-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 11293#L726-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 11294#L326-18 assume !(1 == ~t3_pc~0); 12143#L326-20 is_transmit3_triggered_~__retres1~3 := 0; 11377#L337-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 11378#L338-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 12142#L734-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 12141#L734-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 12140#L345-18 assume 1 == ~t4_pc~0; 12138#L346-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 12137#L356-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 11025#L357-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 11004#L742-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 11005#L742-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 12135#L364-18 assume 1 == ~t5_pc~0; 11234#L365-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 11093#L375-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 11232#L376-6 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 11233#L750-18 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 11237#L750-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11137#L639-3 assume !(1 == ~M_E~0); 11138#L639-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12415#L644-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12413#L649-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12412#L654-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12411#L659-3 assume !(1 == ~T5_E~0); 12410#L664-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12409#L669-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12408#L674-3 assume !(1 == ~E_3~0); 12406#L679-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11078#L684-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11079#L689-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 11335#L429-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 10903#L461-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 11268#L462-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 11386#L909 assume !(0 == start_simulation_~tmp~3); 11360#L909-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 11337#L429-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 10908#L461-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 11269#L462-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 10999#L864 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 11000#L871 stop_simulation_#res := stop_simulation_~__retres2~0; 11106#L872 start_simulation_#t~ret15 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 11218#L922 assume !(0 != start_simulation_~tmp___0~1); 11275#L890-3 [2018-11-18 16:15:52,998 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:52,998 INFO L82 PathProgramCache]: Analyzing trace with hash -768239361, now seen corresponding path program 1 times [2018-11-18 16:15:52,998 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:15:52,998 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:15:52,999 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:52,999 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:15:52,999 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:53,003 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:15:53,023 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:15:53,023 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 16:15:53,023 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 16:15:53,023 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 16:15:53,023 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:53,023 INFO L82 PathProgramCache]: Analyzing trace with hash 1742767233, now seen corresponding path program 1 times [2018-11-18 16:15:53,023 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:15:53,024 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:15:53,024 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:53,024 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:15:53,024 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:53,028 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:15:53,055 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:15:53,055 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 16:15:53,055 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 16:15:53,056 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 16:15:53,056 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 16:15:53,056 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 16:15:53,056 INFO L87 Difference]: Start difference. First operand 1601 states and 2299 transitions. cyclomatic complexity: 700 Second operand 3 states. [2018-11-18 16:15:53,111 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:15:53,112 INFO L93 Difference]: Finished difference Result 3097 states and 4410 transitions. [2018-11-18 16:15:53,112 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 16:15:53,113 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3097 states and 4410 transitions. [2018-11-18 16:15:53,122 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3006 [2018-11-18 16:15:53,129 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3097 states to 3097 states and 4410 transitions. [2018-11-18 16:15:53,129 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3097 [2018-11-18 16:15:53,130 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3097 [2018-11-18 16:15:53,131 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3097 states and 4410 transitions. [2018-11-18 16:15:53,133 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 16:15:53,133 INFO L705 BuchiCegarLoop]: Abstraction has 3097 states and 4410 transitions. [2018-11-18 16:15:53,135 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3097 states and 4410 transitions. [2018-11-18 16:15:53,154 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3097 to 3077. [2018-11-18 16:15:53,154 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3077 states. [2018-11-18 16:15:53,158 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3077 states to 3077 states and 4386 transitions. [2018-11-18 16:15:53,158 INFO L728 BuchiCegarLoop]: Abstraction has 3077 states and 4386 transitions. [2018-11-18 16:15:53,159 INFO L608 BuchiCegarLoop]: Abstraction has 3077 states and 4386 transitions. [2018-11-18 16:15:53,159 INFO L442 BuchiCegarLoop]: ======== Iteration 10============ [2018-11-18 16:15:53,159 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3077 states and 4386 transitions. [2018-11-18 16:15:53,167 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2994 [2018-11-18 16:15:53,167 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 16:15:53,167 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 16:15:53,168 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:53,168 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:53,168 INFO L794 eck$LassoCheckResult]: Stem: 16002#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 15955#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 15709#L853 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 15710#L384 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15642#L391 assume 1 == ~m_i~0;~m_st~0 := 0; 15643#L391-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15660#L396-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15755#L401-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15756#L406-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15611#L411-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 15612#L416-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15618#L576 assume !(0 == ~M_E~0); 15598#L576-2 assume !(0 == ~T1_E~0); 15599#L581-1 assume !(0 == ~T2_E~0); 15894#L586-1 assume !(0 == ~T3_E~0); 15895#L591-1 assume !(0 == ~T4_E~0); 15787#L596-1 assume !(0 == ~T5_E~0); 15788#L601-1 assume !(0 == ~E_1~0); 15844#L606-1 assume !(0 == ~E_2~0); 15673#L611-1 assume !(0 == ~E_3~0); 15674#L616-1 assume !(0 == ~E_4~0); 15542#L621-1 assume !(0 == ~E_5~0); 15543#L626-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15751#L269 assume !(1 == ~m_pc~0); 15662#L269-2 is_master_triggered_~__retres1~0 := 0; 15741#L280 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15663#L281 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 15664#L710 assume !(0 != activate_threads_~tmp~1); 15665#L710-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15666#L288 assume !(1 == ~t1_pc~0); 15789#L288-2 is_transmit1_triggered_~__retres1~1 := 0; 15791#L299 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 15792#L300 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 15908#L718 assume !(0 != activate_threads_~tmp___0~0); 15917#L718-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15918#L307 assume !(1 == ~t2_pc~0); 15958#L307-2 is_transmit2_triggered_~__retres1~2 := 0; 15956#L318 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 15957#L319 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 16033#L726 assume !(0 != activate_threads_~tmp___1~0); 16034#L726-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 16035#L326 assume !(1 == ~t3_pc~0); 16054#L326-2 is_transmit3_triggered_~__retres1~3 := 0; 16055#L337 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 16067#L338 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 16100#L734 assume !(0 != activate_threads_~tmp___2~0); 16111#L734-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 15588#L345 assume !(1 == ~t4_pc~0); 15589#L345-2 is_transmit4_triggered_~__retres1~4 := 0; 15586#L356 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 15587#L357 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 15560#L742 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 15532#L742-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 15533#L364 assume !(1 == ~t5_pc~0); 15843#L364-2 is_transmit5_triggered_~__retres1~5 := 0; 15841#L375 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 15759#L376 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 15760#L750 assume !(0 != activate_threads_~tmp___4~0); 15800#L750-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15806#L639 assume !(1 == ~M_E~0); 15845#L639-2 assume !(1 == ~T1_E~0); 15667#L644-1 assume !(1 == ~T2_E~0); 15668#L649-1 assume !(1 == ~T3_E~0); 15539#L654-1 assume !(1 == ~T4_E~0); 15540#L659-1 assume !(1 == ~T5_E~0); 15616#L664-1 assume !(1 == ~E_1~0); 15617#L669-1 assume !(1 == ~E_2~0); 15919#L674-1 assume !(1 == ~E_3~0); 15920#L679-1 assume !(1 == ~E_4~0); 15807#L684-1 assume !(1 == ~E_5~0); 15808#L689-1 assume { :end_inline_reset_delta_events } true; 16072#L890-3 [2018-11-18 16:15:53,168 INFO L796 eck$LassoCheckResult]: Loop: 16072#L890-3 assume true; 17232#L890-1 assume !false; 17231#L891 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 17227#L551 assume true; 17226#L471-1 assume !false; 17225#L472 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 17223#L429 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 17218#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 17216#L462 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 17212#L476 assume !(0 != eval_~tmp~0); 17213#L566 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 18599#L384-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 18598#L576-3 assume !(0 == ~M_E~0); 18597#L576-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18596#L581-3 assume !(0 == ~T2_E~0); 18595#L586-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 18594#L591-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18592#L596-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 18590#L601-3 assume 0 == ~E_1~0;~E_1~0 := 1; 18589#L606-3 assume 0 == ~E_2~0;~E_2~0 := 1; 18588#L611-3 assume !(0 == ~E_3~0); 18587#L616-3 assume 0 == ~E_4~0;~E_4~0 := 1; 18572#L621-3 assume !(0 == ~E_5~0); 15976#L626-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15670#L269-18 assume !(1 == ~m_pc~0); 15672#L269-20 is_master_triggered_~__retres1~0 := 0; 15698#L280-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15704#L281-6 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 16079#L710-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 16080#L710-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15927#L288-18 assume 1 == ~t1_pc~0; 15859#L289-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 15860#L299-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 15862#L300-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 15863#L718-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 15885#L718-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15886#L307-18 assume !(1 == ~t2_pc~0); 16040#L307-20 is_transmit2_triggered_~__retres1~2 := 0; 15946#L318-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 15947#L319-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 15986#L726-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 15987#L726-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 15996#L326-18 assume !(1 == ~t3_pc~0); 16112#L326-20 is_transmit3_triggered_~__retres1~3 := 0; 16062#L337-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 16063#L338-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 16090#L734-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 16091#L734-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 15555#L345-18 assume 1 == ~t4_pc~0; 15556#L346-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 15561#L356-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 15577#L357-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 15713#L742-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 15714#L742-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 15818#L364-18 assume !(1 == ~t5_pc~0); 15819#L364-20 is_transmit5_triggered_~__retres1~5 := 0; 17500#L375-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 17498#L376-6 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 17496#L750-18 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 17494#L750-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17492#L639-3 assume !(1 == ~M_E~0); 17040#L639-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17489#L644-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17487#L649-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17485#L654-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17483#L659-3 assume !(1 == ~T5_E~0); 17481#L664-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17478#L669-3 assume 1 == ~E_2~0;~E_2~0 := 2; 17476#L674-3 assume !(1 == ~E_3~0); 17474#L679-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17472#L684-3 assume 1 == ~E_5~0;~E_5~0 := 2; 17470#L689-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 17466#L429-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 17461#L461-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 17458#L462-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 16176#L909 assume !(0 == start_simulation_~tmp~3); 16177#L909-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 17258#L429-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 17251#L461-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 17250#L462-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 17246#L864 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 17244#L871 stop_simulation_#res := stop_simulation_~__retres2~0; 17242#L872 start_simulation_#t~ret15 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 17240#L922 assume !(0 != start_simulation_~tmp___0~1); 16072#L890-3 [2018-11-18 16:15:53,168 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:53,168 INFO L82 PathProgramCache]: Analyzing trace with hash 372112350, now seen corresponding path program 1 times [2018-11-18 16:15:53,169 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:15:53,169 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:15:53,169 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:53,169 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:15:53,169 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:53,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:15:53,234 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:15:53,234 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 16:15:53,234 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 16:15:53,234 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 16:15:53,234 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:53,235 INFO L82 PathProgramCache]: Analyzing trace with hash 1582821761, now seen corresponding path program 1 times [2018-11-18 16:15:53,235 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:15:53,235 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:15:53,235 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:53,235 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:15:53,235 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:53,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:15:53,251 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:15:53,251 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 16:15:53,252 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 16:15:53,252 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 16:15:53,252 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 16:15:53,252 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 16:15:53,252 INFO L87 Difference]: Start difference. First operand 3077 states and 4386 transitions. cyclomatic complexity: 1313 Second operand 5 states. [2018-11-18 16:15:53,376 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:15:53,376 INFO L93 Difference]: Finished difference Result 7368 states and 10499 transitions. [2018-11-18 16:15:53,377 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 16:15:53,377 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7368 states and 10499 transitions. [2018-11-18 16:15:53,395 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7228 [2018-11-18 16:15:53,412 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7368 states to 7368 states and 10499 transitions. [2018-11-18 16:15:53,412 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7368 [2018-11-18 16:15:53,416 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7368 [2018-11-18 16:15:53,417 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7368 states and 10499 transitions. [2018-11-18 16:15:53,422 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 16:15:53,422 INFO L705 BuchiCegarLoop]: Abstraction has 7368 states and 10499 transitions. [2018-11-18 16:15:53,426 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7368 states and 10499 transitions. [2018-11-18 16:15:53,459 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7368 to 3224. [2018-11-18 16:15:53,460 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3224 states. [2018-11-18 16:15:53,466 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3224 states to 3224 states and 4533 transitions. [2018-11-18 16:15:53,466 INFO L728 BuchiCegarLoop]: Abstraction has 3224 states and 4533 transitions. [2018-11-18 16:15:53,466 INFO L608 BuchiCegarLoop]: Abstraction has 3224 states and 4533 transitions. [2018-11-18 16:15:53,466 INFO L442 BuchiCegarLoop]: ======== Iteration 11============ [2018-11-18 16:15:53,466 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3224 states and 4533 transitions. [2018-11-18 16:15:53,472 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3138 [2018-11-18 16:15:53,473 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 16:15:53,473 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 16:15:53,474 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:53,474 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:53,474 INFO L794 eck$LassoCheckResult]: Stem: 26471#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 26433#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 26173#L853 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 26174#L384 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26108#L391 assume 1 == ~m_i~0;~m_st~0 := 0; 26109#L391-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26127#L396-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26227#L401-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 26228#L406-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26076#L411-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26077#L416-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26083#L576 assume !(0 == ~M_E~0); 26063#L576-2 assume !(0 == ~T1_E~0); 26064#L581-1 assume !(0 == ~T2_E~0); 26369#L586-1 assume !(0 == ~T3_E~0); 26370#L591-1 assume !(0 == ~T4_E~0); 26264#L596-1 assume !(0 == ~T5_E~0); 26265#L601-1 assume !(0 == ~E_1~0); 26315#L606-1 assume !(0 == ~E_2~0); 26140#L611-1 assume !(0 == ~E_3~0); 26141#L616-1 assume !(0 == ~E_4~0); 26001#L621-1 assume !(0 == ~E_5~0); 26002#L626-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 26223#L269 assume !(1 == ~m_pc~0); 26129#L269-2 is_master_triggered_~__retres1~0 := 0; 26215#L280 is_master_triggered_#res := is_master_triggered_~__retres1~0; 26130#L281 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 26131#L710 assume !(0 != activate_threads_~tmp~1); 26132#L710-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 26133#L288 assume !(1 == ~t1_pc~0); 26266#L288-2 is_transmit1_triggered_~__retres1~1 := 0; 26268#L299 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 26269#L300 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 26384#L718 assume !(0 != activate_threads_~tmp___0~0); 26394#L718-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 26395#L307 assume !(1 == ~t2_pc~0); 26436#L307-2 is_transmit2_triggered_~__retres1~2 := 0; 26434#L318 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 26435#L319 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 26503#L726 assume !(0 != activate_threads_~tmp___1~0); 26504#L726-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 26505#L326 assume !(1 == ~t3_pc~0); 26528#L326-2 is_transmit3_triggered_~__retres1~3 := 0; 26529#L337 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 26542#L338 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 26576#L734 assume !(0 != activate_threads_~tmp___2~0); 26586#L734-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 26051#L345 assume !(1 == ~t4_pc~0); 26052#L345-2 is_transmit4_triggered_~__retres1~4 := 0; 26049#L356 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 26050#L357 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 26019#L742 assume !(0 != activate_threads_~tmp___3~0); 25990#L742-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 25991#L364 assume !(1 == ~t5_pc~0); 26314#L364-2 is_transmit5_triggered_~__retres1~5 := 0; 26312#L375 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 26236#L376 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 26237#L750 assume !(0 != activate_threads_~tmp___4~0); 26274#L750-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26280#L639 assume !(1 == ~M_E~0); 26316#L639-2 assume !(1 == ~T1_E~0); 26134#L644-1 assume !(1 == ~T2_E~0); 26135#L649-1 assume !(1 == ~T3_E~0); 25997#L654-1 assume !(1 == ~T4_E~0); 25998#L659-1 assume !(1 == ~T5_E~0); 26081#L664-1 assume !(1 == ~E_1~0); 26082#L669-1 assume !(1 == ~E_2~0); 26396#L674-1 assume !(1 == ~E_3~0); 26397#L679-1 assume !(1 == ~E_4~0); 26281#L684-1 assume !(1 == ~E_5~0); 26282#L689-1 assume { :end_inline_reset_delta_events } true; 26547#L890-3 [2018-11-18 16:15:53,474 INFO L796 eck$LassoCheckResult]: Loop: 26547#L890-3 assume true; 28579#L890-1 assume !false; 28576#L891 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 27972#L551 assume true; 28571#L471-1 assume !false; 28567#L472 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 28460#L429 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 28454#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 28452#L462 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 28404#L476 assume !(0 != eval_~tmp~0); 26004#L566 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 26005#L384-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 26067#L576-3 assume !(0 == ~M_E~0); 26068#L576-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 26072#L581-3 assume !(0 == ~T2_E~0); 26385#L586-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 26386#L591-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 26271#L596-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 26272#L601-3 assume 0 == ~E_1~0;~E_1~0 := 1; 26546#L606-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29194#L611-3 assume !(0 == ~E_3~0); 26510#L616-3 assume 0 == ~E_4~0;~E_4~0 := 1; 26010#L621-3 assume !(0 == ~E_5~0); 26011#L626-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 26137#L269-18 assume !(1 == ~m_pc~0); 26139#L269-20 is_master_triggered_~__retres1~0 := 0; 26164#L280-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 26169#L281-6 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 26551#L710-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 26552#L710-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 26404#L288-18 assume 1 == ~t1_pc~0; 26331#L289-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 26332#L299-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 26334#L300-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 26335#L718-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 26360#L718-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 26361#L307-18 assume !(1 == ~t2_pc~0); 26512#L307-20 is_transmit2_triggered_~__retres1~2 := 0; 26423#L318-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 26424#L319-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 26458#L726-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 26459#L726-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 26467#L326-18 assume !(1 == ~t3_pc~0); 26570#L326-20 is_transmit3_triggered_~__retres1~3 := 0; 26537#L337-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 26538#L338-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 26567#L734-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 26568#L734-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 26573#L345-18 assume !(1 == ~t4_pc~0); 26020#L345-20 is_transmit4_triggered_~__retres1~4 := 0; 26021#L356-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 26039#L357-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 26177#L742-18 assume !(0 != activate_threads_~tmp___3~0); 26178#L742-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 26182#L364-18 assume !(1 == ~t5_pc~0); 26292#L364-20 is_transmit5_triggered_~__retres1~5 := 0; 26305#L375-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 26306#L376-6 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 26412#L750-18 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 26417#L750-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26319#L639-3 assume !(1 == ~M_E~0); 26320#L639-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 29083#L644-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 29081#L649-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 26006#L654-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 26007#L659-3 assume !(1 == ~T5_E~0); 26084#L664-3 assume 1 == ~E_1~0;~E_1~0 := 2; 26085#L669-3 assume 1 == ~E_2~0;~E_2~0 := 2; 28908#L674-3 assume !(1 == ~E_3~0); 28907#L679-3 assume 1 == ~E_4~0;~E_4~0 := 2; 28906#L684-3 assume 1 == ~E_5~0;~E_5~0 := 2; 28905#L689-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 28902#L429-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 28898#L461-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 28897#L462-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 26671#L909 assume !(0 == start_simulation_~tmp~3); 26673#L909-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 28597#L429-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 28590#L461-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 28588#L462-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 28587#L864 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 28585#L871 stop_simulation_#res := stop_simulation_~__retres2~0; 28583#L872 start_simulation_#t~ret15 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 28582#L922 assume !(0 != start_simulation_~tmp___0~1); 26547#L890-3 [2018-11-18 16:15:53,475 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:53,475 INFO L82 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 1 times [2018-11-18 16:15:53,475 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:15:53,475 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:15:53,475 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:53,475 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:15:53,476 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:53,480 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 16:15:53,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 16:15:53,506 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:53,506 INFO L82 PathProgramCache]: Analyzing trace with hash 92764766, now seen corresponding path program 1 times [2018-11-18 16:15:53,506 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:15:53,506 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:15:53,507 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:53,507 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:15:53,507 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:53,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:15:53,527 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:15:53,528 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 16:15:53,528 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 16:15:53,528 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 16:15:53,528 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 16:15:53,528 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 16:15:53,528 INFO L87 Difference]: Start difference. First operand 3224 states and 4533 transitions. cyclomatic complexity: 1313 Second operand 3 states. [2018-11-18 16:15:53,560 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:15:53,560 INFO L93 Difference]: Finished difference Result 3727 states and 5240 transitions. [2018-11-18 16:15:53,561 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 16:15:53,561 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3727 states and 5240 transitions. [2018-11-18 16:15:53,569 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3586 [2018-11-18 16:15:53,579 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3727 states to 3727 states and 5240 transitions. [2018-11-18 16:15:53,579 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3727 [2018-11-18 16:15:53,581 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3727 [2018-11-18 16:15:53,581 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3727 states and 5240 transitions. [2018-11-18 16:15:53,584 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 16:15:53,584 INFO L705 BuchiCegarLoop]: Abstraction has 3727 states and 5240 transitions. [2018-11-18 16:15:53,586 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3727 states and 5240 transitions. [2018-11-18 16:15:53,609 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3727 to 3727. [2018-11-18 16:15:53,610 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3727 states. [2018-11-18 16:15:53,614 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3727 states to 3727 states and 5240 transitions. [2018-11-18 16:15:53,614 INFO L728 BuchiCegarLoop]: Abstraction has 3727 states and 5240 transitions. [2018-11-18 16:15:53,614 INFO L608 BuchiCegarLoop]: Abstraction has 3727 states and 5240 transitions. [2018-11-18 16:15:53,614 INFO L442 BuchiCegarLoop]: ======== Iteration 12============ [2018-11-18 16:15:53,614 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3727 states and 5240 transitions. [2018-11-18 16:15:53,621 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3586 [2018-11-18 16:15:53,621 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 16:15:53,621 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 16:15:53,622 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:53,622 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:53,622 INFO L794 eck$LassoCheckResult]: Stem: 33455#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 33405#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 33129#L853 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 33130#L384 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 33061#L391 assume 1 == ~m_i~0;~m_st~0 := 0; 33062#L391-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33078#L396-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33183#L401-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33184#L406-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 33029#L411-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 33030#L416-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33036#L576 assume !(0 == ~M_E~0); 33016#L576-2 assume !(0 == ~T1_E~0); 33017#L581-1 assume !(0 == ~T2_E~0); 33329#L586-1 assume !(0 == ~T3_E~0); 33330#L591-1 assume !(0 == ~T4_E~0); 33218#L596-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 33219#L601-1 assume !(0 == ~E_1~0); 33542#L606-1 assume !(0 == ~E_2~0); 33091#L611-1 assume !(0 == ~E_3~0); 33092#L616-1 assume !(0 == ~E_4~0); 33616#L621-1 assume !(0 == ~E_5~0); 33429#L626-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 33430#L269 assume !(1 == ~m_pc~0); 33614#L269-2 is_master_triggered_~__retres1~0 := 0; 33177#L280 is_master_triggered_#res := is_master_triggered_~__retres1~0; 33178#L281 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 33114#L710 assume !(0 != activate_threads_~tmp~1); 33115#L710-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 33221#L288 assume !(1 == ~t1_pc~0); 33222#L288-2 is_transmit1_triggered_~__retres1~1 := 0; 33225#L299 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 33226#L300 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 33347#L718 assume !(0 != activate_threads_~tmp___0~0); 33358#L718-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 33359#L307 assume !(1 == ~t2_pc~0); 33413#L307-2 is_transmit2_triggered_~__retres1~2 := 0; 33414#L318 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 33489#L319 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 33490#L726 assume !(0 != activate_threads_~tmp___1~0); 33491#L726-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 33492#L326 assume !(1 == ~t3_pc~0); 33521#L326-2 is_transmit3_triggered_~__retres1~3 := 0; 33522#L337 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 33609#L338 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 33608#L734 assume !(0 != activate_threads_~tmp___2~0); 33607#L734-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 33606#L345 assume !(1 == ~t4_pc~0); 33009#L345-2 is_transmit4_triggered_~__retres1~4 := 0; 33001#L356 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 33002#L357 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 32975#L742 assume !(0 != activate_threads_~tmp___3~0); 32976#L742-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 33273#L364 assume !(1 == ~t5_pc~0); 33274#L364-2 is_transmit5_triggered_~__retres1~5 := 0; 33275#L375 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 33591#L376 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 33590#L750 assume !(0 != activate_threads_~tmp___4~0); 33589#L750-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33588#L639 assume !(1 == ~M_E~0); 33587#L639-2 assume !(1 == ~T1_E~0); 33586#L644-1 assume !(1 == ~T2_E~0); 33585#L649-1 assume !(1 == ~T3_E~0); 32954#L654-1 assume !(1 == ~T4_E~0); 32955#L659-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 33034#L664-1 assume !(1 == ~E_1~0); 33035#L669-1 assume !(1 == ~E_2~0); 33360#L674-1 assume !(1 == ~E_3~0); 33361#L679-1 assume !(1 == ~E_4~0); 33239#L684-1 assume !(1 == ~E_5~0); 33240#L689-1 assume { :end_inline_reset_delta_events } true; 33544#L890-3 [2018-11-18 16:15:53,623 INFO L796 eck$LassoCheckResult]: Loop: 33544#L890-3 assume true; 35433#L890-1 assume !false; 35422#L891 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 35412#L551 assume true; 35401#L471-1 assume !false; 35389#L472 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 35385#L429 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 35378#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 35376#L462 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 35373#L476 assume !(0 != eval_~tmp~0); 35374#L566 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 35918#L384-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 35915#L576-3 assume !(0 == ~M_E~0); 35913#L576-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 35911#L581-3 assume !(0 == ~T2_E~0); 35909#L586-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 35907#L591-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 35905#L596-3 assume !(0 == ~T5_E~0); 33543#L601-3 assume 0 == ~E_1~0;~E_1~0 := 1; 33283#L606-3 assume 0 == ~E_2~0;~E_2~0 := 1; 33104#L611-3 assume !(0 == ~E_3~0); 33105#L616-3 assume 0 == ~E_4~0;~E_4~0 := 1; 32966#L621-3 assume !(0 == ~E_5~0); 32967#L626-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 33088#L269-18 assume !(1 == ~m_pc~0); 33090#L269-20 is_master_triggered_~__retres1~0 := 0; 33118#L280-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 33549#L281-6 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 33550#L710-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 33551#L710-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 33371#L288-18 assume 1 == ~t1_pc~0; 33293#L289-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 33294#L299-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 33296#L300-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 33297#L718-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 33320#L718-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 33321#L307-18 assume !(1 == ~t2_pc~0); 36656#L307-20 is_transmit2_triggered_~__retres1~2 := 0; 33397#L318-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 33398#L319-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 33438#L726-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 33439#L726-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 36653#L326-18 assume !(1 == ~t3_pc~0); 33582#L326-20 is_transmit3_triggered_~__retres1~3 := 0; 33529#L337-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 33530#L338-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 33565#L734-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 33566#L734-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 32970#L345-18 assume 1 == ~t4_pc~0; 32971#L346-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 36642#L356-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 36641#L357-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 36640#L742-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 33138#L742-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 33139#L364-18 assume !(1 == ~t5_pc~0); 33248#L364-20 is_transmit5_triggered_~__retres1~5 := 0; 36627#L375-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 36626#L376-6 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 35957#L750-18 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 35745#L750-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35744#L639-3 assume !(1 == ~M_E~0); 35743#L639-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 36413#L644-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36412#L649-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36411#L654-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 36406#L659-3 assume !(1 == ~T5_E~0); 36405#L664-3 assume 1 == ~E_1~0;~E_1~0 := 2; 36404#L669-3 assume 1 == ~E_2~0;~E_2~0 := 2; 36403#L674-3 assume !(1 == ~E_3~0); 36402#L679-3 assume 1 == ~E_4~0;~E_4~0 := 2; 36401#L684-3 assume 1 == ~E_5~0;~E_5~0 := 2; 33742#L689-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 33743#L429-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 35513#L461-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 35511#L462-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 35509#L909 assume !(0 == start_simulation_~tmp~3); 35506#L909-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 35504#L429-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 35497#L461-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 35495#L462-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 35494#L864 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 35450#L871 stop_simulation_#res := stop_simulation_~__retres2~0; 35444#L872 start_simulation_#t~ret15 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 35443#L922 assume !(0 != start_simulation_~tmp___0~1); 33544#L890-3 [2018-11-18 16:15:53,623 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:53,623 INFO L82 PathProgramCache]: Analyzing trace with hash 687638424, now seen corresponding path program 1 times [2018-11-18 16:15:53,623 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:15:53,623 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:15:53,624 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:53,624 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:15:53,624 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:53,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:15:53,654 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:15:53,654 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 16:15:53,655 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 16:15:53,655 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 16:15:53,655 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:53,655 INFO L82 PathProgramCache]: Analyzing trace with hash 366668035, now seen corresponding path program 1 times [2018-11-18 16:15:53,655 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:15:53,655 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:15:53,656 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:53,656 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:15:53,656 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:53,660 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:15:53,683 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:15:53,683 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 16:15:53,683 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 16:15:53,683 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 16:15:53,683 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 16:15:53,683 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 16:15:53,684 INFO L87 Difference]: Start difference. First operand 3727 states and 5240 transitions. cyclomatic complexity: 1517 Second operand 3 states. [2018-11-18 16:15:53,701 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:15:53,701 INFO L93 Difference]: Finished difference Result 3224 states and 4507 transitions. [2018-11-18 16:15:53,702 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 16:15:53,702 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3224 states and 4507 transitions. [2018-11-18 16:15:53,708 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3138 [2018-11-18 16:15:53,716 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3224 states to 3224 states and 4507 transitions. [2018-11-18 16:15:53,716 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3224 [2018-11-18 16:15:53,718 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3224 [2018-11-18 16:15:53,718 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3224 states and 4507 transitions. [2018-11-18 16:15:53,721 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 16:15:53,721 INFO L705 BuchiCegarLoop]: Abstraction has 3224 states and 4507 transitions. [2018-11-18 16:15:53,723 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3224 states and 4507 transitions. [2018-11-18 16:15:53,744 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3224 to 3224. [2018-11-18 16:15:53,744 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3224 states. [2018-11-18 16:15:53,748 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3224 states to 3224 states and 4507 transitions. [2018-11-18 16:15:53,748 INFO L728 BuchiCegarLoop]: Abstraction has 3224 states and 4507 transitions. [2018-11-18 16:15:53,748 INFO L608 BuchiCegarLoop]: Abstraction has 3224 states and 4507 transitions. [2018-11-18 16:15:53,748 INFO L442 BuchiCegarLoop]: ======== Iteration 13============ [2018-11-18 16:15:53,748 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3224 states and 4507 transitions. [2018-11-18 16:15:53,754 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3138 [2018-11-18 16:15:53,754 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 16:15:53,754 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 16:15:53,755 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:53,755 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:53,755 INFO L794 eck$LassoCheckResult]: Stem: 40370#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 40331#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 40083#L853 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 40084#L384 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 40019#L391 assume 1 == ~m_i~0;~m_st~0 := 0; 40020#L391-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 40037#L396-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 40128#L401-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 40129#L406-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 39987#L411-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 39988#L416-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 39994#L576 assume !(0 == ~M_E~0); 39974#L576-2 assume !(0 == ~T1_E~0); 39975#L581-1 assume !(0 == ~T2_E~0); 40264#L586-1 assume !(0 == ~T3_E~0); 40265#L591-1 assume !(0 == ~T4_E~0); 40163#L596-1 assume !(0 == ~T5_E~0); 40164#L601-1 assume !(0 == ~E_1~0); 40213#L606-1 assume !(0 == ~E_2~0); 40050#L611-1 assume !(0 == ~E_3~0); 40051#L616-1 assume !(0 == ~E_4~0); 39917#L621-1 assume !(0 == ~E_5~0); 39918#L626-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 40124#L269 assume !(1 == ~m_pc~0); 40039#L269-2 is_master_triggered_~__retres1~0 := 0; 40116#L280 is_master_triggered_#res := is_master_triggered_~__retres1~0; 40040#L281 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 40041#L710 assume !(0 != activate_threads_~tmp~1); 40042#L710-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 40043#L288 assume !(1 == ~t1_pc~0); 40165#L288-2 is_transmit1_triggered_~__retres1~1 := 0; 40167#L299 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 40168#L300 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 40278#L718 assume !(0 != activate_threads_~tmp___0~0); 40287#L718-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 40288#L307 assume !(1 == ~t2_pc~0); 40334#L307-2 is_transmit2_triggered_~__retres1~2 := 0; 40332#L318 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 40333#L319 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 40402#L726 assume !(0 != activate_threads_~tmp___1~0); 40403#L726-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 40404#L326 assume !(1 == ~t3_pc~0); 40424#L326-2 is_transmit3_triggered_~__retres1~3 := 0; 40425#L337 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 40439#L338 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 40471#L734 assume !(0 != activate_threads_~tmp___2~0); 40478#L734-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 39963#L345 assume !(1 == ~t4_pc~0); 39964#L345-2 is_transmit4_triggered_~__retres1~4 := 0; 39961#L356 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 39962#L357 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 39935#L742 assume !(0 != activate_threads_~tmp___3~0); 39907#L742-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 39908#L364 assume !(1 == ~t5_pc~0); 40212#L364-2 is_transmit5_triggered_~__retres1~5 := 0; 40210#L375 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 40135#L376 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 40136#L750 assume !(0 != activate_threads_~tmp___4~0); 40173#L750-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40179#L639 assume !(1 == ~M_E~0); 40214#L639-2 assume !(1 == ~T1_E~0); 40044#L644-1 assume !(1 == ~T2_E~0); 40045#L649-1 assume !(1 == ~T3_E~0); 39914#L654-1 assume !(1 == ~T4_E~0); 39915#L659-1 assume !(1 == ~T5_E~0); 39992#L664-1 assume !(1 == ~E_1~0); 39993#L669-1 assume !(1 == ~E_2~0); 40289#L674-1 assume !(1 == ~E_3~0); 40290#L679-1 assume !(1 == ~E_4~0); 40180#L684-1 assume !(1 == ~E_5~0); 40181#L689-1 assume { :end_inline_reset_delta_events } true; 40444#L890-3 [2018-11-18 16:15:53,756 INFO L796 eck$LassoCheckResult]: Loop: 40444#L890-3 assume true; 41590#L890-1 assume !false; 41589#L891 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 41585#L551 assume true; 41584#L471-1 assume !false; 41583#L472 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 41581#L429 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 41576#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 41575#L462 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 41572#L476 assume !(0 != eval_~tmp~0); 41573#L566 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 43127#L384-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 43126#L576-3 assume !(0 == ~M_E~0); 43125#L576-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 43124#L581-3 assume !(0 == ~T2_E~0); 43123#L586-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 43122#L591-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 43121#L596-3 assume !(0 == ~T5_E~0); 43120#L601-3 assume 0 == ~E_1~0;~E_1~0 := 1; 43119#L606-3 assume 0 == ~E_2~0;~E_2~0 := 1; 43118#L611-3 assume !(0 == ~E_3~0); 43117#L616-3 assume 0 == ~E_4~0;~E_4~0 := 1; 43116#L621-3 assume !(0 == ~E_5~0); 43115#L626-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 43113#L269-18 assume !(1 == ~m_pc~0); 43110#L269-20 is_master_triggered_~__retres1~0 := 0; 43107#L280-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 43105#L281-6 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 43103#L710-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 43101#L710-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 40300#L288-18 assume 1 == ~t1_pc~0; 40229#L289-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 40230#L299-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 40232#L300-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 40233#L718-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 40255#L718-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 40256#L307-18 assume !(1 == ~t2_pc~0); 40409#L307-20 is_transmit2_triggered_~__retres1~2 := 0; 40323#L318-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 40324#L319-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 40356#L726-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 40357#L726-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 40365#L326-18 assume !(1 == ~t3_pc~0); 40467#L326-20 is_transmit3_triggered_~__retres1~3 := 0; 40434#L337-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 40435#L338-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 40463#L734-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 42980#L734-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 42979#L345-18 assume !(1 == ~t4_pc~0); 42977#L345-20 is_transmit4_triggered_~__retres1~4 := 0; 42975#L356-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 42973#L357-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 42972#L742-18 assume !(0 != activate_threads_~tmp___3~0); 42970#L742-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 42969#L364-18 assume !(1 == ~t5_pc~0); 42968#L364-20 is_transmit5_triggered_~__retres1~5 := 0; 42967#L375-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 42966#L376-6 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 42965#L750-18 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 42964#L750-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40649#L639-3 assume !(1 == ~M_E~0); 40646#L639-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 40644#L644-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 40642#L649-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 40639#L654-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 40637#L659-3 assume !(1 == ~T5_E~0); 40635#L664-3 assume 1 == ~E_1~0;~E_1~0 := 2; 40633#L669-3 assume 1 == ~E_2~0;~E_2~0 := 2; 40631#L674-3 assume !(1 == ~E_3~0); 40629#L679-3 assume 1 == ~E_4~0;~E_4~0 := 2; 40628#L684-3 assume 1 == ~E_5~0;~E_5~0 := 2; 40627#L689-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 40624#L429-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 40606#L461-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 40601#L462-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 40445#L909 assume !(0 == start_simulation_~tmp~3); 40446#L909-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 41616#L429-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 41609#L461-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 41608#L462-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 41604#L864 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 41602#L871 stop_simulation_#res := stop_simulation_~__retres2~0; 41600#L872 start_simulation_#t~ret15 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 41598#L922 assume !(0 != start_simulation_~tmp___0~1); 40444#L890-3 [2018-11-18 16:15:53,756 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:53,756 INFO L82 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 2 times [2018-11-18 16:15:53,756 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:15:53,756 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:15:53,757 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:53,757 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:15:53,757 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:53,760 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 16:15:53,765 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 16:15:53,776 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:53,776 INFO L82 PathProgramCache]: Analyzing trace with hash -1123388960, now seen corresponding path program 1 times [2018-11-18 16:15:53,776 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:15:53,776 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:15:53,776 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:53,777 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:15:53,777 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:53,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:15:53,814 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:15:53,814 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 16:15:53,815 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 16:15:53,815 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 16:15:53,815 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 16:15:53,815 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 16:15:53,815 INFO L87 Difference]: Start difference. First operand 3224 states and 4507 transitions. cyclomatic complexity: 1287 Second operand 5 states. [2018-11-18 16:15:53,882 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:15:53,883 INFO L93 Difference]: Finished difference Result 5770 states and 7951 transitions. [2018-11-18 16:15:53,884 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-18 16:15:53,884 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5770 states and 7951 transitions. [2018-11-18 16:15:53,896 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5676 [2018-11-18 16:15:53,912 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5770 states to 5770 states and 7951 transitions. [2018-11-18 16:15:53,912 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5770 [2018-11-18 16:15:53,916 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5770 [2018-11-18 16:15:53,916 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5770 states and 7951 transitions. [2018-11-18 16:15:53,920 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 16:15:53,920 INFO L705 BuchiCegarLoop]: Abstraction has 5770 states and 7951 transitions. [2018-11-18 16:15:53,924 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5770 states and 7951 transitions. [2018-11-18 16:15:53,959 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5770 to 3248. [2018-11-18 16:15:53,959 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3248 states. [2018-11-18 16:15:53,964 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3248 states to 3248 states and 4531 transitions. [2018-11-18 16:15:53,964 INFO L728 BuchiCegarLoop]: Abstraction has 3248 states and 4531 transitions. [2018-11-18 16:15:53,964 INFO L608 BuchiCegarLoop]: Abstraction has 3248 states and 4531 transitions. [2018-11-18 16:15:53,964 INFO L442 BuchiCegarLoop]: ======== Iteration 14============ [2018-11-18 16:15:53,965 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3248 states and 4531 transitions. [2018-11-18 16:15:53,972 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3162 [2018-11-18 16:15:53,972 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 16:15:53,972 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 16:15:53,973 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:53,973 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:53,973 INFO L794 eck$LassoCheckResult]: Stem: 49399#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 49355#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 49097#L853 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 49098#L384 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 49030#L391 assume 1 == ~m_i~0;~m_st~0 := 0; 49031#L391-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 49046#L396-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 49144#L401-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 49145#L406-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 48998#L411-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 48999#L416-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49005#L576 assume !(0 == ~M_E~0); 48985#L576-2 assume !(0 == ~T1_E~0); 48986#L581-1 assume !(0 == ~T2_E~0); 49279#L586-1 assume !(0 == ~T3_E~0); 49280#L591-1 assume !(0 == ~T4_E~0); 49180#L596-1 assume !(0 == ~T5_E~0); 49181#L601-1 assume !(0 == ~E_1~0); 49228#L606-1 assume !(0 == ~E_2~0); 49059#L611-1 assume !(0 == ~E_3~0); 49060#L616-1 assume !(0 == ~E_4~0); 48927#L621-1 assume !(0 == ~E_5~0); 48928#L626-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 49140#L269 assume !(1 == ~m_pc~0); 49048#L269-2 is_master_triggered_~__retres1~0 := 0; 49131#L280 is_master_triggered_#res := is_master_triggered_~__retres1~0; 49049#L281 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 49050#L710 assume !(0 != activate_threads_~tmp~1); 49051#L710-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 49052#L288 assume !(1 == ~t1_pc~0); 49182#L288-2 is_transmit1_triggered_~__retres1~1 := 0; 49184#L299 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 49185#L300 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 49295#L718 assume !(0 != activate_threads_~tmp___0~0); 49304#L718-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 49305#L307 assume !(1 == ~t2_pc~0); 49358#L307-2 is_transmit2_triggered_~__retres1~2 := 0; 49356#L318 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 49357#L319 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 49433#L726 assume !(0 != activate_threads_~tmp___1~0); 49434#L726-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 49435#L326 assume !(1 == ~t3_pc~0); 49459#L326-2 is_transmit3_triggered_~__retres1~3 := 0; 49460#L337 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 49473#L338 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 49514#L734 assume !(0 != activate_threads_~tmp___2~0); 49524#L734-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 48974#L345 assume !(1 == ~t4_pc~0); 48975#L345-2 is_transmit4_triggered_~__retres1~4 := 0; 48972#L356 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 48973#L357 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 48945#L742 assume !(0 != activate_threads_~tmp___3~0); 48917#L742-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 48918#L364 assume !(1 == ~t5_pc~0); 49227#L364-2 is_transmit5_triggered_~__retres1~5 := 0; 49225#L375 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 49152#L376 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 49153#L750 assume !(0 != activate_threads_~tmp___4~0); 49190#L750-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49196#L639 assume !(1 == ~M_E~0); 49229#L639-2 assume !(1 == ~T1_E~0); 49053#L644-1 assume !(1 == ~T2_E~0); 49054#L649-1 assume !(1 == ~T3_E~0); 48924#L654-1 assume !(1 == ~T4_E~0); 48925#L659-1 assume !(1 == ~T5_E~0); 49003#L664-1 assume !(1 == ~E_1~0); 49004#L669-1 assume !(1 == ~E_2~0); 49306#L674-1 assume !(1 == ~E_3~0); 49307#L679-1 assume !(1 == ~E_4~0); 49197#L684-1 assume !(1 == ~E_5~0); 49198#L689-1 assume { :end_inline_reset_delta_events } true; 49377#L890-3 [2018-11-18 16:15:53,974 INFO L796 eck$LassoCheckResult]: Loop: 49377#L890-3 assume true; 49378#L890-1 assume !false; 52119#L891 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 49010#L551 assume true; 49495#L471-1 assume !false; 49369#L472 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 49370#L429 assume !(0 == ~m_st~0); 48991#L433 assume !(0 == ~t1_st~0); 48992#L437 assume !(0 == ~t2_st~0); 49223#L441 assume !(0 == ~t3_st~0); 49132#L445 assume !(0 == ~t4_st~0); 49133#L449 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 49494#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 50841#L462 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 50842#L476 assume !(0 != eval_~tmp~0); 48930#L566 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 48931#L384-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 48989#L576-3 assume !(0 == ~M_E~0); 48990#L576-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 48994#L581-3 assume !(0 == ~T2_E~0); 51607#L586-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 51606#L591-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 49187#L596-3 assume !(0 == ~T5_E~0); 49188#L601-3 assume 0 == ~E_1~0;~E_1~0 := 1; 49234#L606-3 assume 0 == ~E_2~0;~E_2~0 := 1; 49235#L611-3 assume !(0 == ~E_3~0); 49439#L616-3 assume 0 == ~E_4~0;~E_4~0 := 1; 49440#L621-3 assume !(0 == ~E_5~0); 51605#L626-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 51604#L269-18 assume !(1 == ~m_pc~0); 49484#L269-20 is_master_triggered_~__retres1~0 := 0; 49091#L280-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 49092#L281-6 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 49488#L710-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 49489#L710-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 49314#L288-18 assume !(1 == ~t1_pc~0); 49315#L288-20 is_transmit1_triggered_~__retres1~1 := 0; 49321#L299-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 49322#L300-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 49269#L718-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 49270#L718-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 49271#L307-18 assume !(1 == ~t2_pc~0); 49444#L307-20 is_transmit2_triggered_~__retres1~2 := 0; 49445#L318-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 49385#L319-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 49386#L726-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 49394#L726-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 49395#L326-18 assume !(1 == ~t3_pc~0); 49525#L326-20 is_transmit3_triggered_~__retres1~3 := 0; 49526#L337-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 49502#L338-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 49503#L734-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 49510#L734-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 49511#L345-18 assume !(1 == ~t4_pc~0); 48946#L345-20 is_transmit4_triggered_~__retres1~4 := 0; 48947#L356-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 51064#L357-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 51065#L742-18 assume !(0 != activate_threads_~tmp___3~0); 49107#L742-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 49108#L364-18 assume !(1 == ~t5_pc~0); 49205#L364-20 is_transmit5_triggered_~__retres1~5 := 0; 49218#L375-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 49219#L376-6 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 49335#L750-18 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 49336#L750-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49232#L639-3 assume !(1 == ~M_E~0); 49233#L639-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 49064#L644-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 49065#L649-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 48932#L654-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 48933#L659-3 assume !(1 == ~T5_E~0); 49006#L664-3 assume 1 == ~E_1~0;~E_1~0 := 2; 49007#L669-3 assume 1 == ~E_2~0;~E_2~0 := 2; 49308#L674-3 assume !(1 == ~E_3~0); 49309#L679-3 assume 1 == ~E_4~0;~E_4~0 := 2; 49178#L684-3 assume 1 == ~E_5~0;~E_5~0 := 2; 49179#L689-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 49478#L429-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 52120#L461-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 49428#L462-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 49429#L909 assume !(0 == start_simulation_~tmp~3); 49481#L909-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 49432#L429-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 49001#L461-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 49374#L462-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 49095#L864 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 49096#L871 stop_simulation_#res := stop_simulation_~__retres2~0; 49203#L872 start_simulation_#t~ret15 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 49310#L922 assume !(0 != start_simulation_~tmp___0~1); 49377#L890-3 [2018-11-18 16:15:53,974 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:53,974 INFO L82 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 3 times [2018-11-18 16:15:53,974 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:15:53,974 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:15:53,975 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:53,975 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:15:53,975 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:53,979 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 16:15:53,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 16:15:53,993 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:53,993 INFO L82 PathProgramCache]: Analyzing trace with hash 1492886640, now seen corresponding path program 1 times [2018-11-18 16:15:53,993 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:15:53,994 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:15:53,994 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:53,994 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:15:53,994 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:53,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:15:54,064 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:15:54,064 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 16:15:54,064 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 16:15:54,064 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 16:15:54,064 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 16:15:54,065 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 16:15:54,065 INFO L87 Difference]: Start difference. First operand 3248 states and 4531 transitions. cyclomatic complexity: 1287 Second operand 5 states. [2018-11-18 16:15:54,190 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:15:54,190 INFO L93 Difference]: Finished difference Result 7372 states and 10360 transitions. [2018-11-18 16:15:54,192 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 16:15:54,192 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7372 states and 10360 transitions. [2018-11-18 16:15:54,208 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 7270 [2018-11-18 16:15:54,221 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7372 states to 7372 states and 10360 transitions. [2018-11-18 16:15:54,221 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7372 [2018-11-18 16:15:54,225 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7372 [2018-11-18 16:15:54,225 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7372 states and 10360 transitions. [2018-11-18 16:15:54,230 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 16:15:54,230 INFO L705 BuchiCegarLoop]: Abstraction has 7372 states and 10360 transitions. [2018-11-18 16:15:54,234 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7372 states and 10360 transitions. [2018-11-18 16:15:54,269 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7372 to 3326. [2018-11-18 16:15:54,269 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3326 states. [2018-11-18 16:15:54,274 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3326 states to 3326 states and 4586 transitions. [2018-11-18 16:15:54,274 INFO L728 BuchiCegarLoop]: Abstraction has 3326 states and 4586 transitions. [2018-11-18 16:15:54,274 INFO L608 BuchiCegarLoop]: Abstraction has 3326 states and 4586 transitions. [2018-11-18 16:15:54,274 INFO L442 BuchiCegarLoop]: ======== Iteration 15============ [2018-11-18 16:15:54,274 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3326 states and 4586 transitions. [2018-11-18 16:15:54,281 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3240 [2018-11-18 16:15:54,281 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 16:15:54,281 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 16:15:54,282 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:54,282 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:54,282 INFO L794 eck$LassoCheckResult]: Stem: 60038#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 59999#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 59738#L853 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 59739#L384 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 59665#L391 assume 1 == ~m_i~0;~m_st~0 := 0; 59666#L391-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 59681#L396-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 59792#L401-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 59793#L406-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 59633#L411-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 59634#L416-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 59640#L576 assume !(0 == ~M_E~0); 59620#L576-2 assume !(0 == ~T1_E~0); 59621#L581-1 assume !(0 == ~T2_E~0); 59938#L586-1 assume !(0 == ~T3_E~0); 59939#L591-1 assume !(0 == ~T4_E~0); 59827#L596-1 assume !(0 == ~T5_E~0); 59828#L601-1 assume !(0 == ~E_1~0); 59884#L606-1 assume !(0 == ~E_2~0); 59694#L611-1 assume !(0 == ~E_3~0); 59695#L616-1 assume !(0 == ~E_4~0); 59561#L621-1 assume !(0 == ~E_5~0); 59562#L626-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 59787#L269 assume !(1 == ~m_pc~0); 59683#L269-2 is_master_triggered_~__retres1~0 := 0; 59776#L280 is_master_triggered_#res := is_master_triggered_~__retres1~0; 59684#L281 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 59685#L710 assume !(0 != activate_threads_~tmp~1); 59686#L710-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 59687#L288 assume !(1 == ~t1_pc~0); 59829#L288-2 is_transmit1_triggered_~__retres1~1 := 0; 59831#L299 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 59832#L300 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 59953#L718 assume !(0 != activate_threads_~tmp___0~0); 59961#L718-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 59962#L307 assume !(1 == ~t2_pc~0); 60002#L307-2 is_transmit2_triggered_~__retres1~2 := 0; 60000#L318 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 60001#L319 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 60067#L726 assume !(0 != activate_threads_~tmp___1~0); 60068#L726-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 60069#L326 assume !(1 == ~t3_pc~0); 60089#L326-2 is_transmit3_triggered_~__retres1~3 := 0; 60090#L337 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 60102#L338 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 60136#L734 assume !(0 != activate_threads_~tmp___2~0); 60144#L734-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 59608#L345 assume !(1 == ~t4_pc~0); 59609#L345-2 is_transmit4_triggered_~__retres1~4 := 0; 59606#L356 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 59607#L357 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 59579#L742 assume !(0 != activate_threads_~tmp___3~0); 59550#L742-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 59551#L364 assume !(1 == ~t5_pc~0); 59882#L364-2 is_transmit5_triggered_~__retres1~5 := 0; 59880#L375 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 59799#L376 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 59800#L750 assume !(0 != activate_threads_~tmp___4~0); 59837#L750-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 59844#L639 assume !(1 == ~M_E~0); 59885#L639-2 assume !(1 == ~T1_E~0); 59688#L644-1 assume !(1 == ~T2_E~0); 59689#L649-1 assume !(1 == ~T3_E~0); 59557#L654-1 assume !(1 == ~T4_E~0); 59558#L659-1 assume !(1 == ~T5_E~0); 59638#L664-1 assume !(1 == ~E_1~0); 59639#L669-1 assume !(1 == ~E_2~0); 59963#L674-1 assume !(1 == ~E_3~0); 59964#L679-1 assume !(1 == ~E_4~0); 59845#L684-1 assume !(1 == ~E_5~0); 59846#L689-1 assume { :end_inline_reset_delta_events } true; 60107#L890-3 [2018-11-18 16:15:54,282 INFO L796 eck$LassoCheckResult]: Loop: 60107#L890-3 assume true; 62263#L890-1 assume !false; 62261#L891 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 62259#L551 assume true; 62258#L471-1 assume !false; 62257#L472 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 60061#L429 assume !(0 == ~m_st~0); 59626#L433 assume !(0 == ~t1_st~0); 59627#L437 assume !(0 == ~t2_st~0); 59878#L441 assume !(0 == ~t3_st~0); 59777#L445 assume !(0 == ~t4_st~0); 59778#L449 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 60122#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 62628#L462 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 62626#L476 assume !(0 != eval_~tmp~0); 62624#L566 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 62622#L384-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 62621#L576-3 assume !(0 == ~M_E~0); 62620#L576-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 62618#L581-3 assume !(0 == ~T2_E~0); 62616#L586-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 62612#L591-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 62609#L596-3 assume !(0 == ~T5_E~0); 62606#L601-3 assume 0 == ~E_1~0;~E_1~0 := 1; 62603#L606-3 assume 0 == ~E_2~0;~E_2~0 := 1; 62600#L611-3 assume !(0 == ~E_3~0); 62597#L616-3 assume 0 == ~E_4~0;~E_4~0 := 1; 62594#L621-3 assume !(0 == ~E_5~0); 62591#L626-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 62590#L269-18 assume !(1 == ~m_pc~0); 62588#L269-20 is_master_triggered_~__retres1~0 := 0; 62587#L280-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 62586#L281-6 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 62585#L710-18 assume !(0 != activate_threads_~tmp~1); 62584#L710-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 62583#L288-18 assume 1 == ~t1_pc~0; 62581#L289-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 62580#L299-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 62579#L300-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 62578#L718-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 62577#L718-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 62576#L307-18 assume !(1 == ~t2_pc~0); 62575#L307-20 is_transmit2_triggered_~__retres1~2 := 0; 62574#L318-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 62573#L319-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 62572#L726-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 62571#L726-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 62570#L326-18 assume !(1 == ~t3_pc~0); 62568#L326-20 is_transmit3_triggered_~__retres1~3 := 0; 62567#L337-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 62566#L338-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 62565#L734-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 62564#L734-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 62563#L345-18 assume 1 == ~t4_pc~0; 62561#L346-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 62559#L356-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 62557#L357-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 62555#L742-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 62554#L742-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 62553#L364-18 assume !(1 == ~t5_pc~0); 62552#L364-20 is_transmit5_triggered_~__retres1~5 := 0; 62551#L375-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 62550#L376-6 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 62549#L750-18 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 62548#L750-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 62547#L639-3 assume !(1 == ~M_E~0); 62544#L639-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 62543#L644-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 62417#L649-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 62416#L654-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 62415#L659-3 assume !(1 == ~T5_E~0); 62414#L664-3 assume 1 == ~E_1~0;~E_1~0 := 2; 62413#L669-3 assume 1 == ~E_2~0;~E_2~0 := 2; 62412#L674-3 assume !(1 == ~E_3~0); 62411#L679-3 assume 1 == ~E_4~0;~E_4~0 := 2; 62410#L684-3 assume 1 == ~E_5~0;~E_5~0 := 2; 62408#L689-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 62381#L429-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 62376#L461-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 62215#L462-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 62216#L909 assume !(0 == start_simulation_~tmp~3); 62325#L909-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 62323#L429-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 62314#L461-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 62310#L462-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 62307#L864 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 62306#L871 stop_simulation_#res := stop_simulation_~__retres2~0; 62267#L872 start_simulation_#t~ret15 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 62266#L922 assume !(0 != start_simulation_~tmp___0~1); 60107#L890-3 [2018-11-18 16:15:54,282 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:54,282 INFO L82 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 4 times [2018-11-18 16:15:54,283 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:15:54,283 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:15:54,283 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:54,283 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:15:54,283 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:54,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 16:15:54,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 16:15:54,302 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:54,302 INFO L82 PathProgramCache]: Analyzing trace with hash -1374150158, now seen corresponding path program 1 times [2018-11-18 16:15:54,302 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:15:54,302 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:15:54,303 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:54,303 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:15:54,303 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:54,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:15:54,325 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:15:54,325 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 16:15:54,325 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 16:15:54,326 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 16:15:54,326 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 16:15:54,326 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 16:15:54,326 INFO L87 Difference]: Start difference. First operand 3326 states and 4586 transitions. cyclomatic complexity: 1264 Second operand 3 states. [2018-11-18 16:15:54,374 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:15:54,374 INFO L93 Difference]: Finished difference Result 5818 states and 7930 transitions. [2018-11-18 16:15:54,375 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 16:15:54,375 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5818 states and 7930 transitions. [2018-11-18 16:15:54,387 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5724 [2018-11-18 16:15:54,395 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5818 states to 5818 states and 7930 transitions. [2018-11-18 16:15:54,396 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5818 [2018-11-18 16:15:54,398 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5818 [2018-11-18 16:15:54,398 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5818 states and 7930 transitions. [2018-11-18 16:15:54,402 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 16:15:54,402 INFO L705 BuchiCegarLoop]: Abstraction has 5818 states and 7930 transitions. [2018-11-18 16:15:54,405 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5818 states and 7930 transitions. [2018-11-18 16:15:54,440 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5818 to 5650. [2018-11-18 16:15:54,440 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5650 states. [2018-11-18 16:15:54,447 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5650 states to 5650 states and 7714 transitions. [2018-11-18 16:15:54,447 INFO L728 BuchiCegarLoop]: Abstraction has 5650 states and 7714 transitions. [2018-11-18 16:15:54,447 INFO L608 BuchiCegarLoop]: Abstraction has 5650 states and 7714 transitions. [2018-11-18 16:15:54,447 INFO L442 BuchiCegarLoop]: ======== Iteration 16============ [2018-11-18 16:15:54,447 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5650 states and 7714 transitions. [2018-11-18 16:15:54,457 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5556 [2018-11-18 16:15:54,457 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 16:15:54,457 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 16:15:54,458 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:54,459 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:54,459 INFO L794 eck$LassoCheckResult]: Stem: 69179#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 69137#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 68880#L853 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 68881#L384 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 68819#L391 assume 1 == ~m_i~0;~m_st~0 := 0; 68820#L391-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 68831#L396-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 68933#L401-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 68934#L406-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 68782#L411-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 68783#L416-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 68789#L576 assume !(0 == ~M_E~0); 68771#L576-2 assume !(0 == ~T1_E~0); 68772#L581-1 assume !(0 == ~T2_E~0); 69078#L586-1 assume !(0 == ~T3_E~0); 69079#L591-1 assume !(0 == ~T4_E~0); 68966#L596-1 assume !(0 == ~T5_E~0); 68967#L601-1 assume !(0 == ~E_1~0); 69019#L606-1 assume !(0 == ~E_2~0); 68845#L611-1 assume !(0 == ~E_3~0); 68846#L616-1 assume !(0 == ~E_4~0); 68711#L621-1 assume !(0 == ~E_5~0); 68712#L626-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 68929#L269 assume !(1 == ~m_pc~0); 68833#L269-2 is_master_triggered_~__retres1~0 := 0; 68916#L280 is_master_triggered_#res := is_master_triggered_~__retres1~0; 68834#L281 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 68835#L710 assume !(0 != activate_threads_~tmp~1); 68836#L710-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 68837#L288 assume !(1 == ~t1_pc~0); 68968#L288-2 is_transmit1_triggered_~__retres1~1 := 0; 68971#L299 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 68972#L300 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 69091#L718 assume !(0 != activate_threads_~tmp___0~0); 69096#L718-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 69097#L307 assume !(1 == ~t2_pc~0); 69140#L307-2 is_transmit2_triggered_~__retres1~2 := 0; 69138#L318 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 69139#L319 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 69211#L726 assume !(0 != activate_threads_~tmp___1~0); 69212#L726-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 69213#L326 assume !(1 == ~t3_pc~0); 69241#L326-2 is_transmit3_triggered_~__retres1~3 := 0; 69242#L337 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 69254#L338 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 69297#L734 assume !(0 != activate_threads_~tmp___2~0); 69306#L734-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 68757#L345 assume !(1 == ~t4_pc~0); 68758#L345-2 is_transmit4_triggered_~__retres1~4 := 0; 68762#L356 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 68935#L357 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 68729#L742 assume !(0 != activate_threads_~tmp___3~0); 68703#L742-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 68704#L364 assume !(1 == ~t5_pc~0); 69018#L364-2 is_transmit5_triggered_~__retres1~5 := 0; 69017#L375 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 68938#L376 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 68939#L750 assume !(0 != activate_threads_~tmp___4~0); 68976#L750-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 68982#L639 assume !(1 == ~M_E~0); 69020#L639-2 assume !(1 == ~T1_E~0); 68840#L644-1 assume !(1 == ~T2_E~0); 68841#L649-1 assume !(1 == ~T3_E~0); 68707#L654-1 assume !(1 == ~T4_E~0); 68708#L659-1 assume !(1 == ~T5_E~0); 68787#L664-1 assume !(1 == ~E_1~0); 68788#L669-1 assume !(1 == ~E_2~0); 69098#L674-1 assume !(1 == ~E_3~0); 69099#L679-1 assume !(1 == ~E_4~0); 68985#L684-1 assume !(1 == ~E_5~0); 68986#L689-1 assume { :end_inline_reset_delta_events } true; 69260#L890-3 [2018-11-18 16:15:54,459 INFO L796 eck$LassoCheckResult]: Loop: 69260#L890-3 assume true; 69770#L890-1 assume !false; 69771#L891 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 71619#L551 assume true; 71616#L471-1 assume !false; 71614#L472 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 71612#L429 assume !(0 == ~m_st~0); 69735#L433 assume !(0 == ~t1_st~0); 69734#L437 assume !(0 == ~t2_st~0); 69733#L441 assume !(0 == ~t3_st~0); 69732#L445 assume !(0 == ~t4_st~0); 69730#L449 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 69729#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 69728#L462 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 69726#L476 assume !(0 != eval_~tmp~0); 69725#L566 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 69724#L384-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 69723#L576-3 assume !(0 == ~M_E~0); 69722#L576-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 69721#L581-3 assume !(0 == ~T2_E~0); 69720#L586-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 69719#L591-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 69718#L596-3 assume !(0 == ~T5_E~0); 69717#L601-3 assume 0 == ~E_1~0;~E_1~0 := 1; 69716#L606-3 assume 0 == ~E_2~0;~E_2~0 := 1; 69715#L611-3 assume !(0 == ~E_3~0); 69714#L616-3 assume 0 == ~E_4~0;~E_4~0 := 1; 69713#L621-3 assume !(0 == ~E_5~0); 69712#L626-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 69711#L269-18 assume !(1 == ~m_pc~0); 69709#L269-20 is_master_triggered_~__retres1~0 := 0; 69708#L280-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 69706#L281-6 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 69704#L710-18 assume !(0 != activate_threads_~tmp~1); 69702#L710-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 69701#L288-18 assume !(1 == ~t1_pc~0); 69699#L288-20 is_transmit1_triggered_~__retres1~1 := 0; 69695#L299-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 69693#L300-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 69691#L718-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 69689#L718-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 69687#L307-18 assume !(1 == ~t2_pc~0); 69685#L307-20 is_transmit2_triggered_~__retres1~2 := 0; 69683#L318-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 69681#L319-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 69679#L726-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 69677#L726-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 69675#L326-18 assume !(1 == ~t3_pc~0); 69671#L326-20 is_transmit3_triggered_~__retres1~3 := 0; 69669#L337-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 69667#L338-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 69665#L734-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 69663#L734-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 69661#L345-18 assume !(1 == ~t4_pc~0); 69659#L345-20 is_transmit4_triggered_~__retres1~4 := 0; 69655#L356-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 69651#L357-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 69647#L742-18 assume !(0 != activate_threads_~tmp___3~0); 69643#L742-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 69641#L364-18 assume !(1 == ~t5_pc~0); 69639#L364-20 is_transmit5_triggered_~__retres1~5 := 0; 69637#L375-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 69635#L376-6 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 69633#L750-18 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 69631#L750-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 69629#L639-3 assume !(1 == ~M_E~0); 69628#L639-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 69551#L644-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 69552#L649-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 69544#L654-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 69545#L659-3 assume !(1 == ~T5_E~0); 69538#L664-3 assume 1 == ~E_1~0;~E_1~0 := 2; 69539#L669-3 assume 1 == ~E_2~0;~E_2~0 := 2; 69531#L674-3 assume !(1 == ~E_3~0); 69532#L679-3 assume 1 == ~E_4~0;~E_4~0 := 2; 69524#L684-3 assume 1 == ~E_5~0;~E_5~0 := 2; 69525#L689-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 69517#L429-1 assume !(0 == ~m_st~0); 69518#L433-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~6 := 1; 69826#L461-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 69822#L462-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 69818#L909 assume 0 == start_simulation_~tmp~3;start_simulation_~kernel_st~0 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 68862#L776 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 68863#L269-21 assume 1 == ~m_pc~0; 68868#L270-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 69263#L280-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 70149#L281-7 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 69916#L710-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 69915#L710-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 69914#L288-21 assume 1 == ~t1_pc~0; 69473#L289-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 69474#L299-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 69034#L300-7 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 69032#L718-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 69033#L718-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 69908#L307-21 assume !(1 == ~t2_pc~0); 69905#L307-23 is_transmit2_triggered_~__retres1~2 := 0; 69903#L318-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 69901#L319-7 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 69899#L726-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 69897#L726-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 69895#L326-21 assume !(1 == ~t3_pc~0); 69892#L326-23 is_transmit3_triggered_~__retres1~3 := 0; 69889#L337-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 69886#L338-7 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 69883#L734-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 69880#L734-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 69878#L345-21 assume 1 == ~t4_pc~0; 69875#L346-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 69872#L356-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 69869#L357-7 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 69866#L742-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 69865#L742-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 69864#L364-21 assume !(1 == ~t5_pc~0); 69863#L364-23 is_transmit5_triggered_~__retres1~5 := 0; 69862#L375-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 69861#L376-7 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 69860#L750-21 assume !(0 != activate_threads_~tmp___4~0); 69859#L750-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 69857#L783 assume 1 == ~M_E~0;~M_E~0 := 2; 69856#L783-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 69855#L788-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 69854#L793-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 69837#L798-1 assume !(1 == ~T4_E~0); 69836#L803-1 assume !(1 == ~T5_E~0); 69834#L808-1 assume 1 == ~E_1~0;~E_1~0 := 2; 69833#L813-1 assume 1 == ~E_2~0;~E_2~0 := 2; 69827#L818-1 assume !(1 == ~E_3~0); 69823#L823-1 assume 1 == ~E_4~0;~E_4~0 := 2; 69819#L828-1 assume 1 == ~E_5~0;~E_5~0 := 2; 69814#L833-1 assume { :end_inline_reset_time_events } true; 69812#L909-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 69809#L429-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 69810#L461-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 69794#L462-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 69795#L864 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 69785#L871 stop_simulation_#res := stop_simulation_~__retres2~0; 69786#L872 start_simulation_#t~ret15 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 69780#L922 assume !(0 != start_simulation_~tmp___0~1); 69260#L890-3 [2018-11-18 16:15:54,459 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:54,460 INFO L82 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 5 times [2018-11-18 16:15:54,460 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:15:54,460 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:15:54,460 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:54,460 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:15:54,460 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:54,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 16:15:54,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 16:15:54,478 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:54,478 INFO L82 PathProgramCache]: Analyzing trace with hash 1765381173, now seen corresponding path program 1 times [2018-11-18 16:15:54,478 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:15:54,478 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:15:54,479 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:54,479 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:15:54,479 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:54,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:15:54,515 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:15:54,516 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 16:15:54,516 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 16:15:54,516 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 16:15:54,516 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 16:15:54,516 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 16:15:54,516 INFO L87 Difference]: Start difference. First operand 5650 states and 7714 transitions. cyclomatic complexity: 2068 Second operand 3 states. [2018-11-18 16:15:54,566 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:15:54,566 INFO L93 Difference]: Finished difference Result 10321 states and 14000 transitions. [2018-11-18 16:15:54,567 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 16:15:54,568 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10321 states and 14000 transitions. [2018-11-18 16:15:54,589 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10212 [2018-11-18 16:15:54,607 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10321 states to 10321 states and 14000 transitions. [2018-11-18 16:15:54,607 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10321 [2018-11-18 16:15:54,611 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10321 [2018-11-18 16:15:54,611 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10321 states and 14000 transitions. [2018-11-18 16:15:54,616 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 16:15:54,616 INFO L705 BuchiCegarLoop]: Abstraction has 10321 states and 14000 transitions. [2018-11-18 16:15:54,622 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10321 states and 14000 transitions. [2018-11-18 16:15:54,687 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10321 to 10297. [2018-11-18 16:15:54,687 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10297 states. [2018-11-18 16:15:54,699 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10297 states to 10297 states and 13976 transitions. [2018-11-18 16:15:54,699 INFO L728 BuchiCegarLoop]: Abstraction has 10297 states and 13976 transitions. [2018-11-18 16:15:54,699 INFO L608 BuchiCegarLoop]: Abstraction has 10297 states and 13976 transitions. [2018-11-18 16:15:54,700 INFO L442 BuchiCegarLoop]: ======== Iteration 17============ [2018-11-18 16:15:54,700 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10297 states and 13976 transitions. [2018-11-18 16:15:54,738 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10188 [2018-11-18 16:15:54,739 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 16:15:54,739 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 16:15:54,742 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:54,742 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:54,742 INFO L794 eck$LassoCheckResult]: Stem: 85150#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 85106#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 84851#L853 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 84852#L384 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 84791#L391 assume 1 == ~m_i~0;~m_st~0 := 0; 84792#L391-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 84803#L396-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 84903#L401-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 84904#L406-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 84755#L411-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 84756#L416-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 84762#L576 assume !(0 == ~M_E~0); 84744#L576-2 assume !(0 == ~T1_E~0); 84745#L581-1 assume !(0 == ~T2_E~0); 85045#L586-1 assume !(0 == ~T3_E~0); 85046#L591-1 assume !(0 == ~T4_E~0); 84938#L596-1 assume !(0 == ~T5_E~0); 84939#L601-1 assume !(0 == ~E_1~0); 84991#L606-1 assume !(0 == ~E_2~0); 84813#L611-1 assume !(0 == ~E_3~0); 84814#L616-1 assume !(0 == ~E_4~0); 84687#L621-1 assume !(0 == ~E_5~0); 84688#L626-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 84899#L269 assume !(1 == ~m_pc~0); 84889#L269-2 is_master_triggered_~__retres1~0 := 0; 84890#L280 is_master_triggered_#res := is_master_triggered_~__retres1~0; 84804#L281 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 84805#L710 assume !(0 != activate_threads_~tmp~1); 84806#L710-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 84807#L288 assume !(1 == ~t1_pc~0); 84940#L288-2 is_transmit1_triggered_~__retres1~1 := 0; 84943#L299 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 84944#L300 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 85059#L718 assume !(0 != activate_threads_~tmp___0~0); 85068#L718-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 85069#L307 assume !(1 == ~t2_pc~0); 85109#L307-2 is_transmit2_triggered_~__retres1~2 := 0; 85107#L318 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 85108#L319 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 85181#L726 assume !(0 != activate_threads_~tmp___1~0); 85182#L726-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 85183#L326 assume !(1 == ~t3_pc~0); 85202#L326-2 is_transmit3_triggered_~__retres1~3 := 0; 85203#L337 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 85216#L338 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 85257#L734 assume !(0 != activate_threads_~tmp___2~0); 85267#L734-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 84732#L345 assume !(1 == ~t4_pc~0); 84733#L345-2 is_transmit4_triggered_~__retres1~4 := 0; 84730#L356 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 84731#L357 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 84705#L742 assume !(0 != activate_threads_~tmp___3~0); 84680#L742-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 84681#L364 assume !(1 == ~t5_pc~0); 84990#L364-2 is_transmit5_triggered_~__retres1~5 := 0; 84988#L375 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 84910#L376 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 84911#L750 assume !(0 != activate_threads_~tmp___4~0); 84948#L750-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 84954#L639 assume !(1 == ~M_E~0); 84992#L639-2 assume !(1 == ~T1_E~0); 84808#L644-1 assume !(1 == ~T2_E~0); 84809#L649-1 assume !(1 == ~T3_E~0); 84684#L654-1 assume !(1 == ~T4_E~0); 84685#L659-1 assume !(1 == ~T5_E~0); 84760#L664-1 assume !(1 == ~E_1~0); 84761#L669-1 assume !(1 == ~E_2~0); 85070#L674-1 assume !(1 == ~E_3~0); 85071#L679-1 assume !(1 == ~E_4~0); 84956#L684-1 assume !(1 == ~E_5~0); 84957#L689-1 assume { :end_inline_reset_delta_events } true; 85222#L890-3 [2018-11-18 16:15:54,743 INFO L796 eck$LassoCheckResult]: Loop: 85222#L890-3 assume true; 85524#L890-1 assume !false; 85476#L891 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 85460#L551 assume true; 85457#L471-1 assume !false; 85454#L472 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 85449#L429 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 85450#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 88280#L462 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 87021#L476 assume 0 != eval_~tmp~0; 87022#L476-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 87965#L484 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1;assume { :begin_inline_master } true; 87966#L55 assume 0 == ~m_pc~0; 88559#L82 assume true; 88603#L66 assume !false; 88602#L67 ~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 88601#L269-3 assume !(1 == ~m_pc~0); 88600#L269-5 is_master_triggered_~__retres1~0 := 0; 88599#L280-1 is_master_triggered_#res := is_master_triggered_~__retres1~0; 88598#L281-1 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 88597#L710-3 assume !(0 != activate_threads_~tmp~1); 88596#L710-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 88595#L288-3 assume 1 == ~t1_pc~0; 88593#L289-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 88592#L299-1 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 88591#L300-1 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 88590#L718-3 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 88589#L718-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 88588#L307-3 assume !(1 == ~t2_pc~0); 88587#L307-5 is_transmit2_triggered_~__retres1~2 := 0; 88586#L318-1 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 88585#L319-1 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 88584#L726-3 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 88583#L726-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 88582#L326-3 assume !(1 == ~t3_pc~0); 88580#L326-5 is_transmit3_triggered_~__retres1~3 := 0; 88579#L337-1 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 88578#L338-1 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 88577#L734-3 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 88576#L734-5 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 88575#L345-3 assume 1 == ~t4_pc~0; 88573#L346-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 88571#L356-1 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 88569#L357-1 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 88567#L742-3 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 88566#L742-5 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 88565#L364-3 assume !(1 == ~t5_pc~0); 88564#L364-5 is_transmit5_triggered_~__retres1~5 := 0; 88563#L375-1 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 88562#L376-1 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 88561#L750-3 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 88560#L750-5 assume { :end_inline_activate_threads } true; 88557#L767 assume { :end_inline_immediate_notify } true;~E_1~0 := 2; 88511#L59 assume true; 88509#L74-1 assume !false; 87840#L75 ~m_pc~0 := 1;~m_st~0 := 2; 87833#L85 assume { :end_inline_master } true; 87610#L481 assume !(0 == ~t1_st~0); 87815#L495 assume !(0 == ~t2_st~0); 87785#L509 assume !(0 == ~t3_st~0); 87777#L523 assume !(0 == ~t4_st~0); 87403#L537 assume !(0 == ~t5_st~0); 87396#L551 assume true; 87394#L471-1 assume !false; 87392#L472 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 87372#L429 assume !(0 == ~m_st~0); 87364#L433 assume !(0 == ~t1_st~0); 87355#L437 assume !(0 == ~t2_st~0); 87334#L441 assume !(0 == ~t3_st~0); 87328#L445 assume !(0 == ~t4_st~0); 87319#L449 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 87312#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 87305#L462 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 87298#L476 assume !(0 != eval_~tmp~0); 87292#L566 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 87286#L384-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 87278#L576-3 assume !(0 == ~M_E~0); 87271#L576-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 87267#L581-3 assume !(0 == ~T2_E~0); 87263#L586-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 87259#L591-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 87255#L596-3 assume !(0 == ~T5_E~0); 87251#L601-3 assume 0 == ~E_1~0;~E_1~0 := 1; 87247#L606-3 assume 0 == ~E_2~0;~E_2~0 := 1; 87241#L611-3 assume !(0 == ~E_3~0); 87236#L616-3 assume 0 == ~E_4~0;~E_4~0 := 1; 87231#L621-3 assume !(0 == ~E_5~0); 87226#L626-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 87220#L269-18 assume 1 == ~m_pc~0; 87216#L270-6 assume !(1 == ~M_E~0); 87212#L269-20 is_master_triggered_~__retres1~0 := 0; 87205#L280-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 87199#L281-6 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 87193#L710-18 assume !(0 != activate_threads_~tmp~1); 87187#L710-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 87182#L288-18 assume 1 == ~t1_pc~0; 87175#L289-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 87168#L299-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 87162#L300-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 87157#L718-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 87151#L718-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 87147#L307-18 assume !(1 == ~t2_pc~0); 87142#L307-20 is_transmit2_triggered_~__retres1~2 := 0; 87137#L318-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 87132#L319-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 87127#L726-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 87122#L726-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 87118#L326-18 assume !(1 == ~t3_pc~0); 87113#L326-20 is_transmit3_triggered_~__retres1~3 := 0; 87109#L337-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 87105#L338-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 87095#L734-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 87094#L734-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 87093#L345-18 assume !(1 == ~t4_pc~0); 87091#L345-20 is_transmit4_triggered_~__retres1~4 := 0; 87089#L356-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 87087#L357-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 87086#L742-18 assume !(0 != activate_threads_~tmp___3~0); 87084#L742-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 87083#L364-18 assume !(1 == ~t5_pc~0); 87082#L364-20 is_transmit5_triggered_~__retres1~5 := 0; 87081#L375-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 87080#L376-6 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 87079#L750-18 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 87078#L750-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 87077#L639-3 assume !(1 == ~M_E~0); 86894#L639-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 87075#L644-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 87074#L649-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 87073#L654-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 87072#L659-3 assume !(1 == ~T5_E~0); 87069#L664-3 assume 1 == ~E_1~0;~E_1~0 := 2; 87067#L669-3 assume 1 == ~E_2~0;~E_2~0 := 2; 87065#L674-3 assume !(1 == ~E_3~0); 87063#L679-3 assume 1 == ~E_4~0;~E_4~0 := 2; 87061#L684-3 assume 1 == ~E_5~0;~E_5~0 := 2; 87059#L689-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 87055#L429-1 assume !(0 == ~m_st~0); 86792#L433-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~6 := 1; 86820#L461-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 86810#L462-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 86541#L909 assume 0 == start_simulation_~tmp~3;start_simulation_~kernel_st~0 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 86539#L776 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 86536#L269-21 assume 1 == ~m_pc~0; 86532#L270-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 86530#L280-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 86528#L281-7 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 86512#L710-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 86457#L710-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 86456#L288-21 assume !(1 == ~t1_pc~0); 86455#L288-23 is_transmit1_triggered_~__retres1~1 := 0; 86453#L299-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 86449#L300-7 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 86447#L718-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 86445#L718-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 86443#L307-21 assume !(1 == ~t2_pc~0); 86440#L307-23 is_transmit2_triggered_~__retres1~2 := 0; 86438#L318-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 86436#L319-7 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 86427#L726-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 86419#L726-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 86414#L326-21 assume !(1 == ~t3_pc~0); 86411#L326-23 is_transmit3_triggered_~__retres1~3 := 0; 86408#L337-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 86406#L338-7 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 86403#L734-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 86398#L734-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 86300#L345-21 assume !(1 == ~t4_pc~0); 86296#L345-23 is_transmit4_triggered_~__retres1~4 := 0; 86292#L356-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 86290#L357-7 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 86288#L742-21 assume !(0 != activate_threads_~tmp___3~0); 86285#L742-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 86282#L364-21 assume !(1 == ~t5_pc~0); 86280#L364-23 is_transmit5_triggered_~__retres1~5 := 0; 86278#L375-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 86276#L376-7 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 86274#L750-21 assume !(0 != activate_threads_~tmp___4~0); 86272#L750-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 86269#L783 assume !(1 == ~M_E~0); 86267#L783-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 86264#L788-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 86262#L793-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 86260#L798-1 assume !(1 == ~T4_E~0); 86258#L803-1 assume !(1 == ~T5_E~0); 86256#L808-1 assume 1 == ~E_1~0;~E_1~0 := 2; 86254#L813-1 assume 1 == ~E_2~0;~E_2~0 := 2; 86252#L818-1 assume !(1 == ~E_3~0); 86250#L823-1 assume 1 == ~E_4~0;~E_4~0 := 2; 86248#L828-1 assume 1 == ~E_5~0;~E_5~0 := 2; 86235#L833-1 assume { :end_inline_reset_time_events } true; 86233#L909-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 86230#L429-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 86228#L461-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 86226#L462-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 86224#L864 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 86221#L871 stop_simulation_#res := stop_simulation_~__retres2~0; 86219#L872 start_simulation_#t~ret15 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 86215#L922 assume !(0 != start_simulation_~tmp___0~1); 86213#L890-3 assume true; 86211#L890-1 assume !false; 86209#L891 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 86052#L551 assume true; 86193#L471-1 assume !false; 86188#L472 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 86182#L429 assume !(0 == ~m_st~0); 86183#L433 assume !(0 == ~t1_st~0); 86716#L437 assume !(0 == ~t2_st~0); 86713#L441 assume !(0 == ~t3_st~0); 86711#L445 assume !(0 == ~t4_st~0); 86708#L449 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 86707#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 86706#L462 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 86705#L476 assume !(0 != eval_~tmp~0); 86704#L566 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 86701#L384-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 86699#L576-3 assume 0 == ~M_E~0;~M_E~0 := 1; 86696#L576-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 86693#L581-3 assume !(0 == ~T2_E~0); 86691#L586-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 86689#L591-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 86683#L596-3 assume !(0 == ~T5_E~0); 86676#L601-3 assume 0 == ~E_1~0;~E_1~0 := 1; 86671#L606-3 assume 0 == ~E_2~0;~E_2~0 := 1; 86667#L611-3 assume !(0 == ~E_3~0); 86663#L616-3 assume 0 == ~E_4~0;~E_4~0 := 1; 86608#L621-3 assume !(0 == ~E_5~0); 86508#L626-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 86504#L269-18 assume 1 == ~m_pc~0; 86502#L270-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 86501#L280-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 86497#L281-6 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 86494#L710-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 86492#L710-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 86490#L288-18 assume !(1 == ~t1_pc~0); 86487#L288-20 is_transmit1_triggered_~__retres1~1 := 0; 86484#L299-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 86482#L300-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 86480#L718-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 86478#L718-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 86476#L307-18 assume !(1 == ~t2_pc~0); 86474#L307-20 is_transmit2_triggered_~__retres1~2 := 0; 86472#L318-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 86468#L319-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 86466#L726-18 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 86464#L726-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 86462#L326-18 assume !(1 == ~t3_pc~0); 86460#L326-20 is_transmit3_triggered_~__retres1~3 := 0; 86431#L337-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 86422#L338-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 86301#L734-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 86297#L734-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 86295#L345-18 assume !(1 == ~t4_pc~0); 86291#L345-20 is_transmit4_triggered_~__retres1~4 := 0; 86289#L356-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 86286#L357-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 86284#L742-18 assume !(0 != activate_threads_~tmp___3~0); 86281#L742-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 86279#L364-18 assume !(1 == ~t5_pc~0); 86277#L364-20 is_transmit5_triggered_~__retres1~5 := 0; 86275#L375-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 86273#L376-6 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 86271#L750-18 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 86268#L750-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 86265#L639-3 assume !(1 == ~M_E~0); 86263#L639-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 86261#L644-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 86259#L649-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 86257#L654-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 86255#L659-3 assume !(1 == ~T5_E~0); 86253#L664-3 assume 1 == ~E_1~0;~E_1~0 := 2; 86251#L669-3 assume 1 == ~E_2~0;~E_2~0 := 2; 86249#L674-3 assume !(1 == ~E_3~0); 86247#L679-3 assume 1 == ~E_4~0;~E_4~0 := 2; 86246#L684-3 assume 1 == ~E_5~0;~E_5~0 := 2; 86245#L689-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 86243#L429-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 86241#L461-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 86238#L462-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 86236#L909 assume 0 == start_simulation_~tmp~3;start_simulation_~kernel_st~0 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 86082#L776 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 86071#L269-21 assume !(1 == ~m_pc~0); 86062#L269-23 is_master_triggered_~__retres1~0 := 0; 86057#L280-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 86049#L281-7 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 86043#L710-21 assume !(0 != activate_threads_~tmp~1); 86038#L710-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 86033#L288-21 assume 1 == ~t1_pc~0; 86029#L289-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 86024#L299-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 86021#L300-7 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 86019#L718-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 86017#L718-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 86015#L307-21 assume !(1 == ~t2_pc~0); 86013#L307-23 is_transmit2_triggered_~__retres1~2 := 0; 86011#L318-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 86009#L319-7 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 86006#L726-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 86000#L726-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 85995#L326-21 assume !(1 == ~t3_pc~0); 85989#L326-23 is_transmit3_triggered_~__retres1~3 := 0; 85983#L337-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 85976#L338-7 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 85973#L734-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 85969#L734-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 85782#L345-21 assume !(1 == ~t4_pc~0); 85778#L345-23 is_transmit4_triggered_~__retres1~4 := 0; 85776#L356-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 85774#L357-7 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 85772#L742-21 assume !(0 != activate_threads_~tmp___3~0); 85769#L742-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 85767#L364-21 assume !(1 == ~t5_pc~0); 85765#L364-23 is_transmit5_triggered_~__retres1~5 := 0; 85763#L375-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 85761#L376-7 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 85759#L750-21 assume !(0 != activate_threads_~tmp___4~0); 85757#L750-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 85754#L783 assume 1 == ~M_E~0;~M_E~0 := 2; 85755#L783-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 88349#L788-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 88345#L793-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 88342#L798-1 assume !(1 == ~T4_E~0); 88337#L803-1 assume !(1 == ~T5_E~0); 88332#L808-1 assume 1 == ~E_1~0;~E_1~0 := 2; 88327#L813-1 assume 1 == ~E_2~0;~E_2~0 := 2; 88323#L818-1 assume !(1 == ~E_3~0); 88318#L823-1 assume 1 == ~E_4~0;~E_4~0 := 2; 87023#L828-1 assume 1 == ~E_5~0;~E_5~0 := 2; 86983#L833-1 assume { :end_inline_reset_time_events } true; 86976#L909-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 86977#L429-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 86967#L461-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 86968#L462-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 85603#L864 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 85604#L871 stop_simulation_#res := stop_simulation_~__retres2~0; 85529#L872 start_simulation_#t~ret15 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 85530#L922 assume !(0 != start_simulation_~tmp___0~1); 85222#L890-3 [2018-11-18 16:15:54,743 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:54,743 INFO L82 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 6 times [2018-11-18 16:15:54,743 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:15:54,744 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:15:54,744 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:54,744 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:15:54,744 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:54,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 16:15:54,752 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 16:15:54,762 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:54,762 INFO L82 PathProgramCache]: Analyzing trace with hash 1687137869, now seen corresponding path program 1 times [2018-11-18 16:15:54,762 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:15:54,762 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:15:54,763 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:54,763 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:15:54,763 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:54,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:15:54,837 INFO L134 CoverageAnalysis]: Checked inductivity of 149 backedges. 17 proven. 0 refuted. 0 times theorem prover too weak. 132 trivial. 0 not checked. [2018-11-18 16:15:54,837 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 16:15:54,837 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 16:15:54,838 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 16:15:54,838 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 16:15:54,838 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 16:15:54,838 INFO L87 Difference]: Start difference. First operand 10297 states and 13976 transitions. cyclomatic complexity: 3687 Second operand 5 states. [2018-11-18 16:15:54,961 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:15:54,962 INFO L93 Difference]: Finished difference Result 19413 states and 26211 transitions. [2018-11-18 16:15:54,963 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 16:15:54,963 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19413 states and 26211 transitions. [2018-11-18 16:15:55,005 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 19304 [2018-11-18 16:15:55,038 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19413 states to 19413 states and 26211 transitions. [2018-11-18 16:15:55,038 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19413 [2018-11-18 16:15:55,047 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19413 [2018-11-18 16:15:55,047 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19413 states and 26211 transitions. [2018-11-18 16:15:55,057 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 16:15:55,058 INFO L705 BuchiCegarLoop]: Abstraction has 19413 states and 26211 transitions. [2018-11-18 16:15:55,067 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19413 states and 26211 transitions. [2018-11-18 16:15:55,154 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19413 to 10555. [2018-11-18 16:15:55,154 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10555 states. [2018-11-18 16:15:55,168 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10555 states to 10555 states and 14163 transitions. [2018-11-18 16:15:55,168 INFO L728 BuchiCegarLoop]: Abstraction has 10555 states and 14163 transitions. [2018-11-18 16:15:55,168 INFO L608 BuchiCegarLoop]: Abstraction has 10555 states and 14163 transitions. [2018-11-18 16:15:55,168 INFO L442 BuchiCegarLoop]: ======== Iteration 18============ [2018-11-18 16:15:55,168 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10555 states and 14163 transitions. [2018-11-18 16:15:55,187 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10446 [2018-11-18 16:15:55,187 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 16:15:55,187 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 16:15:55,189 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:55,189 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:55,190 INFO L794 eck$LassoCheckResult]: Stem: 114913#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 114860#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 114579#L853 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 114580#L384 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 114518#L391 assume 1 == ~m_i~0;~m_st~0 := 0; 114519#L391-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 114527#L396-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 114635#L401-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 114636#L406-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 114481#L411-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 114482#L416-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 114488#L576 assume !(0 == ~M_E~0); 114469#L576-2 assume !(0 == ~T1_E~0); 114470#L581-1 assume !(0 == ~T2_E~0); 114781#L586-1 assume !(0 == ~T3_E~0); 114782#L591-1 assume !(0 == ~T4_E~0); 114670#L596-1 assume !(0 == ~T5_E~0); 114671#L601-1 assume !(0 == ~E_1~0); 114721#L606-1 assume !(0 == ~E_2~0); 114538#L611-1 assume !(0 == ~E_3~0); 114539#L616-1 assume !(0 == ~E_4~0); 114411#L621-1 assume !(0 == ~E_5~0); 114412#L626-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 114631#L269 assume !(1 == ~m_pc~0); 114614#L269-2 is_master_triggered_~__retres1~0 := 0; 114615#L280 is_master_triggered_#res := is_master_triggered_~__retres1~0; 114528#L281 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 114529#L710 assume !(0 != activate_threads_~tmp~1); 114530#L710-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 114531#L288 assume !(1 == ~t1_pc~0); 114672#L288-2 is_transmit1_triggered_~__retres1~1 := 0; 114675#L299 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 114676#L300 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 114794#L718 assume !(0 != activate_threads_~tmp___0~0); 114799#L718-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 114800#L307 assume !(1 == ~t2_pc~0); 114863#L307-2 is_transmit2_triggered_~__retres1~2 := 0; 114861#L318 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 114862#L319 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 114950#L726 assume !(0 != activate_threads_~tmp___1~0); 114951#L726-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 114952#L326 assume !(1 == ~t3_pc~0); 114983#L326-2 is_transmit3_triggered_~__retres1~3 := 0; 114984#L337 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 114996#L338 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 115041#L734 assume !(0 != activate_threads_~tmp___2~0); 115049#L734-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 114457#L345 assume !(1 == ~t4_pc~0); 114458#L345-2 is_transmit4_triggered_~__retres1~4 := 0; 114455#L356 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 114456#L357 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 114429#L742 assume !(0 != activate_threads_~tmp___3~0); 114404#L742-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 114405#L364 assume !(1 == ~t5_pc~0); 114720#L364-2 is_transmit5_triggered_~__retres1~5 := 0; 114719#L375 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 114642#L376 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 114643#L750 assume !(0 != activate_threads_~tmp___4~0); 114680#L750-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 114686#L639 assume !(1 == ~M_E~0); 114722#L639-2 assume !(1 == ~T1_E~0); 114534#L644-1 assume !(1 == ~T2_E~0); 114535#L649-1 assume !(1 == ~T3_E~0); 114408#L654-1 assume !(1 == ~T4_E~0); 114409#L659-1 assume !(1 == ~T5_E~0); 114486#L664-1 assume !(1 == ~E_1~0); 114487#L669-1 assume !(1 == ~E_2~0); 114801#L674-1 assume !(1 == ~E_3~0); 114802#L679-1 assume !(1 == ~E_4~0); 114687#L684-1 assume !(1 == ~E_5~0); 114688#L689-1 assume { :end_inline_reset_delta_events } true; 115002#L890-3 [2018-11-18 16:15:55,190 INFO L796 eck$LassoCheckResult]: Loop: 115002#L890-3 assume true; 117378#L890-1 assume !false; 117376#L891 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 117372#L551 assume true; 117370#L471-1 assume !false; 117368#L472 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 117363#L429 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 117361#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 117359#L462 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 117357#L476 assume 0 != eval_~tmp~0; 117353#L476-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 117350#L484 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1;assume { :begin_inline_master } true; 116504#L55 assume 0 == ~m_pc~0; 116503#L82 assume true; 116502#L66 assume !false; 116501#L67 ~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 116500#L269-3 assume !(1 == ~m_pc~0); 116499#L269-5 is_master_triggered_~__retres1~0 := 0; 116498#L280-1 is_master_triggered_#res := is_master_triggered_~__retres1~0; 116497#L281-1 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 116493#L710-3 assume !(0 != activate_threads_~tmp~1); 115084#L710-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 115085#L288-3 assume !(1 == ~t1_pc~0); 116489#L288-5 is_transmit1_triggered_~__retres1~1 := 0; 116486#L299-1 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 116484#L300-1 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 115172#L718-3 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 114779#L718-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 114780#L307-3 assume !(1 == ~t2_pc~0); 115171#L307-5 is_transmit2_triggered_~__retres1~2 := 0; 117039#L318-1 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 117038#L319-1 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 117037#L726-3 assume !(0 != activate_threads_~tmp___1~0); 117036#L726-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 117035#L326-3 assume !(1 == ~t3_pc~0); 117033#L326-5 is_transmit3_triggered_~__retres1~3 := 0; 117031#L337-1 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 117030#L338-1 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 117029#L734-3 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 117026#L734-5 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 117021#L345-3 assume !(1 == ~t4_pc~0); 117019#L345-5 is_transmit4_triggered_~__retres1~4 := 0; 117017#L356-1 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 117015#L357-1 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 117013#L742-3 assume !(0 != activate_threads_~tmp___3~0); 117010#L742-5 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 117007#L364-3 assume !(1 == ~t5_pc~0); 117005#L364-5 is_transmit5_triggered_~__retres1~5 := 0; 117003#L375-1 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 117001#L376-1 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 116999#L750-3 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 116997#L750-5 assume { :end_inline_activate_threads } true; 116990#L767 assume { :end_inline_immediate_notify } true;~E_1~0 := 2; 116988#L59 assume true; 116985#L74-1 assume !false; 116983#L75 ~m_pc~0 := 1;~m_st~0 := 2; 116981#L85 assume { :end_inline_master } true; 116976#L481 assume !(0 == ~t1_st~0); 116971#L495 assume !(0 == ~t2_st~0); 116932#L509 assume !(0 == ~t3_st~0); 116928#L523 assume !(0 == ~t4_st~0); 116923#L537 assume !(0 == ~t5_st~0); 116921#L551 assume true; 118563#L471-1 assume !false; 118562#L472 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 118561#L429 assume !(0 == ~m_st~0); 117045#L433 assume !(0 == ~t1_st~0); 118558#L437 assume !(0 == ~t2_st~0); 118559#L441 assume !(0 == ~t3_st~0); 118560#L445 assume !(0 == ~t4_st~0); 118557#L449 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 118556#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 118554#L462 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 118552#L476 assume !(0 != eval_~tmp~0); 118551#L566 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 118550#L384-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 118549#L576-3 assume !(0 == ~M_E~0); 118548#L576-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 118547#L581-3 assume !(0 == ~T2_E~0); 118546#L586-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 118545#L591-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 118544#L596-3 assume !(0 == ~T5_E~0); 118543#L601-3 assume 0 == ~E_1~0;~E_1~0 := 1; 118542#L606-3 assume 0 == ~E_2~0;~E_2~0 := 1; 118541#L611-3 assume !(0 == ~E_3~0); 118540#L616-3 assume 0 == ~E_4~0;~E_4~0 := 1; 118539#L621-3 assume !(0 == ~E_5~0); 118538#L626-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 118536#L269-18 assume 1 == ~m_pc~0; 118535#L270-6 assume !(1 == ~M_E~0); 118534#L269-20 is_master_triggered_~__retres1~0 := 0; 118533#L280-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 118532#L281-6 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 118531#L710-18 assume !(0 != activate_threads_~tmp~1); 118530#L710-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 118529#L288-18 assume !(1 == ~t1_pc~0); 118528#L288-20 is_transmit1_triggered_~__retres1~1 := 0; 118526#L299-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 118525#L300-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 118524#L718-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 118523#L718-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 118522#L307-18 assume !(1 == ~t2_pc~0); 118521#L307-20 is_transmit2_triggered_~__retres1~2 := 0; 118520#L318-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 118519#L319-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 118517#L726-18 assume !(0 != activate_threads_~tmp___1~0); 118516#L726-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 118514#L326-18 assume !(1 == ~t3_pc~0); 118511#L326-20 is_transmit3_triggered_~__retres1~3 := 0; 118509#L337-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 118507#L338-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 118505#L734-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 118502#L734-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 118500#L345-18 assume 1 == ~t4_pc~0; 118497#L346-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 118494#L356-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 118491#L357-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 118488#L742-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 118486#L742-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 118484#L364-18 assume !(1 == ~t5_pc~0); 118482#L364-20 is_transmit5_triggered_~__retres1~5 := 0; 118480#L375-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 118478#L376-6 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 118475#L750-18 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 118473#L750-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 118471#L639-3 assume !(1 == ~M_E~0); 118307#L639-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 118467#L644-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 118464#L649-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 118461#L654-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 118460#L659-3 assume !(1 == ~T5_E~0); 118457#L664-3 assume 1 == ~E_1~0;~E_1~0 := 2; 118452#L669-3 assume 1 == ~E_2~0;~E_2~0 := 2; 118448#L674-3 assume !(1 == ~E_3~0); 118444#L679-3 assume 1 == ~E_4~0;~E_4~0 := 2; 118441#L684-3 assume 1 == ~E_5~0;~E_5~0 := 2; 118436#L689-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 118431#L429-1 assume !(0 == ~m_st~0); 117865#L433-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~6 := 1; 118420#L461-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 118416#L462-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 118411#L909 assume 0 == start_simulation_~tmp~3;start_simulation_~kernel_st~0 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 118209#L776 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 118402#L269-21 assume 1 == ~m_pc~0; 118396#L270-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 118390#L280-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 118384#L281-7 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 118376#L710-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 118371#L710-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 118367#L288-21 assume 1 == ~t1_pc~0; 118361#L289-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 118356#L299-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 118351#L300-7 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 118346#L718-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 118341#L718-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 118335#L307-21 assume !(1 == ~t2_pc~0); 118329#L307-23 is_transmit2_triggered_~__retres1~2 := 0; 118323#L318-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 118318#L319-7 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 118314#L726-21 assume !(0 != activate_threads_~tmp___1~0); 118309#L726-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 118304#L326-21 assume !(1 == ~t3_pc~0); 118299#L326-23 is_transmit3_triggered_~__retres1~3 := 0; 118296#L337-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 118293#L338-7 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 118023#L734-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 117858#L734-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 117148#L345-21 assume !(1 == ~t4_pc~0); 117144#L345-23 is_transmit4_triggered_~__retres1~4 := 0; 117142#L356-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 117140#L357-7 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 117138#L742-21 assume !(0 != activate_threads_~tmp___3~0); 117135#L742-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 117133#L364-21 assume !(1 == ~t5_pc~0); 117130#L364-23 is_transmit5_triggered_~__retres1~5 := 0; 117128#L375-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 117126#L376-7 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 117124#L750-21 assume !(0 != activate_threads_~tmp___4~0); 117122#L750-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 117119#L783 assume !(1 == ~M_E~0); 117117#L783-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 117115#L788-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 117113#L793-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 117107#L798-1 assume !(1 == ~T4_E~0); 117105#L803-1 assume !(1 == ~T5_E~0); 117103#L808-1 assume 1 == ~E_1~0;~E_1~0 := 2; 117101#L813-1 assume 1 == ~E_2~0;~E_2~0 := 2; 117098#L818-1 assume !(1 == ~E_3~0); 117096#L823-1 assume 1 == ~E_4~0;~E_4~0 := 2; 117094#L828-1 assume 1 == ~E_5~0;~E_5~0 := 2; 116578#L833-1 assume { :end_inline_reset_time_events } true; 116576#L909-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 116573#L429-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 116569#L461-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 116567#L462-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 116565#L864 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 116563#L871 stop_simulation_#res := stop_simulation_~__retres2~0; 116560#L872 start_simulation_#t~ret15 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 116558#L922 assume !(0 != start_simulation_~tmp___0~1); 116556#L890-3 assume true; 116384#L890-1 assume !false; 115975#L891 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 115691#L551 assume true; 115971#L471-1 assume !false; 115968#L472 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 115965#L429 assume !(0 == ~m_st~0); 115966#L433 assume !(0 == ~t1_st~0); 118152#L437 assume !(0 == ~t2_st~0); 118150#L441 assume !(0 == ~t3_st~0); 118148#L445 assume !(0 == ~t4_st~0); 118145#L449 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 118143#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 118141#L462 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 118139#L476 assume !(0 != eval_~tmp~0); 117816#L566 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 117812#L384-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 117807#L576-3 assume 0 == ~M_E~0;~M_E~0 := 1; 117802#L576-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 117796#L581-3 assume !(0 == ~T2_E~0); 117791#L586-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 117785#L591-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 117780#L596-3 assume !(0 == ~T5_E~0); 117774#L601-3 assume 0 == ~E_1~0;~E_1~0 := 1; 117768#L606-3 assume 0 == ~E_2~0;~E_2~0 := 1; 117764#L611-3 assume !(0 == ~E_3~0); 117759#L616-3 assume 0 == ~E_4~0;~E_4~0 := 1; 117754#L621-3 assume !(0 == ~E_5~0); 117749#L626-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 117742#L269-18 assume 1 == ~m_pc~0; 117737#L270-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 117732#L280-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 117726#L281-6 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 117720#L710-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 117715#L710-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 117708#L288-18 assume !(1 == ~t1_pc~0); 117703#L288-20 is_transmit1_triggered_~__retres1~1 := 0; 117698#L299-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 117695#L300-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 117692#L718-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 117688#L718-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 117685#L307-18 assume !(1 == ~t2_pc~0); 117681#L307-20 is_transmit2_triggered_~__retres1~2 := 0; 117677#L318-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 116662#L319-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 116659#L726-18 assume !(0 != activate_threads_~tmp___1~0); 116657#L726-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 116655#L326-18 assume !(1 == ~t3_pc~0); 116652#L326-20 is_transmit3_triggered_~__retres1~3 := 0; 116650#L337-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 116648#L338-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 116646#L734-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 116644#L734-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 116643#L345-18 assume 1 == ~t4_pc~0; 116641#L346-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 116637#L356-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 116635#L357-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 116631#L742-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 116628#L742-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 116626#L364-18 assume !(1 == ~t5_pc~0); 116624#L364-20 is_transmit5_triggered_~__retres1~5 := 0; 116622#L375-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 116620#L376-6 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 116618#L750-18 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 116616#L750-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 116613#L639-3 assume !(1 == ~M_E~0); 116610#L639-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 116608#L644-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 116606#L649-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 116604#L654-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 116602#L659-3 assume !(1 == ~T5_E~0); 116600#L664-3 assume 1 == ~E_1~0;~E_1~0 := 2; 116598#L669-3 assume 1 == ~E_2~0;~E_2~0 := 2; 116596#L674-3 assume !(1 == ~E_3~0); 116594#L679-3 assume 1 == ~E_4~0;~E_4~0 := 2; 116592#L684-3 assume 1 == ~E_5~0;~E_5~0 := 2; 116590#L689-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 116586#L429-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 116584#L461-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 116582#L462-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 116579#L909 assume 0 == start_simulation_~tmp~3;start_simulation_~kernel_st~0 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 116580#L776 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 117570#L269-21 assume !(1 == ~m_pc~0); 117568#L269-23 is_master_triggered_~__retres1~0 := 0; 117566#L280-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 117562#L281-7 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 117560#L710-21 assume !(0 != activate_threads_~tmp~1); 117558#L710-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 117556#L288-21 assume !(1 == ~t1_pc~0); 117553#L288-23 is_transmit1_triggered_~__retres1~1 := 0; 117550#L299-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 117548#L300-7 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 117546#L718-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 117544#L718-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 117542#L307-21 assume !(1 == ~t2_pc~0); 117540#L307-23 is_transmit2_triggered_~__retres1~2 := 0; 117538#L318-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 117534#L319-7 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 117532#L726-21 assume !(0 != activate_threads_~tmp___1~0); 117530#L726-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 117528#L326-21 assume !(1 == ~t3_pc~0); 117526#L326-23 is_transmit3_triggered_~__retres1~3 := 0; 117525#L337-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 117521#L338-7 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 117517#L734-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 117516#L734-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 117515#L345-21 assume !(1 == ~t4_pc~0); 117513#L345-23 is_transmit4_triggered_~__retres1~4 := 0; 117862#L356-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 117445#L357-7 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 117441#L742-21 assume !(0 != activate_threads_~tmp___3~0); 117438#L742-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 117436#L364-21 assume !(1 == ~t5_pc~0); 117434#L364-23 is_transmit5_triggered_~__retres1~5 := 0; 117429#L375-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 117424#L376-7 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 117423#L750-21 assume !(0 != activate_threads_~tmp___4~0); 117422#L750-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 117420#L783 assume 1 == ~M_E~0;~M_E~0 := 2; 117419#L783-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 117417#L788-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 117416#L793-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 117414#L798-1 assume !(1 == ~T4_E~0); 117412#L803-1 assume !(1 == ~T5_E~0); 117410#L808-1 assume 1 == ~E_1~0;~E_1~0 := 2; 117408#L813-1 assume 1 == ~E_2~0;~E_2~0 := 2; 117406#L818-1 assume !(1 == ~E_3~0); 117403#L823-1 assume 1 == ~E_4~0;~E_4~0 := 2; 117401#L828-1 assume 1 == ~E_5~0;~E_5~0 := 2; 117399#L833-1 assume { :end_inline_reset_time_events } true; 117397#L909-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 117394#L429-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 117392#L461-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 117390#L462-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 117388#L864 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 117386#L871 stop_simulation_#res := stop_simulation_~__retres2~0; 117384#L872 start_simulation_#t~ret15 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 117382#L922 assume !(0 != start_simulation_~tmp___0~1); 115002#L890-3 [2018-11-18 16:15:55,190 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:55,190 INFO L82 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 7 times [2018-11-18 16:15:55,190 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:15:55,191 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:15:55,191 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:55,191 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:15:55,191 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:55,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 16:15:55,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 16:15:55,208 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:55,208 INFO L82 PathProgramCache]: Analyzing trace with hash 1324034510, now seen corresponding path program 1 times [2018-11-18 16:15:55,209 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:15:55,209 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:15:55,209 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:55,209 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:15:55,209 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:55,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:15:55,337 INFO L134 CoverageAnalysis]: Checked inductivity of 150 backedges. 17 proven. 0 refuted. 0 times theorem prover too weak. 133 trivial. 0 not checked. [2018-11-18 16:15:55,337 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 16:15:55,337 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 16:15:55,337 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 16:15:55,338 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 16:15:55,338 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 16:15:55,338 INFO L87 Difference]: Start difference. First operand 10555 states and 14163 transitions. cyclomatic complexity: 3616 Second operand 5 states. [2018-11-18 16:15:55,532 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:15:55,532 INFO L93 Difference]: Finished difference Result 29090 states and 38802 transitions. [2018-11-18 16:15:55,533 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 16:15:55,533 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 29090 states and 38802 transitions. [2018-11-18 16:15:55,621 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 28830 [2018-11-18 16:15:55,698 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 29090 states to 29090 states and 38802 transitions. [2018-11-18 16:15:55,698 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 29090 [2018-11-18 16:15:55,713 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 29090 [2018-11-18 16:15:55,713 INFO L73 IsDeterministic]: Start isDeterministic. Operand 29090 states and 38802 transitions. [2018-11-18 16:15:55,730 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 16:15:55,730 INFO L705 BuchiCegarLoop]: Abstraction has 29090 states and 38802 transitions. [2018-11-18 16:15:55,746 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29090 states and 38802 transitions. [2018-11-18 16:15:55,874 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29090 to 11026. [2018-11-18 16:15:55,874 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11026 states. [2018-11-18 16:15:55,891 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11026 states to 11026 states and 14634 transitions. [2018-11-18 16:15:55,891 INFO L728 BuchiCegarLoop]: Abstraction has 11026 states and 14634 transitions. [2018-11-18 16:15:55,891 INFO L608 BuchiCegarLoop]: Abstraction has 11026 states and 14634 transitions. [2018-11-18 16:15:55,891 INFO L442 BuchiCegarLoop]: ======== Iteration 19============ [2018-11-18 16:15:55,891 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11026 states and 14634 transitions. [2018-11-18 16:15:55,915 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10914 [2018-11-18 16:15:55,915 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 16:15:55,915 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 16:15:55,919 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:55,919 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:55,919 INFO L794 eck$LassoCheckResult]: Stem: 154626#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 154575#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 154247#L853 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 154248#L384 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 154182#L391 assume 1 == ~m_i~0;~m_st~0 := 0; 154183#L391-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 154192#L396-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 154312#L401-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 154313#L406-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 154144#L411-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 154145#L416-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 154151#L576 assume !(0 == ~M_E~0); 154133#L576-2 assume !(0 == ~T1_E~0); 154134#L581-1 assume !(0 == ~T2_E~0); 154471#L586-1 assume !(0 == ~T3_E~0); 154472#L591-1 assume !(0 == ~T4_E~0); 154345#L596-1 assume !(0 == ~T5_E~0); 154346#L601-1 assume !(0 == ~E_1~0); 154409#L606-1 assume !(0 == ~E_2~0); 154203#L611-1 assume !(0 == ~E_3~0); 154204#L616-1 assume !(0 == ~E_4~0); 154070#L621-1 assume !(0 == ~E_5~0); 154071#L626-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 154307#L269 assume !(1 == ~m_pc~0); 154293#L269-2 is_master_triggered_~__retres1~0 := 0; 154294#L280 is_master_triggered_#res := is_master_triggered_~__retres1~0; 154193#L281 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 154194#L710 assume !(0 != activate_threads_~tmp~1); 154195#L710-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 154196#L288 assume !(1 == ~t1_pc~0); 154347#L288-2 is_transmit1_triggered_~__retres1~1 := 0; 154351#L299 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 154352#L300 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 154497#L718 assume !(0 != activate_threads_~tmp___0~0); 154498#L718-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 154502#L307 assume !(1 == ~t2_pc~0); 154578#L307-2 is_transmit2_triggered_~__retres1~2 := 0; 154576#L318 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 154577#L319 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 154667#L726 assume !(0 != activate_threads_~tmp___1~0); 154668#L726-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 154669#L326 assume !(1 == ~t3_pc~0); 154696#L326-2 is_transmit3_triggered_~__retres1~3 := 0; 154697#L337 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 154710#L338 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 154771#L734 assume !(0 != activate_threads_~tmp___2~0); 154788#L734-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 154119#L345 assume !(1 == ~t4_pc~0); 154120#L345-2 is_transmit4_triggered_~__retres1~4 := 0; 154125#L356 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 154314#L357 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 154088#L742 assume !(0 != activate_threads_~tmp___3~0); 154063#L742-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 154064#L364 assume !(1 == ~t5_pc~0); 154406#L364-2 is_transmit5_triggered_~__retres1~5 := 0; 154405#L375 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 154317#L376 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 154318#L750 assume !(0 != activate_threads_~tmp___4~0); 154357#L750-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 154364#L639 assume !(1 == ~M_E~0); 154410#L639-2 assume !(1 == ~T1_E~0); 154199#L644-1 assume !(1 == ~T2_E~0); 154200#L649-1 assume !(1 == ~T3_E~0); 154067#L654-1 assume !(1 == ~T4_E~0); 154068#L659-1 assume !(1 == ~T5_E~0); 154149#L664-1 assume !(1 == ~E_1~0); 154150#L669-1 assume !(1 == ~E_2~0); 154504#L674-1 assume !(1 == ~E_3~0); 154505#L679-1 assume !(1 == ~E_4~0); 154365#L684-1 assume !(1 == ~E_5~0); 154366#L689-1 assume { :end_inline_reset_delta_events } true; 154720#L890-3 [2018-11-18 16:15:55,919 INFO L796 eck$LassoCheckResult]: Loop: 154720#L890-3 assume true; 157545#L890-1 assume !false; 157431#L891 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 157427#L551 assume true; 157425#L471-1 assume !false; 157408#L472 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 157310#L429 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 157307#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 157305#L462 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 157303#L476 assume 0 != eval_~tmp~0; 157299#L476-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 157296#L484 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1;assume { :begin_inline_master } true; 157294#L55 assume 0 == ~m_pc~0; 154940#L82 assume true; 154941#L66 assume !false; 154936#L67 ~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 154937#L269-3 assume !(1 == ~m_pc~0); 154241#L269-5 is_master_triggered_~__retres1~0 := 0; 154242#L280-1 is_master_triggered_#res := is_master_triggered_~__retres1~0; 154190#L281-1 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 154191#L710-3 assume !(0 != activate_threads_~tmp~1); 154209#L710-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 154210#L288-3 assume !(1 == ~t1_pc~0); 154475#L288-5 is_transmit1_triggered_~__retres1~1 := 0; 154529#L299-1 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 155118#L300-1 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 155119#L718-3 assume !(0 != activate_threads_~tmp___0~0); 154469#L718-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 154470#L307-3 assume !(1 == ~t2_pc~0); 154588#L307-5 is_transmit2_triggered_~__retres1~2 := 0; 157178#L318-1 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 157176#L319-1 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 157174#L726-3 assume !(0 != activate_threads_~tmp___1~0); 154674#L726-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 154675#L326-3 assume !(1 == ~t3_pc~0); 154700#L326-5 is_transmit3_triggered_~__retres1~3 := 0; 154703#L337-1 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 154714#L338-1 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 154772#L734-3 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 154779#L734-5 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 154127#L345-3 assume 1 == ~t4_pc~0; 154128#L346-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 154122#L356-1 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 154123#L357-1 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 158350#L742-3 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 154066#L742-5 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 154072#L364-3 assume !(1 == ~t5_pc~0); 154389#L364-5 is_transmit5_triggered_~__retres1~5 := 0; 157406#L375-1 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 157377#L376-1 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 157370#L750-3 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 157337#L750-5 assume { :end_inline_activate_threads } true; 157285#L767 assume { :end_inline_immediate_notify } true;~E_1~0 := 2; 157283#L59 assume true; 157275#L74-1 assume !false; 157269#L75 ~m_pc~0 := 1;~m_st~0 := 2; 157263#L85 assume { :end_inline_master } true; 157255#L481 assume !(0 == ~t1_st~0); 157247#L495 assume !(0 == ~t2_st~0); 157243#L509 assume !(0 == ~t3_st~0); 157414#L523 assume !(0 == ~t4_st~0); 157382#L537 assume !(0 == ~t5_st~0); 157379#L551 assume true; 157374#L471-1 assume !false; 157367#L472 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 156904#L429 assume !(0 == ~m_st~0); 156902#L433 assume !(0 == ~t1_st~0); 156900#L437 assume !(0 == ~t2_st~0); 156898#L441 assume !(0 == ~t3_st~0); 156896#L445 assume !(0 == ~t4_st~0); 156893#L449 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 156891#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 156889#L462 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 156886#L476 assume !(0 != eval_~tmp~0); 156884#L566 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 156882#L384-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 156877#L576-3 assume !(0 == ~M_E~0); 156875#L576-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 156873#L581-3 assume !(0 == ~T2_E~0); 156872#L586-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 156871#L591-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 156869#L596-3 assume !(0 == ~T5_E~0); 156856#L601-3 assume 0 == ~E_1~0;~E_1~0 := 1; 156854#L606-3 assume 0 == ~E_2~0;~E_2~0 := 1; 156852#L611-3 assume !(0 == ~E_3~0); 156850#L616-3 assume 0 == ~E_4~0;~E_4~0 := 1; 156848#L621-3 assume !(0 == ~E_5~0); 156846#L626-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 156844#L269-18 assume 1 == ~m_pc~0; 156843#L270-6 assume !(1 == ~M_E~0); 156842#L269-20 is_master_triggered_~__retres1~0 := 0; 156841#L280-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 156840#L281-6 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 156839#L710-18 assume !(0 != activate_threads_~tmp~1); 156838#L710-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 156837#L288-18 assume 1 == ~t1_pc~0; 156835#L289-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 156833#L299-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 156831#L300-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 156829#L718-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 156827#L718-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 156813#L307-18 assume !(1 == ~t2_pc~0); 156809#L307-20 is_transmit2_triggered_~__retres1~2 := 0; 156806#L318-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 156803#L319-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 156800#L726-18 assume !(0 != activate_threads_~tmp___1~0); 156797#L726-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 156794#L326-18 assume !(1 == ~t3_pc~0); 156778#L326-20 is_transmit3_triggered_~__retres1~3 := 0; 156772#L337-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 156767#L338-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 156761#L734-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 156755#L734-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 156750#L345-18 assume 1 == ~t4_pc~0; 156744#L346-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 156738#L356-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 156730#L357-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 156723#L742-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 156707#L742-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 156700#L364-18 assume !(1 == ~t5_pc~0); 156694#L364-20 is_transmit5_triggered_~__retres1~5 := 0; 156686#L375-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 156679#L376-6 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 156672#L750-18 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 156665#L750-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 156643#L639-3 assume !(1 == ~M_E~0); 156639#L639-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 156637#L644-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 156634#L649-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 156632#L654-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 156630#L659-3 assume !(1 == ~T5_E~0); 156627#L664-3 assume 1 == ~E_1~0;~E_1~0 := 2; 156625#L669-3 assume 1 == ~E_2~0;~E_2~0 := 2; 156623#L674-3 assume !(1 == ~E_3~0); 156621#L679-3 assume 1 == ~E_4~0;~E_4~0 := 2; 156619#L684-3 assume 1 == ~E_5~0;~E_5~0 := 2; 156617#L689-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 156610#L429-1 assume !(0 == ~m_st~0); 156447#L433-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~6 := 1; 156587#L461-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 156579#L462-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 156430#L909 assume 0 == start_simulation_~tmp~3;start_simulation_~kernel_st~0 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 156398#L776 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 156395#L269-21 assume 1 == ~m_pc~0; 156391#L270-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 156388#L280-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 156385#L281-7 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 156374#L710-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 156373#L710-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 156372#L288-21 assume 1 == ~t1_pc~0; 156370#L289-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 156368#L299-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 156366#L300-7 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 156364#L718-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 156359#L718-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 156354#L307-21 assume !(1 == ~t2_pc~0); 156347#L307-23 is_transmit2_triggered_~__retres1~2 := 0; 156342#L318-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 156326#L319-7 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 156320#L726-21 assume !(0 != activate_threads_~tmp___1~0); 156315#L726-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 156309#L326-21 assume !(1 == ~t3_pc~0); 156301#L326-23 is_transmit3_triggered_~__retres1~3 := 0; 156295#L337-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 156275#L338-7 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 156255#L734-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 156250#L734-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 156244#L345-21 assume 1 == ~t4_pc~0; 156226#L346-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 156219#L356-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 156213#L357-7 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 156205#L742-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 156198#L742-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 156190#L364-21 assume !(1 == ~t5_pc~0); 156181#L364-23 is_transmit5_triggered_~__retres1~5 := 0; 156174#L375-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 156167#L376-7 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 156159#L750-21 assume !(0 != activate_threads_~tmp___4~0); 156153#L750-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 156129#L783 assume !(1 == ~M_E~0); 156123#L783-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 156117#L788-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 156111#L793-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 156104#L798-1 assume !(1 == ~T4_E~0); 156098#L803-1 assume !(1 == ~T5_E~0); 156092#L808-1 assume 1 == ~E_1~0;~E_1~0 := 2; 156086#L813-1 assume 1 == ~E_2~0;~E_2~0 := 2; 156081#L818-1 assume !(1 == ~E_3~0); 156063#L823-1 assume 1 == ~E_4~0;~E_4~0 := 2; 156018#L828-1 assume 1 == ~E_5~0;~E_5~0 := 2; 155737#L833-1 assume { :end_inline_reset_time_events } true; 155735#L909-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 155732#L429-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 155731#L461-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 155729#L462-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 155698#L864 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 155695#L871 stop_simulation_#res := stop_simulation_~__retres2~0; 155693#L872 start_simulation_#t~ret15 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 155691#L922 assume !(0 != start_simulation_~tmp___0~1); 155689#L890-3 assume true; 155687#L890-1 assume !false; 155685#L891 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 155678#L551 assume true; 155676#L471-1 assume !false; 155674#L472 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 155671#L429 assume !(0 == ~m_st~0); 155672#L433 assume !(0 == ~t1_st~0); 156323#L437 assume !(0 == ~t2_st~0); 156317#L441 assume !(0 == ~t3_st~0); 156313#L445 assume !(0 == ~t4_st~0); 156304#L449 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 156298#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 156276#L462 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 156256#L476 assume !(0 != eval_~tmp~0); 156251#L566 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 156245#L384-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 156240#L576-3 assume 0 == ~M_E~0;~M_E~0 := 1; 156222#L576-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 156216#L581-3 assume !(0 == ~T2_E~0); 156209#L586-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 156201#L591-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 156193#L596-3 assume !(0 == ~T5_E~0); 156184#L601-3 assume 0 == ~E_1~0;~E_1~0 := 1; 156176#L606-3 assume 0 == ~E_2~0;~E_2~0 := 1; 156169#L611-3 assume !(0 == ~E_3~0); 156162#L616-3 assume 0 == ~E_4~0;~E_4~0 := 1; 156155#L621-3 assume !(0 == ~E_5~0); 156150#L626-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 156148#L269-18 assume 1 == ~m_pc~0; 156146#L270-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 156145#L280-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 156144#L281-6 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 156142#L710-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 156141#L710-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 156140#L288-18 assume 1 == ~t1_pc~0; 156138#L289-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 156136#L299-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 156134#L300-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 156132#L718-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 156125#L718-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 156119#L307-18 assume !(1 == ~t2_pc~0); 156113#L307-20 is_transmit2_triggered_~__retres1~2 := 0; 156107#L318-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 156101#L319-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 156095#L726-18 assume !(0 != activate_threads_~tmp___1~0); 156089#L726-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 156066#L326-18 assume !(1 == ~t3_pc~0); 156059#L326-20 is_transmit3_triggered_~__retres1~3 := 0; 156055#L337-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 156048#L338-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 156043#L734-18 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 156015#L734-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 156012#L345-18 assume !(1 == ~t4_pc~0); 156010#L345-20 is_transmit4_triggered_~__retres1~4 := 0; 156006#L356-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 156003#L357-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 156000#L742-18 assume !(0 != activate_threads_~tmp___3~0); 155997#L742-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 155995#L364-18 assume !(1 == ~t5_pc~0); 155993#L364-20 is_transmit5_triggered_~__retres1~5 := 0; 155992#L375-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 155979#L376-6 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 155977#L750-18 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 155975#L750-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 155971#L639-3 assume !(1 == ~M_E~0); 155968#L639-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 155965#L644-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 155962#L649-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 155765#L654-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 155761#L659-3 assume !(1 == ~T5_E~0); 155759#L664-3 assume 1 == ~E_1~0;~E_1~0 := 2; 155757#L669-3 assume 1 == ~E_2~0;~E_2~0 := 2; 155755#L674-3 assume !(1 == ~E_3~0); 155752#L679-3 assume 1 == ~E_4~0;~E_4~0 := 2; 155750#L684-3 assume 1 == ~E_5~0;~E_5~0 := 2; 155748#L689-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 155745#L429-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 155743#L461-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 155741#L462-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 155738#L909 assume 0 == start_simulation_~tmp~3;start_simulation_~kernel_st~0 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 155739#L776 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 156396#L269-21 assume !(1 == ~m_pc~0); 156397#L269-23 is_master_triggered_~__retres1~0 := 0; 158102#L280-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 158101#L281-7 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 158100#L710-21 assume !(0 != activate_threads_~tmp~1); 158099#L710-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 158098#L288-21 assume 1 == ~t1_pc~0; 158096#L289-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 158094#L299-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 158092#L300-7 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 158090#L718-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 158088#L718-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 158085#L307-21 assume !(1 == ~t2_pc~0); 158083#L307-23 is_transmit2_triggered_~__retres1~2 := 0; 158076#L318-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 158070#L319-7 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 158069#L726-21 assume !(0 != activate_threads_~tmp___1~0); 158066#L726-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 158026#L326-21 assume !(1 == ~t3_pc~0); 158022#L326-23 is_transmit3_triggered_~__retres1~3 := 0; 158020#L337-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 158018#L338-7 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 158013#L734-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 158009#L734-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 158001#L345-21 assume 1 == ~t4_pc~0; 157999#L346-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 158000#L356-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 158005#L357-7 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 157989#L742-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 157988#L742-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 157927#L364-21 assume !(1 == ~t5_pc~0); 157917#L364-23 is_transmit5_triggered_~__retres1~5 := 0; 157722#L375-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 157714#L376-7 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 157694#L750-21 assume !(0 != activate_threads_~tmp___4~0); 157693#L750-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 157691#L783 assume 1 == ~M_E~0;~M_E~0 := 2; 157690#L783-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 157688#L788-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 157687#L793-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 157686#L798-1 assume !(1 == ~T4_E~0); 157685#L803-1 assume !(1 == ~T5_E~0); 157585#L808-1 assume 1 == ~E_1~0;~E_1~0 := 2; 157574#L813-1 assume 1 == ~E_2~0;~E_2~0 := 2; 157568#L818-1 assume !(1 == ~E_3~0); 157567#L823-1 assume 1 == ~E_4~0;~E_4~0 := 2; 157566#L828-1 assume 1 == ~E_5~0;~E_5~0 := 2; 157564#L833-1 assume { :end_inline_reset_time_events } true; 157562#L909-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 157559#L429-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 157557#L461-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 157555#L462-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 157553#L864 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 157551#L871 stop_simulation_#res := stop_simulation_~__retres2~0; 157549#L872 start_simulation_#t~ret15 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 157547#L922 assume !(0 != start_simulation_~tmp___0~1); 154720#L890-3 [2018-11-18 16:15:55,920 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:55,920 INFO L82 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 8 times [2018-11-18 16:15:55,920 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:15:55,920 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:15:55,921 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:55,921 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:15:55,921 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:55,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 16:15:55,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 16:15:55,937 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:55,937 INFO L82 PathProgramCache]: Analyzing trace with hash -1922944745, now seen corresponding path program 1 times [2018-11-18 16:15:55,938 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:15:55,938 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:15:55,938 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:55,938 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:15:55,938 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:55,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:15:56,054 INFO L134 CoverageAnalysis]: Checked inductivity of 150 backedges. 17 proven. 0 refuted. 0 times theorem prover too weak. 133 trivial. 0 not checked. [2018-11-18 16:15:56,054 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 16:15:56,054 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 16:15:56,054 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 16:15:56,054 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 16:15:56,055 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 16:15:56,055 INFO L87 Difference]: Start difference. First operand 11026 states and 14634 transitions. cyclomatic complexity: 3616 Second operand 5 states. [2018-11-18 16:15:56,144 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:15:56,144 INFO L93 Difference]: Finished difference Result 15798 states and 20861 transitions. [2018-11-18 16:15:56,146 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 16:15:56,146 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15798 states and 20861 transitions. [2018-11-18 16:15:56,178 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 15686 [2018-11-18 16:15:56,202 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15798 states to 15798 states and 20861 transitions. [2018-11-18 16:15:56,203 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15798 [2018-11-18 16:15:56,209 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15798 [2018-11-18 16:15:56,209 INFO L73 IsDeterministic]: Start isDeterministic. Operand 15798 states and 20861 transitions. [2018-11-18 16:15:56,216 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 16:15:56,216 INFO L705 BuchiCegarLoop]: Abstraction has 15798 states and 20861 transitions. [2018-11-18 16:15:56,222 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15798 states and 20861 transitions. [2018-11-18 16:15:56,277 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15798 to 11074. [2018-11-18 16:15:56,277 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11074 states. [2018-11-18 16:15:56,285 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11074 states to 11074 states and 14541 transitions. [2018-11-18 16:15:56,285 INFO L728 BuchiCegarLoop]: Abstraction has 11074 states and 14541 transitions. [2018-11-18 16:15:56,285 INFO L608 BuchiCegarLoop]: Abstraction has 11074 states and 14541 transitions. [2018-11-18 16:15:56,285 INFO L442 BuchiCegarLoop]: ======== Iteration 20============ [2018-11-18 16:15:56,286 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11074 states and 14541 transitions. [2018-11-18 16:15:56,304 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10962 [2018-11-18 16:15:56,304 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 16:15:56,304 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 16:15:56,307 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:56,307 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:56,308 INFO L794 eck$LassoCheckResult]: Stem: 181450#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 181395#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 181084#L853 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 181085#L384 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 181018#L391 assume 1 == ~m_i~0;~m_st~0 := 0; 181019#L391-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 181033#L396-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 181151#L401-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 181152#L406-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 180985#L411-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 180986#L416-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 180992#L576 assume !(0 == ~M_E~0); 180972#L576-2 assume !(0 == ~T1_E~0); 180973#L581-1 assume !(0 == ~T2_E~0); 181309#L586-1 assume !(0 == ~T3_E~0); 181310#L591-1 assume !(0 == ~T4_E~0); 181186#L596-1 assume !(0 == ~T5_E~0); 181187#L601-1 assume !(0 == ~E_1~0); 181252#L606-1 assume !(0 == ~E_2~0); 181044#L611-1 assume !(0 == ~E_3~0); 181045#L616-1 assume !(0 == ~E_4~0); 180909#L621-1 assume !(0 == ~E_5~0); 180910#L626-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 181146#L269 assume !(1 == ~m_pc~0); 181133#L269-2 is_master_triggered_~__retres1~0 := 0; 181134#L280 is_master_triggered_#res := is_master_triggered_~__retres1~0; 181034#L281 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 181035#L710 assume !(0 != activate_threads_~tmp~1); 181037#L710-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 181038#L288 assume !(1 == ~t1_pc~0); 181188#L288-2 is_transmit1_triggered_~__retres1~1 := 0; 181362#L299 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 181633#L300 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 181334#L718 assume !(0 != activate_threads_~tmp___0~0); 181335#L718-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 181336#L307 assume !(1 == ~t2_pc~0); 181398#L307-2 is_transmit2_triggered_~__retres1~2 := 0; 181396#L318 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 181397#L319 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 181487#L726 assume !(0 != activate_threads_~tmp___1~0); 181488#L726-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 181489#L326 assume !(1 == ~t3_pc~0); 181527#L326-2 is_transmit3_triggered_~__retres1~3 := 0; 181528#L337 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 181546#L338 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 181605#L734 assume !(0 != activate_threads_~tmp___2~0); 181624#L734-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 180957#L345 assume !(1 == ~t4_pc~0); 180958#L345-2 is_transmit4_triggered_~__retres1~4 := 0; 180955#L356 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 180956#L357 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 180928#L742 assume !(0 != activate_threads_~tmp___3~0); 180898#L742-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 180899#L364 assume !(1 == ~t5_pc~0); 181247#L364-2 is_transmit5_triggered_~__retres1~5 := 0; 181245#L375 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 181158#L376 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 181159#L750 assume !(0 != activate_threads_~tmp___4~0); 181199#L750-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 181206#L639 assume !(1 == ~M_E~0); 181253#L639-2 assume !(1 == ~T1_E~0); 181039#L644-1 assume !(1 == ~T2_E~0); 181040#L649-1 assume !(1 == ~T3_E~0); 180905#L654-1 assume !(1 == ~T4_E~0); 180906#L659-1 assume !(1 == ~T5_E~0); 180990#L664-1 assume !(1 == ~E_1~0); 180991#L669-1 assume !(1 == ~E_2~0); 181337#L674-1 assume !(1 == ~E_3~0); 181338#L679-1 assume !(1 == ~E_4~0); 181207#L684-1 assume !(1 == ~E_5~0); 181208#L689-1 assume { :end_inline_reset_delta_events } true; 181556#L890-3 [2018-11-18 16:15:56,308 INFO L796 eck$LassoCheckResult]: Loop: 181556#L890-3 assume true; 184469#L890-1 assume !false; 184467#L891 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 181875#L551 assume true; 184465#L471-1 assume !false; 184464#L472 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 184462#L429 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 184461#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 184460#L462 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 184459#L476 assume 0 != eval_~tmp~0; 184457#L476-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 184456#L484 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1;assume { :begin_inline_master } true; 181458#L55 assume 0 == ~m_pc~0; 181075#L82 assume true; 181076#L66 assume !false; 181238#L67 ~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 181126#L269-3 assume !(1 == ~m_pc~0); 181079#L269-5 is_master_triggered_~__retres1~0 := 0; 181080#L280-1 is_master_triggered_#res := is_master_triggered_~__retres1~0; 181028#L281-1 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 181029#L710-3 assume !(0 != activate_threads_~tmp~1); 181041#L710-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 181048#L288-3 assume 1 == ~t1_pc~0; 181360#L289-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 181771#L299-1 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 181772#L300-1 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 181760#L718-3 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 181340#L718-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 181794#L307-3 assume !(1 == ~t2_pc~0); 181795#L307-5 is_transmit2_triggered_~__retres1~2 := 0; 184084#L318-1 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 184083#L319-1 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 184080#L726-3 assume !(0 != activate_threads_~tmp___1~0); 184078#L726-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 184076#L326-3 assume !(1 == ~t3_pc~0); 184073#L326-5 is_transmit3_triggered_~__retres1~3 := 0; 184071#L337-1 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 184069#L338-1 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 184067#L734-3 assume !(0 != activate_threads_~tmp___2~0); 184063#L734-5 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 184058#L345-3 assume 1 == ~t4_pc~0; 184059#L346-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 184060#L356-1 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 184086#L357-1 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 184048#L742-3 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 184046#L742-5 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 184044#L364-3 assume !(1 == ~t5_pc~0); 184042#L364-5 is_transmit5_triggered_~__retres1~5 := 0; 184040#L375-1 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 184038#L376-1 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 184035#L750-3 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 184033#L750-5 assume { :end_inline_activate_threads } true; 184027#L767 assume { :end_inline_immediate_notify } true;~E_1~0 := 2; 184023#L59 assume true; 184021#L74-1 assume !false; 184019#L75 ~m_pc~0 := 1;~m_st~0 := 2; 184017#L85 assume { :end_inline_master } true; 183731#L481 assume !(0 == ~t1_st~0); 184009#L495 assume !(0 == ~t2_st~0); 183975#L509 assume !(0 == ~t3_st~0); 183970#L523 assume !(0 == ~t4_st~0); 183964#L537 assume !(0 == ~t5_st~0); 183960#L551 assume true; 184098#L471-1 assume !false; 184097#L472 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 184096#L429 assume !(0 == ~m_st~0); 183742#L433 assume !(0 == ~t1_st~0); 184093#L437 assume !(0 == ~t2_st~0); 184094#L441 assume !(0 == ~t3_st~0); 184095#L445 assume !(0 == ~t4_st~0); 184091#L449 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 184092#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 184297#L462 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 184296#L476 assume !(0 != eval_~tmp~0); 184292#L566 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 184289#L384-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 184286#L576-3 assume !(0 == ~M_E~0); 184284#L576-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 184282#L581-3 assume !(0 == ~T2_E~0); 184278#L586-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 184276#L591-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 184274#L596-3 assume !(0 == ~T5_E~0); 184272#L601-3 assume 0 == ~E_1~0;~E_1~0 := 1; 184269#L606-3 assume 0 == ~E_2~0;~E_2~0 := 1; 184267#L611-3 assume !(0 == ~E_3~0); 184265#L616-3 assume 0 == ~E_4~0;~E_4~0 := 1; 184263#L621-3 assume !(0 == ~E_5~0); 184261#L626-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 184258#L269-18 assume 1 == ~m_pc~0; 184256#L270-6 assume !(1 == ~M_E~0); 184254#L269-20 is_master_triggered_~__retres1~0 := 0; 184251#L280-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 184249#L281-6 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 184247#L710-18 assume !(0 != activate_threads_~tmp~1); 184245#L710-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 184243#L288-18 assume 1 == ~t1_pc~0; 184241#L289-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 184242#L299-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 184308#L300-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 184230#L718-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 184228#L718-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 184225#L307-18 assume !(1 == ~t2_pc~0); 184223#L307-20 is_transmit2_triggered_~__retres1~2 := 0; 184221#L318-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 184219#L319-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 184217#L726-18 assume !(0 != activate_threads_~tmp___1~0); 184215#L726-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 184213#L326-18 assume !(1 == ~t3_pc~0); 184210#L326-20 is_transmit3_triggered_~__retres1~3 := 0; 184209#L337-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 184208#L338-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 184207#L734-18 assume !(0 != activate_threads_~tmp___2~0); 184206#L734-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 184204#L345-18 assume 1 == ~t4_pc~0; 184202#L346-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 184203#L356-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 184205#L357-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 184194#L742-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 184192#L742-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 184190#L364-18 assume !(1 == ~t5_pc~0); 184188#L364-20 is_transmit5_triggered_~__retres1~5 := 0; 184186#L375-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 184184#L376-6 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 184180#L750-18 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 184178#L750-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 184176#L639-3 assume !(1 == ~M_E~0); 184172#L639-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 184169#L644-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 184167#L649-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 184165#L654-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 184163#L659-3 assume !(1 == ~T5_E~0); 184161#L664-3 assume 1 == ~E_1~0;~E_1~0 := 2; 184159#L669-3 assume 1 == ~E_2~0;~E_2~0 := 2; 184157#L674-3 assume !(1 == ~E_3~0); 184155#L679-3 assume 1 == ~E_4~0;~E_4~0 := 2; 184154#L684-3 assume 1 == ~E_5~0;~E_5~0 := 2; 184153#L689-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 184152#L429-1 assume !(0 == ~m_st~0); 183784#L433-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~6 := 1; 184145#L461-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 184143#L462-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 184140#L909 assume 0 == start_simulation_~tmp~3;start_simulation_~kernel_st~0 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 184141#L776 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 184425#L269-21 assume 1 == ~m_pc~0; 184422#L270-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 184423#L280-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 184415#L281-7 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 184416#L710-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 185199#L710-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 185198#L288-21 assume 1 == ~t1_pc~0; 185196#L289-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 185194#L299-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 185192#L300-7 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 185190#L718-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 181276#L718-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 181277#L307-21 assume !(1 == ~t2_pc~0); 181490#L307-23 is_transmit2_triggered_~__retres1~2 := 0; 186537#L318-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 186536#L319-7 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 186535#L726-21 assume !(0 != activate_threads_~tmp___1~0); 181446#L726-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 181447#L326-21 assume !(1 == ~t3_pc~0); 182866#L326-23 is_transmit3_triggered_~__retres1~3 := 0; 182864#L337-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 182862#L338-7 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 182860#L734-21 assume !(0 != activate_threads_~tmp___2~0); 182858#L734-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 182854#L345-21 assume 1 == ~t4_pc~0; 182851#L346-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 182849#L356-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 182847#L357-7 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 182829#L742-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 182826#L742-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 182824#L364-21 assume !(1 == ~t5_pc~0); 182822#L364-23 is_transmit5_triggered_~__retres1~5 := 0; 182820#L375-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 182816#L376-7 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 182814#L750-21 assume !(0 != activate_threads_~tmp___4~0); 182810#L750-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 182694#L783 assume !(1 == ~M_E~0); 182684#L783-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 182680#L788-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 182559#L793-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 182555#L798-1 assume !(1 == ~T4_E~0); 182552#L803-1 assume !(1 == ~T5_E~0); 182547#L808-1 assume 1 == ~E_1~0;~E_1~0 := 2; 182542#L813-1 assume 1 == ~E_2~0;~E_2~0 := 2; 182536#L818-1 assume !(1 == ~E_3~0); 182532#L823-1 assume 1 == ~E_4~0;~E_4~0 := 2; 182529#L828-1 assume 1 == ~E_5~0;~E_5~0 := 2; 182524#L833-1 assume { :end_inline_reset_time_events } true; 182521#L909-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 182517#L429-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 182514#L461-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 182511#L462-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 182507#L864 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 182503#L871 stop_simulation_#res := stop_simulation_~__retres2~0; 182500#L872 start_simulation_#t~ret15 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 182497#L922 assume !(0 != start_simulation_~tmp___0~1); 182494#L890-3 assume true; 182490#L890-1 assume !false; 182487#L891 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 182171#L551 assume true; 182477#L471-1 assume !false; 182471#L472 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 182463#L429 assume !(0 == ~m_st~0); 182464#L433 assume !(0 == ~t1_st~0); 183279#L437 assume !(0 == ~t2_st~0); 183280#L441 assume !(0 == ~t3_st~0); 183281#L445 assume !(0 == ~t4_st~0); 183277#L449 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 183278#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 184319#L462 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 184318#L476 assume !(0 != eval_~tmp~0); 184316#L566 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 184315#L384-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 184314#L576-3 assume 0 == ~M_E~0;~M_E~0 := 1; 184313#L576-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 184311#L581-3 assume !(0 == ~T2_E~0); 184310#L586-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 184309#L591-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 184307#L596-3 assume !(0 == ~T5_E~0); 184306#L601-3 assume 0 == ~E_1~0;~E_1~0 := 1; 184305#L606-3 assume 0 == ~E_2~0;~E_2~0 := 1; 184304#L611-3 assume !(0 == ~E_3~0); 184303#L616-3 assume 0 == ~E_4~0;~E_4~0 := 1; 184302#L621-3 assume !(0 == ~E_5~0); 184300#L626-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 184298#L269-18 assume 1 == ~m_pc~0; 184293#L270-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 184294#L280-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 184287#L281-6 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 184288#L710-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 186668#L710-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 186666#L288-18 assume 1 == ~t1_pc~0; 186664#L289-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 186661#L299-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 186657#L300-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 186653#L718-18 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 186650#L718-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 186647#L307-18 assume !(1 == ~t2_pc~0); 186645#L307-20 is_transmit2_triggered_~__retres1~2 := 0; 186643#L318-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 186641#L319-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 186639#L726-18 assume !(0 != activate_threads_~tmp___1~0); 186549#L726-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 182870#L326-18 assume !(1 == ~t3_pc~0); 182867#L326-20 is_transmit3_triggered_~__retres1~3 := 0; 182865#L337-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 182863#L338-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 182861#L734-18 assume !(0 != activate_threads_~tmp___2~0); 182859#L734-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 182857#L345-18 assume 1 == ~t4_pc~0; 182855#L346-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 182856#L356-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 182879#L357-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 182845#L742-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 182844#L742-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 182842#L364-18 assume !(1 == ~t5_pc~0); 182840#L364-20 is_transmit5_triggered_~__retres1~5 := 0; 182838#L375-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 182835#L376-6 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 182833#L750-18 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 182831#L750-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 182827#L639-3 assume !(1 == ~M_E~0); 182825#L639-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 182823#L644-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 182821#L649-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 182696#L654-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 182685#L659-3 assume !(1 == ~T5_E~0); 182681#L664-3 assume 1 == ~E_1~0;~E_1~0 := 2; 182560#L669-3 assume 1 == ~E_2~0;~E_2~0 := 2; 182556#L674-3 assume !(1 == ~E_3~0); 182553#L679-3 assume 1 == ~E_4~0;~E_4~0 := 2; 182548#L684-3 assume 1 == ~E_5~0;~E_5~0 := 2; 182543#L689-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 182537#L429-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 182533#L461-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 182530#L462-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 182525#L909 assume 0 == start_simulation_~tmp~3;start_simulation_~kernel_st~0 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 182526#L776 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 184588#L269-21 assume !(1 == ~m_pc~0); 184586#L269-23 is_master_triggered_~__retres1~0 := 0; 184585#L280-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 184584#L281-7 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 184583#L710-21 assume !(0 != activate_threads_~tmp~1); 184581#L710-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 184580#L288-21 assume !(1 == ~t1_pc~0); 184578#L288-23 is_transmit1_triggered_~__retres1~1 := 0; 184576#L299-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 184574#L300-7 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 184573#L718-21 assume !(0 != activate_threads_~tmp___0~0); 184571#L718-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 184569#L307-21 assume !(1 == ~t2_pc~0); 184568#L307-23 is_transmit2_triggered_~__retres1~2 := 0; 184567#L318-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 184566#L319-7 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 184565#L726-21 assume !(0 != activate_threads_~tmp___1~0); 184564#L726-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 184561#L326-21 assume !(1 == ~t3_pc~0); 184558#L326-23 is_transmit3_triggered_~__retres1~3 := 0; 184556#L337-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 184554#L338-7 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 184552#L734-21 assume !(0 != activate_threads_~tmp___2~0); 184550#L734-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 184548#L345-21 assume 1 == ~t4_pc~0; 184546#L346-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 184547#L356-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 184570#L357-7 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 184535#L742-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 184532#L742-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 184530#L364-21 assume !(1 == ~t5_pc~0); 184528#L364-23 is_transmit5_triggered_~__retres1~5 := 0; 184526#L375-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 184524#L376-7 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 184522#L750-21 assume !(0 != activate_threads_~tmp___4~0); 184520#L750-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 184517#L783 assume 1 == ~M_E~0;~M_E~0 := 2; 184516#L783-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 184513#L788-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 184511#L793-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 184509#L798-1 assume !(1 == ~T4_E~0); 184507#L803-1 assume !(1 == ~T5_E~0); 184505#L808-1 assume 1 == ~E_1~0;~E_1~0 := 2; 184503#L813-1 assume 1 == ~E_2~0;~E_2~0 := 2; 184499#L818-1 assume !(1 == ~E_3~0); 184497#L823-1 assume 1 == ~E_4~0;~E_4~0 := 2; 184495#L828-1 assume 1 == ~E_5~0;~E_5~0 := 2; 184493#L833-1 assume { :end_inline_reset_time_events } true; 184490#L909-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 184487#L429-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 184485#L461-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 184482#L462-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 184480#L864 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 184478#L871 stop_simulation_#res := stop_simulation_~__retres2~0; 184476#L872 start_simulation_#t~ret15 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 184474#L922 assume !(0 != start_simulation_~tmp___0~1); 181556#L890-3 [2018-11-18 16:15:56,308 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:56,309 INFO L82 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 9 times [2018-11-18 16:15:56,309 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:15:56,309 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:15:56,309 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:56,309 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:15:56,309 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:56,313 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 16:15:56,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 16:15:56,327 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:56,327 INFO L82 PathProgramCache]: Analyzing trace with hash 680990508, now seen corresponding path program 1 times [2018-11-18 16:15:56,328 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:15:56,328 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:15:56,328 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:56,328 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:15:56,328 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:56,335 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:15:56,498 INFO L134 CoverageAnalysis]: Checked inductivity of 150 backedges. 17 proven. 0 refuted. 0 times theorem prover too weak. 133 trivial. 0 not checked. [2018-11-18 16:15:56,498 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 16:15:56,498 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 16:15:56,499 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 16:15:56,499 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 16:15:56,499 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 16:15:56,499 INFO L87 Difference]: Start difference. First operand 11074 states and 14541 transitions. cyclomatic complexity: 3475 Second operand 5 states. [2018-11-18 16:15:56,701 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:15:56,701 INFO L93 Difference]: Finished difference Result 18218 states and 23985 transitions. [2018-11-18 16:15:56,701 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 16:15:56,702 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18218 states and 23985 transitions. [2018-11-18 16:15:56,758 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 18074 [2018-11-18 16:15:56,798 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18218 states to 18218 states and 23985 transitions. [2018-11-18 16:15:56,798 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18218 [2018-11-18 16:15:56,808 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18218 [2018-11-18 16:15:56,808 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18218 states and 23985 transitions. [2018-11-18 16:15:56,818 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 16:15:56,818 INFO L705 BuchiCegarLoop]: Abstraction has 18218 states and 23985 transitions. [2018-11-18 16:15:56,827 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18218 states and 23985 transitions. [2018-11-18 16:15:56,908 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18218 to 11308. [2018-11-18 16:15:56,908 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11308 states. [2018-11-18 16:15:56,921 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11308 states to 11308 states and 14696 transitions. [2018-11-18 16:15:56,921 INFO L728 BuchiCegarLoop]: Abstraction has 11308 states and 14696 transitions. [2018-11-18 16:15:56,921 INFO L608 BuchiCegarLoop]: Abstraction has 11308 states and 14696 transitions. [2018-11-18 16:15:56,921 INFO L442 BuchiCegarLoop]: ======== Iteration 21============ [2018-11-18 16:15:56,921 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11308 states and 14696 transitions. [2018-11-18 16:15:56,947 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11196 [2018-11-18 16:15:56,947 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 16:15:56,947 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 16:15:56,951 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:56,951 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:56,951 INFO L794 eck$LassoCheckResult]: Stem: 210773#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 210724#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 210393#L853 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 210394#L384 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 210330#L391 assume 1 == ~m_i~0;~m_st~0 := 0; 210331#L391-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 210339#L396-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 210466#L401-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 210467#L406-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 210291#L411-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 210292#L416-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 210298#L576 assume !(0 == ~M_E~0); 210279#L576-2 assume !(0 == ~T1_E~0); 210280#L581-1 assume !(0 == ~T2_E~0); 210632#L586-1 assume !(0 == ~T3_E~0); 210633#L591-1 assume !(0 == ~T4_E~0); 210503#L596-1 assume !(0 == ~T5_E~0); 210504#L601-1 assume !(0 == ~E_1~0); 210570#L606-1 assume !(0 == ~E_2~0); 210352#L611-1 assume !(0 == ~E_3~0); 210353#L616-1 assume !(0 == ~E_4~0); 210214#L621-1 assume !(0 == ~E_5~0); 210215#L626-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 210461#L269 assume !(1 == ~m_pc~0); 210447#L269-2 is_master_triggered_~__retres1~0 := 0; 210448#L280 is_master_triggered_#res := is_master_triggered_~__retres1~0; 210342#L281 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 210343#L710 assume !(0 != activate_threads_~tmp~1); 210344#L710-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 210345#L288 assume !(1 == ~t1_pc~0); 210505#L288-2 is_transmit1_triggered_~__retres1~1 := 0; 210693#L299 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 210937#L300 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 210653#L718 assume !(0 != activate_threads_~tmp___0~0); 210654#L718-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 210658#L307 assume !(1 == ~t2_pc~0); 210727#L307-2 is_transmit2_triggered_~__retres1~2 := 0; 210725#L318 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 210726#L319 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 210812#L726 assume !(0 != activate_threads_~tmp___1~0); 210813#L726-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 210814#L326 assume !(1 == ~t3_pc~0); 210849#L326-2 is_transmit3_triggered_~__retres1~3 := 0; 210850#L337 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 210864#L338 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 210919#L734 assume !(0 != activate_threads_~tmp___2~0); 210932#L734-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 210264#L345 assume !(1 == ~t4_pc~0); 210265#L345-2 is_transmit4_triggered_~__retres1~4 := 0; 210262#L356 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 210263#L357 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 210232#L742 assume !(0 != activate_threads_~tmp___3~0); 210207#L742-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 210208#L364 assume !(1 == ~t5_pc~0); 210568#L364-2 is_transmit5_triggered_~__retres1~5 := 0; 210567#L375 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 210475#L376 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 210476#L750 assume !(0 != activate_threads_~tmp___4~0); 210514#L750-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 210520#L639 assume !(1 == ~M_E~0); 210571#L639-2 assume !(1 == ~T1_E~0); 210348#L644-1 assume !(1 == ~T2_E~0); 210349#L649-1 assume !(1 == ~T3_E~0); 210211#L654-1 assume !(1 == ~T4_E~0); 210212#L659-1 assume !(1 == ~T5_E~0); 210296#L664-1 assume !(1 == ~E_1~0); 210297#L669-1 assume !(1 == ~E_2~0); 210660#L674-1 assume !(1 == ~E_3~0); 210661#L679-1 assume !(1 == ~E_4~0); 210522#L684-1 assume !(1 == ~E_5~0); 210523#L689-1 assume { :end_inline_reset_delta_events } true; 210870#L890-3 [2018-11-18 16:15:56,952 INFO L796 eck$LassoCheckResult]: Loop: 210870#L890-3 assume true; 211115#L890-1 assume !false; 211107#L891 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 211102#L551 assume true; 211101#L471-1 assume !false; 211100#L472 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 211098#L429 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 211097#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 211096#L462 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 211095#L476 assume 0 != eval_~tmp~0; 211093#L476-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 211091#L484 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1;assume { :begin_inline_master } true; 211088#L55 assume 0 == ~m_pc~0; 211089#L82 assume true; 211084#L66 assume !false; 211085#L67 ~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 211080#L269-3 assume !(1 == ~m_pc~0); 211081#L269-5 is_master_triggered_~__retres1~0 := 0; 211076#L280-1 is_master_triggered_#res := is_master_triggered_~__retres1~0; 211077#L281-1 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 211072#L710-3 assume !(0 != activate_threads_~tmp~1); 211073#L710-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 211067#L288-3 assume !(1 == ~t1_pc~0); 211069#L288-5 is_transmit1_triggered_~__retres1~1 := 0; 211061#L299-1 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 211062#L300-1 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 211054#L718-3 assume !(0 != activate_threads_~tmp___0~0); 211053#L718-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 211048#L307-3 assume !(1 == ~t2_pc~0); 211049#L307-5 is_transmit2_triggered_~__retres1~2 := 0; 212481#L318-1 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 212479#L319-1 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 212477#L726-3 assume !(0 != activate_threads_~tmp___1~0); 212475#L726-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 212473#L326-3 assume !(1 == ~t3_pc~0); 212470#L326-5 is_transmit3_triggered_~__retres1~3 := 0; 212467#L337-1 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 212465#L338-1 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 212463#L734-3 assume !(0 != activate_threads_~tmp___2~0); 212461#L734-5 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 212453#L345-3 assume !(1 == ~t4_pc~0); 212451#L345-5 is_transmit4_triggered_~__retres1~4 := 0; 212449#L356-1 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 212447#L357-1 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 212444#L742-3 assume !(0 != activate_threads_~tmp___3~0); 212441#L742-5 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 212439#L364-3 assume !(1 == ~t5_pc~0); 212437#L364-5 is_transmit5_triggered_~__retres1~5 := 0; 212435#L375-1 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 212433#L376-1 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 212431#L750-3 assume !(0 != activate_threads_~tmp___4~0); 212429#L750-5 assume { :end_inline_activate_threads } true; 212386#L767 assume { :end_inline_immediate_notify } true;~E_1~0 := 2; 212384#L59 assume true; 212380#L74-1 assume !false; 212378#L75 ~m_pc~0 := 1;~m_st~0 := 2; 212376#L85 assume { :end_inline_master } true; 212341#L481 assume !(0 == ~t1_st~0); 212336#L495 assume !(0 == ~t2_st~0); 212315#L509 assume !(0 == ~t3_st~0); 212305#L523 assume !(0 == ~t4_st~0); 212296#L537 assume !(0 == ~t5_st~0); 212292#L551 assume true; 212290#L471-1 assume !false; 212288#L472 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 212285#L429 assume !(0 == ~m_st~0); 212284#L433 assume !(0 == ~t1_st~0); 212283#L437 assume !(0 == ~t2_st~0); 212282#L441 assume !(0 == ~t3_st~0); 212281#L445 assume !(0 == ~t4_st~0); 212279#L449 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 212278#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 212277#L462 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 212275#L476 assume !(0 != eval_~tmp~0); 212274#L566 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 212273#L384-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 212272#L576-3 assume !(0 == ~M_E~0); 212271#L576-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 212270#L581-3 assume !(0 == ~T2_E~0); 212269#L586-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 212268#L591-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 212267#L596-3 assume !(0 == ~T5_E~0); 212266#L601-3 assume 0 == ~E_1~0;~E_1~0 := 1; 212265#L606-3 assume 0 == ~E_2~0;~E_2~0 := 1; 212264#L611-3 assume !(0 == ~E_3~0); 212263#L616-3 assume 0 == ~E_4~0;~E_4~0 := 1; 212262#L621-3 assume !(0 == ~E_5~0); 212261#L626-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 212259#L269-18 assume 1 == ~m_pc~0; 212258#L270-6 assume !(1 == ~M_E~0); 212257#L269-20 is_master_triggered_~__retres1~0 := 0; 212256#L280-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 212255#L281-6 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 212254#L710-18 assume !(0 != activate_threads_~tmp~1); 212253#L710-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 212252#L288-18 assume !(1 == ~t1_pc~0); 212251#L288-20 is_transmit1_triggered_~__retres1~1 := 0; 212249#L299-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 212247#L300-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 212245#L718-18 assume !(0 != activate_threads_~tmp___0~0); 212243#L718-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 212242#L307-18 assume !(1 == ~t2_pc~0); 212241#L307-20 is_transmit2_triggered_~__retres1~2 := 0; 212239#L318-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 212237#L319-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 212235#L726-18 assume !(0 != activate_threads_~tmp___1~0); 212234#L726-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 212232#L326-18 assume !(1 == ~t3_pc~0); 212228#L326-20 is_transmit3_triggered_~__retres1~3 := 0; 212224#L337-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 212220#L338-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 212216#L734-18 assume !(0 != activate_threads_~tmp___2~0); 212211#L734-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 212204#L345-18 assume !(1 == ~t4_pc~0); 212197#L345-20 is_transmit4_triggered_~__retres1~4 := 0; 212189#L356-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 212181#L357-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 212175#L742-18 assume !(0 != activate_threads_~tmp___3~0); 212170#L742-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 212164#L364-18 assume !(1 == ~t5_pc~0); 212159#L364-20 is_transmit5_triggered_~__retres1~5 := 0; 212154#L375-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 212149#L376-6 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 212145#L750-18 assume !(0 != activate_threads_~tmp___4~0); 212141#L750-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 212136#L639-3 assume !(1 == ~M_E~0); 212075#L639-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 212127#L644-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 212122#L649-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 212115#L654-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 212109#L659-3 assume !(1 == ~T5_E~0); 212105#L664-3 assume 1 == ~E_1~0;~E_1~0 := 2; 212100#L669-3 assume 1 == ~E_2~0;~E_2~0 := 2; 212094#L674-3 assume !(1 == ~E_3~0); 212088#L679-3 assume 1 == ~E_4~0;~E_4~0 := 2; 212082#L684-3 assume 1 == ~E_5~0;~E_5~0 := 2; 212078#L689-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 212072#L429-1 assume !(0 == ~m_st~0); 211207#L433-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~6 := 1; 212052#L461-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 212043#L462-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 212035#L909 assume 0 == start_simulation_~tmp~3;start_simulation_~kernel_st~0 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 211477#L776 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 212025#L269-21 assume 1 == ~m_pc~0; 212020#L270-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 212014#L280-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 212008#L281-7 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 211894#L710-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 211892#L710-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 211890#L288-21 assume !(1 == ~t1_pc~0); 211887#L288-23 is_transmit1_triggered_~__retres1~1 := 0; 211884#L299-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 211881#L300-7 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 211878#L718-21 assume !(0 != activate_threads_~tmp___0~0); 211875#L718-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 211873#L307-21 assume !(1 == ~t2_pc~0); 211871#L307-23 is_transmit2_triggered_~__retres1~2 := 0; 211868#L318-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 211865#L319-7 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 211862#L726-21 assume !(0 != activate_threads_~tmp___1~0); 211859#L726-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 211857#L326-21 assume !(1 == ~t3_pc~0); 211855#L326-23 is_transmit3_triggered_~__retres1~3 := 0; 211854#L337-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 211851#L338-7 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 211849#L734-21 assume !(0 != activate_threads_~tmp___2~0); 211847#L734-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 211845#L345-21 assume !(1 == ~t4_pc~0); 211843#L345-23 is_transmit4_triggered_~__retres1~4 := 0; 211840#L356-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 211837#L357-7 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 211833#L742-21 assume !(0 != activate_threads_~tmp___3~0); 211829#L742-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 211826#L364-21 assume !(1 == ~t5_pc~0); 211823#L364-23 is_transmit5_triggered_~__retres1~5 := 0; 211448#L375-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 211443#L376-7 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 211439#L750-21 assume !(0 != activate_threads_~tmp___4~0); 211437#L750-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 211434#L783 assume !(1 == ~M_E~0); 211432#L783-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 211429#L788-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 211427#L793-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 211425#L798-1 assume !(1 == ~T4_E~0); 211423#L803-1 assume !(1 == ~T5_E~0); 211421#L808-1 assume 1 == ~E_1~0;~E_1~0 := 2; 211419#L813-1 assume 1 == ~E_2~0;~E_2~0 := 2; 211417#L818-1 assume !(1 == ~E_3~0); 211415#L823-1 assume 1 == ~E_4~0;~E_4~0 := 2; 211414#L828-1 assume 1 == ~E_5~0;~E_5~0 := 2; 211395#L833-1 assume { :end_inline_reset_time_events } true; 211394#L909-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 211392#L429-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 211393#L461-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 211904#L462-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 211900#L864 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 211450#L871 stop_simulation_#res := stop_simulation_~__retres2~0; 211381#L872 start_simulation_#t~ret15 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 211348#L922 assume !(0 != start_simulation_~tmp___0~1); 211346#L890-3 assume true; 211324#L890-1 assume !false; 211313#L891 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 211305#L551 assume true; 211303#L471-1 assume !false; 211301#L472 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 211298#L429 assume !(0 == ~m_st~0); 211296#L433 assume !(0 == ~t1_st~0); 211295#L437 assume !(0 == ~t2_st~0); 211294#L441 assume !(0 == ~t3_st~0); 211293#L445 assume !(0 == ~t4_st~0); 211291#L449 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 211290#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 211289#L462 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 211287#L476 assume !(0 != eval_~tmp~0); 211286#L566 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 211285#L384-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 211284#L576-3 assume 0 == ~M_E~0;~M_E~0 := 1; 211283#L576-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 211282#L581-3 assume !(0 == ~T2_E~0); 211281#L586-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 211280#L591-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 211279#L596-3 assume !(0 == ~T5_E~0); 211278#L601-3 assume 0 == ~E_1~0;~E_1~0 := 1; 211277#L606-3 assume 0 == ~E_2~0;~E_2~0 := 1; 211276#L611-3 assume !(0 == ~E_3~0); 211275#L616-3 assume 0 == ~E_4~0;~E_4~0 := 1; 211274#L621-3 assume !(0 == ~E_5~0); 211273#L626-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 211271#L269-18 assume 1 == ~m_pc~0; 211269#L270-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 211268#L280-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 211267#L281-6 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 211265#L710-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 211264#L710-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 211263#L288-18 assume !(1 == ~t1_pc~0); 211262#L288-20 is_transmit1_triggered_~__retres1~1 := 0; 211260#L299-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 211258#L300-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 211256#L718-18 assume !(0 != activate_threads_~tmp___0~0); 211254#L718-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 211253#L307-18 assume !(1 == ~t2_pc~0); 211252#L307-20 is_transmit2_triggered_~__retres1~2 := 0; 211251#L318-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 211250#L319-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 211249#L726-18 assume !(0 != activate_threads_~tmp___1~0); 211248#L726-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 211247#L326-18 assume !(1 == ~t3_pc~0); 211245#L326-20 is_transmit3_triggered_~__retres1~3 := 0; 211244#L337-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 211243#L338-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 211242#L734-18 assume !(0 != activate_threads_~tmp___2~0); 211241#L734-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 211240#L345-18 assume !(1 == ~t4_pc~0); 211239#L345-20 is_transmit4_triggered_~__retres1~4 := 0; 211237#L356-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 211235#L357-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 211233#L742-18 assume !(0 != activate_threads_~tmp___3~0); 211231#L742-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 211230#L364-18 assume !(1 == ~t5_pc~0); 211229#L364-20 is_transmit5_triggered_~__retres1~5 := 0; 211228#L375-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 211227#L376-6 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 211226#L750-18 assume !(0 != activate_threads_~tmp___4~0); 211225#L750-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 211223#L639-3 assume 1 == ~M_E~0;~M_E~0 := 2; 211222#L639-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 211221#L644-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 211219#L649-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 211220#L654-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 211980#L659-3 assume !(1 == ~T5_E~0); 211978#L664-3 assume 1 == ~E_1~0;~E_1~0 := 2; 211213#L669-3 assume 1 == ~E_2~0;~E_2~0 := 2; 211214#L674-3 assume !(1 == ~E_3~0); 211466#L679-3 assume 1 == ~E_4~0;~E_4~0 := 2; 211464#L684-3 assume 1 == ~E_5~0;~E_5~0 := 2; 211208#L689-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 211206#L429-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 211205#L461-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 211204#L462-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 211201#L909 assume 0 == start_simulation_~tmp~3;start_simulation_~kernel_st~0 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 211202#L776 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 211852#L269-21 assume !(1 == ~m_pc~0); 211850#L269-23 is_master_triggered_~__retres1~0 := 0; 211848#L280-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 211846#L281-7 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 211844#L710-21 assume !(0 != activate_threads_~tmp~1); 211841#L710-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 211838#L288-21 assume !(1 == ~t1_pc~0); 211835#L288-23 is_transmit1_triggered_~__retres1~1 := 0; 211831#L299-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 211828#L300-7 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 211825#L718-21 assume !(0 != activate_threads_~tmp___0~0); 211822#L718-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 211821#L307-21 assume !(1 == ~t2_pc~0); 211820#L307-23 is_transmit2_triggered_~__retres1~2 := 0; 211819#L318-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 211818#L319-7 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 211815#L726-21 assume !(0 != activate_threads_~tmp___1~0); 211813#L726-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 211809#L326-21 assume !(1 == ~t3_pc~0); 211804#L326-23 is_transmit3_triggered_~__retres1~3 := 0; 211800#L337-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 211796#L338-7 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 211792#L734-21 assume !(0 != activate_threads_~tmp___2~0); 211786#L734-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 211772#L345-21 assume 1 == ~t4_pc~0; 211771#L346-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 211768#L356-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 211756#L357-7 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 211746#L742-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 211739#L742-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 211732#L364-21 assume !(1 == ~t5_pc~0); 211724#L364-23 is_transmit5_triggered_~__retres1~5 := 0; 211719#L375-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 211714#L376-7 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 211708#L750-21 assume !(0 != activate_threads_~tmp___4~0); 211700#L750-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 211692#L783 assume 1 == ~M_E~0;~M_E~0 := 2; 211693#L783-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 212740#L788-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 212735#L793-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 212733#L798-1 assume !(1 == ~T4_E~0); 212732#L803-1 assume !(1 == ~T5_E~0); 212731#L808-1 assume 1 == ~E_1~0;~E_1~0 := 2; 212730#L813-1 assume 1 == ~E_2~0;~E_2~0 := 2; 212729#L818-1 assume !(1 == ~E_3~0); 212728#L823-1 assume 1 == ~E_4~0;~E_4~0 := 2; 212727#L828-1 assume 1 == ~E_5~0;~E_5~0 := 2; 211200#L833-1 assume { :end_inline_reset_time_events } true; 211198#L909-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 211195#L429-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 211193#L461-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 211191#L462-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 211190#L864 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 211151#L871 stop_simulation_#res := stop_simulation_~__retres2~0; 211137#L872 start_simulation_#t~ret15 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 211129#L922 assume !(0 != start_simulation_~tmp___0~1); 210870#L890-3 [2018-11-18 16:15:56,952 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:56,953 INFO L82 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 10 times [2018-11-18 16:15:56,953 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:15:56,953 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:15:56,953 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:56,954 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:15:56,954 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:56,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 16:15:56,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 16:15:56,973 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:56,974 INFO L82 PathProgramCache]: Analyzing trace with hash 234534252, now seen corresponding path program 1 times [2018-11-18 16:15:56,974 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:15:56,974 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:15:56,975 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:56,975 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:15:56,975 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:56,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:15:57,104 INFO L134 CoverageAnalysis]: Checked inductivity of 150 backedges. 38 proven. 0 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-11-18 16:15:57,105 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 16:15:57,105 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 16:15:57,105 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 16:15:57,106 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 16:15:57,106 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 16:15:57,106 INFO L87 Difference]: Start difference. First operand 11308 states and 14696 transitions. cyclomatic complexity: 3396 Second operand 3 states. [2018-11-18 16:15:57,197 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:15:57,197 INFO L93 Difference]: Finished difference Result 10861 states and 13877 transitions. [2018-11-18 16:15:57,199 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 16:15:57,199 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10861 states and 13877 transitions. [2018-11-18 16:15:57,220 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10752 [2018-11-18 16:15:57,232 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10861 states to 10861 states and 13877 transitions. [2018-11-18 16:15:57,232 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10861 [2018-11-18 16:15:57,236 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10861 [2018-11-18 16:15:57,236 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10861 states and 13877 transitions. [2018-11-18 16:15:57,241 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 16:15:57,241 INFO L705 BuchiCegarLoop]: Abstraction has 10861 states and 13877 transitions. [2018-11-18 16:15:57,245 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10861 states and 13877 transitions. [2018-11-18 16:15:57,285 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10861 to 10861. [2018-11-18 16:15:57,285 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10861 states. [2018-11-18 16:15:57,293 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10861 states to 10861 states and 13877 transitions. [2018-11-18 16:15:57,293 INFO L728 BuchiCegarLoop]: Abstraction has 10861 states and 13877 transitions. [2018-11-18 16:15:57,293 INFO L608 BuchiCegarLoop]: Abstraction has 10861 states and 13877 transitions. [2018-11-18 16:15:57,294 INFO L442 BuchiCegarLoop]: ======== Iteration 22============ [2018-11-18 16:15:57,294 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10861 states and 13877 transitions. [2018-11-18 16:15:57,311 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10752 [2018-11-18 16:15:57,311 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 16:15:57,311 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 16:15:57,313 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:57,313 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:57,314 INFO L794 eck$LassoCheckResult]: Stem: 232868#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 232826#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 232556#L853 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 232557#L384 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 232497#L391 assume 1 == ~m_i~0;~m_st~0 := 0; 232498#L391-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 232508#L396-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 232611#L401-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 232612#L406-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 232462#L411-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 232463#L416-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 232469#L576 assume !(0 == ~M_E~0); 232451#L576-2 assume !(0 == ~T1_E~0); 232452#L581-1 assume !(0 == ~T2_E~0); 232752#L586-1 assume !(0 == ~T3_E~0); 232753#L591-1 assume !(0 == ~T4_E~0); 232646#L596-1 assume !(0 == ~T5_E~0); 232647#L601-1 assume !(0 == ~E_1~0); 232702#L606-1 assume !(0 == ~E_2~0); 232518#L611-1 assume !(0 == ~E_3~0); 232519#L616-1 assume !(0 == ~E_4~0); 232389#L621-1 assume !(0 == ~E_5~0); 232390#L626-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 232607#L269 assume !(1 == ~m_pc~0); 232592#L269-2 is_master_triggered_~__retres1~0 := 0; 232593#L280 is_master_triggered_#res := is_master_triggered_~__retres1~0; 232509#L281 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 232510#L710 assume !(0 != activate_threads_~tmp~1); 232511#L710-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 232512#L288 assume !(1 == ~t1_pc~0); 232648#L288-2 is_transmit1_triggered_~__retres1~1 := 0; 232652#L299 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 232653#L300 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 232768#L718 assume !(0 != activate_threads_~tmp___0~0); 232777#L718-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 232779#L307 assume !(1 == ~t2_pc~0); 232829#L307-2 is_transmit2_triggered_~__retres1~2 := 0; 232827#L318 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 232828#L319 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 232903#L726 assume !(0 != activate_threads_~tmp___1~0); 232904#L726-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 232905#L326 assume !(1 == ~t3_pc~0); 232928#L326-2 is_transmit3_triggered_~__retres1~3 := 0; 232929#L337 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 232944#L338 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 232986#L734 assume !(0 != activate_threads_~tmp___2~0); 232994#L734-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 232437#L345 assume !(1 == ~t4_pc~0); 232438#L345-2 is_transmit4_triggered_~__retres1~4 := 0; 232435#L356 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 232436#L357 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 232407#L742 assume !(0 != activate_threads_~tmp___3~0); 232382#L742-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 232383#L364 assume !(1 == ~t5_pc~0); 232701#L364-2 is_transmit5_triggered_~__retres1~5 := 0; 232699#L375 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 232618#L376 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 232619#L750 assume !(0 != activate_threads_~tmp___4~0); 232658#L750-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 232665#L639 assume !(1 == ~M_E~0); 232703#L639-2 assume !(1 == ~T1_E~0); 232513#L644-1 assume !(1 == ~T2_E~0); 232514#L649-1 assume !(1 == ~T3_E~0); 232386#L654-1 assume !(1 == ~T4_E~0); 232387#L659-1 assume !(1 == ~T5_E~0); 232467#L664-1 assume !(1 == ~E_1~0); 232468#L669-1 assume !(1 == ~E_2~0); 232780#L674-1 assume !(1 == ~E_3~0); 232781#L679-1 assume !(1 == ~E_4~0); 232666#L684-1 assume !(1 == ~E_5~0); 232667#L689-1 assume { :end_inline_reset_delta_events } true; 232951#L890-3 [2018-11-18 16:15:57,314 INFO L796 eck$LassoCheckResult]: Loop: 232951#L890-3 assume true; 238807#L890-1 assume !false; 238805#L891 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 238800#L551 assume true; 238797#L471-1 assume !false; 238795#L472 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 238793#L429 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 238791#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 238788#L462 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 238785#L476 assume 0 != eval_~tmp~0; 238779#L476-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 238776#L484 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1;assume { :begin_inline_master } true; 238777#L55 assume 0 == ~m_pc~0; 236442#L82 assume true; 240262#L66 assume !false; 240260#L67 ~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 240253#L269-3 assume !(1 == ~m_pc~0); 233042#L269-5 is_master_triggered_~__retres1~0 := 0; 232604#L280-1 is_master_triggered_#res := is_master_triggered_~__retres1~0; 232505#L281-1 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 232506#L710-3 assume !(0 != activate_threads_~tmp~1); 232515#L710-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 232524#L288-3 assume 1 == ~t1_pc~0; 232758#L289-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 232759#L299-1 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 232762#L300-1 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 232763#L718-3 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 232756#L718-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 232757#L307-3 assume !(1 == ~t2_pc~0); 232816#L307-5 is_transmit2_triggered_~__retres1~2 := 0; 232817#L318-1 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 232830#L319-1 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 232864#L726-3 assume !(0 != activate_threads_~tmp___1~0); 232908#L726-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 232932#L326-3 assume !(1 == ~t3_pc~0); 232934#L326-5 is_transmit3_triggered_~__retres1~3 := 0; 232938#L337-1 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 233036#L338-1 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 232995#L734-3 assume !(0 != activate_threads_~tmp___2~0); 232991#L734-5 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 232444#L345-3 assume !(1 == ~t4_pc~0); 232423#L345-5 is_transmit4_triggered_~__retres1~4 := 0; 232424#L356-1 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 232440#L357-1 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 232384#L742-3 assume !(0 != activate_threads_~tmp___3~0); 232385#L742-5 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 232391#L364-3 assume !(1 == ~t5_pc~0); 232689#L364-5 is_transmit5_triggered_~__retres1~5 := 0; 236624#L375-1 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 236621#L376-1 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 236619#L750-3 assume !(0 != activate_threads_~tmp___4~0); 236617#L750-5 assume { :end_inline_activate_threads } true; 236440#L767 assume { :end_inline_immediate_notify } true;~E_1~0 := 2; 236439#L59 assume true; 236437#L74-1 assume !false; 236435#L75 ~m_pc~0 := 1;~m_st~0 := 2; 236434#L85 assume { :end_inline_master } true; 236433#L481 assume !(0 == ~t1_st~0); 236428#L495 assume !(0 == ~t2_st~0); 236427#L509 assume !(0 == ~t3_st~0); 238662#L523 assume !(0 == ~t4_st~0); 238587#L537 assume !(0 == ~t5_st~0); 238583#L551 assume true; 238581#L471-1 assume !false; 238579#L472 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 235447#L429 assume !(0 == ~m_st~0); 235445#L433 assume !(0 == ~t1_st~0); 235441#L437 assume !(0 == ~t2_st~0); 235439#L441 assume !(0 == ~t3_st~0); 235437#L445 assume !(0 == ~t4_st~0); 235434#L449 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 235431#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 235429#L462 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 235426#L476 assume !(0 != eval_~tmp~0); 235424#L566 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 235422#L384-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 235420#L576-3 assume !(0 == ~M_E~0); 235418#L576-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 235416#L581-3 assume !(0 == ~T2_E~0); 235415#L586-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 235414#L591-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 235410#L596-3 assume !(0 == ~T5_E~0); 235408#L601-3 assume !(0 == ~E_1~0); 235406#L606-3 assume 0 == ~E_2~0;~E_2~0 := 1; 235404#L611-3 assume !(0 == ~E_3~0); 235403#L616-3 assume 0 == ~E_4~0;~E_4~0 := 1; 235402#L621-3 assume !(0 == ~E_5~0); 235401#L626-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 235400#L269-18 assume 1 == ~m_pc~0; 235399#L270-6 assume !(1 == ~M_E~0); 235398#L269-20 is_master_triggered_~__retres1~0 := 0; 235397#L280-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 235395#L281-6 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 235393#L710-18 assume !(0 != activate_threads_~tmp~1); 235391#L710-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 235390#L288-18 assume !(1 == ~t1_pc~0); 235386#L288-20 is_transmit1_triggered_~__retres1~1 := 0; 235384#L299-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 235382#L300-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 235379#L718-18 assume !(0 != activate_threads_~tmp___0~0); 235376#L718-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 235373#L307-18 assume !(1 == ~t2_pc~0); 235371#L307-20 is_transmit2_triggered_~__retres1~2 := 0; 235367#L318-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 235364#L319-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 235361#L726-18 assume !(0 != activate_threads_~tmp___1~0); 235358#L726-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 235355#L326-18 assume !(1 == ~t3_pc~0); 235350#L326-20 is_transmit3_triggered_~__retres1~3 := 0; 235347#L337-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 235344#L338-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 235341#L734-18 assume !(0 != activate_threads_~tmp___2~0); 235337#L734-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 235333#L345-18 assume !(1 == ~t4_pc~0); 235328#L345-20 is_transmit4_triggered_~__retres1~4 := 0; 235321#L356-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 235315#L357-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 235309#L742-18 assume !(0 != activate_threads_~tmp___3~0); 235303#L742-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 235299#L364-18 assume !(1 == ~t5_pc~0); 235295#L364-20 is_transmit5_triggered_~__retres1~5 := 0; 235291#L375-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 235286#L376-6 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 235281#L750-18 assume !(0 != activate_threads_~tmp___4~0); 235276#L750-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 235271#L639-3 assume !(1 == ~M_E~0); 235265#L639-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 235261#L644-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 235257#L649-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 235253#L654-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 235249#L659-3 assume !(1 == ~T5_E~0); 235245#L664-3 assume !(1 == ~E_1~0); 235241#L669-3 assume 1 == ~E_2~0;~E_2~0 := 2; 235235#L674-3 assume !(1 == ~E_3~0); 235230#L679-3 assume 1 == ~E_4~0;~E_4~0 := 2; 235225#L684-3 assume 1 == ~E_5~0;~E_5~0 := 2; 235220#L689-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 235217#L429-1 assume !(0 == ~m_st~0); 235113#L433-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~6 := 1; 235201#L461-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 235197#L462-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 235153#L909 assume 0 == start_simulation_~tmp~3;start_simulation_~kernel_st~0 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 235151#L776 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 235149#L269-21 assume 1 == ~m_pc~0; 235147#L270-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 235145#L280-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 235143#L281-7 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 235083#L710-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 235081#L710-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 235079#L288-21 assume !(1 == ~t1_pc~0); 235076#L288-23 is_transmit1_triggered_~__retres1~1 := 0; 235074#L299-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 235072#L300-7 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 235070#L718-21 assume !(0 != activate_threads_~tmp___0~0); 235068#L718-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 235066#L307-21 assume !(1 == ~t2_pc~0); 235064#L307-23 is_transmit2_triggered_~__retres1~2 := 0; 235062#L318-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 235059#L319-7 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 235057#L726-21 assume !(0 != activate_threads_~tmp___1~0); 235055#L726-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 235053#L326-21 assume !(1 == ~t3_pc~0); 235050#L326-23 is_transmit3_triggered_~__retres1~3 := 0; 235048#L337-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 235044#L338-7 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 235042#L734-21 assume !(0 != activate_threads_~tmp___2~0); 235040#L734-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 235038#L345-21 assume !(1 == ~t4_pc~0); 235033#L345-23 is_transmit4_triggered_~__retres1~4 := 0; 235031#L356-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 235029#L357-7 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 235027#L742-21 assume !(0 != activate_threads_~tmp___3~0); 235024#L742-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 235022#L364-21 assume !(1 == ~t5_pc~0); 235020#L364-23 is_transmit5_triggered_~__retres1~5 := 0; 235018#L375-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 235015#L376-7 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 235013#L750-21 assume !(0 != activate_threads_~tmp___4~0); 235011#L750-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 235008#L783 assume !(1 == ~M_E~0); 235006#L783-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 235004#L788-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 235002#L793-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 235000#L798-1 assume !(1 == ~T4_E~0); 234998#L803-1 assume !(1 == ~T5_E~0); 234996#L808-1 assume !(1 == ~E_1~0); 234994#L813-1 assume 1 == ~E_2~0;~E_2~0 := 2; 234992#L818-1 assume !(1 == ~E_3~0); 234989#L823-1 assume 1 == ~E_4~0;~E_4~0 := 2; 234987#L828-1 assume 1 == ~E_5~0;~E_5~0 := 2; 234983#L833-1 assume { :end_inline_reset_time_events } true; 234982#L909-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 234979#L429-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 234977#L461-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 234975#L462-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 234973#L864 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 234971#L871 stop_simulation_#res := stop_simulation_~__retres2~0; 234969#L872 start_simulation_#t~ret15 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 234967#L922 assume !(0 != start_simulation_~tmp___0~1); 234965#L890-3 assume true; 234963#L890-1 assume !false; 234961#L891 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 234957#L551 assume true; 234955#L471-1 assume !false; 234954#L472 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 234952#L429 assume !(0 == ~m_st~0); 234953#L433 assume !(0 == ~t1_st~0); 235146#L437 assume !(0 == ~t2_st~0); 235144#L441 assume !(0 == ~t3_st~0); 235142#L445 assume !(0 == ~t4_st~0); 235140#L449 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 235139#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 235137#L462 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 235136#L476 assume !(0 != eval_~tmp~0); 235135#L566 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 235134#L384-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 235132#L576-3 assume 0 == ~M_E~0;~M_E~0 := 1; 235130#L576-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 235128#L581-3 assume !(0 == ~T2_E~0); 235126#L586-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 235124#L591-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 235122#L596-3 assume !(0 == ~T5_E~0); 235120#L601-3 assume !(0 == ~E_1~0); 235118#L606-3 assume 0 == ~E_2~0;~E_2~0 := 1; 235116#L611-3 assume !(0 == ~E_3~0); 235114#L616-3 assume 0 == ~E_4~0;~E_4~0 := 1; 235111#L621-3 assume !(0 == ~E_5~0); 235109#L626-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 235106#L269-18 assume 1 == ~m_pc~0; 235102#L270-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 235101#L280-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 235098#L281-6 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 235094#L710-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 235092#L710-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 235090#L288-18 assume !(1 == ~t1_pc~0); 235087#L288-20 is_transmit1_triggered_~__retres1~1 := 0; 235082#L299-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 235080#L300-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 235077#L718-18 assume !(0 != activate_threads_~tmp___0~0); 235075#L718-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 235073#L307-18 assume !(1 == ~t2_pc~0); 235071#L307-20 is_transmit2_triggered_~__retres1~2 := 0; 235069#L318-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 235067#L319-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 235065#L726-18 assume !(0 != activate_threads_~tmp___1~0); 235063#L726-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 235061#L326-18 assume !(1 == ~t3_pc~0); 235058#L326-20 is_transmit3_triggered_~__retres1~3 := 0; 235056#L337-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 235054#L338-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 235051#L734-18 assume !(0 != activate_threads_~tmp___2~0); 235049#L734-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 235047#L345-18 assume !(1 == ~t4_pc~0); 235043#L345-20 is_transmit4_triggered_~__retres1~4 := 0; 235041#L356-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 235039#L357-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 235035#L742-18 assume !(0 != activate_threads_~tmp___3~0); 235032#L742-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 235030#L364-18 assume !(1 == ~t5_pc~0); 235028#L364-20 is_transmit5_triggered_~__retres1~5 := 0; 235025#L375-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 235023#L376-6 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 235021#L750-18 assume !(0 != activate_threads_~tmp___4~0); 235019#L750-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 235016#L639-3 assume !(1 == ~M_E~0); 235014#L639-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 235012#L644-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 235010#L649-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 235007#L654-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 235005#L659-3 assume !(1 == ~T5_E~0); 235003#L664-3 assume !(1 == ~E_1~0); 235001#L669-3 assume 1 == ~E_2~0;~E_2~0 := 2; 234999#L674-3 assume !(1 == ~E_3~0); 234997#L679-3 assume 1 == ~E_4~0;~E_4~0 := 2; 234995#L684-3 assume 1 == ~E_5~0;~E_5~0 := 2; 234993#L689-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 234990#L429-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 234988#L461-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 234986#L462-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 234984#L909 assume 0 == start_simulation_~tmp~3;start_simulation_~kernel_st~0 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 234985#L776 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 235099#L269-21 assume !(1 == ~m_pc~0); 235100#L269-23 is_master_triggered_~__retres1~0 := 0; 237816#L280-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 237815#L281-7 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 237814#L710-21 assume !(0 != activate_threads_~tmp~1); 237813#L710-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 237812#L288-21 assume !(1 == ~t1_pc~0); 237810#L288-23 is_transmit1_triggered_~__retres1~1 := 0; 237808#L299-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 237807#L300-7 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 237806#L718-21 assume !(0 != activate_threads_~tmp___0~0); 237805#L718-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 237803#L307-21 assume !(1 == ~t2_pc~0); 237800#L307-23 is_transmit2_triggered_~__retres1~2 := 0; 237798#L318-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 237796#L319-7 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 237794#L726-21 assume !(0 != activate_threads_~tmp___1~0); 237790#L726-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 237788#L326-21 assume !(1 == ~t3_pc~0); 237784#L326-23 is_transmit3_triggered_~__retres1~3 := 0; 237782#L337-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 237780#L338-7 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 237778#L734-21 assume !(0 != activate_threads_~tmp___2~0); 237776#L734-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 237774#L345-21 assume !(1 == ~t4_pc~0); 237770#L345-23 is_transmit4_triggered_~__retres1~4 := 0; 237768#L356-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 237766#L357-7 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 237764#L742-21 assume !(0 != activate_threads_~tmp___3~0); 237762#L742-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 237761#L364-21 assume !(1 == ~t5_pc~0); 237760#L364-23 is_transmit5_triggered_~__retres1~5 := 0; 237759#L375-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 237758#L376-7 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 237757#L750-21 assume !(0 != activate_threads_~tmp___4~0); 237755#L750-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 237753#L783 assume 1 == ~M_E~0;~M_E~0 := 2; 237754#L783-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 238848#L788-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 238846#L793-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 238844#L798-1 assume !(1 == ~T4_E~0); 238842#L803-1 assume !(1 == ~T5_E~0); 238840#L808-1 assume !(1 == ~E_1~0); 238838#L813-1 assume 1 == ~E_2~0;~E_2~0 := 2; 238836#L818-1 assume !(1 == ~E_3~0); 238834#L823-1 assume 1 == ~E_4~0;~E_4~0 := 2; 238833#L828-1 assume 1 == ~E_5~0;~E_5~0 := 2; 238830#L833-1 assume { :end_inline_reset_time_events } true; 238828#L909-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 238825#L429-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 238823#L461-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 238821#L462-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 238819#L864 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 238817#L871 stop_simulation_#res := stop_simulation_~__retres2~0; 238815#L872 start_simulation_#t~ret15 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 238813#L922 assume !(0 != start_simulation_~tmp___0~1); 232951#L890-3 [2018-11-18 16:15:57,314 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:57,314 INFO L82 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 11 times [2018-11-18 16:15:57,315 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:15:57,315 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:15:57,315 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:57,315 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:15:57,315 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:57,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 16:15:57,323 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 16:15:57,330 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:57,330 INFO L82 PathProgramCache]: Analyzing trace with hash 1583555592, now seen corresponding path program 1 times [2018-11-18 16:15:57,331 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:15:57,331 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:15:57,331 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:57,331 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:15:57,331 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:57,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:15:57,395 INFO L134 CoverageAnalysis]: Checked inductivity of 151 backedges. 17 proven. 0 refuted. 0 times theorem prover too weak. 134 trivial. 0 not checked. [2018-11-18 16:15:57,395 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 16:15:57,395 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 16:15:57,396 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 16:15:57,396 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 16:15:57,396 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 16:15:57,396 INFO L87 Difference]: Start difference. First operand 10861 states and 13877 transitions. cyclomatic complexity: 3024 Second operand 3 states. [2018-11-18 16:15:57,448 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:15:57,448 INFO L93 Difference]: Finished difference Result 17787 states and 22534 transitions. [2018-11-18 16:15:57,448 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 16:15:57,449 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17787 states and 22534 transitions. [2018-11-18 16:15:57,485 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 17572 [2018-11-18 16:15:57,510 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17787 states to 17787 states and 22534 transitions. [2018-11-18 16:15:57,510 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17787 [2018-11-18 16:15:57,519 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17787 [2018-11-18 16:15:57,519 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17787 states and 22534 transitions. [2018-11-18 16:15:57,528 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 16:15:57,528 INFO L705 BuchiCegarLoop]: Abstraction has 17787 states and 22534 transitions. [2018-11-18 16:15:57,536 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17787 states and 22534 transitions. [2018-11-18 16:15:57,610 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17787 to 17787. [2018-11-18 16:15:57,611 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17787 states. [2018-11-18 16:15:57,627 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17787 states to 17787 states and 22534 transitions. [2018-11-18 16:15:57,627 INFO L728 BuchiCegarLoop]: Abstraction has 17787 states and 22534 transitions. [2018-11-18 16:15:57,627 INFO L608 BuchiCegarLoop]: Abstraction has 17787 states and 22534 transitions. [2018-11-18 16:15:57,627 INFO L442 BuchiCegarLoop]: ======== Iteration 23============ [2018-11-18 16:15:57,627 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17787 states and 22534 transitions. [2018-11-18 16:15:57,659 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 17572 [2018-11-18 16:15:57,659 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 16:15:57,659 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 16:15:57,662 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:57,662 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:57,662 INFO L794 eck$LassoCheckResult]: Stem: 261508#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 261462#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 261206#L853 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 261207#L384 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 261145#L391 assume 1 == ~m_i~0;~m_st~0 := 0; 261146#L391-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 261159#L396-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 273720#L401-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 273719#L406-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 273718#L411-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 273717#L416-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 273716#L576 assume !(0 == ~M_E~0); 273715#L576-2 assume !(0 == ~T1_E~0); 273714#L581-1 assume !(0 == ~T2_E~0); 273713#L586-1 assume !(0 == ~T3_E~0); 273712#L591-1 assume !(0 == ~T4_E~0); 273711#L596-1 assume !(0 == ~T5_E~0); 273710#L601-1 assume !(0 == ~E_1~0); 273709#L606-1 assume !(0 == ~E_2~0); 273708#L611-1 assume !(0 == ~E_3~0); 273707#L616-1 assume !(0 == ~E_4~0); 273706#L621-1 assume !(0 == ~E_5~0); 273705#L626-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 273704#L269 assume !(1 == ~m_pc~0); 273703#L269-2 is_master_triggered_~__retres1~0 := 0; 273702#L280 is_master_triggered_#res := is_master_triggered_~__retres1~0; 273701#L281 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 273700#L710 assume !(0 != activate_threads_~tmp~1); 273699#L710-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 273697#L288 assume !(1 == ~t1_pc~0); 273696#L288-2 is_transmit1_triggered_~__retres1~1 := 0; 273695#L299 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 273694#L300 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 273693#L718 assume !(0 != activate_threads_~tmp___0~0); 273692#L718-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 273691#L307 assume !(1 == ~t2_pc~0); 273690#L307-2 is_transmit2_triggered_~__retres1~2 := 0; 273689#L318 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 273688#L319 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 273687#L726 assume !(0 != activate_threads_~tmp___1~0); 273686#L726-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 273685#L326 assume !(1 == ~t3_pc~0); 273683#L326-2 is_transmit3_triggered_~__retres1~3 := 0; 273682#L337 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 273681#L338 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 273680#L734 assume !(0 != activate_threads_~tmp___2~0); 273679#L734-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 273678#L345 assume !(1 == ~t4_pc~0); 273675#L345-2 is_transmit4_triggered_~__retres1~4 := 0; 273674#L356 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 273673#L357 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 273672#L742 assume !(0 != activate_threads_~tmp___3~0); 273670#L742-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 273669#L364 assume !(1 == ~t5_pc~0); 273668#L364-2 is_transmit5_triggered_~__retres1~5 := 0; 273665#L375 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 273663#L376 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 273661#L750 assume !(0 != activate_threads_~tmp___4~0); 273659#L750-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 261494#L639 assume !(1 == ~M_E~0); 261349#L639-2 assume !(1 == ~T1_E~0); 261165#L644-1 assume !(1 == ~T2_E~0); 261166#L649-1 assume !(1 == ~T3_E~0); 273627#L654-1 assume !(1 == ~T4_E~0); 273625#L659-1 assume !(1 == ~T5_E~0); 273622#L664-1 assume !(1 == ~E_1~0); 273620#L669-1 assume !(1 == ~E_2~0); 273618#L674-1 assume !(1 == ~E_3~0); 273617#L679-1 assume !(1 == ~E_4~0); 261311#L684-1 assume !(1 == ~E_5~0); 261312#L689-1 assume { :end_inline_reset_delta_events } true; 273531#L890-3 [2018-11-18 16:15:57,663 INFO L796 eck$LassoCheckResult]: Loop: 273531#L890-3 assume true; 273522#L890-1 assume !false; 272669#L891 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 272664#L551 assume true; 272662#L471-1 assume !false; 272661#L472 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 272659#L429 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 272657#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 272655#L462 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 272653#L476 assume 0 != eval_~tmp~0; 272650#L476-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 272647#L484 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1;assume { :begin_inline_master } true; 272648#L55 assume 0 == ~m_pc~0; 270484#L82 assume true; 273266#L66 assume !false; 273263#L67 ~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 273261#L269-3 assume !(1 == ~m_pc~0); 273259#L269-5 is_master_triggered_~__retres1~0 := 0; 273257#L280-1 is_master_triggered_#res := is_master_triggered_~__retres1~0; 273255#L281-1 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 273253#L710-3 assume !(0 != activate_threads_~tmp~1); 273251#L710-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 273249#L288-3 assume 1 == ~t1_pc~0; 273246#L289-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 273243#L299-1 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 273241#L300-1 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 273184#L718-3 assume !(0 != activate_threads_~tmp___0~0); 271993#L718-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 271991#L307-3 assume !(1 == ~t2_pc~0); 271989#L307-5 is_transmit2_triggered_~__retres1~2 := 0; 271987#L318-1 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 271985#L319-1 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 271982#L726-3 assume !(0 != activate_threads_~tmp___1~0); 271980#L726-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 270533#L326-3 assume !(1 == ~t3_pc~0); 270530#L326-5 is_transmit3_triggered_~__retres1~3 := 0; 270528#L337-1 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 270526#L338-1 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 270523#L734-3 assume !(0 != activate_threads_~tmp___2~0); 270521#L734-5 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 270515#L345-3 assume 1 == ~t4_pc~0; 270516#L346-1 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 270517#L356-1 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 271128#L357-1 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 270505#L742-3 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 270501#L742-5 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 270499#L364-3 assume !(1 == ~t5_pc~0); 270497#L364-5 is_transmit5_triggered_~__retres1~5 := 0; 270495#L375-1 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 270492#L376-1 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 270490#L750-3 assume !(0 != activate_threads_~tmp___4~0); 270488#L750-5 assume { :end_inline_activate_threads } true; 270482#L767 assume { :end_inline_immediate_notify } true;~E_1~0 := 2; 270480#L59 assume true; 269944#L74-1 assume !false; 269771#L75 ~m_pc~0 := 1;~m_st~0 := 2; 269625#L85 assume { :end_inline_master } true; 269624#L481 assume !(0 == ~t1_st~0); 269554#L495 assume !(0 == ~t2_st~0); 269552#L509 assume !(0 == ~t3_st~0); 270111#L523 assume !(0 == ~t4_st~0); 269321#L537 assume !(0 == ~t5_st~0); 269320#L551 assume true; 269797#L471-1 assume !false; 269051#L472 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 269032#L429 assume !(0 == ~m_st~0); 269029#L433 assume !(0 == ~t1_st~0); 269027#L437 assume !(0 == ~t2_st~0); 269025#L441 assume !(0 == ~t3_st~0); 269023#L445 assume !(0 == ~t4_st~0); 269020#L449 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 269018#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 269016#L462 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 269013#L476 assume !(0 != eval_~tmp~0); 269010#L566 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 269008#L384-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 269005#L576-3 assume !(0 == ~M_E~0); 269002#L576-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 268999#L581-3 assume !(0 == ~T2_E~0); 268997#L586-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 268993#L591-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 261677#L596-3 assume !(0 == ~T5_E~0); 261674#L601-3 assume !(0 == ~E_1~0); 261670#L606-3 assume 0 == ~E_2~0;~E_2~0 := 1; 261669#L611-3 assume !(0 == ~E_3~0); 261663#L616-3 assume 0 == ~E_4~0;~E_4~0 := 1; 261664#L621-3 assume !(0 == ~E_5~0); 268968#L626-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 268963#L269-18 assume 1 == ~m_pc~0; 268959#L270-6 assume !(1 == ~M_E~0); 268954#L269-20 is_master_triggered_~__retres1~0 := 0; 268950#L280-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 268944#L281-6 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 268940#L710-18 assume !(0 != activate_threads_~tmp~1); 268936#L710-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 268932#L288-18 assume !(1 == ~t1_pc~0); 268927#L288-20 is_transmit1_triggered_~__retres1~1 := 0; 268923#L299-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 268919#L300-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 268914#L718-18 assume !(0 != activate_threads_~tmp___0~0); 268909#L718-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 268904#L307-18 assume !(1 == ~t2_pc~0); 268897#L307-20 is_transmit2_triggered_~__retres1~2 := 0; 268892#L318-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 268888#L319-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 268884#L726-18 assume !(0 != activate_threads_~tmp___1~0); 268881#L726-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 268878#L326-18 assume !(1 == ~t3_pc~0); 268873#L326-20 is_transmit3_triggered_~__retres1~3 := 0; 268868#L337-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 268863#L338-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 268859#L734-18 assume !(0 != activate_threads_~tmp___2~0); 268854#L734-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 268850#L345-18 assume 1 == ~t4_pc~0; 268845#L346-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 268838#L356-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 268833#L357-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 268828#L742-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 268824#L742-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 268820#L364-18 assume !(1 == ~t5_pc~0); 268817#L364-20 is_transmit5_triggered_~__retres1~5 := 0; 268786#L375-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 268782#L376-6 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 268778#L750-18 assume !(0 != activate_threads_~tmp___4~0); 268776#L750-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 267524#L639-3 assume !(1 == ~M_E~0); 267519#L639-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 267517#L644-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 267515#L649-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 267513#L654-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 267511#L659-3 assume !(1 == ~T5_E~0); 267509#L664-3 assume !(1 == ~E_1~0); 267506#L669-3 assume 1 == ~E_2~0;~E_2~0 := 2; 267504#L674-3 assume !(1 == ~E_3~0); 267502#L679-3 assume 1 == ~E_4~0;~E_4~0 := 2; 267500#L684-3 assume 1 == ~E_5~0;~E_5~0 := 2; 267498#L689-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 267496#L429-1 assume !(0 == ~m_st~0); 266542#L433-1 assume !(0 == ~t1_st~0); 267491#L437-1 assume 0 == ~t2_st~0;exists_runnable_thread_~__retres1~6 := 1; 267485#L461-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 267483#L462-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 267480#L909 assume 0 == start_simulation_~tmp~3;start_simulation_~kernel_st~0 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 267467#L776 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 267463#L269-21 assume 1 == ~m_pc~0; 267456#L270-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 267446#L280-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 267439#L281-7 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 267434#L710-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 267433#L710-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 267432#L288-21 assume !(1 == ~t1_pc~0); 267430#L288-23 is_transmit1_triggered_~__retres1~1 := 0; 267429#L299-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 267428#L300-7 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 267426#L718-21 assume !(0 != activate_threads_~tmp___0~0); 267424#L718-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 267421#L307-21 assume !(1 == ~t2_pc~0); 267419#L307-23 is_transmit2_triggered_~__retres1~2 := 0; 267417#L318-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 267415#L319-7 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 267413#L726-21 assume !(0 != activate_threads_~tmp___1~0); 267411#L726-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 267409#L326-21 assume !(1 == ~t3_pc~0); 267406#L326-23 is_transmit3_triggered_~__retres1~3 := 0; 267404#L337-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 267402#L338-7 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 267400#L734-21 assume !(0 != activate_threads_~tmp___2~0); 267398#L734-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 267386#L345-21 assume 1 == ~t4_pc~0; 267374#L346-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 267366#L356-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 267357#L357-7 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 267337#L742-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 267329#L742-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 267322#L364-21 assume !(1 == ~t5_pc~0); 267316#L364-23 is_transmit5_triggered_~__retres1~5 := 0; 267309#L375-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 267306#L376-7 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 267304#L750-21 assume !(0 != activate_threads_~tmp___4~0); 267302#L750-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 267299#L783 assume !(1 == ~M_E~0); 267297#L783-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 267295#L788-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 267293#L793-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 267291#L798-1 assume !(1 == ~T4_E~0); 267289#L803-1 assume !(1 == ~T5_E~0); 267288#L808-1 assume !(1 == ~E_1~0); 267286#L813-1 assume 1 == ~E_2~0;~E_2~0 := 2; 267284#L818-1 assume !(1 == ~E_3~0); 267282#L823-1 assume 1 == ~E_4~0;~E_4~0 := 2; 266638#L828-1 assume 1 == ~E_5~0;~E_5~0 := 2; 266450#L833-1 assume { :end_inline_reset_time_events } true; 266447#L909-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 266444#L429-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 266442#L461-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 266440#L462-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 266438#L864 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 266436#L871 stop_simulation_#res := stop_simulation_~__retres2~0; 266434#L872 start_simulation_#t~ret15 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 266432#L922 assume !(0 != start_simulation_~tmp___0~1); 266431#L890-3 assume true; 266430#L890-1 assume !false; 266426#L891 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 266421#L551 assume true; 266419#L471-1 assume !false; 266417#L472 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 266414#L429 assume !(0 == ~m_st~0); 266415#L433 assume !(0 == ~t1_st~0); 267264#L437 assume !(0 == ~t2_st~0); 267262#L441 assume !(0 == ~t3_st~0); 267260#L445 assume !(0 == ~t4_st~0); 267258#L449 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6 := 0; 267255#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 267253#L462 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 267251#L476 assume !(0 != eval_~tmp~0); 267248#L566 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 267246#L384-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 267244#L576-3 assume 0 == ~M_E~0;~M_E~0 := 1; 267242#L576-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 267239#L581-3 assume !(0 == ~T2_E~0); 267237#L586-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 267235#L591-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 267232#L596-3 assume !(0 == ~T5_E~0); 267230#L601-3 assume !(0 == ~E_1~0); 267228#L606-3 assume 0 == ~E_2~0;~E_2~0 := 1; 267226#L611-3 assume !(0 == ~E_3~0); 267224#L616-3 assume 0 == ~E_4~0;~E_4~0 := 1; 267222#L621-3 assume !(0 == ~E_5~0); 267220#L626-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 267213#L269-18 assume 1 == ~m_pc~0; 267207#L270-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 267201#L280-6 is_master_triggered_#res := is_master_triggered_~__retres1~0; 267195#L281-6 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 267189#L710-18 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 267182#L710-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 267174#L288-18 assume !(1 == ~t1_pc~0); 267165#L288-20 is_transmit1_triggered_~__retres1~1 := 0; 267156#L299-6 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 267150#L300-6 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 267143#L718-18 assume !(0 != activate_threads_~tmp___0~0); 267136#L718-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 267130#L307-18 assume !(1 == ~t2_pc~0); 267123#L307-20 is_transmit2_triggered_~__retres1~2 := 0; 267115#L318-6 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 267109#L319-6 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 267096#L726-18 assume !(0 != activate_threads_~tmp___1~0); 267072#L726-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 267044#L326-18 assume !(1 == ~t3_pc~0); 267036#L326-20 is_transmit3_triggered_~__retres1~3 := 0; 267030#L337-6 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 267023#L338-6 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 267017#L734-18 assume !(0 != activate_threads_~tmp___2~0); 267012#L734-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 267007#L345-18 assume 1 == ~t4_pc~0; 267000#L346-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 266994#L356-6 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 266985#L357-6 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 266977#L742-18 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 266968#L742-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 266962#L364-18 assume !(1 == ~t5_pc~0); 266581#L364-20 is_transmit5_triggered_~__retres1~5 := 0; 266577#L375-6 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 266575#L376-6 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 266573#L750-18 assume !(0 != activate_threads_~tmp___4~0); 266571#L750-20 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 266567#L639-3 assume 1 == ~M_E~0;~M_E~0 := 2; 266565#L639-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 266563#L644-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 266561#L649-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 266559#L654-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 266557#L659-3 assume !(1 == ~T5_E~0); 266555#L664-3 assume !(1 == ~E_1~0); 266553#L669-3 assume 1 == ~E_2~0;~E_2~0 := 2; 266551#L674-3 assume !(1 == ~E_3~0); 266549#L679-3 assume 1 == ~E_4~0;~E_4~0 := 2; 266546#L684-3 assume 1 == ~E_5~0;~E_5~0 := 2; 266544#L689-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 266541#L429-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 266539#L461-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 266537#L462-1 start_simulation_#t~ret14 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret14;havoc start_simulation_#t~ret14; 265112#L909 assume 0 == start_simulation_~tmp~3;start_simulation_~kernel_st~0 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 265110#L776 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 265107#L269-21 assume !(1 == ~m_pc~0); 265105#L269-23 is_master_triggered_~__retres1~0 := 0; 265103#L280-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 265101#L281-7 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 265100#L710-21 assume !(0 != activate_threads_~tmp~1); 265099#L710-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 265095#L288-21 assume !(1 == ~t1_pc~0); 265092#L288-23 is_transmit1_triggered_~__retres1~1 := 0; 265090#L299-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 265088#L300-7 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 265087#L718-21 assume !(0 != activate_threads_~tmp___0~0); 265086#L718-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 265085#L307-21 assume !(1 == ~t2_pc~0); 265084#L307-23 is_transmit2_triggered_~__retres1~2 := 0; 265083#L318-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 265082#L319-7 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 265080#L726-21 assume !(0 != activate_threads_~tmp___1~0); 265079#L726-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 265078#L326-21 assume !(1 == ~t3_pc~0); 265076#L326-23 is_transmit3_triggered_~__retres1~3 := 0; 265075#L337-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 265074#L338-7 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 265072#L734-21 assume !(0 != activate_threads_~tmp___2~0); 265071#L734-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 265070#L345-21 assume 1 == ~t4_pc~0; 265068#L346-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 265069#L356-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 265073#L357-7 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 265060#L742-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 265058#L742-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 265056#L364-21 assume !(1 == ~t5_pc~0); 265054#L364-23 is_transmit5_triggered_~__retres1~5 := 0; 265052#L375-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 265049#L376-7 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 265047#L750-21 assume !(0 != activate_threads_~tmp___4~0); 265045#L750-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 265042#L783 assume 1 == ~M_E~0;~M_E~0 := 2; 265043#L783-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 273614#L788-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 273612#L793-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 273610#L798-1 assume !(1 == ~T4_E~0); 273608#L803-1 assume !(1 == ~T5_E~0); 273606#L808-1 assume !(1 == ~E_1~0); 273604#L813-1 assume 1 == ~E_2~0;~E_2~0 := 2; 273602#L818-1 assume !(1 == ~E_3~0); 273600#L823-1 assume 1 == ~E_4~0;~E_4~0 := 2; 273598#L828-1 assume 1 == ~E_5~0;~E_5~0 := 2; 273596#L833-1 assume { :end_inline_reset_time_events } true; 273594#L909-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret13, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 273590#L429-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 273588#L461-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 273586#L462-2 stop_simulation_#t~ret13 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret13;havoc stop_simulation_#t~ret13; 273584#L864 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 273582#L871 stop_simulation_#res := stop_simulation_~__retres2~0; 273553#L872 start_simulation_#t~ret15 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret15;havoc start_simulation_#t~ret15; 273540#L922 assume !(0 != start_simulation_~tmp___0~1); 273531#L890-3 [2018-11-18 16:15:57,663 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:57,663 INFO L82 PathProgramCache]: Analyzing trace with hash -1177503526, now seen corresponding path program 1 times [2018-11-18 16:15:57,663 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:15:57,663 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:15:57,664 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:57,664 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:15:57,664 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:57,666 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:15:57,702 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:15:57,702 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 16:15:57,702 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 16:15:57,702 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 16:15:57,703 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:57,703 INFO L82 PathProgramCache]: Analyzing trace with hash 150305082, now seen corresponding path program 1 times [2018-11-18 16:15:57,703 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:15:57,703 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:15:57,703 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:57,703 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:15:57,704 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:57,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:15:57,765 INFO L134 CoverageAnalysis]: Checked inductivity of 151 backedges. 17 proven. 0 refuted. 0 times theorem prover too weak. 134 trivial. 0 not checked. [2018-11-18 16:15:57,765 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 16:15:57,765 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-11-18 16:15:57,766 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 16:15:57,766 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 16:15:57,766 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 16:15:57,766 INFO L87 Difference]: Start difference. First operand 17787 states and 22534 transitions. cyclomatic complexity: 4755 Second operand 3 states. [2018-11-18 16:15:57,799 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:15:57,800 INFO L93 Difference]: Finished difference Result 17716 states and 22443 transitions. [2018-11-18 16:15:57,800 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 16:15:57,800 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17716 states and 22443 transitions. [2018-11-18 16:15:57,915 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 17572 [2018-11-18 16:15:57,933 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17716 states to 17716 states and 22443 transitions. [2018-11-18 16:15:57,934 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17716 [2018-11-18 16:15:57,940 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17716 [2018-11-18 16:15:57,940 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17716 states and 22443 transitions. [2018-11-18 16:15:57,946 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 16:15:57,946 INFO L705 BuchiCegarLoop]: Abstraction has 17716 states and 22443 transitions. [2018-11-18 16:15:57,953 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17716 states and 22443 transitions. [2018-11-18 16:15:58,022 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17716 to 17716. [2018-11-18 16:15:58,022 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17716 states. [2018-11-18 16:15:58,038 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17716 states to 17716 states and 22443 transitions. [2018-11-18 16:15:58,039 INFO L728 BuchiCegarLoop]: Abstraction has 17716 states and 22443 transitions. [2018-11-18 16:15:58,039 INFO L608 BuchiCegarLoop]: Abstraction has 17716 states and 22443 transitions. [2018-11-18 16:15:58,039 INFO L442 BuchiCegarLoop]: ======== Iteration 24============ [2018-11-18 16:15:58,039 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17716 states and 22443 transitions. [2018-11-18 16:15:58,067 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 17572 [2018-11-18 16:15:58,067 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 16:15:58,067 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 16:15:58,068 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:58,068 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:58,068 INFO L794 eck$LassoCheckResult]: Stem: 297013#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 296971#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 296718#L853 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 296719#L384 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 296659#L391 assume 1 == ~m_i~0;~m_st~0 := 0; 296660#L391-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 296670#L396-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 296766#L401-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 296767#L406-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 296626#L411-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 296627#L416-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 296632#L576 assume !(0 == ~M_E~0); 296616#L576-2 assume !(0 == ~T1_E~0); 296617#L581-1 assume !(0 == ~T2_E~0); 296903#L586-1 assume !(0 == ~T3_E~0); 296904#L591-1 assume !(0 == ~T4_E~0); 296801#L596-1 assume !(0 == ~T5_E~0); 296802#L601-1 assume !(0 == ~E_1~0); 296858#L606-1 assume !(0 == ~E_2~0); 296680#L611-1 assume !(0 == ~E_3~0); 296681#L616-1 assume !(0 == ~E_4~0); 296556#L621-1 assume !(0 == ~E_5~0); 296557#L626-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 296761#L269 assume !(1 == ~m_pc~0); 296751#L269-2 is_master_triggered_~__retres1~0 := 0; 296752#L280 is_master_triggered_#res := is_master_triggered_~__retres1~0; 296671#L281 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 296672#L710 assume !(0 != activate_threads_~tmp~1); 296673#L710-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 296674#L288 assume !(1 == ~t1_pc~0); 296803#L288-2 is_transmit1_triggered_~__retres1~1 := 0; 296807#L299 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 296808#L300 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 296918#L718 assume !(0 != activate_threads_~tmp___0~0); 296928#L718-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 296929#L307 assume !(1 == ~t2_pc~0); 296974#L307-2 is_transmit2_triggered_~__retres1~2 := 0; 296972#L318 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 296973#L319 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 297053#L726 assume !(0 != activate_threads_~tmp___1~0); 297054#L726-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 297055#L326 assume !(1 == ~t3_pc~0); 297077#L326-2 is_transmit3_triggered_~__retres1~3 := 0; 297078#L337 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 297091#L338 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 297131#L734 assume !(0 != activate_threads_~tmp___2~0); 297140#L734-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 296602#L345 assume !(1 == ~t4_pc~0); 296603#L345-2 is_transmit4_triggered_~__retres1~4 := 0; 296600#L356 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 296601#L357 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 296574#L742 assume !(0 != activate_threads_~tmp___3~0); 296549#L742-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 296550#L364 assume !(1 == ~t5_pc~0); 296857#L364-2 is_transmit5_triggered_~__retres1~5 := 0; 296855#L375 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 296773#L376 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 296774#L750 assume !(0 != activate_threads_~tmp___4~0); 296812#L750-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 296818#L639 assume !(1 == ~M_E~0); 296859#L639-2 assume !(1 == ~T1_E~0); 296675#L644-1 assume !(1 == ~T2_E~0); 296676#L649-1 assume !(1 == ~T3_E~0); 296553#L654-1 assume !(1 == ~T4_E~0); 296554#L659-1 assume !(1 == ~T5_E~0); 296630#L664-1 assume !(1 == ~E_1~0); 296631#L669-1 assume !(1 == ~E_2~0); 296930#L674-1 assume !(1 == ~E_3~0); 296931#L679-1 assume !(1 == ~E_4~0); 296820#L684-1 assume !(1 == ~E_5~0); 296821#L689-1 assume { :end_inline_reset_delta_events } true; 297096#L890-3 assume true; 307318#L890-1 assume !false; 307316#L891 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 307311#L551 [2018-11-18 16:15:58,068 INFO L796 eck$LassoCheckResult]: Loop: 307311#L551 assume true; 307309#L471-1 assume !false; 307305#L472 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 307302#L429 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 307300#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 307298#L462 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 307295#L476 assume 0 != eval_~tmp~0; 307292#L476-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 307290#L484 assume !(0 != eval_~tmp_ndt_1~0); 306931#L481 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 306924#L498 assume !(0 != eval_~tmp_ndt_2~0); 306918#L495 assume !(0 == ~t2_st~0); 306911#L509 assume !(0 == ~t3_st~0); 309504#L523 assume !(0 == ~t4_st~0); 307315#L537 assume !(0 == ~t5_st~0); 307311#L551 [2018-11-18 16:15:58,068 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:58,069 INFO L82 PathProgramCache]: Analyzing trace with hash -1516689527, now seen corresponding path program 1 times [2018-11-18 16:15:58,069 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:15:58,069 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:15:58,069 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:58,069 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:15:58,070 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:58,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 16:15:58,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 16:15:58,092 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:58,092 INFO L82 PathProgramCache]: Analyzing trace with hash -1145637537, now seen corresponding path program 1 times [2018-11-18 16:15:58,092 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:15:58,092 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:15:58,093 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:58,096 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:15:58,096 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:58,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 16:15:58,099 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 16:15:58,100 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:58,100 INFO L82 PathProgramCache]: Analyzing trace with hash 524864727, now seen corresponding path program 1 times [2018-11-18 16:15:58,101 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:15:58,101 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:15:58,102 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:58,102 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:15:58,102 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:58,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:15:58,136 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:15:58,136 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 16:15:58,136 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 16:15:58,209 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 16:15:58,210 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 16:15:58,210 INFO L87 Difference]: Start difference. First operand 17716 states and 22443 transitions. cyclomatic complexity: 4735 Second operand 3 states. [2018-11-18 16:15:58,372 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:15:58,373 INFO L93 Difference]: Finished difference Result 20780 states and 26208 transitions. [2018-11-18 16:15:58,373 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 16:15:58,373 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 20780 states and 26208 transitions. [2018-11-18 16:15:58,418 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 20448 [2018-11-18 16:15:58,448 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 20780 states to 20780 states and 26208 transitions. [2018-11-18 16:15:58,448 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20780 [2018-11-18 16:15:58,458 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20780 [2018-11-18 16:15:58,458 INFO L73 IsDeterministic]: Start isDeterministic. Operand 20780 states and 26208 transitions. [2018-11-18 16:15:58,468 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 16:15:58,469 INFO L705 BuchiCegarLoop]: Abstraction has 20780 states and 26208 transitions. [2018-11-18 16:15:58,478 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20780 states and 26208 transitions. [2018-11-18 16:15:58,580 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20780 to 19724. [2018-11-18 16:15:58,580 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19724 states. [2018-11-18 16:15:58,601 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19724 states to 19724 states and 24912 transitions. [2018-11-18 16:15:58,602 INFO L728 BuchiCegarLoop]: Abstraction has 19724 states and 24912 transitions. [2018-11-18 16:15:58,602 INFO L608 BuchiCegarLoop]: Abstraction has 19724 states and 24912 transitions. [2018-11-18 16:15:58,602 INFO L442 BuchiCegarLoop]: ======== Iteration 25============ [2018-11-18 16:15:58,602 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19724 states and 24912 transitions. [2018-11-18 16:15:58,648 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 19392 [2018-11-18 16:15:58,648 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 16:15:58,648 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 16:15:58,649 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:58,649 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:58,649 INFO L794 eck$LassoCheckResult]: Stem: 335541#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 335487#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 335222#L853 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 335223#L384 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 335165#L391 assume 1 == ~m_i~0;~m_st~0 := 0; 335166#L391-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 335174#L396-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 335273#L401-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 335274#L406-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 335128#L411-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 335129#L416-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 335134#L576 assume !(0 == ~M_E~0); 335117#L576-2 assume !(0 == ~T1_E~0); 335118#L581-1 assume !(0 == ~T2_E~0); 335417#L586-1 assume !(0 == ~T3_E~0); 335418#L591-1 assume !(0 == ~T4_E~0); 335308#L596-1 assume !(0 == ~T5_E~0); 335309#L601-1 assume !(0 == ~E_1~0); 335367#L606-1 assume !(0 == ~E_2~0); 335185#L611-1 assume !(0 == ~E_3~0); 335186#L616-1 assume !(0 == ~E_4~0); 335060#L621-1 assume !(0 == ~E_5~0); 335061#L626-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 335268#L269 assume !(1 == ~m_pc~0); 335258#L269-2 is_master_triggered_~__retres1~0 := 0; 335259#L280 is_master_triggered_#res := is_master_triggered_~__retres1~0; 335176#L281 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 335177#L710 assume !(0 != activate_threads_~tmp~1); 335178#L710-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 335179#L288 assume !(1 == ~t1_pc~0); 335310#L288-2 is_transmit1_triggered_~__retres1~1 := 0; 335313#L299 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 335314#L300 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 335432#L718 assume !(0 != activate_threads_~tmp___0~0); 335439#L718-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 335440#L307 assume !(1 == ~t2_pc~0); 335490#L307-2 is_transmit2_triggered_~__retres1~2 := 0; 335488#L318 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 335489#L319 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 335575#L726 assume !(0 != activate_threads_~tmp___1~0); 335576#L726-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 335577#L326 assume !(1 == ~t3_pc~0); 335599#L326-2 is_transmit3_triggered_~__retres1~3 := 0; 335600#L337 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 335613#L338 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 335650#L734 assume !(0 != activate_threads_~tmp___2~0); 335659#L734-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 335105#L345 assume !(1 == ~t4_pc~0); 335106#L345-2 is_transmit4_triggered_~__retres1~4 := 0; 335103#L356 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 335104#L357 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 335078#L742 assume !(0 != activate_threads_~tmp___3~0); 335053#L742-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 335054#L364 assume !(1 == ~t5_pc~0); 335365#L364-2 is_transmit5_triggered_~__retres1~5 := 0; 335363#L375 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 335280#L376 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 335281#L750 assume !(0 != activate_threads_~tmp___4~0); 335318#L750-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 335324#L639 assume !(1 == ~M_E~0); 335368#L639-2 assume !(1 == ~T1_E~0); 335181#L644-1 assume !(1 == ~T2_E~0); 335182#L649-1 assume !(1 == ~T3_E~0); 335057#L654-1 assume !(1 == ~T4_E~0); 335058#L659-1 assume !(1 == ~T5_E~0); 335132#L664-1 assume !(1 == ~E_1~0); 335133#L669-1 assume !(1 == ~E_2~0); 335442#L674-1 assume !(1 == ~E_3~0); 335443#L679-1 assume !(1 == ~E_4~0); 335326#L684-1 assume !(1 == ~E_5~0); 335327#L689-1 assume { :end_inline_reset_delta_events } true; 335619#L890-3 assume true; 348130#L890-1 assume !false; 348124#L891 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 348118#L551 [2018-11-18 16:15:58,649 INFO L796 eck$LassoCheckResult]: Loop: 348118#L551 assume true; 348115#L471-1 assume !false; 348112#L472 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 348109#L429 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 348107#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 348105#L462 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 348103#L476 assume 0 != eval_~tmp~0; 348100#L476-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 348097#L484 assume !(0 != eval_~tmp_ndt_1~0); 348098#L481 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 348164#L498 assume !(0 != eval_~tmp_ndt_2~0); 348155#L495 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 348139#L512 assume !(0 != eval_~tmp_ndt_3~0); 348135#L509 assume !(0 == ~t3_st~0); 348129#L523 assume !(0 == ~t4_st~0); 348123#L537 assume !(0 == ~t5_st~0); 348118#L551 [2018-11-18 16:15:58,649 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:58,650 INFO L82 PathProgramCache]: Analyzing trace with hash -1516689527, now seen corresponding path program 2 times [2018-11-18 16:15:58,650 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:15:58,650 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:15:58,650 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:58,651 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:15:58,651 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:58,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 16:15:58,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 16:15:58,668 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:58,668 INFO L82 PathProgramCache]: Analyzing trace with hash -1325098298, now seen corresponding path program 1 times [2018-11-18 16:15:58,669 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:15:58,669 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:15:58,669 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:58,669 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:15:58,669 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:58,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 16:15:58,672 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 16:15:58,673 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:58,673 INFO L82 PathProgramCache]: Analyzing trace with hash -1079135666, now seen corresponding path program 1 times [2018-11-18 16:15:58,673 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:15:58,673 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:15:58,674 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:58,674 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:15:58,674 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:58,678 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:15:58,700 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:15:58,700 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 16:15:58,700 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 16:15:58,768 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 16:15:58,768 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 16:15:58,769 INFO L87 Difference]: Start difference. First operand 19724 states and 24912 transitions. cyclomatic complexity: 5198 Second operand 3 states. [2018-11-18 16:15:58,828 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:15:58,828 INFO L93 Difference]: Finished difference Result 32098 states and 40377 transitions. [2018-11-18 16:15:58,828 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 16:15:58,828 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 32098 states and 40377 transitions. [2018-11-18 16:15:58,901 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 31514 [2018-11-18 16:15:58,945 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 32098 states to 32098 states and 40377 transitions. [2018-11-18 16:15:58,945 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 32098 [2018-11-18 16:15:58,960 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 32098 [2018-11-18 16:15:58,961 INFO L73 IsDeterministic]: Start isDeterministic. Operand 32098 states and 40377 transitions. [2018-11-18 16:15:58,977 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 16:15:58,977 INFO L705 BuchiCegarLoop]: Abstraction has 32098 states and 40377 transitions. [2018-11-18 16:15:58,992 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32098 states and 40377 transitions. [2018-11-18 16:15:59,147 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32098 to 32098. [2018-11-18 16:15:59,147 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 32098 states. [2018-11-18 16:15:59,174 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32098 states to 32098 states and 40377 transitions. [2018-11-18 16:15:59,174 INFO L728 BuchiCegarLoop]: Abstraction has 32098 states and 40377 transitions. [2018-11-18 16:15:59,174 INFO L608 BuchiCegarLoop]: Abstraction has 32098 states and 40377 transitions. [2018-11-18 16:15:59,174 INFO L442 BuchiCegarLoop]: ======== Iteration 26============ [2018-11-18 16:15:59,174 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 32098 states and 40377 transitions. [2018-11-18 16:15:59,238 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 31514 [2018-11-18 16:15:59,238 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 16:15:59,238 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 16:15:59,239 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:59,239 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:15:59,239 INFO L794 eck$LassoCheckResult]: Stem: 387384#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 387334#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 387051#L853 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 387052#L384 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 386989#L391 assume 1 == ~m_i~0;~m_st~0 := 0; 386990#L391-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 387003#L396-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 387106#L401-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 387107#L406-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 386959#L411-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 386960#L416-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 386965#L576 assume !(0 == ~M_E~0); 386946#L576-2 assume !(0 == ~T1_E~0); 386947#L581-1 assume !(0 == ~T2_E~0); 387255#L586-1 assume !(0 == ~T3_E~0); 387256#L591-1 assume !(0 == ~T4_E~0); 387142#L596-1 assume !(0 == ~T5_E~0); 387143#L601-1 assume !(0 == ~E_1~0); 387203#L606-1 assume !(0 == ~E_2~0); 387014#L611-1 assume !(0 == ~E_3~0); 387015#L616-1 assume !(0 == ~E_4~0); 386890#L621-1 assume !(0 == ~E_5~0); 386891#L626-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 387101#L269 assume !(1 == ~m_pc~0); 387085#L269-2 is_master_triggered_~__retres1~0 := 0; 387086#L280 is_master_triggered_#res := is_master_triggered_~__retres1~0; 387004#L281 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 387005#L710 assume !(0 != activate_threads_~tmp~1); 387007#L710-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 387008#L288 assume !(1 == ~t1_pc~0); 387144#L288-2 is_transmit1_triggered_~__retres1~1 := 0; 387146#L299 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 387147#L300 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 387270#L718 assume !(0 != activate_threads_~tmp___0~0); 387279#L718-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 387281#L307 assume !(1 == ~t2_pc~0); 387337#L307-2 is_transmit2_triggered_~__retres1~2 := 0; 387335#L318 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 387336#L319 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 387417#L726 assume !(0 != activate_threads_~tmp___1~0); 387418#L726-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 387419#L326 assume !(1 == ~t3_pc~0); 387448#L326-2 is_transmit3_triggered_~__retres1~3 := 0; 387449#L337 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 387462#L338 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 387516#L734 assume !(0 != activate_threads_~tmp___2~0); 387533#L734-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 386935#L345 assume !(1 == ~t4_pc~0); 386936#L345-2 is_transmit4_triggered_~__retres1~4 := 0; 386933#L356 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 386934#L357 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 386908#L742 assume !(0 != activate_threads_~tmp___3~0); 386880#L742-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 386881#L364 assume !(1 == ~t5_pc~0); 387199#L364-2 is_transmit5_triggered_~__retres1~5 := 0; 387196#L375 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 387114#L376 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 387115#L750 assume !(0 != activate_threads_~tmp___4~0); 387154#L750-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 387160#L639 assume !(1 == ~M_E~0); 387204#L639-2 assume !(1 == ~T1_E~0); 387009#L644-1 assume !(1 == ~T2_E~0); 387010#L649-1 assume !(1 == ~T3_E~0); 386887#L654-1 assume !(1 == ~T4_E~0); 386888#L659-1 assume !(1 == ~T5_E~0); 386963#L664-1 assume !(1 == ~E_1~0); 386964#L669-1 assume !(1 == ~E_2~0); 387282#L674-1 assume !(1 == ~E_3~0); 387283#L679-1 assume !(1 == ~E_4~0); 387161#L684-1 assume !(1 == ~E_5~0); 387162#L689-1 assume { :end_inline_reset_delta_events } true; 387469#L890-3 assume true; 405127#L890-1 assume !false; 405029#L891 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 405022#L551 [2018-11-18 16:15:59,239 INFO L796 eck$LassoCheckResult]: Loop: 405022#L551 assume true; 405020#L471-1 assume !false; 405017#L472 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 405014#L429 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 405012#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 405010#L462 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 403169#L476 assume 0 != eval_~tmp~0; 403162#L476-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 403136#L484 assume !(0 != eval_~tmp_ndt_1~0); 403124#L481 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 403121#L498 assume !(0 != eval_~tmp_ndt_2~0); 403117#L495 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 403110#L512 assume !(0 != eval_~tmp_ndt_3~0); 403111#L509 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 405130#L526 assume !(0 != eval_~tmp_ndt_4~0); 405098#L523 assume !(0 == ~t4_st~0); 405028#L537 assume !(0 == ~t5_st~0); 405022#L551 [2018-11-18 16:15:59,240 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:59,240 INFO L82 PathProgramCache]: Analyzing trace with hash -1516689527, now seen corresponding path program 3 times [2018-11-18 16:15:59,240 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:15:59,240 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:15:59,241 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:59,241 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:15:59,241 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:59,247 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 16:15:59,252 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 16:15:59,265 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:59,265 INFO L82 PathProgramCache]: Analyzing trace with hash 1866145095, now seen corresponding path program 1 times [2018-11-18 16:15:59,266 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:15:59,266 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:15:59,269 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:59,270 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:15:59,270 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:59,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 16:15:59,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 16:15:59,275 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:15:59,275 INFO L82 PathProgramCache]: Analyzing trace with hash 901052095, now seen corresponding path program 1 times [2018-11-18 16:15:59,275 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:15:59,275 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:15:59,276 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:59,276 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:15:59,276 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:15:59,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:15:59,319 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:15:59,319 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 16:15:59,319 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 16:15:59,456 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 16:15:59,456 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 16:15:59,456 INFO L87 Difference]: Start difference. First operand 32098 states and 40377 transitions. cyclomatic complexity: 8289 Second operand 3 states. [2018-11-18 16:15:59,699 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:15:59,699 INFO L93 Difference]: Finished difference Result 56636 states and 71043 transitions. [2018-11-18 16:15:59,699 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 16:15:59,699 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 56636 states and 71043 transitions. [2018-11-18 16:15:59,836 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 55548 [2018-11-18 16:15:59,917 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 56636 states to 56636 states and 71043 transitions. [2018-11-18 16:15:59,918 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 56636 [2018-11-18 16:15:59,939 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 56636 [2018-11-18 16:15:59,939 INFO L73 IsDeterministic]: Start isDeterministic. Operand 56636 states and 71043 transitions. [2018-11-18 16:15:59,956 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 16:15:59,956 INFO L705 BuchiCegarLoop]: Abstraction has 56636 states and 71043 transitions. [2018-11-18 16:15:59,974 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 56636 states and 71043 transitions. [2018-11-18 16:16:00,213 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 56636 to 54660. [2018-11-18 16:16:00,213 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54660 states. [2018-11-18 16:16:00,270 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54660 states to 54660 states and 68839 transitions. [2018-11-18 16:16:00,270 INFO L728 BuchiCegarLoop]: Abstraction has 54660 states and 68839 transitions. [2018-11-18 16:16:00,270 INFO L608 BuchiCegarLoop]: Abstraction has 54660 states and 68839 transitions. [2018-11-18 16:16:00,270 INFO L442 BuchiCegarLoop]: ======== Iteration 27============ [2018-11-18 16:16:00,270 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 54660 states and 68839 transitions. [2018-11-18 16:16:00,375 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 53572 [2018-11-18 16:16:00,375 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 16:16:00,375 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 16:16:00,376 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:16:00,376 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:16:00,376 INFO L794 eck$LassoCheckResult]: Stem: 476133#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 476083#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 475802#L853 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 475803#L384 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 475740#L391 assume 1 == ~m_i~0;~m_st~0 := 0; 475741#L391-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 475755#L396-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 475858#L401-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 475859#L406-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 475707#L411-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 475708#L416-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 475713#L576 assume !(0 == ~M_E~0); 475694#L576-2 assume !(0 == ~T1_E~0); 475695#L581-1 assume !(0 == ~T2_E~0); 476010#L586-1 assume !(0 == ~T3_E~0); 476011#L591-1 assume !(0 == ~T4_E~0); 475894#L596-1 assume !(0 == ~T5_E~0); 475895#L601-1 assume !(0 == ~E_1~0); 475959#L606-1 assume !(0 == ~E_2~0); 475765#L611-1 assume !(0 == ~E_3~0); 475766#L616-1 assume !(0 == ~E_4~0); 475633#L621-1 assume !(0 == ~E_5~0); 475634#L626-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 475854#L269 assume !(1 == ~m_pc~0); 475843#L269-2 is_master_triggered_~__retres1~0 := 0; 475844#L280 is_master_triggered_#res := is_master_triggered_~__retres1~0; 475756#L281 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 475757#L710 assume !(0 != activate_threads_~tmp~1); 475758#L710-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 475759#L288 assume !(1 == ~t1_pc~0); 475896#L288-2 is_transmit1_triggered_~__retres1~1 := 0; 475898#L299 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 475899#L300 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 476025#L718 assume !(0 != activate_threads_~tmp___0~0); 476034#L718-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 476035#L307 assume !(1 == ~t2_pc~0); 476086#L307-2 is_transmit2_triggered_~__retres1~2 := 0; 476084#L318 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 476085#L319 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 476169#L726 assume !(0 != activate_threads_~tmp___1~0); 476170#L726-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 476171#L326 assume !(1 == ~t3_pc~0); 476198#L326-2 is_transmit3_triggered_~__retres1~3 := 0; 476199#L337 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 476213#L338 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 476265#L734 assume !(0 != activate_threads_~tmp___2~0); 476280#L734-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 475681#L345 assume !(1 == ~t4_pc~0); 475682#L345-2 is_transmit4_triggered_~__retres1~4 := 0; 475679#L356 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 475680#L357 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 475651#L742 assume !(0 != activate_threads_~tmp___3~0); 475622#L742-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 475623#L364 assume !(1 == ~t5_pc~0); 475958#L364-2 is_transmit5_triggered_~__retres1~5 := 0; 475955#L375 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 475866#L376 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 475867#L750 assume !(0 != activate_threads_~tmp___4~0); 475907#L750-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 475915#L639 assume !(1 == ~M_E~0); 475960#L639-2 assume !(1 == ~T1_E~0); 475760#L644-1 assume !(1 == ~T2_E~0); 475761#L649-1 assume !(1 == ~T3_E~0); 475629#L654-1 assume !(1 == ~T4_E~0); 475630#L659-1 assume !(1 == ~T5_E~0); 475711#L664-1 assume !(1 == ~E_1~0); 475712#L669-1 assume !(1 == ~E_2~0); 476036#L674-1 assume !(1 == ~E_3~0); 476037#L679-1 assume !(1 == ~E_4~0); 475916#L684-1 assume !(1 == ~E_5~0); 475917#L689-1 assume { :end_inline_reset_delta_events } true; 476219#L890-3 assume true; 503679#L890-1 assume !false; 496792#L891 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 496786#L551 [2018-11-18 16:16:00,376 INFO L796 eck$LassoCheckResult]: Loop: 496786#L551 assume true; 496784#L471-1 assume !false; 496781#L472 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 496777#L429 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 496778#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 503506#L462 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 503504#L476 assume 0 != eval_~tmp~0; 503502#L476-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 503500#L484 assume !(0 != eval_~tmp_ndt_1~0); 496761#L481 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 496758#L498 assume !(0 != eval_~tmp_ndt_2~0); 496755#L495 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 496751#L512 assume !(0 != eval_~tmp_ndt_3~0); 496752#L509 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 499519#L526 assume !(0 != eval_~tmp_ndt_4~0); 499515#L523 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 495648#L540 assume !(0 != eval_~tmp_ndt_5~0); 499511#L537 assume !(0 == ~t5_st~0); 496786#L551 [2018-11-18 16:16:00,376 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:16:00,377 INFO L82 PathProgramCache]: Analyzing trace with hash -1516689527, now seen corresponding path program 4 times [2018-11-18 16:16:00,377 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:16:00,377 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:16:00,378 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:16:00,378 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:16:00,378 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:16:00,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 16:16:00,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 16:16:00,395 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:16:00,396 INFO L82 PathProgramCache]: Analyzing trace with hash 2015751902, now seen corresponding path program 1 times [2018-11-18 16:16:00,396 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:16:00,396 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:16:00,396 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:16:00,396 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:16:00,396 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:16:00,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 16:16:00,399 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 16:16:00,400 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:16:00,401 INFO L82 PathProgramCache]: Analyzing trace with hash -2132327322, now seen corresponding path program 1 times [2018-11-18 16:16:00,401 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:16:00,401 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:16:00,401 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:16:00,402 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:16:00,402 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:16:00,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 16:16:00,433 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 16:16:00,433 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 16:16:00,433 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 16:16:00,566 WARN L180 SmtUtils]: Spent 131.00 ms on a formula simplification. DAG size of input: 44 DAG size of output: 42 [2018-11-18 16:16:00,589 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 16:16:00,589 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 16:16:00,589 INFO L87 Difference]: Start difference. First operand 54660 states and 68839 transitions. cyclomatic complexity: 14189 Second operand 3 states. [2018-11-18 16:16:00,753 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 16:16:00,753 INFO L93 Difference]: Finished difference Result 65322 states and 82241 transitions. [2018-11-18 16:16:00,755 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 16:16:00,755 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 65322 states and 82241 transitions. [2018-11-18 16:16:00,949 INFO L131 ngComponentsAnalysis]: Automaton has 11 accepting balls. 62770 [2018-11-18 16:16:01,036 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 65322 states to 65322 states and 82241 transitions. [2018-11-18 16:16:01,036 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 65322 [2018-11-18 16:16:01,060 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 65322 [2018-11-18 16:16:01,061 INFO L73 IsDeterministic]: Start isDeterministic. Operand 65322 states and 82241 transitions. [2018-11-18 16:16:01,081 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 16:16:01,081 INFO L705 BuchiCegarLoop]: Abstraction has 65322 states and 82241 transitions. [2018-11-18 16:16:01,102 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65322 states and 82241 transitions. [2018-11-18 16:16:01,605 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65322 to 65322. [2018-11-18 16:16:01,606 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 65322 states. [2018-11-18 16:16:01,668 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65322 states to 65322 states and 82241 transitions. [2018-11-18 16:16:01,668 INFO L728 BuchiCegarLoop]: Abstraction has 65322 states and 82241 transitions. [2018-11-18 16:16:01,668 INFO L608 BuchiCegarLoop]: Abstraction has 65322 states and 82241 transitions. [2018-11-18 16:16:01,668 INFO L442 BuchiCegarLoop]: ======== Iteration 28============ [2018-11-18 16:16:01,669 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 65322 states and 82241 transitions. [2018-11-18 16:16:01,778 INFO L131 ngComponentsAnalysis]: Automaton has 11 accepting balls. 62770 [2018-11-18 16:16:01,778 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 16:16:01,779 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 16:16:01,779 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:16:01,779 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 16:16:01,779 INFO L794 eck$LassoCheckResult]: Stem: 596136#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 596083#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~7;havoc main_~__retres1~7;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 595794#L853 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret14, start_simulation_#t~ret15, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 595795#L384 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 595729#L391 assume 1 == ~m_i~0;~m_st~0 := 0; 595730#L391-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 595744#L396-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 595851#L401-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 595852#L406-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 595697#L411-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 595698#L416-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 595703#L576 assume !(0 == ~M_E~0); 595684#L576-2 assume !(0 == ~T1_E~0); 595685#L581-1 assume !(0 == ~T2_E~0); 596006#L586-1 assume !(0 == ~T3_E~0); 596007#L591-1 assume !(0 == ~T4_E~0); 595888#L596-1 assume !(0 == ~T5_E~0); 595889#L601-1 assume !(0 == ~E_1~0); 595952#L606-1 assume !(0 == ~E_2~0); 595755#L611-1 assume !(0 == ~E_3~0); 595756#L616-1 assume !(0 == ~E_4~0); 595623#L621-1 assume !(0 == ~E_5~0); 595624#L626-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7, activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 595847#L269 assume !(1 == ~m_pc~0); 595832#L269-2 is_master_triggered_~__retres1~0 := 0; 595833#L280 is_master_triggered_#res := is_master_triggered_~__retres1~0; 595745#L281 activate_threads_#t~ret7 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret7;havoc activate_threads_#t~ret7; 595746#L710 assume !(0 != activate_threads_~tmp~1); 595748#L710-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 595749#L288 assume !(1 == ~t1_pc~0); 595886#L288-2 is_transmit1_triggered_~__retres1~1 := 0; 595890#L299 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 595891#L300 activate_threads_#t~ret8 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 596023#L718 assume !(0 != activate_threads_~tmp___0~0); 596032#L718-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 596034#L307 assume !(1 == ~t2_pc~0); 596086#L307-2 is_transmit2_triggered_~__retres1~2 := 0; 596084#L318 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 596085#L319 activate_threads_#t~ret9 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 596175#L726 assume !(0 != activate_threads_~tmp___1~0); 596176#L726-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 596177#L326 assume !(1 == ~t3_pc~0); 596207#L326-2 is_transmit3_triggered_~__retres1~3 := 0; 596208#L337 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 596221#L338 activate_threads_#t~ret10 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 596279#L734 assume !(0 != activate_threads_~tmp___2~0); 596292#L734-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 595671#L345 assume !(1 == ~t4_pc~0); 595672#L345-2 is_transmit4_triggered_~__retres1~4 := 0; 595669#L356 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 595670#L357 activate_threads_#t~ret11 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 595641#L742 assume !(0 != activate_threads_~tmp___3~0); 595612#L742-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 595613#L364 assume !(1 == ~t5_pc~0); 595950#L364-2 is_transmit5_triggered_~__retres1~5 := 0; 595947#L375 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 595858#L376 activate_threads_#t~ret12 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 595859#L750 assume !(0 != activate_threads_~tmp___4~0); 595897#L750-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 595904#L639 assume !(1 == ~M_E~0); 595953#L639-2 assume !(1 == ~T1_E~0); 595750#L644-1 assume !(1 == ~T2_E~0); 595751#L649-1 assume !(1 == ~T3_E~0); 595619#L654-1 assume !(1 == ~T4_E~0); 595620#L659-1 assume !(1 == ~T5_E~0); 595701#L664-1 assume !(1 == ~E_1~0); 595702#L669-1 assume !(1 == ~E_2~0); 596035#L674-1 assume !(1 == ~E_3~0); 596036#L679-1 assume !(1 == ~E_4~0); 595905#L684-1 assume !(1 == ~E_5~0); 595906#L689-1 assume { :end_inline_reset_delta_events } true; 596231#L890-3 assume true; 632086#L890-1 assume !false; 632084#L891 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_~tmp~0;havoc eval_~tmp~0; 632081#L551 [2018-11-18 16:16:01,780 INFO L796 eck$LassoCheckResult]: Loop: 632081#L551 assume true; 632079#L471-1 assume !false; 632078#L472 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~6;havoc exists_runnable_thread_~__retres1~6; 632076#L429 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6 := 1; 632074#L461 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~6; 632072#L462 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 632071#L476 assume 0 != eval_~tmp~0; 632069#L476-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 632067#L484 assume !(0 != eval_~tmp_ndt_1~0); 632066#L481 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 631848#L498 assume !(0 != eval_~tmp_ndt_2~0); 632064#L495 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 595764#L512 assume !(0 != eval_~tmp_ndt_3~0); 595765#L509 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 659750#L526 assume !(0 != eval_~tmp_ndt_4~0); 632099#L523 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 632096#L540 assume !(0 != eval_~tmp_ndt_5~0); 632094#L537 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 632083#L554 assume !(0 != eval_~tmp_ndt_6~0); 632081#L551 [2018-11-18 16:16:01,780 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:16:01,780 INFO L82 PathProgramCache]: Analyzing trace with hash -1516689527, now seen corresponding path program 5 times [2018-11-18 16:16:01,780 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:16:01,780 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:16:01,780 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:16:01,781 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:16:01,781 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:16:01,784 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 16:16:01,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 16:16:01,797 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:16:01,797 INFO L82 PathProgramCache]: Analyzing trace with hash -1936200401, now seen corresponding path program 1 times [2018-11-18 16:16:01,797 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:16:01,797 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:16:01,798 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:16:01,798 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 16:16:01,798 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:16:01,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 16:16:01,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 16:16:01,803 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 16:16:01,803 INFO L82 PathProgramCache]: Analyzing trace with hash -1677637465, now seen corresponding path program 1 times [2018-11-18 16:16:01,803 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 16:16:01,803 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 16:16:01,804 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:16:01,804 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 16:16:01,804 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 16:16:01,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 16:16:01,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 16:16:02,280 WARN L180 SmtUtils]: Spent 345.00 ms on a formula simplification. DAG size of input: 188 DAG size of output: 126 [2018-11-18 16:16:02,401 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 18.11 04:16:02 BoogieIcfgContainer [2018-11-18 16:16:02,401 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2018-11-18 16:16:02,401 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-18 16:16:02,401 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-18 16:16:02,405 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-18 16:16:02,405 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 04:15:51" (3/4) ... [2018-11-18 16:16:02,408 INFO L141 WitnessPrinter]: Generating witness for non-termination counterexample [2018-11-18 16:16:02,454 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_dbb4afbb-caeb-472f-b19b-2b0b4ce518c7/bin-2019/uautomizer/witness.graphml [2018-11-18 16:16:02,454 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-18 16:16:02,455 INFO L168 Benchmark]: Toolchain (without parser) took 11903.56 ms. Allocated memory was 1.0 GB in the beginning and 2.0 GB in the end (delta: 945.8 MB). Free memory was 959.2 MB in the beginning and 1.0 GB in the end (delta: -49.7 MB). Peak memory consumption was 896.1 MB. Max. memory is 11.5 GB. [2018-11-18 16:16:02,455 INFO L168 Benchmark]: CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 985.6 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-18 16:16:02,455 INFO L168 Benchmark]: CACSL2BoogieTranslator took 227.19 ms. Allocated memory is still 1.0 GB. Free memory was 959.2 MB in the beginning and 940.5 MB in the end (delta: 18.8 MB). Peak memory consumption was 18.8 MB. Max. memory is 11.5 GB. [2018-11-18 16:16:02,456 INFO L168 Benchmark]: Boogie Procedure Inliner took 84.46 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 145.2 MB). Free memory was 937.8 MB in the beginning and 1.1 GB in the end (delta: -196.7 MB). Peak memory consumption was 14.7 MB. Max. memory is 11.5 GB. [2018-11-18 16:16:02,456 INFO L168 Benchmark]: Boogie Preprocessor took 50.86 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. [2018-11-18 16:16:02,456 INFO L168 Benchmark]: RCFGBuilder took 834.44 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 104.0 MB). Peak memory consumption was 104.0 MB. Max. memory is 11.5 GB. [2018-11-18 16:16:02,456 INFO L168 Benchmark]: BuchiAutomizer took 10650.18 ms. Allocated memory was 1.2 GB in the beginning and 2.0 GB in the end (delta: 800.6 MB). Free memory was 1.0 GB in the beginning and 1.0 GB in the end (delta: 16.2 MB). Peak memory consumption was 816.8 MB. Max. memory is 11.5 GB. [2018-11-18 16:16:02,457 INFO L168 Benchmark]: Witness Printer took 53.04 ms. Allocated memory is still 2.0 GB. Free memory is still 1.0 GB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-18 16:16:02,458 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 985.6 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 227.19 ms. Allocated memory is still 1.0 GB. Free memory was 959.2 MB in the beginning and 940.5 MB in the end (delta: 18.8 MB). Peak memory consumption was 18.8 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 84.46 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 145.2 MB). Free memory was 937.8 MB in the beginning and 1.1 GB in the end (delta: -196.7 MB). Peak memory consumption was 14.7 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 50.86 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. * RCFGBuilder took 834.44 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 104.0 MB). Peak memory consumption was 104.0 MB. Max. memory is 11.5 GB. * BuchiAutomizer took 10650.18 ms. Allocated memory was 1.2 GB in the beginning and 2.0 GB in the end (delta: 800.6 MB). Free memory was 1.0 GB in the beginning and 1.0 GB in the end (delta: 16.2 MB). Peak memory consumption was 816.8 MB. Max. memory is 11.5 GB. * Witness Printer took 53.04 ms. Allocated memory is still 2.0 GB. Free memory is still 1.0 GB. There was no memory consumed. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 27 terminating modules (27 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.27 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 65322 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 10.5s and 28 iterations. TraceHistogramMax:3. Analysis of lassos took 3.4s. Construction of modules took 0.9s. Büchi inclusion checks took 1.2s. Highest rank in rank-based complementation 0. Minimization of det autom 27. Minimization of nondet autom 0. Automata minimization 2.3s AutomataMinimizationTime, 27 MinimizatonAttempts, 52518 StatesRemovedByMinimization, 13 NontrivialMinimizations. Non-live state removal took 1.5s Buchi closure took 0.1s. Biggest automaton had 65322 states and ocurred in iteration 27. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 20705 SDtfs, 24983 SDslu, 23527 SDs, 0 SdLazy, 844 SolverSat, 377 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.9s Time LassoAnalysisResults: nont1 unkn0 SFLI11 SFLT0 conc4 concLT0 SILN0 SILU0 SILI12 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 471]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {__retres1=0, t3_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@51b77dd=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4d0298ec=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7c6b9095=0, tmp=1, t5_i=1, __retres1=0, kernel_st=1, t2_st=0, t4_i=1, E_3=2, t4_pc=0, E_5=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@35f5480c=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@476c38c4=0, \result=0, E_1=2, tmp_ndt_2=0, \result=0, __retres1=0, \result=0, tmp_ndt_4=0, tmp_ndt_6=0, m_st=0, tmp___2=0, tmp___0=0, t3_pc=0, tmp=0, \result=0, __retres1=0, m_pc=0, tmp___4=0, \result=0, __retres1=0, \result=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@753ea8b5=0, \result=0, T2_E=2, tmp___0=0, t1_pc=0, t5_st=0, __retres1=1, E_2=2, E_4=2, T1_E=2, tmp_ndt_1=0, M_E=2, tmp=0, tmp_ndt_3=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@2920bc16=0, __retres1=0, T5_E=2, t2_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@68844281=0, T4_E=2, t3_i=1, t4_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@44689616=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@12180b1a=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@40171928=0, t1_st=0, tmp_ndt_5=0, t5_pc=0, t2_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@10a2d8e0=0, tmp___3=0, tmp___1=0, T3_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@171a4251=0, t1_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@536e027a=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@315daa7=0, \result=1} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 471]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int t4_pc = 0; [L20] int t5_pc = 0; [L21] int m_st ; [L22] int t1_st ; [L23] int t2_st ; [L24] int t3_st ; [L25] int t4_st ; [L26] int t5_st ; [L27] int m_i ; [L28] int t1_i ; [L29] int t2_i ; [L30] int t3_i ; [L31] int t4_i ; [L32] int t5_i ; [L33] int M_E = 2; [L34] int T1_E = 2; [L35] int T2_E = 2; [L36] int T3_E = 2; [L37] int T4_E = 2; [L38] int T5_E = 2; [L39] int E_1 = 2; [L40] int E_2 = 2; [L41] int E_3 = 2; [L42] int E_4 = 2; [L43] int E_5 = 2; [L935] int __retres1 ; [L939] CALL init_model() [L846] m_i = 1 [L847] t1_i = 1 [L848] t2_i = 1 [L849] t3_i = 1 [L850] t4_i = 1 [L851] RET t5_i = 1 [L939] init_model() [L940] CALL start_simulation() [L876] int kernel_st ; [L877] int tmp ; [L878] int tmp___0 ; [L882] kernel_st = 0 [L883] FCALL update_channels() [L884] CALL init_threads() [L391] COND TRUE m_i == 1 [L392] m_st = 0 [L396] COND TRUE t1_i == 1 [L397] t1_st = 0 [L401] COND TRUE t2_i == 1 [L402] t2_st = 0 [L406] COND TRUE t3_i == 1 [L407] t3_st = 0 [L411] COND TRUE t4_i == 1 [L412] t4_st = 0 [L416] COND TRUE t5_i == 1 [L417] RET t5_st = 0 [L884] init_threads() [L885] CALL fire_delta_events() [L576] COND FALSE !(M_E == 0) [L581] COND FALSE !(T1_E == 0) [L586] COND FALSE !(T2_E == 0) [L591] COND FALSE !(T3_E == 0) [L596] COND FALSE !(T4_E == 0) [L601] COND FALSE !(T5_E == 0) [L606] COND FALSE !(E_1 == 0) [L611] COND FALSE !(E_2 == 0) [L616] COND FALSE !(E_3 == 0) [L621] COND FALSE !(E_4 == 0) [L626] COND FALSE, RET !(E_5 == 0) [L885] fire_delta_events() [L886] CALL activate_threads() [L699] int tmp ; [L700] int tmp___0 ; [L701] int tmp___1 ; [L702] int tmp___2 ; [L703] int tmp___3 ; [L704] int tmp___4 ; [L708] CALL, EXPR is_master_triggered() [L266] int __retres1 ; [L269] COND FALSE !(m_pc == 1) [L279] __retres1 = 0 [L281] RET return (__retres1); [L708] EXPR is_master_triggered() [L708] tmp = is_master_triggered() [L710] COND FALSE !(\read(tmp)) [L716] CALL, EXPR is_transmit1_triggered() [L285] int __retres1 ; [L288] COND FALSE !(t1_pc == 1) [L298] __retres1 = 0 [L300] RET return (__retres1); [L716] EXPR is_transmit1_triggered() [L716] tmp___0 = is_transmit1_triggered() [L718] COND FALSE !(\read(tmp___0)) [L724] CALL, EXPR is_transmit2_triggered() [L304] int __retres1 ; [L307] COND FALSE !(t2_pc == 1) [L317] __retres1 = 0 [L319] RET return (__retres1); [L724] EXPR is_transmit2_triggered() [L724] tmp___1 = is_transmit2_triggered() [L726] COND FALSE !(\read(tmp___1)) [L732] CALL, EXPR is_transmit3_triggered() [L323] int __retres1 ; [L326] COND FALSE !(t3_pc == 1) [L336] __retres1 = 0 [L338] RET return (__retres1); [L732] EXPR is_transmit3_triggered() [L732] tmp___2 = is_transmit3_triggered() [L734] COND FALSE !(\read(tmp___2)) [L740] CALL, EXPR is_transmit4_triggered() [L342] int __retres1 ; [L345] COND FALSE !(t4_pc == 1) [L355] __retres1 = 0 [L357] RET return (__retres1); [L740] EXPR is_transmit4_triggered() [L740] tmp___3 = is_transmit4_triggered() [L742] COND FALSE !(\read(tmp___3)) [L748] CALL, EXPR is_transmit5_triggered() [L361] int __retres1 ; [L364] COND FALSE !(t5_pc == 1) [L374] __retres1 = 0 [L376] RET return (__retres1); [L748] EXPR is_transmit5_triggered() [L748] tmp___4 = is_transmit5_triggered() [L750] COND FALSE, RET !(\read(tmp___4)) [L886] activate_threads() [L887] CALL reset_delta_events() [L639] COND FALSE !(M_E == 1) [L644] COND FALSE !(T1_E == 1) [L649] COND FALSE !(T2_E == 1) [L654] COND FALSE !(T3_E == 1) [L659] COND FALSE !(T4_E == 1) [L664] COND FALSE !(T5_E == 1) [L669] COND FALSE !(E_1 == 1) [L674] COND FALSE !(E_2 == 1) [L679] COND FALSE !(E_3 == 1) [L684] COND FALSE !(E_4 == 1) [L689] COND FALSE, RET !(E_5 == 1) [L887] reset_delta_events() [L890] COND TRUE 1 [L893] kernel_st = 1 [L894] CALL eval() [L467] int tmp ; Loop: [L471] COND TRUE 1 [L474] CALL, EXPR exists_runnable_thread() [L426] int __retres1 ; [L429] COND TRUE m_st == 0 [L430] __retres1 = 1 [L462] RET return (__retres1); [L474] EXPR exists_runnable_thread() [L474] tmp = exists_runnable_thread() [L476] COND TRUE \read(tmp) [L481] COND TRUE m_st == 0 [L482] int tmp_ndt_1; [L483] tmp_ndt_1 = __VERIFIER_nondet_int() [L484] COND FALSE !(\read(tmp_ndt_1)) [L495] COND TRUE t1_st == 0 [L496] int tmp_ndt_2; [L497] tmp_ndt_2 = __VERIFIER_nondet_int() [L498] COND FALSE !(\read(tmp_ndt_2)) [L509] COND TRUE t2_st == 0 [L510] int tmp_ndt_3; [L511] tmp_ndt_3 = __VERIFIER_nondet_int() [L512] COND FALSE !(\read(tmp_ndt_3)) [L523] COND TRUE t3_st == 0 [L524] int tmp_ndt_4; [L525] tmp_ndt_4 = __VERIFIER_nondet_int() [L526] COND FALSE !(\read(tmp_ndt_4)) [L537] COND TRUE t4_st == 0 [L538] int tmp_ndt_5; [L539] tmp_ndt_5 = __VERIFIER_nondet_int() [L540] COND FALSE !(\read(tmp_ndt_5)) [L551] COND TRUE t5_st == 0 [L552] int tmp_ndt_6; [L553] tmp_ndt_6 = __VERIFIER_nondet_int() [L554] COND FALSE !(\read(tmp_ndt_6)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...