./Ultimate.py --spec ../../sv-benchmarks/c/Termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.06_false-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 5842f4b8 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_c6703cb5-0709-4fd4-a613-f346af7a7a19/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_c6703cb5-0709-4fd4-a613-f346af7a7a19/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_c6703cb5-0709-4fd4-a613-f346af7a7a19/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_c6703cb5-0709-4fd4-a613-f346af7a7a19/bin-2019/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.06_false-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_c6703cb5-0709-4fd4-a613-f346af7a7a19/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_c6703cb5-0709-4fd4-a613-f346af7a7a19/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 7b5159bbdd5292a1bc0941c897062f30a665bf67 ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.1.23-5842f4b [2018-11-18 15:29:24,166 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-18 15:29:24,167 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-18 15:29:24,175 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-18 15:29:24,176 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-18 15:29:24,176 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-18 15:29:24,177 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-18 15:29:24,178 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-18 15:29:24,179 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-18 15:29:24,180 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-18 15:29:24,181 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-18 15:29:24,181 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-18 15:29:24,181 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-18 15:29:24,182 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-18 15:29:24,183 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-18 15:29:24,183 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-18 15:29:24,184 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-18 15:29:24,185 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-18 15:29:24,186 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-18 15:29:24,187 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-18 15:29:24,188 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-18 15:29:24,189 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-18 15:29:24,190 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-18 15:29:24,190 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-18 15:29:24,190 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-18 15:29:24,191 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-18 15:29:24,192 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-18 15:29:24,192 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-18 15:29:24,193 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-18 15:29:24,194 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-18 15:29:24,194 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-18 15:29:24,194 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-18 15:29:24,194 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-18 15:29:24,194 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-18 15:29:24,195 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-18 15:29:24,196 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-18 15:29:24,196 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_c6703cb5-0709-4fd4-a613-f346af7a7a19/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2018-11-18 15:29:24,206 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-18 15:29:24,206 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-18 15:29:24,207 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-18 15:29:24,207 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-18 15:29:24,207 INFO L133 SettingsManager]: * Use SBE=true [2018-11-18 15:29:24,207 INFO L131 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2018-11-18 15:29:24,207 INFO L133 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2018-11-18 15:29:24,207 INFO L133 SettingsManager]: * Use old map elimination=false [2018-11-18 15:29:24,208 INFO L133 SettingsManager]: * Use external solver (rank synthesis)=false [2018-11-18 15:29:24,208 INFO L133 SettingsManager]: * Use only trivial implications for array writes=true [2018-11-18 15:29:24,208 INFO L133 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2018-11-18 15:29:24,208 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-18 15:29:24,208 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-18 15:29:24,208 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-11-18 15:29:24,208 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-18 15:29:24,209 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-18 15:29:24,209 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-18 15:29:24,209 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2018-11-18 15:29:24,209 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2018-11-18 15:29:24,209 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2018-11-18 15:29:24,209 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-18 15:29:24,209 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-18 15:29:24,209 INFO L133 SettingsManager]: * Assume nondeterminstic values are in range=false [2018-11-18 15:29:24,210 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-18 15:29:24,210 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2018-11-18 15:29:24,210 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-18 15:29:24,210 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-18 15:29:24,210 INFO L133 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2018-11-18 15:29:24,210 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-18 15:29:24,210 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-18 15:29:24,211 INFO L133 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2018-11-18 15:29:24,211 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-11-18 15:29:24,211 INFO L133 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_c6703cb5-0709-4fd4-a613-f346af7a7a19/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 7b5159bbdd5292a1bc0941c897062f30a665bf67 [2018-11-18 15:29:24,235 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-18 15:29:24,244 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-18 15:29:24,247 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-18 15:29:24,248 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-18 15:29:24,248 INFO L276 PluginConnector]: CDTParser initialized [2018-11-18 15:29:24,248 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_c6703cb5-0709-4fd4-a613-f346af7a7a19/bin-2019/uautomizer/../../sv-benchmarks/c/systemc/transmitter.06_false-unreach-call_false-termination.cil.c [2018-11-18 15:29:24,284 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_c6703cb5-0709-4fd4-a613-f346af7a7a19/bin-2019/uautomizer/data/9111f5595/9993420addbc42459981122f16665615/FLAG9eff815e9 [2018-11-18 15:29:24,713 INFO L307 CDTParser]: Found 1 translation units. [2018-11-18 15:29:24,713 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_c6703cb5-0709-4fd4-a613-f346af7a7a19/sv-benchmarks/c/systemc/transmitter.06_false-unreach-call_false-termination.cil.c [2018-11-18 15:29:24,722 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_c6703cb5-0709-4fd4-a613-f346af7a7a19/bin-2019/uautomizer/data/9111f5595/9993420addbc42459981122f16665615/FLAG9eff815e9 [2018-11-18 15:29:24,730 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_c6703cb5-0709-4fd4-a613-f346af7a7a19/bin-2019/uautomizer/data/9111f5595/9993420addbc42459981122f16665615 [2018-11-18 15:29:24,733 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-18 15:29:24,734 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-18 15:29:24,734 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-18 15:29:24,735 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-18 15:29:24,737 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-18 15:29:24,737 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 03:29:24" (1/1) ... [2018-11-18 15:29:24,739 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@415b4b46 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:29:24, skipping insertion in model container [2018-11-18 15:29:24,739 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 03:29:24" (1/1) ... [2018-11-18 15:29:24,745 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-18 15:29:24,773 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-18 15:29:24,920 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 15:29:24,924 INFO L191 MainTranslator]: Completed pre-run [2018-11-18 15:29:24,956 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 15:29:24,967 INFO L195 MainTranslator]: Completed translation [2018-11-18 15:29:24,967 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:29:24 WrapperNode [2018-11-18 15:29:24,967 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-18 15:29:24,967 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-18 15:29:24,967 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-18 15:29:24,968 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-18 15:29:25,009 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:29:24" (1/1) ... [2018-11-18 15:29:25,016 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:29:24" (1/1) ... [2018-11-18 15:29:25,054 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-18 15:29:25,055 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-18 15:29:25,055 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-18 15:29:25,055 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-18 15:29:25,063 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:29:24" (1/1) ... [2018-11-18 15:29:25,063 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:29:24" (1/1) ... [2018-11-18 15:29:25,066 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:29:24" (1/1) ... [2018-11-18 15:29:25,067 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:29:24" (1/1) ... [2018-11-18 15:29:25,077 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:29:24" (1/1) ... [2018-11-18 15:29:25,093 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:29:24" (1/1) ... [2018-11-18 15:29:25,095 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:29:24" (1/1) ... [2018-11-18 15:29:25,100 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-18 15:29:25,101 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-18 15:29:25,101 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-18 15:29:25,101 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-18 15:29:25,102 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:29:24" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_c6703cb5-0709-4fd4-a613-f346af7a7a19/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 15:29:25,157 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-18 15:29:25,157 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-18 15:29:26,037 INFO L278 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-18 15:29:26,038 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 03:29:26 BoogieIcfgContainer [2018-11-18 15:29:26,038 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-18 15:29:26,038 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2018-11-18 15:29:26,038 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2018-11-18 15:29:26,041 INFO L276 PluginConnector]: BuchiAutomizer initialized [2018-11-18 15:29:26,041 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-18 15:29:26,042 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 18.11 03:29:24" (1/3) ... [2018-11-18 15:29:26,042 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5f77328c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 18.11 03:29:26, skipping insertion in model container [2018-11-18 15:29:26,042 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-18 15:29:26,043 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 03:29:24" (2/3) ... [2018-11-18 15:29:26,043 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5f77328c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 18.11 03:29:26, skipping insertion in model container [2018-11-18 15:29:26,043 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-18 15:29:26,043 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 03:29:26" (3/3) ... [2018-11-18 15:29:26,045 INFO L375 chiAutomizerObserver]: Analyzing ICFG transmitter.06_false-unreach-call_false-termination.cil.c [2018-11-18 15:29:26,082 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-18 15:29:26,083 INFO L374 BuchiCegarLoop]: Interprodecural is true [2018-11-18 15:29:26,083 INFO L375 BuchiCegarLoop]: Hoare is false [2018-11-18 15:29:26,083 INFO L376 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2018-11-18 15:29:26,083 INFO L377 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-18 15:29:26,083 INFO L378 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-18 15:29:26,083 INFO L379 BuchiCegarLoop]: Difference is false [2018-11-18 15:29:26,084 INFO L380 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-18 15:29:26,084 INFO L383 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2018-11-18 15:29:26,105 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 643 states. [2018-11-18 15:29:26,143 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 550 [2018-11-18 15:29:26,143 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:29:26,143 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:29:26,153 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:26,153 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:26,153 INFO L442 BuchiCegarLoop]: ======== Iteration 1============ [2018-11-18 15:29:26,153 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 643 states. [2018-11-18 15:29:26,162 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 550 [2018-11-18 15:29:26,162 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:29:26,162 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:29:26,165 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:26,165 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:26,171 INFO L794 eck$LassoCheckResult]: Stem: 429#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 321#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 595#L977true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 55#L444true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 446#L451true assume !(1 == ~m_i~0);~m_st~0 := 2; 449#L451-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 134#L456-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 345#L461-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 57#L466-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 574#L471-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 263#L476-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 631#L481-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 454#L660true assume !(0 == ~M_E~0); 460#L660-2true assume !(0 == ~T1_E~0); 5#L665-1true assume !(0 == ~T2_E~0); 354#L670-1true assume !(0 == ~T3_E~0); 62#L675-1true assume !(0 == ~T4_E~0); 582#L680-1true assume !(0 == ~T5_E~0); 272#L685-1true assume !(0 == ~T6_E~0); 639#L690-1true assume 0 == ~E_1~0;~E_1~0 := 1; 168#L695-1true assume !(0 == ~E_2~0); 554#L700-1true assume !(0 == ~E_3~0); 406#L705-1true assume !(0 == ~E_4~0); 102#L710-1true assume !(0 == ~E_5~0); 479#L715-1true assume !(0 == ~E_6~0); 24#L720-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 149#L310true assume 1 == ~m_pc~0; 243#L311true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 147#L321true is_master_triggered_#res := is_master_triggered_~__retres1~0; 242#L322true activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 411#L815true assume !(0 != activate_threads_~tmp~1); 402#L815-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 324#L329true assume !(1 == ~t1_pc~0); 332#L329-2true is_transmit1_triggered_~__retres1~1 := 0; 322#L340true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 452#L341true activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 590#L823true assume !(0 != activate_threads_~tmp___0~0); 591#L823-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 529#L348true assume 1 == ~t2_pc~0; 613#L349true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 526#L359true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 611#L360true activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 109#L831true assume !(0 != activate_threads_~tmp___1~0); 99#L831-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 60#L367true assume !(1 == ~t3_pc~0); 43#L367-2true is_transmit3_triggered_~__retres1~3 := 0; 59#L378true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 136#L379true activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 280#L839true assume !(0 != activate_threads_~tmp___2~0); 282#L839-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 204#L386true assume 1 == ~t4_pc~0; 143#L387true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 203#L397true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 142#L398true activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 487#L847true assume !(0 != activate_threads_~tmp___3~0); 471#L847-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 577#L405true assume 1 == ~t5_pc~0; 348#L406true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 576#L416true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 347#L417true activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 492#L855true assume !(0 != activate_threads_~tmp___4~0); 494#L855-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 84#L424true assume !(1 == ~t6_pc~0); 88#L424-2true is_transmit6_triggered_~__retres1~6 := 0; 82#L435true is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 517#L436true activate_threads_#t~ret14 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 34#L863true assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 17#L863-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 551#L733true assume !(1 == ~M_E~0); 555#L733-2true assume !(1 == ~T1_E~0); 404#L738-1true assume !(1 == ~T2_E~0); 101#L743-1true assume !(1 == ~T3_E~0); 476#L748-1true assume 1 == ~T4_E~0;~T4_E~0 := 2; 21#L753-1true assume !(1 == ~T5_E~0); 365#L758-1true assume !(1 == ~T6_E~0); 67#L763-1true assume !(1 == ~E_1~0); 592#L768-1true assume !(1 == ~E_2~0); 266#L773-1true assume !(1 == ~E_3~0); 634#L778-1true assume !(1 == ~E_4~0); 164#L783-1true assume !(1 == ~E_5~0); 549#L788-1true assume 1 == ~E_6~0;~E_6~0 := 2; 401#L793-1true assume { :end_inline_reset_delta_events } true; 173#L1014-3true [2018-11-18 15:29:26,173 INFO L796 eck$LassoCheckResult]: Loop: 173#L1014-3true assume true; 184#L1014-1true assume !false; 287#L1015true start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 641#L635true assume !true; 407#L650true assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 58#L444-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 463#L660-3true assume 0 == ~M_E~0;~M_E~0 := 1; 467#L660-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 12#L665-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 358#L670-3true assume !(0 == ~T3_E~0); 63#L675-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 586#L680-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 275#L685-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 644#L690-3true assume 0 == ~E_1~0;~E_1~0 := 1; 157#L695-3true assume 0 == ~E_2~0;~E_2~0 := 1; 539#L700-3true assume 0 == ~E_3~0;~E_3~0 := 1; 213#L705-3true assume 0 == ~E_4~0;~E_4~0 := 1; 96#L710-3true assume !(0 == ~E_5~0); 459#L715-3true assume 0 == ~E_6~0;~E_6~0 := 1; 8#L720-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 273#L310-21true assume !(1 == ~m_pc~0); 276#L310-23true is_master_triggered_~__retres1~0 := 0; 308#L321-7true is_master_triggered_#res := is_master_triggered_~__retres1~0; 234#L322-7true activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 198#L815-21true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 179#L815-23true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 455#L329-21true assume !(1 == ~t1_pc~0); 461#L329-23true is_transmit1_triggered_~__retres1~1 := 0; 316#L340-7true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 413#L341-7true activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 379#L823-21true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 381#L823-23true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 637#L348-21true assume !(1 == ~t2_pc~0); 643#L348-23true is_transmit2_triggered_~__retres1~2 := 0; 515#L359-7true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 604#L360-7true activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 78#L831-21true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 565#L831-23true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 22#L367-21true assume 1 == ~t3_pc~0; 112#L368-7true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 37#L378-7true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 111#L379-7true activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 231#L839-21true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 236#L839-23true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 166#L386-21true assume !(1 == ~t4_pc~0); 169#L386-23true is_transmit4_triggered_~__retres1~4 := 0; 195#L397-7true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 300#L398-7true activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 442#L847-21true assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 417#L847-23true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 364#L405-21true assume !(1 == ~t5_pc~0); 352#L405-23true is_transmit5_triggered_~__retres1~5 := 0; 375#L416-7true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 340#L417-7true activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 602#L855-21true assume !(0 != activate_threads_~tmp___4~0); 606#L855-23true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 550#L424-21true assume !(1 == ~t6_pc~0); 552#L424-23true is_transmit6_triggered_~__retres1~6 := 0; 74#L435-7true is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 507#L436-7true activate_threads_#t~ret14 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 131#L863-21true assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 114#L863-23true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 557#L733-3true assume !(1 == ~M_E~0); 543#L733-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 409#L738-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 94#L743-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 457#L748-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 4#L753-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 353#L758-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 61#L763-3true assume 1 == ~E_1~0;~E_1~0 := 2; 580#L768-3true assume !(1 == ~E_2~0); 271#L773-3true assume 1 == ~E_3~0;~E_3~0 := 2; 638#L778-3true assume 1 == ~E_4~0;~E_4~0 := 2; 167#L783-3true assume 1 == ~E_5~0;~E_5~0 := 2; 553#L788-3true assume 1 == ~E_6~0;~E_6~0 := 2; 405#L793-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 344#L494-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 258#L531-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 51#L532-1true start_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 366#L1033true assume !(0 == start_simulation_~tmp~3); 369#L1033-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 346#L494-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 262#L531-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 54#L532-2true stop_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 594#L988true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 27#L995true stop_simulation_#res := stop_simulation_~__retres2~0; 104#L996true start_simulation_#t~ret17 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 424#L1046true assume !(0 != start_simulation_~tmp___0~1); 173#L1014-3true [2018-11-18 15:29:26,178 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:26,179 INFO L82 PathProgramCache]: Analyzing trace with hash -1010496615, now seen corresponding path program 1 times [2018-11-18 15:29:26,181 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:26,181 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:26,211 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:26,211 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:26,211 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:26,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:26,301 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:29:26,302 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:29:26,303 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:29:26,306 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 15:29:26,306 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:26,306 INFO L82 PathProgramCache]: Analyzing trace with hash -1131246656, now seen corresponding path program 1 times [2018-11-18 15:29:26,306 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:26,306 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:26,307 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:26,307 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:26,308 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:26,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:26,326 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:29:26,327 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:29:26,327 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 15:29:26,328 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:29:26,338 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:29:26,339 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:29:26,340 INFO L87 Difference]: Start difference. First operand 643 states. Second operand 3 states. [2018-11-18 15:29:26,379 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:29:26,379 INFO L93 Difference]: Finished difference Result 642 states and 953 transitions. [2018-11-18 15:29:26,381 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:29:26,383 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 642 states and 953 transitions. [2018-11-18 15:29:26,387 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 547 [2018-11-18 15:29:26,395 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 642 states to 636 states and 947 transitions. [2018-11-18 15:29:26,395 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 636 [2018-11-18 15:29:26,397 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 636 [2018-11-18 15:29:26,397 INFO L73 IsDeterministic]: Start isDeterministic. Operand 636 states and 947 transitions. [2018-11-18 15:29:26,400 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:29:26,401 INFO L705 BuchiCegarLoop]: Abstraction has 636 states and 947 transitions. [2018-11-18 15:29:26,413 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 636 states and 947 transitions. [2018-11-18 15:29:26,440 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 636 to 636. [2018-11-18 15:29:26,440 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 636 states. [2018-11-18 15:29:26,442 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 636 states to 636 states and 947 transitions. [2018-11-18 15:29:26,443 INFO L728 BuchiCegarLoop]: Abstraction has 636 states and 947 transitions. [2018-11-18 15:29:26,443 INFO L608 BuchiCegarLoop]: Abstraction has 636 states and 947 transitions. [2018-11-18 15:29:26,443 INFO L442 BuchiCegarLoop]: ======== Iteration 2============ [2018-11-18 15:29:26,443 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 636 states and 947 transitions. [2018-11-18 15:29:26,446 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 547 [2018-11-18 15:29:26,446 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:29:26,446 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:29:26,448 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:26,448 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:26,448 INFO L794 eck$LassoCheckResult]: Stem: 1829#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 1722#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1723#L977 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 1393#L444 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1394#L451 assume 1 == ~m_i~0;~m_st~0 := 0; 1842#L451-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1501#L456-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1502#L461-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1395#L466-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1396#L471-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1670#L476-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1671#L481-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1845#L660 assume !(0 == ~M_E~0); 1846#L660-2 assume !(0 == ~T1_E~0); 1300#L665-1 assume !(0 == ~T2_E~0); 1301#L670-1 assume !(0 == ~T3_E~0); 1404#L675-1 assume !(0 == ~T4_E~0); 1405#L680-1 assume !(0 == ~T5_E~0); 1679#L685-1 assume !(0 == ~T6_E~0); 1680#L690-1 assume 0 == ~E_1~0;~E_1~0 := 1; 1565#L695-1 assume !(0 == ~E_2~0); 1566#L700-1 assume !(0 == ~E_3~0); 1813#L705-1 assume !(0 == ~E_4~0); 1471#L710-1 assume !(0 == ~E_5~0); 1472#L715-1 assume !(0 == ~E_6~0); 1336#L720-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1337#L310 assume 1 == ~m_pc~0; 1526#L311 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 1524#L321 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1525#L322 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 1654#L815 assume !(0 != activate_threads_~tmp~1); 1809#L815-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1726#L329 assume !(1 == ~t1_pc~0); 1727#L329-2 is_transmit1_triggered_~__retres1~1 := 0; 1724#L340 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1725#L341 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1844#L823 assume !(0 != activate_threads_~tmp___0~0); 1917#L823-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1896#L348 assume 1 == ~t2_pc~0; 1897#L349 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1894#L359 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1895#L360 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1480#L831 assume !(0 != activate_threads_~tmp___1~0); 1466#L831-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1400#L367 assume !(1 == ~t3_pc~0); 1368#L367-2 is_transmit3_triggered_~__retres1~3 := 0; 1369#L378 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1399#L379 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1504#L839 assume !(0 != activate_threads_~tmp___2~0); 1686#L839-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1609#L386 assume 1 == ~t4_pc~0; 1511#L387 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1512#L397 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1509#L398 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1510#L847 assume !(0 != activate_threads_~tmp___3~0); 1850#L847-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1851#L405 assume 1 == ~t5_pc~0; 1769#L406 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 1770#L416 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1767#L417 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1768#L855 assume !(0 != activate_threads_~tmp___4~0); 1857#L855-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1447#L424 assume !(1 == ~t6_pc~0); 1448#L424-2 is_transmit6_triggered_~__retres1~6 := 0; 1443#L435 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1444#L436 activate_threads_#t~ret14 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1355#L863 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 1323#L863-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1324#L733 assume !(1 == ~M_E~0); 1907#L733-2 assume !(1 == ~T1_E~0); 1811#L738-1 assume !(1 == ~T2_E~0); 1469#L743-1 assume !(1 == ~T3_E~0); 1470#L748-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1331#L753-1 assume !(1 == ~T5_E~0); 1332#L758-1 assume !(1 == ~T6_E~0); 1416#L763-1 assume !(1 == ~E_1~0); 1417#L768-1 assume !(1 == ~E_2~0); 1674#L773-1 assume !(1 == ~E_3~0); 1675#L778-1 assume !(1 == ~E_4~0); 1558#L783-1 assume !(1 == ~E_5~0); 1559#L788-1 assume 1 == ~E_6~0;~E_6~0 := 2; 1808#L793-1 assume { :end_inline_reset_delta_events } true; 1571#L1014-3 [2018-11-18 15:29:26,449 INFO L796 eck$LassoCheckResult]: Loop: 1571#L1014-3 assume true; 1572#L1014-1 assume !false; 1590#L1015 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 1303#L635 assume true; 1554#L541-1 assume !false; 1555#L542 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 1662#L494 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 1379#L531 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 1376#L532 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 1377#L546 assume !(0 != eval_~tmp~0); 1814#L650 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 1397#L444-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 1398#L660-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1848#L660-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1316#L665-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1317#L670-3 assume !(0 == ~T3_E~0); 1406#L675-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1407#L680-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1682#L685-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1683#L690-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1545#L695-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1546#L700-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1615#L705-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1463#L710-3 assume !(0 == ~E_5~0); 1464#L715-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1305#L720-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1306#L310-21 assume 1 == ~m_pc~0; 1645#L311-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 1647#L321-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1644#L322-7 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 1603#L815-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1582#L815-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1583#L329-21 assume 1 == ~t1_pc~0; 1819#L330-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1712#L340-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1713#L341-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1791#L823-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1792#L823-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1794#L348-21 assume 1 == ~t2_pc~0; 1921#L349-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1888#L359-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1889#L360-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1435#L831-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 1436#L831-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1333#L367-21 assume !(1 == ~t3_pc~0); 1298#L367-23 is_transmit3_triggered_~__retres1~3 := 0; 1299#L378-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1360#L379-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1481#L839-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1636#L839-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1560#L386-21 assume 1 == ~t4_pc~0; 1561#L387-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1567#L397-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1600#L398-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1693#L847-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1821#L847-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1781#L405-21 assume 1 == ~t5_pc~0; 1760#L406-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 1761#L416-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1758#L417-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1759#L855-21 assume !(0 != activate_threads_~tmp___4~0); 1920#L855-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1906#L424-21 assume 1 == ~t6_pc~0; 1878#L425-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 1430#L435-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1431#L436-7 activate_threads_#t~ret14 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1497#L863-21 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 1483#L863-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1484#L733-3 assume !(1 == ~M_E~0); 1904#L733-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1815#L738-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1459#L743-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1460#L748-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1296#L753-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1297#L758-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1402#L763-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1403#L768-3 assume !(1 == ~E_2~0); 1677#L773-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1678#L778-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1563#L783-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1564#L788-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1812#L793-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 1765#L494-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 1384#L531-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 1381#L532-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 1382#L1033 assume !(0 == start_simulation_~tmp~3); 1783#L1033-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 1766#L494-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 1391#L531-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 1388#L532-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 1389#L988 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1340#L995 stop_simulation_#res := stop_simulation_~__retres2~0; 1341#L996 start_simulation_#t~ret17 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 1473#L1046 assume !(0 != start_simulation_~tmp___0~1); 1571#L1014-3 [2018-11-18 15:29:26,449 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:26,449 INFO L82 PathProgramCache]: Analyzing trace with hash -1849530277, now seen corresponding path program 1 times [2018-11-18 15:29:26,449 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:26,450 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:26,450 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:26,450 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:26,450 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:26,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:26,500 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:29:26,500 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:29:26,501 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:29:26,501 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 15:29:26,501 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:26,501 INFO L82 PathProgramCache]: Analyzing trace with hash -1472042610, now seen corresponding path program 1 times [2018-11-18 15:29:26,501 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:26,501 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:26,502 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:26,502 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:26,502 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:26,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:26,558 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:29:26,559 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:29:26,559 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:29:26,559 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:29:26,559 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:29:26,560 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:29:26,560 INFO L87 Difference]: Start difference. First operand 636 states and 947 transitions. cyclomatic complexity: 312 Second operand 3 states. [2018-11-18 15:29:26,582 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:29:26,582 INFO L93 Difference]: Finished difference Result 636 states and 946 transitions. [2018-11-18 15:29:26,583 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:29:26,584 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 636 states and 946 transitions. [2018-11-18 15:29:26,588 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 547 [2018-11-18 15:29:26,592 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 636 states to 636 states and 946 transitions. [2018-11-18 15:29:26,592 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 636 [2018-11-18 15:29:26,593 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 636 [2018-11-18 15:29:26,593 INFO L73 IsDeterministic]: Start isDeterministic. Operand 636 states and 946 transitions. [2018-11-18 15:29:26,595 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:29:26,595 INFO L705 BuchiCegarLoop]: Abstraction has 636 states and 946 transitions. [2018-11-18 15:29:26,597 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 636 states and 946 transitions. [2018-11-18 15:29:26,607 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 636 to 636. [2018-11-18 15:29:26,608 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 636 states. [2018-11-18 15:29:26,610 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 636 states to 636 states and 946 transitions. [2018-11-18 15:29:26,610 INFO L728 BuchiCegarLoop]: Abstraction has 636 states and 946 transitions. [2018-11-18 15:29:26,610 INFO L608 BuchiCegarLoop]: Abstraction has 636 states and 946 transitions. [2018-11-18 15:29:26,610 INFO L442 BuchiCegarLoop]: ======== Iteration 3============ [2018-11-18 15:29:26,610 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 636 states and 946 transitions. [2018-11-18 15:29:26,613 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 547 [2018-11-18 15:29:26,614 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:29:26,614 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:29:26,615 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:26,615 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:26,616 INFO L794 eck$LassoCheckResult]: Stem: 3109#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 3001#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 3002#L977 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 2672#L444 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2673#L451 assume 1 == ~m_i~0;~m_st~0 := 0; 3121#L451-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2780#L456-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2781#L461-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2674#L466-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2675#L471-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2949#L476-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2950#L481-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3124#L660 assume !(0 == ~M_E~0); 3125#L660-2 assume !(0 == ~T1_E~0); 2579#L665-1 assume !(0 == ~T2_E~0); 2580#L670-1 assume !(0 == ~T3_E~0); 2683#L675-1 assume !(0 == ~T4_E~0); 2684#L680-1 assume !(0 == ~T5_E~0); 2958#L685-1 assume !(0 == ~T6_E~0); 2959#L690-1 assume 0 == ~E_1~0;~E_1~0 := 1; 2844#L695-1 assume !(0 == ~E_2~0); 2845#L700-1 assume !(0 == ~E_3~0); 3092#L705-1 assume !(0 == ~E_4~0); 2750#L710-1 assume !(0 == ~E_5~0); 2751#L715-1 assume !(0 == ~E_6~0); 2615#L720-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2616#L310 assume 1 == ~m_pc~0; 2805#L311 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 2803#L321 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2804#L322 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2933#L815 assume !(0 != activate_threads_~tmp~1); 3088#L815-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3005#L329 assume !(1 == ~t1_pc~0); 3006#L329-2 is_transmit1_triggered_~__retres1~1 := 0; 3003#L340 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3004#L341 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 3123#L823 assume !(0 != activate_threads_~tmp___0~0); 3196#L823-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3176#L348 assume 1 == ~t2_pc~0; 3177#L349 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3173#L359 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3174#L360 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2759#L831 assume !(0 != activate_threads_~tmp___1~0); 2745#L831-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2679#L367 assume !(1 == ~t3_pc~0); 2647#L367-2 is_transmit3_triggered_~__retres1~3 := 0; 2648#L378 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2678#L379 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2785#L839 assume !(0 != activate_threads_~tmp___2~0); 2966#L839-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2888#L386 assume 1 == ~t4_pc~0; 2790#L387 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2791#L397 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2788#L398 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2789#L847 assume !(0 != activate_threads_~tmp___3~0); 3129#L847-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3130#L405 assume 1 == ~t5_pc~0; 3048#L406 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 3049#L416 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3046#L417 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3047#L855 assume !(0 != activate_threads_~tmp___4~0); 3136#L855-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2726#L424 assume !(1 == ~t6_pc~0); 2727#L424-2 is_transmit6_triggered_~__retres1~6 := 0; 2724#L435 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2725#L436 activate_threads_#t~ret14 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2634#L863 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 2605#L863-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2606#L733 assume !(1 == ~M_E~0); 3186#L733-2 assume !(1 == ~T1_E~0); 3090#L738-1 assume !(1 == ~T2_E~0); 2748#L743-1 assume !(1 == ~T3_E~0); 2749#L748-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2610#L753-1 assume !(1 == ~T5_E~0); 2611#L758-1 assume !(1 == ~T6_E~0); 2695#L763-1 assume !(1 == ~E_1~0); 2696#L768-1 assume !(1 == ~E_2~0); 2954#L773-1 assume !(1 == ~E_3~0); 2955#L778-1 assume !(1 == ~E_4~0); 2837#L783-1 assume !(1 == ~E_5~0); 2838#L788-1 assume 1 == ~E_6~0;~E_6~0 := 2; 3087#L793-1 assume { :end_inline_reset_delta_events } true; 2850#L1014-3 [2018-11-18 15:29:26,616 INFO L796 eck$LassoCheckResult]: Loop: 2850#L1014-3 assume true; 2851#L1014-1 assume !false; 2869#L1015 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 2582#L635 assume true; 2833#L541-1 assume !false; 2834#L542 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 2944#L494 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 2658#L531 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 2655#L532 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 2656#L546 assume !(0 != eval_~tmp~0); 3093#L650 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 2676#L444-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 2677#L660-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3127#L660-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2593#L665-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2594#L670-3 assume !(0 == ~T3_E~0); 2685#L675-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2686#L680-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2961#L685-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2962#L690-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2824#L695-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2825#L700-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2894#L705-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2742#L710-3 assume !(0 == ~E_5~0); 2743#L715-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2584#L720-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2585#L310-21 assume 1 == ~m_pc~0; 2924#L311-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 2926#L321-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2923#L322-7 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 2882#L815-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2861#L815-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2862#L329-21 assume 1 == ~t1_pc~0; 3098#L330-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2991#L340-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2992#L341-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 3070#L823-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3071#L823-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3073#L348-21 assume 1 == ~t2_pc~0; 3200#L349-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3167#L359-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3168#L360-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2714#L831-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2715#L831-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2612#L367-21 assume !(1 == ~t3_pc~0); 2577#L367-23 is_transmit3_triggered_~__retres1~3 := 0; 2578#L378-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2639#L379-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2760#L839-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2918#L839-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2839#L386-21 assume 1 == ~t4_pc~0; 2840#L387-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2846#L397-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2879#L398-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2972#L847-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 3101#L847-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3060#L405-21 assume 1 == ~t5_pc~0; 3041#L406-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 3042#L416-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3037#L417-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3038#L855-21 assume !(0 != activate_threads_~tmp___4~0); 3199#L855-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 3185#L424-21 assume 1 == ~t6_pc~0; 3158#L425-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 2709#L435-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2710#L436-7 activate_threads_#t~ret14 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2776#L863-21 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 2762#L863-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2763#L733-3 assume !(1 == ~M_E~0); 3183#L733-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3094#L738-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2738#L743-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2739#L748-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2575#L753-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2576#L758-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2681#L763-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2682#L768-3 assume !(1 == ~E_2~0); 2956#L773-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2957#L778-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2842#L783-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2843#L788-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3091#L793-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 3044#L494-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 2665#L531-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 2660#L532-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 2661#L1033 assume !(0 == start_simulation_~tmp~3); 3062#L1033-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 3045#L494-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 2670#L531-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 2667#L532-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 2668#L988 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2622#L995 stop_simulation_#res := stop_simulation_~__retres2~0; 2623#L996 start_simulation_#t~ret17 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 2752#L1046 assume !(0 != start_simulation_~tmp___0~1); 2850#L1014-3 [2018-11-18 15:29:26,617 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:26,617 INFO L82 PathProgramCache]: Analyzing trace with hash 227806621, now seen corresponding path program 1 times [2018-11-18 15:29:26,617 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:26,617 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:26,618 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:26,618 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:26,618 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:26,624 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:26,664 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:29:26,664 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:29:26,664 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:29:26,664 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 15:29:26,664 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:26,664 INFO L82 PathProgramCache]: Analyzing trace with hash -1472042610, now seen corresponding path program 2 times [2018-11-18 15:29:26,664 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:26,665 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:26,665 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:26,665 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:26,665 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:26,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:26,708 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:29:26,708 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:29:26,708 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:29:26,709 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:29:26,709 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:29:26,709 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:29:26,709 INFO L87 Difference]: Start difference. First operand 636 states and 946 transitions. cyclomatic complexity: 311 Second operand 3 states. [2018-11-18 15:29:26,736 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:29:26,736 INFO L93 Difference]: Finished difference Result 636 states and 945 transitions. [2018-11-18 15:29:26,737 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:29:26,737 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 636 states and 945 transitions. [2018-11-18 15:29:26,741 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 547 [2018-11-18 15:29:26,744 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 636 states to 636 states and 945 transitions. [2018-11-18 15:29:26,744 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 636 [2018-11-18 15:29:26,745 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 636 [2018-11-18 15:29:26,745 INFO L73 IsDeterministic]: Start isDeterministic. Operand 636 states and 945 transitions. [2018-11-18 15:29:26,746 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:29:26,746 INFO L705 BuchiCegarLoop]: Abstraction has 636 states and 945 transitions. [2018-11-18 15:29:26,747 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 636 states and 945 transitions. [2018-11-18 15:29:26,755 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 636 to 636. [2018-11-18 15:29:26,755 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 636 states. [2018-11-18 15:29:26,757 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 636 states to 636 states and 945 transitions. [2018-11-18 15:29:26,757 INFO L728 BuchiCegarLoop]: Abstraction has 636 states and 945 transitions. [2018-11-18 15:29:26,758 INFO L608 BuchiCegarLoop]: Abstraction has 636 states and 945 transitions. [2018-11-18 15:29:26,758 INFO L442 BuchiCegarLoop]: ======== Iteration 4============ [2018-11-18 15:29:26,758 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 636 states and 945 transitions. [2018-11-18 15:29:26,760 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 547 [2018-11-18 15:29:26,761 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:29:26,761 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:29:26,762 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:26,762 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:26,763 INFO L794 eck$LassoCheckResult]: Stem: 4387#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 4277#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 4278#L977 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 3948#L444 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3949#L451 assume 1 == ~m_i~0;~m_st~0 := 0; 4399#L451-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4059#L456-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4060#L461-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3953#L466-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3954#L471-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4228#L476-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4229#L481-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4403#L660 assume !(0 == ~M_E~0); 4404#L660-2 assume !(0 == ~T1_E~0); 3856#L665-1 assume !(0 == ~T2_E~0); 3857#L670-1 assume !(0 == ~T3_E~0); 3962#L675-1 assume !(0 == ~T4_E~0); 3963#L680-1 assume !(0 == ~T5_E~0); 4237#L685-1 assume !(0 == ~T6_E~0); 4238#L690-1 assume 0 == ~E_1~0;~E_1~0 := 1; 4123#L695-1 assume !(0 == ~E_2~0); 4124#L700-1 assume !(0 == ~E_3~0); 4371#L705-1 assume !(0 == ~E_4~0); 4029#L710-1 assume !(0 == ~E_5~0); 4030#L715-1 assume !(0 == ~E_6~0); 3894#L720-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3895#L310 assume 1 == ~m_pc~0; 4084#L311 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 4079#L321 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4080#L322 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 4212#L815 assume !(0 != activate_threads_~tmp~1); 4367#L815-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4284#L329 assume !(1 == ~t1_pc~0); 4285#L329-2 is_transmit1_triggered_~__retres1~1 := 0; 4279#L340 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4280#L341 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 4402#L823 assume !(0 != activate_threads_~tmp___0~0); 4475#L823-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4454#L348 assume 1 == ~t2_pc~0; 4455#L349 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4452#L359 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4453#L360 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 4038#L831 assume !(0 != activate_threads_~tmp___1~0); 4024#L831-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3958#L367 assume !(1 == ~t3_pc~0); 3926#L367-2 is_transmit3_triggered_~__retres1~3 := 0; 3927#L378 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3957#L379 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 4062#L839 assume !(0 != activate_threads_~tmp___2~0); 4244#L839-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4167#L386 assume 1 == ~t4_pc~0; 4069#L387 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4070#L397 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4067#L398 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4068#L847 assume !(0 != activate_threads_~tmp___3~0); 4408#L847-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4409#L405 assume 1 == ~t5_pc~0; 4327#L406 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 4328#L416 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4325#L417 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4326#L855 assume !(0 != activate_threads_~tmp___4~0); 4415#L855-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 4005#L424 assume !(1 == ~t6_pc~0); 4006#L424-2 is_transmit6_triggered_~__retres1~6 := 0; 4001#L435 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 4002#L436 activate_threads_#t~ret14 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3913#L863 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 3881#L863-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3882#L733 assume !(1 == ~M_E~0); 4465#L733-2 assume !(1 == ~T1_E~0); 4369#L738-1 assume !(1 == ~T2_E~0); 4027#L743-1 assume !(1 == ~T3_E~0); 4028#L748-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3889#L753-1 assume !(1 == ~T5_E~0); 3890#L758-1 assume !(1 == ~T6_E~0); 3974#L763-1 assume !(1 == ~E_1~0); 3975#L768-1 assume !(1 == ~E_2~0); 4232#L773-1 assume !(1 == ~E_3~0); 4233#L778-1 assume !(1 == ~E_4~0); 4114#L783-1 assume !(1 == ~E_5~0); 4115#L788-1 assume 1 == ~E_6~0;~E_6~0 := 2; 4366#L793-1 assume { :end_inline_reset_delta_events } true; 4129#L1014-3 [2018-11-18 15:29:26,763 INFO L796 eck$LassoCheckResult]: Loop: 4129#L1014-3 assume true; 4130#L1014-1 assume !false; 4148#L1015 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 3861#L635 assume true; 4112#L541-1 assume !false; 4113#L542 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 4219#L494 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 3937#L531 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 3934#L532 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 3935#L546 assume !(0 != eval_~tmp~0); 4372#L650 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 3955#L444-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 3956#L660-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4406#L660-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3872#L665-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3873#L670-3 assume !(0 == ~T3_E~0); 3964#L675-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3965#L680-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4240#L685-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4241#L690-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4103#L695-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4104#L700-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4173#L705-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4021#L710-3 assume !(0 == ~E_5~0); 4022#L715-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3863#L720-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3864#L310-21 assume 1 == ~m_pc~0; 4203#L311-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 4205#L321-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4202#L322-7 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 4161#L815-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4140#L815-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4141#L329-21 assume 1 == ~t1_pc~0; 4377#L330-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 4270#L340-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4271#L341-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 4349#L823-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4350#L823-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4352#L348-21 assume !(1 == ~t2_pc~0); 4480#L348-23 is_transmit2_triggered_~__retres1~2 := 0; 4446#L359-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4447#L360-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3993#L831-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 3994#L831-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3891#L367-21 assume !(1 == ~t3_pc~0); 3858#L367-23 is_transmit3_triggered_~__retres1~3 := 0; 3859#L378-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3918#L379-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 4039#L839-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 4197#L839-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4118#L386-21 assume 1 == ~t4_pc~0; 4119#L387-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4125#L397-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4158#L398-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4251#L847-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 4380#L847-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4339#L405-21 assume 1 == ~t5_pc~0; 4320#L406-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 4321#L416-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4316#L417-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4317#L855-21 assume !(0 != activate_threads_~tmp___4~0); 4478#L855-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 4464#L424-21 assume 1 == ~t6_pc~0; 4437#L425-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 3988#L435-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 3989#L436-7 activate_threads_#t~ret14 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4055#L863-21 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 4041#L863-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4042#L733-3 assume !(1 == ~M_E~0); 4462#L733-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4373#L738-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4017#L743-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4018#L748-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3854#L753-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3855#L758-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3960#L763-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3961#L768-3 assume !(1 == ~E_2~0); 4235#L773-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4236#L778-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4121#L783-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4122#L788-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4370#L793-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 4323#L494-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 3944#L531-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 3939#L532-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 3940#L1033 assume !(0 == start_simulation_~tmp~3); 4341#L1033-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 4324#L494-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 3951#L531-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 3946#L532-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 3947#L988 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 3901#L995 stop_simulation_#res := stop_simulation_~__retres2~0; 3902#L996 start_simulation_#t~ret17 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 4031#L1046 assume !(0 != start_simulation_~tmp___0~1); 4129#L1014-3 [2018-11-18 15:29:26,763 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:26,764 INFO L82 PathProgramCache]: Analyzing trace with hash -1506297829, now seen corresponding path program 1 times [2018-11-18 15:29:26,764 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:26,764 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:26,765 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:26,765 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:29:26,765 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:26,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:26,797 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:29:26,798 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:29:26,798 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:29:26,798 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 15:29:26,798 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:26,799 INFO L82 PathProgramCache]: Analyzing trace with hash -1464292051, now seen corresponding path program 1 times [2018-11-18 15:29:26,799 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:26,799 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:26,800 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:26,800 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:26,800 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:26,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:26,851 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:29:26,852 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:29:26,852 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:29:26,852 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:29:26,852 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:29:26,853 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:29:26,853 INFO L87 Difference]: Start difference. First operand 636 states and 945 transitions. cyclomatic complexity: 310 Second operand 3 states. [2018-11-18 15:29:26,884 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:29:26,888 INFO L93 Difference]: Finished difference Result 636 states and 944 transitions. [2018-11-18 15:29:26,888 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:29:26,888 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 636 states and 944 transitions. [2018-11-18 15:29:26,891 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 547 [2018-11-18 15:29:26,894 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 636 states to 636 states and 944 transitions. [2018-11-18 15:29:26,894 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 636 [2018-11-18 15:29:26,894 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 636 [2018-11-18 15:29:26,894 INFO L73 IsDeterministic]: Start isDeterministic. Operand 636 states and 944 transitions. [2018-11-18 15:29:26,895 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:29:26,896 INFO L705 BuchiCegarLoop]: Abstraction has 636 states and 944 transitions. [2018-11-18 15:29:26,897 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 636 states and 944 transitions. [2018-11-18 15:29:26,904 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 636 to 636. [2018-11-18 15:29:26,904 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 636 states. [2018-11-18 15:29:26,905 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 636 states to 636 states and 944 transitions. [2018-11-18 15:29:26,906 INFO L728 BuchiCegarLoop]: Abstraction has 636 states and 944 transitions. [2018-11-18 15:29:26,906 INFO L608 BuchiCegarLoop]: Abstraction has 636 states and 944 transitions. [2018-11-18 15:29:26,906 INFO L442 BuchiCegarLoop]: ======== Iteration 5============ [2018-11-18 15:29:26,906 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 636 states and 944 transitions. [2018-11-18 15:29:26,909 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 547 [2018-11-18 15:29:26,909 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:29:26,909 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:29:26,910 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:26,910 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:26,910 INFO L794 eck$LassoCheckResult]: Stem: 5666#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 5556#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 5557#L977 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 5227#L444 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5228#L451 assume 1 == ~m_i~0;~m_st~0 := 0; 5678#L451-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5338#L456-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5339#L461-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5232#L466-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5233#L471-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5507#L476-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5508#L481-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5682#L660 assume !(0 == ~M_E~0); 5683#L660-2 assume !(0 == ~T1_E~0); 5135#L665-1 assume !(0 == ~T2_E~0); 5136#L670-1 assume !(0 == ~T3_E~0); 5241#L675-1 assume !(0 == ~T4_E~0); 5242#L680-1 assume !(0 == ~T5_E~0); 5516#L685-1 assume !(0 == ~T6_E~0); 5517#L690-1 assume 0 == ~E_1~0;~E_1~0 := 1; 5402#L695-1 assume !(0 == ~E_2~0); 5403#L700-1 assume !(0 == ~E_3~0); 5650#L705-1 assume !(0 == ~E_4~0); 5308#L710-1 assume !(0 == ~E_5~0); 5309#L715-1 assume !(0 == ~E_6~0); 5173#L720-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5174#L310 assume 1 == ~m_pc~0; 5363#L311 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 5358#L321 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5359#L322 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 5491#L815 assume !(0 != activate_threads_~tmp~1); 5646#L815-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5563#L329 assume !(1 == ~t1_pc~0); 5564#L329-2 is_transmit1_triggered_~__retres1~1 := 0; 5558#L340 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5559#L341 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 5681#L823 assume !(0 != activate_threads_~tmp___0~0); 5754#L823-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5733#L348 assume 1 == ~t2_pc~0; 5734#L349 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5731#L359 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5732#L360 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 5317#L831 assume !(0 != activate_threads_~tmp___1~0); 5303#L831-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5237#L367 assume !(1 == ~t3_pc~0); 5205#L367-2 is_transmit3_triggered_~__retres1~3 := 0; 5206#L378 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5236#L379 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 5341#L839 assume !(0 != activate_threads_~tmp___2~0); 5523#L839-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5446#L386 assume 1 == ~t4_pc~0; 5348#L387 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5349#L397 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5346#L398 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 5347#L847 assume !(0 != activate_threads_~tmp___3~0); 5687#L847-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5688#L405 assume 1 == ~t5_pc~0; 5606#L406 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 5607#L416 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5604#L417 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 5605#L855 assume !(0 != activate_threads_~tmp___4~0); 5694#L855-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 5284#L424 assume !(1 == ~t6_pc~0); 5285#L424-2 is_transmit6_triggered_~__retres1~6 := 0; 5280#L435 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 5281#L436 activate_threads_#t~ret14 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5192#L863 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 5160#L863-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5161#L733 assume !(1 == ~M_E~0); 5744#L733-2 assume !(1 == ~T1_E~0); 5648#L738-1 assume !(1 == ~T2_E~0); 5306#L743-1 assume !(1 == ~T3_E~0); 5307#L748-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5168#L753-1 assume !(1 == ~T5_E~0); 5169#L758-1 assume !(1 == ~T6_E~0); 5253#L763-1 assume !(1 == ~E_1~0); 5254#L768-1 assume !(1 == ~E_2~0); 5511#L773-1 assume !(1 == ~E_3~0); 5512#L778-1 assume !(1 == ~E_4~0); 5393#L783-1 assume !(1 == ~E_5~0); 5394#L788-1 assume 1 == ~E_6~0;~E_6~0 := 2; 5645#L793-1 assume { :end_inline_reset_delta_events } true; 5408#L1014-3 [2018-11-18 15:29:26,911 INFO L796 eck$LassoCheckResult]: Loop: 5408#L1014-3 assume true; 5409#L1014-1 assume !false; 5427#L1015 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 5140#L635 assume true; 5391#L541-1 assume !false; 5392#L542 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 5498#L494 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 5216#L531 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 5213#L532 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 5214#L546 assume !(0 != eval_~tmp~0); 5651#L650 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 5234#L444-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 5235#L660-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5685#L660-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5151#L665-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5152#L670-3 assume !(0 == ~T3_E~0); 5243#L675-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5244#L680-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5519#L685-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5520#L690-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5382#L695-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5383#L700-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5452#L705-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5300#L710-3 assume !(0 == ~E_5~0); 5301#L715-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5142#L720-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5143#L310-21 assume 1 == ~m_pc~0; 5482#L311-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 5484#L321-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5481#L322-7 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 5440#L815-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 5419#L815-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5420#L329-21 assume 1 == ~t1_pc~0; 5656#L330-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 5549#L340-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5550#L341-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 5628#L823-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 5629#L823-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 5631#L348-21 assume 1 == ~t2_pc~0; 5758#L349-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5725#L359-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5726#L360-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 5272#L831-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 5273#L831-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5170#L367-21 assume !(1 == ~t3_pc~0); 5137#L367-23 is_transmit3_triggered_~__retres1~3 := 0; 5138#L378-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 5197#L379-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 5318#L839-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 5476#L839-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5397#L386-21 assume 1 == ~t4_pc~0; 5398#L387-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5404#L397-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5437#L398-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 5530#L847-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 5659#L847-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5618#L405-21 assume !(1 == ~t5_pc~0); 5601#L405-23 is_transmit5_triggered_~__retres1~5 := 0; 5600#L416-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5595#L417-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 5596#L855-21 assume !(0 != activate_threads_~tmp___4~0); 5757#L855-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 5743#L424-21 assume 1 == ~t6_pc~0; 5716#L425-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 5267#L435-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 5268#L436-7 activate_threads_#t~ret14 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5334#L863-21 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 5320#L863-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5321#L733-3 assume !(1 == ~M_E~0); 5741#L733-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5652#L738-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5296#L743-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5297#L748-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5133#L753-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5134#L758-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5239#L763-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5240#L768-3 assume !(1 == ~E_2~0); 5514#L773-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5515#L778-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5400#L783-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5401#L788-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5649#L793-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 5602#L494-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 5223#L531-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 5218#L532-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 5219#L1033 assume !(0 == start_simulation_~tmp~3); 5620#L1033-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 5603#L494-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 5230#L531-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 5225#L532-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 5226#L988 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5180#L995 stop_simulation_#res := stop_simulation_~__retres2~0; 5181#L996 start_simulation_#t~ret17 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 5310#L1046 assume !(0 != start_simulation_~tmp___0~1); 5408#L1014-3 [2018-11-18 15:29:26,911 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:26,911 INFO L82 PathProgramCache]: Analyzing trace with hash 1901446621, now seen corresponding path program 1 times [2018-11-18 15:29:26,911 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:26,911 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:26,912 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:26,912 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:26,912 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:26,916 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:26,939 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:29:26,940 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:29:26,940 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:29:26,940 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 15:29:26,940 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:26,940 INFO L82 PathProgramCache]: Analyzing trace with hash -948721939, now seen corresponding path program 1 times [2018-11-18 15:29:26,940 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:26,941 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:26,941 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:26,941 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:26,941 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:26,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:26,973 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:29:26,974 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:29:26,974 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:29:26,974 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:29:26,974 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:29:26,974 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:29:26,975 INFO L87 Difference]: Start difference. First operand 636 states and 944 transitions. cyclomatic complexity: 309 Second operand 3 states. [2018-11-18 15:29:26,984 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:29:26,985 INFO L93 Difference]: Finished difference Result 636 states and 943 transitions. [2018-11-18 15:29:26,986 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:29:26,986 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 636 states and 943 transitions. [2018-11-18 15:29:26,989 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 547 [2018-11-18 15:29:26,991 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 636 states to 636 states and 943 transitions. [2018-11-18 15:29:26,992 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 636 [2018-11-18 15:29:26,992 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 636 [2018-11-18 15:29:26,992 INFO L73 IsDeterministic]: Start isDeterministic. Operand 636 states and 943 transitions. [2018-11-18 15:29:26,993 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:29:26,993 INFO L705 BuchiCegarLoop]: Abstraction has 636 states and 943 transitions. [2018-11-18 15:29:26,994 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 636 states and 943 transitions. [2018-11-18 15:29:27,000 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 636 to 636. [2018-11-18 15:29:27,000 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 636 states. [2018-11-18 15:29:27,002 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 636 states to 636 states and 943 transitions. [2018-11-18 15:29:27,002 INFO L728 BuchiCegarLoop]: Abstraction has 636 states and 943 transitions. [2018-11-18 15:29:27,002 INFO L608 BuchiCegarLoop]: Abstraction has 636 states and 943 transitions. [2018-11-18 15:29:27,002 INFO L442 BuchiCegarLoop]: ======== Iteration 6============ [2018-11-18 15:29:27,002 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 636 states and 943 transitions. [2018-11-18 15:29:27,004 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 547 [2018-11-18 15:29:27,004 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:29:27,005 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:29:27,006 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:27,006 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:27,006 INFO L794 eck$LassoCheckResult]: Stem: 6945#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 6838#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 6839#L977 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 6509#L444 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6510#L451 assume 1 == ~m_i~0;~m_st~0 := 0; 6958#L451-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6617#L456-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6618#L461-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6511#L466-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6512#L471-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6786#L476-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6787#L481-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6961#L660 assume !(0 == ~M_E~0); 6962#L660-2 assume !(0 == ~T1_E~0); 6416#L665-1 assume !(0 == ~T2_E~0); 6417#L670-1 assume !(0 == ~T3_E~0); 6520#L675-1 assume !(0 == ~T4_E~0); 6521#L680-1 assume !(0 == ~T5_E~0); 6795#L685-1 assume !(0 == ~T6_E~0); 6796#L690-1 assume 0 == ~E_1~0;~E_1~0 := 1; 6681#L695-1 assume !(0 == ~E_2~0); 6682#L700-1 assume !(0 == ~E_3~0); 6929#L705-1 assume !(0 == ~E_4~0); 6587#L710-1 assume !(0 == ~E_5~0); 6588#L715-1 assume !(0 == ~E_6~0); 6452#L720-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6453#L310 assume 1 == ~m_pc~0; 6642#L311 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 6640#L321 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6641#L322 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 6770#L815 assume !(0 != activate_threads_~tmp~1); 6925#L815-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6842#L329 assume !(1 == ~t1_pc~0); 6843#L329-2 is_transmit1_triggered_~__retres1~1 := 0; 6840#L340 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6841#L341 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 6960#L823 assume !(0 != activate_threads_~tmp___0~0); 7033#L823-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7012#L348 assume 1 == ~t2_pc~0; 7013#L349 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 7010#L359 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7011#L360 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 6596#L831 assume !(0 != activate_threads_~tmp___1~0); 6582#L831-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6516#L367 assume !(1 == ~t3_pc~0); 6484#L367-2 is_transmit3_triggered_~__retres1~3 := 0; 6485#L378 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6515#L379 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 6620#L839 assume !(0 != activate_threads_~tmp___2~0); 6802#L839-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6725#L386 assume 1 == ~t4_pc~0; 6627#L387 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 6628#L397 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6625#L398 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 6626#L847 assume !(0 != activate_threads_~tmp___3~0); 6966#L847-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 6967#L405 assume 1 == ~t5_pc~0; 6885#L406 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 6886#L416 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 6883#L417 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 6884#L855 assume !(0 != activate_threads_~tmp___4~0); 6973#L855-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 6563#L424 assume !(1 == ~t6_pc~0); 6564#L424-2 is_transmit6_triggered_~__retres1~6 := 0; 6559#L435 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 6560#L436 activate_threads_#t~ret14 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 6471#L863 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 6439#L863-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6440#L733 assume !(1 == ~M_E~0); 7023#L733-2 assume !(1 == ~T1_E~0); 6927#L738-1 assume !(1 == ~T2_E~0); 6585#L743-1 assume !(1 == ~T3_E~0); 6586#L748-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6447#L753-1 assume !(1 == ~T5_E~0); 6448#L758-1 assume !(1 == ~T6_E~0); 6532#L763-1 assume !(1 == ~E_1~0); 6533#L768-1 assume !(1 == ~E_2~0); 6790#L773-1 assume !(1 == ~E_3~0); 6791#L778-1 assume !(1 == ~E_4~0); 6674#L783-1 assume !(1 == ~E_5~0); 6675#L788-1 assume 1 == ~E_6~0;~E_6~0 := 2; 6924#L793-1 assume { :end_inline_reset_delta_events } true; 6687#L1014-3 [2018-11-18 15:29:27,006 INFO L796 eck$LassoCheckResult]: Loop: 6687#L1014-3 assume true; 6688#L1014-1 assume !false; 6706#L1015 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 6419#L635 assume true; 6670#L541-1 assume !false; 6671#L542 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 6778#L494 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 6495#L531 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 6492#L532 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 6493#L546 assume !(0 != eval_~tmp~0); 6930#L650 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 6513#L444-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 6514#L660-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6964#L660-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6432#L665-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6433#L670-3 assume !(0 == ~T3_E~0); 6522#L675-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6523#L680-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6798#L685-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6799#L690-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6661#L695-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6662#L700-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6731#L705-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6579#L710-3 assume !(0 == ~E_5~0); 6580#L715-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6421#L720-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6422#L310-21 assume 1 == ~m_pc~0; 6761#L311-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 6763#L321-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6760#L322-7 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 6719#L815-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 6698#L815-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6699#L329-21 assume 1 == ~t1_pc~0; 6935#L330-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 6828#L340-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6829#L341-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 6907#L823-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 6908#L823-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6910#L348-21 assume 1 == ~t2_pc~0; 7037#L349-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 7004#L359-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7005#L360-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 6551#L831-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 6552#L831-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6449#L367-21 assume 1 == ~t3_pc~0; 6450#L368-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 6415#L378-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6476#L379-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 6597#L839-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 6752#L839-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6676#L386-21 assume 1 == ~t4_pc~0; 6677#L387-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 6683#L397-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6716#L398-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 6809#L847-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 6937#L847-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 6897#L405-21 assume 1 == ~t5_pc~0; 6876#L406-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 6877#L416-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 6874#L417-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 6875#L855-21 assume !(0 != activate_threads_~tmp___4~0); 7036#L855-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 7022#L424-21 assume 1 == ~t6_pc~0; 6994#L425-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 6546#L435-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 6547#L436-7 activate_threads_#t~ret14 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 6613#L863-21 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 6599#L863-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6600#L733-3 assume !(1 == ~M_E~0); 7020#L733-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6931#L738-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6575#L743-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6576#L748-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6412#L753-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6413#L758-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6518#L763-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6519#L768-3 assume !(1 == ~E_2~0); 6793#L773-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6794#L778-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6679#L783-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6680#L788-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6928#L793-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 6881#L494-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 6500#L531-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 6497#L532-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 6498#L1033 assume !(0 == start_simulation_~tmp~3); 6899#L1033-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 6882#L494-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 6507#L531-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 6504#L532-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 6505#L988 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 6456#L995 stop_simulation_#res := stop_simulation_~__retres2~0; 6457#L996 start_simulation_#t~ret17 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 6589#L1046 assume !(0 != start_simulation_~tmp___0~1); 6687#L1014-3 [2018-11-18 15:29:27,006 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:27,007 INFO L82 PathProgramCache]: Analyzing trace with hash -482478117, now seen corresponding path program 1 times [2018-11-18 15:29:27,007 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:27,007 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:27,007 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:27,007 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:27,008 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:27,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:27,027 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:29:27,027 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:29:27,027 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:29:27,027 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 15:29:27,028 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:27,028 INFO L82 PathProgramCache]: Analyzing trace with hash 258294447, now seen corresponding path program 1 times [2018-11-18 15:29:27,028 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:27,028 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:27,029 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:27,029 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:27,029 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:27,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:27,066 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:29:27,066 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:29:27,066 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:29:27,066 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:29:27,066 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:29:27,067 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:29:27,067 INFO L87 Difference]: Start difference. First operand 636 states and 943 transitions. cyclomatic complexity: 308 Second operand 3 states. [2018-11-18 15:29:27,080 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:29:27,080 INFO L93 Difference]: Finished difference Result 636 states and 942 transitions. [2018-11-18 15:29:27,084 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:29:27,084 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 636 states and 942 transitions. [2018-11-18 15:29:27,086 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 547 [2018-11-18 15:29:27,087 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 636 states to 636 states and 942 transitions. [2018-11-18 15:29:27,087 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 636 [2018-11-18 15:29:27,088 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 636 [2018-11-18 15:29:27,088 INFO L73 IsDeterministic]: Start isDeterministic. Operand 636 states and 942 transitions. [2018-11-18 15:29:27,089 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:29:27,089 INFO L705 BuchiCegarLoop]: Abstraction has 636 states and 942 transitions. [2018-11-18 15:29:27,090 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 636 states and 942 transitions. [2018-11-18 15:29:27,093 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 636 to 636. [2018-11-18 15:29:27,093 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 636 states. [2018-11-18 15:29:27,095 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 636 states to 636 states and 942 transitions. [2018-11-18 15:29:27,095 INFO L728 BuchiCegarLoop]: Abstraction has 636 states and 942 transitions. [2018-11-18 15:29:27,095 INFO L608 BuchiCegarLoop]: Abstraction has 636 states and 942 transitions. [2018-11-18 15:29:27,095 INFO L442 BuchiCegarLoop]: ======== Iteration 7============ [2018-11-18 15:29:27,095 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 636 states and 942 transitions. [2018-11-18 15:29:27,097 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 547 [2018-11-18 15:29:27,097 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:29:27,097 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:29:27,098 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:27,098 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:27,098 INFO L794 eck$LassoCheckResult]: Stem: 8225#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 8117#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 8118#L977 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 7788#L444 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7789#L451 assume 1 == ~m_i~0;~m_st~0 := 0; 8237#L451-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7896#L456-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7897#L461-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7790#L466-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7791#L471-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8065#L476-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 8066#L481-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8240#L660 assume !(0 == ~M_E~0); 8241#L660-2 assume !(0 == ~T1_E~0); 7695#L665-1 assume !(0 == ~T2_E~0); 7696#L670-1 assume !(0 == ~T3_E~0); 7799#L675-1 assume !(0 == ~T4_E~0); 7800#L680-1 assume !(0 == ~T5_E~0); 8074#L685-1 assume !(0 == ~T6_E~0); 8075#L690-1 assume 0 == ~E_1~0;~E_1~0 := 1; 7960#L695-1 assume !(0 == ~E_2~0); 7961#L700-1 assume !(0 == ~E_3~0); 8208#L705-1 assume !(0 == ~E_4~0); 7866#L710-1 assume !(0 == ~E_5~0); 7867#L715-1 assume !(0 == ~E_6~0); 7731#L720-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7732#L310 assume 1 == ~m_pc~0; 7921#L311 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 7919#L321 is_master_triggered_#res := is_master_triggered_~__retres1~0; 7920#L322 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 8049#L815 assume !(0 != activate_threads_~tmp~1); 8204#L815-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8121#L329 assume !(1 == ~t1_pc~0); 8122#L329-2 is_transmit1_triggered_~__retres1~1 := 0; 8119#L340 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8120#L341 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 8239#L823 assume !(0 != activate_threads_~tmp___0~0); 8312#L823-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8292#L348 assume 1 == ~t2_pc~0; 8293#L349 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 8289#L359 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8290#L360 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 7875#L831 assume !(0 != activate_threads_~tmp___1~0); 7861#L831-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7795#L367 assume !(1 == ~t3_pc~0); 7763#L367-2 is_transmit3_triggered_~__retres1~3 := 0; 7764#L378 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7794#L379 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 7901#L839 assume !(0 != activate_threads_~tmp___2~0); 8082#L839-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 8004#L386 assume 1 == ~t4_pc~0; 7906#L387 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 7907#L397 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7904#L398 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 7905#L847 assume !(0 != activate_threads_~tmp___3~0); 8245#L847-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 8246#L405 assume 1 == ~t5_pc~0; 8164#L406 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 8165#L416 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 8162#L417 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 8163#L855 assume !(0 != activate_threads_~tmp___4~0); 8252#L855-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 7842#L424 assume !(1 == ~t6_pc~0); 7843#L424-2 is_transmit6_triggered_~__retres1~6 := 0; 7840#L435 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 7841#L436 activate_threads_#t~ret14 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 7750#L863 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 7721#L863-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7722#L733 assume !(1 == ~M_E~0); 8302#L733-2 assume !(1 == ~T1_E~0); 8206#L738-1 assume !(1 == ~T2_E~0); 7864#L743-1 assume !(1 == ~T3_E~0); 7865#L748-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7726#L753-1 assume !(1 == ~T5_E~0); 7727#L758-1 assume !(1 == ~T6_E~0); 7811#L763-1 assume !(1 == ~E_1~0); 7812#L768-1 assume !(1 == ~E_2~0); 8070#L773-1 assume !(1 == ~E_3~0); 8071#L778-1 assume !(1 == ~E_4~0); 7953#L783-1 assume !(1 == ~E_5~0); 7954#L788-1 assume 1 == ~E_6~0;~E_6~0 := 2; 8203#L793-1 assume { :end_inline_reset_delta_events } true; 7966#L1014-3 [2018-11-18 15:29:27,098 INFO L796 eck$LassoCheckResult]: Loop: 7966#L1014-3 assume true; 7967#L1014-1 assume !false; 7985#L1015 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 7698#L635 assume true; 7949#L541-1 assume !false; 7950#L542 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 8060#L494 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 7774#L531 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 7771#L532 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 7772#L546 assume !(0 != eval_~tmp~0); 8209#L650 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 7792#L444-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 7793#L660-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8243#L660-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7709#L665-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7710#L670-3 assume !(0 == ~T3_E~0); 7801#L675-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7802#L680-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8077#L685-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8078#L690-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7940#L695-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7941#L700-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8010#L705-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7858#L710-3 assume !(0 == ~E_5~0); 7859#L715-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7700#L720-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7701#L310-21 assume 1 == ~m_pc~0; 8040#L311-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 8042#L321-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8039#L322-7 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 7998#L815-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 7977#L815-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 7978#L329-21 assume 1 == ~t1_pc~0; 8214#L330-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 8107#L340-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8108#L341-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 8186#L823-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 8187#L823-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8189#L348-21 assume 1 == ~t2_pc~0; 8316#L349-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 8283#L359-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8284#L360-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 7830#L831-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 7831#L831-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 7728#L367-21 assume 1 == ~t3_pc~0; 7729#L368-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 7694#L378-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7755#L379-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 7876#L839-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 8034#L839-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7955#L386-21 assume 1 == ~t4_pc~0; 7956#L387-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 7962#L397-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 7995#L398-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 8088#L847-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 8217#L847-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 8176#L405-21 assume 1 == ~t5_pc~0; 8157#L406-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 8158#L416-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 8153#L417-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 8154#L855-21 assume !(0 != activate_threads_~tmp___4~0); 8315#L855-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 8301#L424-21 assume 1 == ~t6_pc~0; 8274#L425-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 7825#L435-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 7826#L436-7 activate_threads_#t~ret14 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 7892#L863-21 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 7878#L863-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7879#L733-3 assume !(1 == ~M_E~0); 8299#L733-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8210#L738-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7854#L743-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7855#L748-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7691#L753-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7692#L758-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7797#L763-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7798#L768-3 assume !(1 == ~E_2~0); 8072#L773-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8073#L778-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7958#L783-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7959#L788-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8207#L793-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 8160#L494-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 7781#L531-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 7776#L532-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 7777#L1033 assume !(0 == start_simulation_~tmp~3); 8178#L1033-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 8161#L494-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 7786#L531-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 7783#L532-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 7784#L988 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 7738#L995 stop_simulation_#res := stop_simulation_~__retres2~0; 7739#L996 start_simulation_#t~ret17 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 7868#L1046 assume !(0 != start_simulation_~tmp___0~1); 7966#L1014-3 [2018-11-18 15:29:27,098 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:27,099 INFO L82 PathProgramCache]: Analyzing trace with hash -559378915, now seen corresponding path program 1 times [2018-11-18 15:29:27,099 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:27,099 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:27,099 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:27,099 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:27,100 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:27,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:27,122 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:29:27,122 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:29:27,122 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 15:29:27,122 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 15:29:27,122 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:27,122 INFO L82 PathProgramCache]: Analyzing trace with hash 258294447, now seen corresponding path program 2 times [2018-11-18 15:29:27,123 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:27,123 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:27,123 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:27,123 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:27,123 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:27,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:27,147 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:29:27,147 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:29:27,147 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:29:27,148 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:29:27,148 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:29:27,148 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:29:27,148 INFO L87 Difference]: Start difference. First operand 636 states and 942 transitions. cyclomatic complexity: 307 Second operand 3 states. [2018-11-18 15:29:27,205 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:29:27,205 INFO L93 Difference]: Finished difference Result 636 states and 929 transitions. [2018-11-18 15:29:27,206 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:29:27,206 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 636 states and 929 transitions. [2018-11-18 15:29:27,208 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 547 [2018-11-18 15:29:27,209 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 636 states to 636 states and 929 transitions. [2018-11-18 15:29:27,209 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 636 [2018-11-18 15:29:27,210 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 636 [2018-11-18 15:29:27,210 INFO L73 IsDeterministic]: Start isDeterministic. Operand 636 states and 929 transitions. [2018-11-18 15:29:27,211 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:29:27,211 INFO L705 BuchiCegarLoop]: Abstraction has 636 states and 929 transitions. [2018-11-18 15:29:27,212 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 636 states and 929 transitions. [2018-11-18 15:29:27,216 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 636 to 636. [2018-11-18 15:29:27,216 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 636 states. [2018-11-18 15:29:27,217 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 636 states to 636 states and 929 transitions. [2018-11-18 15:29:27,217 INFO L728 BuchiCegarLoop]: Abstraction has 636 states and 929 transitions. [2018-11-18 15:29:27,217 INFO L608 BuchiCegarLoop]: Abstraction has 636 states and 929 transitions. [2018-11-18 15:29:27,218 INFO L442 BuchiCegarLoop]: ======== Iteration 8============ [2018-11-18 15:29:27,218 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 636 states and 929 transitions. [2018-11-18 15:29:27,219 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 547 [2018-11-18 15:29:27,219 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:29:27,219 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:29:27,220 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:27,220 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:27,220 INFO L794 eck$LassoCheckResult]: Stem: 9503#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 9393#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 9394#L977 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 9064#L444 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9065#L451 assume 1 == ~m_i~0;~m_st~0 := 0; 9515#L451-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9175#L456-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9176#L461-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9069#L466-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9070#L471-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9344#L476-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 9345#L481-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9519#L660 assume !(0 == ~M_E~0); 9520#L660-2 assume !(0 == ~T1_E~0); 8972#L665-1 assume !(0 == ~T2_E~0); 8973#L670-1 assume !(0 == ~T3_E~0); 9078#L675-1 assume !(0 == ~T4_E~0); 9079#L680-1 assume !(0 == ~T5_E~0); 9353#L685-1 assume !(0 == ~T6_E~0); 9354#L690-1 assume !(0 == ~E_1~0); 9239#L695-1 assume !(0 == ~E_2~0); 9240#L700-1 assume !(0 == ~E_3~0); 9487#L705-1 assume !(0 == ~E_4~0); 9145#L710-1 assume !(0 == ~E_5~0); 9146#L715-1 assume !(0 == ~E_6~0); 9010#L720-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9011#L310 assume 1 == ~m_pc~0; 9200#L311 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 9195#L321 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9196#L322 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 9328#L815 assume !(0 != activate_threads_~tmp~1); 9483#L815-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9400#L329 assume !(1 == ~t1_pc~0); 9401#L329-2 is_transmit1_triggered_~__retres1~1 := 0; 9395#L340 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9396#L341 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 9518#L823 assume !(0 != activate_threads_~tmp___0~0); 9591#L823-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9570#L348 assume 1 == ~t2_pc~0; 9571#L349 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 9568#L359 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9569#L360 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 9154#L831 assume !(0 != activate_threads_~tmp___1~0); 9140#L831-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9074#L367 assume !(1 == ~t3_pc~0); 9042#L367-2 is_transmit3_triggered_~__retres1~3 := 0; 9043#L378 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9073#L379 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 9178#L839 assume !(0 != activate_threads_~tmp___2~0); 9360#L839-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9283#L386 assume 1 == ~t4_pc~0; 9185#L387 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 9186#L397 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9183#L398 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 9184#L847 assume !(0 != activate_threads_~tmp___3~0); 9524#L847-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 9525#L405 assume 1 == ~t5_pc~0; 9443#L406 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 9444#L416 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 9441#L417 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 9442#L855 assume !(0 != activate_threads_~tmp___4~0); 9531#L855-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 9121#L424 assume !(1 == ~t6_pc~0); 9122#L424-2 is_transmit6_triggered_~__retres1~6 := 0; 9117#L435 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 9118#L436 activate_threads_#t~ret14 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 9029#L863 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 8997#L863-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8998#L733 assume !(1 == ~M_E~0); 9581#L733-2 assume !(1 == ~T1_E~0); 9485#L738-1 assume !(1 == ~T2_E~0); 9143#L743-1 assume !(1 == ~T3_E~0); 9144#L748-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9005#L753-1 assume !(1 == ~T5_E~0); 9006#L758-1 assume !(1 == ~T6_E~0); 9090#L763-1 assume !(1 == ~E_1~0); 9091#L768-1 assume !(1 == ~E_2~0); 9348#L773-1 assume !(1 == ~E_3~0); 9349#L778-1 assume !(1 == ~E_4~0); 9230#L783-1 assume !(1 == ~E_5~0); 9231#L788-1 assume 1 == ~E_6~0;~E_6~0 := 2; 9482#L793-1 assume { :end_inline_reset_delta_events } true; 9245#L1014-3 [2018-11-18 15:29:27,220 INFO L796 eck$LassoCheckResult]: Loop: 9245#L1014-3 assume true; 9246#L1014-1 assume !false; 9264#L1015 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 8977#L635 assume true; 9228#L541-1 assume !false; 9229#L542 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 9335#L494 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 9053#L531 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 9050#L532 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 9051#L546 assume !(0 != eval_~tmp~0); 9488#L650 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 9071#L444-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 9072#L660-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9522#L660-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8988#L665-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8989#L670-3 assume !(0 == ~T3_E~0); 9080#L675-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9081#L680-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9356#L685-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9357#L690-3 assume !(0 == ~E_1~0); 9219#L695-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9220#L700-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9289#L705-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9137#L710-3 assume !(0 == ~E_5~0); 9138#L715-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8979#L720-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8980#L310-21 assume 1 == ~m_pc~0; 9319#L311-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 9321#L321-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 9318#L322-7 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 9277#L815-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 9256#L815-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9257#L329-21 assume !(1 == ~t1_pc~0); 9494#L329-23 is_transmit1_triggered_~__retres1~1 := 0; 9386#L340-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9387#L341-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 9465#L823-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 9466#L823-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9468#L348-21 assume 1 == ~t2_pc~0; 9595#L349-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 9562#L359-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9563#L360-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 9109#L831-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 9110#L831-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 9007#L367-21 assume 1 == ~t3_pc~0; 9008#L368-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 8975#L378-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9034#L379-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 9155#L839-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 9313#L839-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9234#L386-21 assume 1 == ~t4_pc~0; 9235#L387-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 9241#L397-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9274#L398-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 9367#L847-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 9496#L847-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 9455#L405-21 assume 1 == ~t5_pc~0; 9436#L406-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 9437#L416-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 9432#L417-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 9433#L855-21 assume !(0 != activate_threads_~tmp___4~0); 9594#L855-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 9580#L424-21 assume 1 == ~t6_pc~0; 9553#L425-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 9104#L435-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 9105#L436-7 activate_threads_#t~ret14 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 9171#L863-21 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 9157#L863-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9158#L733-3 assume !(1 == ~M_E~0); 9578#L733-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9489#L738-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9133#L743-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9134#L748-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8970#L753-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8971#L758-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9076#L763-3 assume !(1 == ~E_1~0); 9077#L768-3 assume !(1 == ~E_2~0); 9351#L773-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9352#L778-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9237#L783-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9238#L788-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9486#L793-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 9439#L494-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 9060#L531-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 9055#L532-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 9056#L1033 assume !(0 == start_simulation_~tmp~3); 9457#L1033-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 9440#L494-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 9067#L531-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 9062#L532-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 9063#L988 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 9017#L995 stop_simulation_#res := stop_simulation_~__retres2~0; 9018#L996 start_simulation_#t~ret17 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 9147#L1046 assume !(0 != start_simulation_~tmp___0~1); 9245#L1014-3 [2018-11-18 15:29:27,221 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:27,221 INFO L82 PathProgramCache]: Analyzing trace with hash -976775521, now seen corresponding path program 1 times [2018-11-18 15:29:27,221 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:27,221 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:27,221 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:27,222 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:29:27,222 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:27,225 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:27,250 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:29:27,250 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:29:27,250 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 15:29:27,250 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 15:29:27,250 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:27,251 INFO L82 PathProgramCache]: Analyzing trace with hash 2123181074, now seen corresponding path program 1 times [2018-11-18 15:29:27,251 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:27,251 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:27,251 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:27,251 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:27,251 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:27,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:27,278 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:29:27,279 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:29:27,279 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:29:27,279 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:29:27,279 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:29:27,279 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:29:27,279 INFO L87 Difference]: Start difference. First operand 636 states and 929 transitions. cyclomatic complexity: 294 Second operand 3 states. [2018-11-18 15:29:27,349 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:29:27,350 INFO L93 Difference]: Finished difference Result 1173 states and 1695 transitions. [2018-11-18 15:29:27,351 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:29:27,351 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1173 states and 1695 transitions. [2018-11-18 15:29:27,354 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1083 [2018-11-18 15:29:27,357 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1173 states to 1173 states and 1695 transitions. [2018-11-18 15:29:27,357 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1173 [2018-11-18 15:29:27,358 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1173 [2018-11-18 15:29:27,358 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1173 states and 1695 transitions. [2018-11-18 15:29:27,359 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:29:27,359 INFO L705 BuchiCegarLoop]: Abstraction has 1173 states and 1695 transitions. [2018-11-18 15:29:27,360 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1173 states and 1695 transitions. [2018-11-18 15:29:27,369 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1173 to 1122. [2018-11-18 15:29:27,369 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1122 states. [2018-11-18 15:29:27,371 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1122 states to 1122 states and 1625 transitions. [2018-11-18 15:29:27,371 INFO L728 BuchiCegarLoop]: Abstraction has 1122 states and 1625 transitions. [2018-11-18 15:29:27,371 INFO L608 BuchiCegarLoop]: Abstraction has 1122 states and 1625 transitions. [2018-11-18 15:29:27,371 INFO L442 BuchiCegarLoop]: ======== Iteration 9============ [2018-11-18 15:29:27,371 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1122 states and 1625 transitions. [2018-11-18 15:29:27,374 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1032 [2018-11-18 15:29:27,374 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:29:27,374 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:29:27,375 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:27,375 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:27,375 INFO L794 eck$LassoCheckResult]: Stem: 11333#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 11225#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 11226#L977 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 10884#L444 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10885#L451 assume 1 == ~m_i~0;~m_st~0 := 0; 11345#L451-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10992#L456-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10993#L461-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10886#L466-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10887#L471-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 11162#L476-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 11163#L481-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11348#L660 assume !(0 == ~M_E~0); 11349#L660-2 assume !(0 == ~T1_E~0); 10790#L665-1 assume !(0 == ~T2_E~0); 10791#L670-1 assume !(0 == ~T3_E~0); 10895#L675-1 assume !(0 == ~T4_E~0); 10896#L680-1 assume !(0 == ~T5_E~0); 11173#L685-1 assume !(0 == ~T6_E~0); 11174#L690-1 assume !(0 == ~E_1~0); 11055#L695-1 assume !(0 == ~E_2~0); 11056#L700-1 assume !(0 == ~E_3~0); 11316#L705-1 assume !(0 == ~E_4~0); 10962#L710-1 assume !(0 == ~E_5~0); 10963#L715-1 assume !(0 == ~E_6~0); 10826#L720-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10827#L310 assume !(1 == ~m_pc~0); 11017#L310-2 is_master_triggered_~__retres1~0 := 0; 11015#L321 is_master_triggered_#res := is_master_triggered_~__retres1~0; 11016#L322 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 11145#L815 assume !(0 != activate_threads_~tmp~1); 11312#L815-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 11229#L329 assume !(1 == ~t1_pc~0); 11230#L329-2 is_transmit1_triggered_~__retres1~1 := 0; 11227#L340 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 11228#L341 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 11347#L823 assume !(0 != activate_threads_~tmp___0~0); 11421#L823-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 11399#L348 assume 1 == ~t2_pc~0; 11400#L349 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 11397#L359 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 11398#L360 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 10971#L831 assume !(0 != activate_threads_~tmp___1~0); 10957#L831-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 10891#L367 assume !(1 == ~t3_pc~0); 10859#L367-2 is_transmit3_triggered_~__retres1~3 := 0; 10860#L378 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 10890#L379 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 10995#L839 assume !(0 != activate_threads_~tmp___2~0); 11184#L839-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 11099#L386 assume 1 == ~t4_pc~0; 11002#L387 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 11003#L397 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 11000#L398 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 11001#L847 assume !(0 != activate_threads_~tmp___3~0); 11353#L847-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 11354#L405 assume 1 == ~t5_pc~0; 11272#L406 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 11273#L416 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 11270#L417 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 11271#L855 assume !(0 != activate_threads_~tmp___4~0); 11360#L855-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 10938#L424 assume !(1 == ~t6_pc~0); 10939#L424-2 is_transmit6_triggered_~__retres1~6 := 0; 10936#L435 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 10937#L436 activate_threads_#t~ret14 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 10845#L863 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 10816#L863-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10817#L733 assume !(1 == ~M_E~0); 11410#L733-2 assume !(1 == ~T1_E~0); 11314#L738-1 assume !(1 == ~T2_E~0); 10960#L743-1 assume !(1 == ~T3_E~0); 10961#L748-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10821#L753-1 assume !(1 == ~T5_E~0); 10822#L758-1 assume !(1 == ~T6_E~0); 10907#L763-1 assume !(1 == ~E_1~0); 10908#L768-1 assume !(1 == ~E_2~0); 11167#L773-1 assume !(1 == ~E_3~0); 11168#L778-1 assume !(1 == ~E_4~0); 11048#L783-1 assume !(1 == ~E_5~0); 11049#L788-1 assume 1 == ~E_6~0;~E_6~0 := 2; 11311#L793-1 assume { :end_inline_reset_delta_events } true; 11061#L1014-3 [2018-11-18 15:29:27,375 INFO L796 eck$LassoCheckResult]: Loop: 11061#L1014-3 assume true; 11062#L1014-1 assume !false; 11080#L1015 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 10795#L635 assume true; 11044#L541-1 assume !false; 11045#L542 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 11155#L494 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 10870#L531 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 10867#L532 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 10868#L546 assume !(0 != eval_~tmp~0); 11317#L650 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 10888#L444-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 10889#L660-3 assume 0 == ~M_E~0;~M_E~0 := 1; 11351#L660-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10804#L665-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10805#L670-3 assume !(0 == ~T3_E~0); 10897#L675-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10898#L680-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11177#L685-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11178#L690-3 assume !(0 == ~E_1~0); 11032#L695-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11033#L700-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11105#L705-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10954#L710-3 assume !(0 == ~E_5~0); 10955#L715-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10792#L720-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 10793#L310-21 assume !(1 == ~m_pc~0); 11176#L310-23 is_master_triggered_~__retres1~0 := 0; 11179#L321-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 11135#L322-7 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 11093#L815-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 11072#L815-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 11073#L329-21 assume !(1 == ~t1_pc~0); 11323#L329-23 is_transmit1_triggered_~__retres1~1 := 0; 11215#L340-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 11216#L341-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 11294#L823-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 11295#L823-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 11297#L348-21 assume 1 == ~t2_pc~0; 11425#L349-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 11391#L359-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 11392#L360-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 10926#L831-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 10927#L831-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 10823#L367-21 assume !(1 == ~t3_pc~0); 10788#L367-23 is_transmit3_triggered_~__retres1~3 := 0; 10789#L378-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 10850#L379-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 10972#L839-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 11127#L839-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 11050#L386-21 assume 1 == ~t4_pc~0; 11051#L387-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 11057#L397-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 11090#L398-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 11196#L847-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 11324#L847-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 11284#L405-21 assume 1 == ~t5_pc~0; 11265#L406-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 11266#L416-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 11261#L417-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 11262#L855-21 assume !(0 != activate_threads_~tmp___4~0); 11424#L855-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 11409#L424-21 assume 1 == ~t6_pc~0; 11382#L425-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 10921#L435-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 10922#L436-7 activate_threads_#t~ret14 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 10988#L863-21 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 10974#L863-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10975#L733-3 assume !(1 == ~M_E~0); 11407#L733-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11318#L738-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 10950#L743-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10951#L748-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10786#L753-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10787#L758-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10893#L763-3 assume !(1 == ~E_1~0); 10894#L768-3 assume !(1 == ~E_2~0); 11170#L773-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11171#L778-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11053#L783-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11054#L788-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11315#L793-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 11268#L494-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 10875#L531-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 10872#L532-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 10873#L1033 assume !(0 == start_simulation_~tmp~3); 11286#L1033-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 11269#L494-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 10882#L531-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 10879#L532-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 10880#L988 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 10833#L995 stop_simulation_#res := stop_simulation_~__retres2~0; 10834#L996 start_simulation_#t~ret17 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 10964#L1046 assume !(0 != start_simulation_~tmp___0~1); 11061#L1014-3 [2018-11-18 15:29:27,375 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:27,376 INFO L82 PathProgramCache]: Analyzing trace with hash -969024962, now seen corresponding path program 1 times [2018-11-18 15:29:27,376 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:27,376 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:27,376 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:27,376 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:27,377 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:27,380 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:27,398 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:29:27,398 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:29:27,398 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 15:29:27,398 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 15:29:27,398 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:27,398 INFO L82 PathProgramCache]: Analyzing trace with hash -2064310256, now seen corresponding path program 1 times [2018-11-18 15:29:27,399 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:27,399 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:27,399 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:27,399 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:27,400 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:27,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:27,431 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:29:27,431 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:29:27,431 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:29:27,431 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:29:27,431 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:29:27,431 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:29:27,432 INFO L87 Difference]: Start difference. First operand 1122 states and 1625 transitions. cyclomatic complexity: 505 Second operand 3 states. [2018-11-18 15:29:27,484 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:29:27,484 INFO L93 Difference]: Finished difference Result 2039 states and 2934 transitions. [2018-11-18 15:29:27,485 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:29:27,485 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2039 states and 2934 transitions. [2018-11-18 15:29:27,489 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1944 [2018-11-18 15:29:27,494 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2039 states to 2039 states and 2934 transitions. [2018-11-18 15:29:27,494 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2039 [2018-11-18 15:29:27,495 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2039 [2018-11-18 15:29:27,495 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2039 states and 2934 transitions. [2018-11-18 15:29:27,497 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:29:27,497 INFO L705 BuchiCegarLoop]: Abstraction has 2039 states and 2934 transitions. [2018-11-18 15:29:27,499 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2039 states and 2934 transitions. [2018-11-18 15:29:27,512 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2039 to 2033. [2018-11-18 15:29:27,512 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2033 states. [2018-11-18 15:29:27,515 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2033 states to 2033 states and 2928 transitions. [2018-11-18 15:29:27,515 INFO L728 BuchiCegarLoop]: Abstraction has 2033 states and 2928 transitions. [2018-11-18 15:29:27,515 INFO L608 BuchiCegarLoop]: Abstraction has 2033 states and 2928 transitions. [2018-11-18 15:29:27,515 INFO L442 BuchiCegarLoop]: ======== Iteration 10============ [2018-11-18 15:29:27,515 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2033 states and 2928 transitions. [2018-11-18 15:29:27,520 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1938 [2018-11-18 15:29:27,520 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:29:27,520 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:29:27,521 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:27,521 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:27,522 INFO L794 eck$LassoCheckResult]: Stem: 14511#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 14398#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 14399#L977 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 14051#L444 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14052#L451 assume 1 == ~m_i~0;~m_st~0 := 0; 14524#L451-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14160#L456-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14161#L461-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14053#L466-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14054#L471-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14336#L476-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14337#L481-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14528#L660 assume !(0 == ~M_E~0); 14529#L660-2 assume !(0 == ~T1_E~0); 13958#L665-1 assume !(0 == ~T2_E~0); 13959#L670-1 assume !(0 == ~T3_E~0); 14062#L675-1 assume !(0 == ~T4_E~0); 14063#L680-1 assume !(0 == ~T5_E~0); 14347#L685-1 assume !(0 == ~T6_E~0); 14348#L690-1 assume !(0 == ~E_1~0); 14223#L695-1 assume !(0 == ~E_2~0); 14224#L700-1 assume !(0 == ~E_3~0); 14492#L705-1 assume !(0 == ~E_4~0); 14129#L710-1 assume !(0 == ~E_5~0); 14130#L715-1 assume !(0 == ~E_6~0); 13994#L720-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 13995#L310 assume !(1 == ~m_pc~0); 14185#L310-2 is_master_triggered_~__retres1~0 := 0; 14183#L321 is_master_triggered_#res := is_master_triggered_~__retres1~0; 14184#L322 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 14315#L815 assume !(0 != activate_threads_~tmp~1); 14488#L815-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 14402#L329 assume !(1 == ~t1_pc~0); 14403#L329-2 is_transmit1_triggered_~__retres1~1 := 0; 14400#L340 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14401#L341 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 14527#L823 assume !(0 != activate_threads_~tmp___0~0); 14605#L823-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 14585#L348 assume !(1 == ~t2_pc~0); 14586#L348-2 is_transmit2_triggered_~__retres1~2 := 0; 14582#L359 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 14583#L360 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 14139#L831 assume !(0 != activate_threads_~tmp___1~0); 14124#L831-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 14058#L367 assume !(1 == ~t3_pc~0); 14026#L367-2 is_transmit3_triggered_~__retres1~3 := 0; 14027#L378 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 14057#L379 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 14165#L839 assume !(0 != activate_threads_~tmp___2~0); 14358#L839-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 14267#L386 assume 1 == ~t4_pc~0; 14170#L387 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 14171#L397 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 14168#L398 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 14169#L847 assume !(0 != activate_threads_~tmp___3~0); 14536#L847-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 14537#L405 assume 1 == ~t5_pc~0; 14445#L406 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 14446#L416 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 14443#L417 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 14444#L855 assume !(0 != activate_threads_~tmp___4~0); 14543#L855-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 14105#L424 assume !(1 == ~t6_pc~0); 14106#L424-2 is_transmit6_triggered_~__retres1~6 := 0; 14103#L435 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 14104#L436 activate_threads_#t~ret14 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 14013#L863 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 13984#L863-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13985#L733 assume !(1 == ~M_E~0); 14594#L733-2 assume !(1 == ~T1_E~0); 14490#L738-1 assume !(1 == ~T2_E~0); 14127#L743-1 assume !(1 == ~T3_E~0); 14128#L748-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13989#L753-1 assume !(1 == ~T5_E~0); 13990#L758-1 assume !(1 == ~T6_E~0); 14074#L763-1 assume !(1 == ~E_1~0); 14075#L768-1 assume !(1 == ~E_2~0); 14342#L773-1 assume !(1 == ~E_3~0); 14343#L778-1 assume !(1 == ~E_4~0); 14216#L783-1 assume !(1 == ~E_5~0); 14217#L788-1 assume 1 == ~E_6~0;~E_6~0 := 2; 14487#L793-1 assume { :end_inline_reset_delta_events } true; 14229#L1014-3 [2018-11-18 15:29:27,522 INFO L796 eck$LassoCheckResult]: Loop: 14229#L1014-3 assume true; 14230#L1014-1 assume !false; 14248#L1015 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 13963#L635 assume true; 14212#L541-1 assume !false; 14213#L542 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 14327#L494 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 14037#L531 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 14034#L532 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 14035#L546 assume !(0 != eval_~tmp~0); 14493#L650 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 14055#L444-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 14056#L660-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14533#L660-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13974#L665-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13975#L670-3 assume !(0 == ~T3_E~0); 14064#L675-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14065#L680-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14351#L685-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14352#L690-3 assume !(0 == ~E_1~0); 14200#L695-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14201#L700-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14274#L705-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14275#L710-3 assume !(0 == ~E_5~0); 15796#L715-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15795#L720-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15794#L310-21 assume !(1 == ~m_pc~0); 15793#L310-23 is_master_triggered_~__retres1~0 := 0; 15792#L321-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15791#L322-7 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 15789#L815-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 15787#L815-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15785#L329-21 assume !(1 == ~t1_pc~0); 15781#L329-23 is_transmit1_triggered_~__retres1~1 := 0; 15779#L340-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 15777#L341-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 15775#L823-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 15773#L823-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15771#L348-21 assume !(1 == ~t2_pc~0); 15766#L348-23 is_transmit2_triggered_~__retres1~2 := 0; 15765#L359-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 15764#L360-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 15763#L831-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 15762#L831-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 13991#L367-21 assume !(1 == ~t3_pc~0); 13956#L367-23 is_transmit3_triggered_~__retres1~3 := 0; 13957#L378-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 14018#L379-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 14140#L839-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 14297#L839-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 14218#L386-21 assume 1 == ~t4_pc~0; 14219#L387-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 14225#L397-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 14258#L398-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 14369#L847-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 14502#L847-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 14457#L405-21 assume 1 == ~t5_pc~0; 14436#L406-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 14437#L416-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 14434#L417-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 14435#L855-21 assume !(0 != activate_threads_~tmp___4~0); 14610#L855-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 14593#L424-21 assume 1 == ~t6_pc~0; 14565#L425-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 14088#L435-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 14089#L436-7 activate_threads_#t~ret14 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 14156#L863-21 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 14142#L863-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14143#L733-3 assume !(1 == ~M_E~0); 14591#L733-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14494#L738-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14495#L743-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14531#L748-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13954#L753-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13955#L758-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14060#L763-3 assume !(1 == ~E_1~0); 14061#L768-3 assume !(1 == ~E_2~0); 14345#L773-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14346#L778-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14221#L783-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14222#L788-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14491#L793-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 14441#L494-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 14044#L531-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 14039#L532-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 14040#L1033 assume !(0 == start_simulation_~tmp~3); 14459#L1033-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 14442#L494-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 14049#L531-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 14046#L532-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 14047#L988 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 14001#L995 stop_simulation_#res := stop_simulation_~__retres2~0; 14002#L996 start_simulation_#t~ret17 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 14131#L1046 assume !(0 != start_simulation_~tmp___0~1); 14229#L1014-3 [2018-11-18 15:29:27,522 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:27,522 INFO L82 PathProgramCache]: Analyzing trace with hash 2050839645, now seen corresponding path program 1 times [2018-11-18 15:29:27,522 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:27,522 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:27,523 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:27,523 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:27,523 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:27,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:27,546 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:29:27,546 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:29:27,546 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 15:29:27,546 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 15:29:27,546 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:27,547 INFO L82 PathProgramCache]: Analyzing trace with hash -2056559697, now seen corresponding path program 1 times [2018-11-18 15:29:27,547 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:27,547 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:27,547 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:27,547 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:27,548 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:27,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:27,575 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:29:27,575 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:29:27,575 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:29:27,575 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:29:27,576 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:29:27,576 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:29:27,576 INFO L87 Difference]: Start difference. First operand 2033 states and 2928 transitions. cyclomatic complexity: 899 Second operand 3 states. [2018-11-18 15:29:27,622 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:29:27,622 INFO L93 Difference]: Finished difference Result 3750 states and 5373 transitions. [2018-11-18 15:29:27,623 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:29:27,623 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3750 states and 5373 transitions. [2018-11-18 15:29:27,634 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3640 [2018-11-18 15:29:27,642 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3750 states to 3750 states and 5373 transitions. [2018-11-18 15:29:27,642 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3750 [2018-11-18 15:29:27,645 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3750 [2018-11-18 15:29:27,645 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3750 states and 5373 transitions. [2018-11-18 15:29:27,648 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:29:27,648 INFO L705 BuchiCegarLoop]: Abstraction has 3750 states and 5373 transitions. [2018-11-18 15:29:27,650 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3750 states and 5373 transitions. [2018-11-18 15:29:27,675 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3750 to 3738. [2018-11-18 15:29:27,676 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3738 states. [2018-11-18 15:29:27,681 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3738 states to 3738 states and 5361 transitions. [2018-11-18 15:29:27,681 INFO L728 BuchiCegarLoop]: Abstraction has 3738 states and 5361 transitions. [2018-11-18 15:29:27,681 INFO L608 BuchiCegarLoop]: Abstraction has 3738 states and 5361 transitions. [2018-11-18 15:29:27,681 INFO L442 BuchiCegarLoop]: ======== Iteration 11============ [2018-11-18 15:29:27,682 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3738 states and 5361 transitions. [2018-11-18 15:29:27,689 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 3628 [2018-11-18 15:29:27,690 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:29:27,690 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:29:27,691 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:27,691 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:27,691 INFO L794 eck$LassoCheckResult]: Stem: 20328#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 20210#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 20211#L977 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 19844#L444 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19845#L451 assume 1 == ~m_i~0;~m_st~0 := 0; 20343#L451-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19956#L456-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 19957#L461-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19846#L466-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19847#L471-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 20139#L476-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 20140#L481-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20348#L660 assume !(0 == ~M_E~0); 20349#L660-2 assume !(0 == ~T1_E~0); 19748#L665-1 assume !(0 == ~T2_E~0); 19749#L670-1 assume !(0 == ~T3_E~0); 19855#L675-1 assume !(0 == ~T4_E~0); 19856#L680-1 assume !(0 == ~T5_E~0); 20151#L685-1 assume !(0 == ~T6_E~0); 20152#L690-1 assume !(0 == ~E_1~0); 20015#L695-1 assume !(0 == ~E_2~0); 20016#L700-1 assume !(0 == ~E_3~0); 20309#L705-1 assume !(0 == ~E_4~0); 19922#L710-1 assume !(0 == ~E_5~0); 19923#L715-1 assume !(0 == ~E_6~0); 19785#L720-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 19786#L310 assume !(1 == ~m_pc~0); 19978#L310-2 is_master_triggered_~__retres1~0 := 0; 19976#L321 is_master_triggered_#res := is_master_triggered_~__retres1~0; 19977#L322 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 20115#L815 assume !(0 != activate_threads_~tmp~1); 20305#L815-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 20214#L329 assume !(1 == ~t1_pc~0); 20215#L329-2 is_transmit1_triggered_~__retres1~1 := 0; 20212#L340 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 20213#L341 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 20346#L823 assume !(0 != activate_threads_~tmp___0~0); 20442#L823-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 20414#L348 assume !(1 == ~t2_pc~0); 20415#L348-2 is_transmit2_triggered_~__retres1~2 := 0; 20410#L359 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 20411#L360 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 19931#L831 assume !(0 != activate_threads_~tmp___1~0); 19917#L831-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 19851#L367 assume !(1 == ~t3_pc~0); 19818#L367-2 is_transmit3_triggered_~__retres1~3 := 0; 19819#L378 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 19850#L379 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 19961#L839 assume !(0 != activate_threads_~tmp___2~0); 20160#L839-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 20065#L386 assume !(1 == ~t4_pc~0); 20066#L386-2 is_transmit4_triggered_~__retres1~4 := 0; 20064#L397 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 19964#L398 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 19965#L847 assume !(0 != activate_threads_~tmp___3~0); 20353#L847-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 20354#L405 assume 1 == ~t5_pc~0; 20257#L406 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 20258#L416 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 20255#L417 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 20256#L855 assume !(0 != activate_threads_~tmp___4~0); 20366#L855-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 19898#L424 assume !(1 == ~t6_pc~0); 19899#L424-2 is_transmit6_triggered_~__retres1~6 := 0; 19896#L435 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 19897#L436 activate_threads_#t~ret14 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 19804#L863 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 19774#L863-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19775#L733 assume !(1 == ~M_E~0); 20424#L733-2 assume !(1 == ~T1_E~0); 20307#L738-1 assume !(1 == ~T2_E~0); 19920#L743-1 assume !(1 == ~T3_E~0); 19921#L748-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19780#L753-1 assume !(1 == ~T5_E~0); 19781#L758-1 assume !(1 == ~T6_E~0); 19867#L763-1 assume !(1 == ~E_1~0); 19868#L768-1 assume !(1 == ~E_2~0); 20145#L773-1 assume !(1 == ~E_3~0); 20146#L778-1 assume !(1 == ~E_4~0); 20009#L783-1 assume !(1 == ~E_5~0); 20010#L788-1 assume 1 == ~E_6~0;~E_6~0 := 2; 20304#L793-1 assume { :end_inline_reset_delta_events } true; 20020#L1014-3 [2018-11-18 15:29:27,692 INFO L796 eck$LassoCheckResult]: Loop: 20020#L1014-3 assume true; 20021#L1014-1 assume !false; 20040#L1015 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 19753#L635 assume true; 20005#L541-1 assume !false; 20006#L542 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 20129#L494 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 19830#L531 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 19827#L532 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 19828#L546 assume !(0 != eval_~tmp~0); 20422#L650 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 23359#L444-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 23358#L660-3 assume 0 == ~M_E~0;~M_E~0 := 1; 23357#L660-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 23356#L665-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 23355#L670-3 assume !(0 == ~T3_E~0); 23354#L675-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 23353#L680-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 23352#L685-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 23351#L690-3 assume !(0 == ~E_1~0); 23350#L695-3 assume 0 == ~E_2~0;~E_2~0 := 1; 23349#L700-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23348#L705-3 assume 0 == ~E_4~0;~E_4~0 := 1; 23347#L710-3 assume !(0 == ~E_5~0); 23346#L715-3 assume 0 == ~E_6~0;~E_6~0 := 1; 23345#L720-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 23344#L310-21 assume !(1 == ~m_pc~0); 23343#L310-23 is_master_triggered_~__retres1~0 := 0; 23342#L321-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 23341#L322-7 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 23340#L815-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 23339#L815-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 20347#L329-21 assume !(1 == ~t1_pc~0); 20316#L329-23 is_transmit1_triggered_~__retres1~1 := 0; 20200#L340-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 20201#L341-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 20281#L823-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 20282#L823-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 20284#L348-21 assume !(1 == ~t2_pc~0); 20478#L348-23 is_transmit2_triggered_~__retres1~2 := 0; 23330#L359-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 23327#L360-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 23325#L831-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 23323#L831-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 23321#L367-21 assume 1 == ~t3_pc~0; 23318#L368-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 23316#L378-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 23313#L379-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 23311#L839-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 23309#L839-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 23307#L386-21 assume !(1 == ~t4_pc~0); 23305#L386-23 is_transmit4_triggered_~__retres1~4 := 0; 23303#L397-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 23301#L398-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 23299#L847-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 23297#L847-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 23295#L405-21 assume 1 == ~t5_pc~0; 23292#L406-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 23290#L416-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 23288#L417-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 23286#L855-21 assume !(0 != activate_threads_~tmp___4~0); 23284#L855-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 23282#L424-21 assume !(1 == ~t6_pc~0); 23280#L424-23 is_transmit6_triggered_~__retres1~6 := 0; 23277#L435-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 23276#L436-7 activate_threads_#t~ret14 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 23275#L863-21 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 23274#L863-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 23273#L733-3 assume !(1 == ~M_E~0); 23272#L733-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 23271#L738-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 23270#L743-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 23269#L748-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23268#L753-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 23267#L758-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23266#L763-3 assume !(1 == ~E_1~0); 23265#L768-3 assume !(1 == ~E_2~0); 23264#L773-3 assume 1 == ~E_3~0;~E_3~0 := 2; 23263#L778-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23262#L783-3 assume 1 == ~E_5~0;~E_5~0 := 2; 23261#L788-3 assume 1 == ~E_6~0;~E_6~0 := 2; 23260#L793-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 23259#L494-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 23252#L531-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 23251#L532-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 23250#L1033 assume !(0 == start_simulation_~tmp~3); 23248#L1033-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 20254#L494-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 19842#L531-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 19839#L532-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 19840#L988 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 19792#L995 stop_simulation_#res := stop_simulation_~__retres2~0; 19793#L996 start_simulation_#t~ret17 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 19924#L1046 assume !(0 != start_simulation_~tmp___0~1); 20020#L1014-3 [2018-11-18 15:29:27,692 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:27,692 INFO L82 PathProgramCache]: Analyzing trace with hash -1325153028, now seen corresponding path program 1 times [2018-11-18 15:29:27,692 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:27,692 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:27,693 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:27,693 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:27,693 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:27,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:27,721 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:29:27,721 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:29:27,721 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 15:29:27,721 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 15:29:27,721 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:27,722 INFO L82 PathProgramCache]: Analyzing trace with hash -682350706, now seen corresponding path program 1 times [2018-11-18 15:29:27,722 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:27,722 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:27,722 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:27,723 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:27,723 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:27,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:27,746 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:29:27,746 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:29:27,746 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:29:27,747 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:29:27,747 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:29:27,747 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:29:27,747 INFO L87 Difference]: Start difference. First operand 3738 states and 5361 transitions. cyclomatic complexity: 1631 Second operand 3 states. [2018-11-18 15:29:27,819 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:29:27,819 INFO L93 Difference]: Finished difference Result 6941 states and 9914 transitions. [2018-11-18 15:29:27,820 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:29:27,820 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6941 states and 9914 transitions. [2018-11-18 15:29:27,841 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 6792 [2018-11-18 15:29:27,887 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6941 states to 6941 states and 9914 transitions. [2018-11-18 15:29:27,887 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6941 [2018-11-18 15:29:27,890 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6941 [2018-11-18 15:29:27,890 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6941 states and 9914 transitions. [2018-11-18 15:29:27,898 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:29:27,898 INFO L705 BuchiCegarLoop]: Abstraction has 6941 states and 9914 transitions. [2018-11-18 15:29:27,901 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6941 states and 9914 transitions. [2018-11-18 15:29:27,946 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6941 to 6917. [2018-11-18 15:29:27,946 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6917 states. [2018-11-18 15:29:27,954 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6917 states to 6917 states and 9890 transitions. [2018-11-18 15:29:27,954 INFO L728 BuchiCegarLoop]: Abstraction has 6917 states and 9890 transitions. [2018-11-18 15:29:27,954 INFO L608 BuchiCegarLoop]: Abstraction has 6917 states and 9890 transitions. [2018-11-18 15:29:27,954 INFO L442 BuchiCegarLoop]: ======== Iteration 12============ [2018-11-18 15:29:27,954 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6917 states and 9890 transitions. [2018-11-18 15:29:27,967 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 6768 [2018-11-18 15:29:27,967 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:29:27,968 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:29:27,969 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:27,969 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:27,969 INFO L794 eck$LassoCheckResult]: Stem: 31026#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 30892#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 30893#L977 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 30527#L444 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30528#L451 assume 1 == ~m_i~0;~m_st~0 := 0; 31038#L451-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 30642#L456-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 30643#L461-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30532#L466-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 30533#L471-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 30821#L476-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 30822#L481-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 31042#L660 assume !(0 == ~M_E~0); 31043#L660-2 assume !(0 == ~T1_E~0); 30432#L665-1 assume !(0 == ~T2_E~0); 30433#L670-1 assume !(0 == ~T3_E~0); 30541#L675-1 assume !(0 == ~T4_E~0); 30542#L680-1 assume !(0 == ~T5_E~0); 30834#L685-1 assume !(0 == ~T6_E~0); 30835#L690-1 assume !(0 == ~E_1~0); 30702#L695-1 assume !(0 == ~E_2~0); 30703#L700-1 assume !(0 == ~E_3~0); 31005#L705-1 assume !(0 == ~E_4~0); 30609#L710-1 assume !(0 == ~E_5~0); 30610#L715-1 assume !(0 == ~E_6~0); 30470#L720-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 30471#L310 assume !(1 == ~m_pc~0); 30664#L310-2 is_master_triggered_~__retres1~0 := 0; 30659#L321 is_master_triggered_#res := is_master_triggered_~__retres1~0; 30660#L322 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 30800#L815 assume !(0 != activate_threads_~tmp~1); 31001#L815-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 30899#L329 assume !(1 == ~t1_pc~0); 30900#L329-2 is_transmit1_triggered_~__retres1~1 := 0; 30894#L340 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 30895#L341 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 31041#L823 assume !(0 != activate_threads_~tmp___0~0); 31125#L823-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 31101#L348 assume !(1 == ~t2_pc~0); 31102#L348-2 is_transmit2_triggered_~__retres1~2 := 0; 31098#L359 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 31099#L360 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 30619#L831 assume !(0 != activate_threads_~tmp___1~0); 30604#L831-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 30537#L367 assume !(1 == ~t3_pc~0); 30504#L367-2 is_transmit3_triggered_~__retres1~3 := 0; 30505#L378 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 30536#L379 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 30645#L839 assume !(0 != activate_threads_~tmp___2~0); 30843#L839-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 30752#L386 assume !(1 == ~t4_pc~0); 30753#L386-2 is_transmit4_triggered_~__retres1~4 := 0; 30751#L397 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 30650#L398 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 30651#L847 assume !(0 != activate_threads_~tmp___3~0); 31048#L847-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 31049#L405 assume !(1 == ~t5_pc~0); 30984#L405-2 is_transmit5_triggered_~__retres1~5 := 0; 30985#L416 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 30940#L417 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 30941#L855 assume !(0 != activate_threads_~tmp___4~0); 31058#L855-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 30584#L424 assume !(1 == ~t6_pc~0); 30585#L424-2 is_transmit6_triggered_~__retres1~6 := 0; 30580#L435 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 30581#L436 activate_threads_#t~ret14 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 30490#L863 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 30457#L863-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30458#L733 assume !(1 == ~M_E~0); 31112#L733-2 assume !(1 == ~T1_E~0); 31003#L738-1 assume !(1 == ~T2_E~0); 30607#L743-1 assume !(1 == ~T3_E~0); 30608#L748-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 30465#L753-1 assume !(1 == ~T5_E~0); 30466#L758-1 assume !(1 == ~T6_E~0); 30553#L763-1 assume !(1 == ~E_1~0); 30554#L768-1 assume !(1 == ~E_2~0); 30826#L773-1 assume !(1 == ~E_3~0); 30827#L778-1 assume !(1 == ~E_4~0); 30694#L783-1 assume !(1 == ~E_5~0); 30695#L788-1 assume 1 == ~E_6~0;~E_6~0 := 2; 30999#L793-1 assume { :end_inline_reset_delta_events } true; 31000#L1014-3 [2018-11-18 15:29:27,969 INFO L796 eck$LassoCheckResult]: Loop: 31000#L1014-3 assume true; 36694#L1014-1 assume !false; 30848#L1015 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 30437#L635 assume true; 30692#L541-1 assume !false; 30693#L542 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 30808#L494 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 30516#L531 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 30513#L532 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 30514#L546 assume !(0 != eval_~tmp~0); 31110#L650 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 37089#L444-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 37088#L660-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37087#L660-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37086#L665-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 37085#L670-3 assume !(0 == ~T3_E~0); 37084#L675-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 37083#L680-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 37082#L685-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 37081#L690-3 assume !(0 == ~E_1~0); 37080#L695-3 assume 0 == ~E_2~0;~E_2~0 := 1; 37079#L700-3 assume 0 == ~E_3~0;~E_3~0 := 1; 37078#L705-3 assume 0 == ~E_4~0;~E_4~0 := 1; 37077#L710-3 assume !(0 == ~E_5~0); 37015#L715-3 assume 0 == ~E_6~0;~E_6~0 := 1; 37013#L720-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 37011#L310-21 assume !(1 == ~m_pc~0); 37009#L310-23 is_master_triggered_~__retres1~0 := 0; 37005#L321-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 37003#L322-7 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 30744#L815-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 30721#L815-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 30722#L329-21 assume !(1 == ~t1_pc~0); 31013#L329-23 is_transmit1_triggered_~__retres1~1 := 0; 36902#L340-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 31011#L341-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 30975#L823-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 30976#L823-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 30979#L348-21 assume !(1 == ~t2_pc~0); 31153#L348-23 is_transmit2_triggered_~__retres1~2 := 0; 31090#L359-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 31091#L360-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 30572#L831-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 30573#L831-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 30467#L367-21 assume !(1 == ~t3_pc~0); 30434#L367-23 is_transmit3_triggered_~__retres1~3 := 0; 30435#L378-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 30496#L379-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 30620#L839-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 30781#L839-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 30698#L386-21 assume !(1 == ~t4_pc~0); 30699#L386-23 is_transmit4_triggered_~__retres1~4 := 0; 30704#L397-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 30741#L398-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 30859#L847-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 31015#L847-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 30960#L405-21 assume !(1 == ~t5_pc~0); 30949#L405-23 is_transmit5_triggered_~__retres1~5 := 0; 30950#L416-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 30931#L417-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 30932#L855-21 assume !(0 != activate_threads_~tmp___4~0); 31130#L855-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 31111#L424-21 assume 1 == ~t6_pc~0; 31082#L425-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 30567#L435-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 30568#L436-7 activate_threads_#t~ret14 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 30637#L863-21 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 30638#L863-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 36797#L733-3 assume !(1 == ~M_E~0); 36796#L733-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 36795#L738-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 36794#L743-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36793#L748-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 36792#L753-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 36791#L758-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 36790#L763-3 assume !(1 == ~E_1~0); 36789#L768-3 assume !(1 == ~E_2~0); 36788#L773-3 assume 1 == ~E_3~0;~E_3~0 := 2; 36787#L778-3 assume 1 == ~E_4~0;~E_4~0 := 2; 36784#L783-3 assume 1 == ~E_5~0;~E_5~0 := 2; 36782#L788-3 assume 1 == ~E_6~0;~E_6~0 := 2; 36780#L793-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 36778#L494-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 36770#L531-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 36768#L532-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 36765#L1033 assume !(0 == start_simulation_~tmp~3); 36766#L1033-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 36920#L494-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 30820#L531-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 30525#L532-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 30526#L988 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 30477#L995 stop_simulation_#res := stop_simulation_~__retres2~0; 30478#L996 start_simulation_#t~ret17 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 30612#L1046 assume !(0 != start_simulation_~tmp___0~1); 31000#L1014-3 [2018-11-18 15:29:27,969 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:27,969 INFO L82 PathProgramCache]: Analyzing trace with hash -686368549, now seen corresponding path program 1 times [2018-11-18 15:29:27,969 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:27,970 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:27,970 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:27,970 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:27,970 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:27,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:27,998 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:29:27,998 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:29:27,998 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 15:29:27,999 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 15:29:27,999 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:27,999 INFO L82 PathProgramCache]: Analyzing trace with hash 1486625581, now seen corresponding path program 1 times [2018-11-18 15:29:27,999 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:27,999 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:28,000 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:28,000 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:28,000 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:28,005 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:28,027 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:29:28,027 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:29:28,027 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:29:28,027 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:29:28,027 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:29:28,027 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:29:28,028 INFO L87 Difference]: Start difference. First operand 6917 states and 9890 transitions. cyclomatic complexity: 2989 Second operand 3 states. [2018-11-18 15:29:28,056 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:29:28,056 INFO L93 Difference]: Finished difference Result 6917 states and 9840 transitions. [2018-11-18 15:29:28,057 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:29:28,057 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6917 states and 9840 transitions. [2018-11-18 15:29:28,073 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 6768 [2018-11-18 15:29:28,093 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6917 states to 6917 states and 9840 transitions. [2018-11-18 15:29:28,093 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6917 [2018-11-18 15:29:28,097 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6917 [2018-11-18 15:29:28,097 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6917 states and 9840 transitions. [2018-11-18 15:29:28,103 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:29:28,103 INFO L705 BuchiCegarLoop]: Abstraction has 6917 states and 9840 transitions. [2018-11-18 15:29:28,107 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6917 states and 9840 transitions. [2018-11-18 15:29:28,154 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6917 to 6917. [2018-11-18 15:29:28,154 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6917 states. [2018-11-18 15:29:28,162 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6917 states to 6917 states and 9840 transitions. [2018-11-18 15:29:28,162 INFO L728 BuchiCegarLoop]: Abstraction has 6917 states and 9840 transitions. [2018-11-18 15:29:28,162 INFO L608 BuchiCegarLoop]: Abstraction has 6917 states and 9840 transitions. [2018-11-18 15:29:28,162 INFO L442 BuchiCegarLoop]: ======== Iteration 13============ [2018-11-18 15:29:28,162 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6917 states and 9840 transitions. [2018-11-18 15:29:28,176 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 6768 [2018-11-18 15:29:28,176 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:29:28,176 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:29:28,177 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:28,178 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:28,178 INFO L794 eck$LassoCheckResult]: Stem: 44842#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 44719#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 44720#L977 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 44365#L444 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 44366#L451 assume 1 == ~m_i~0;~m_st~0 := 0; 44854#L451-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 44476#L456-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 44477#L461-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 44370#L466-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 44371#L471-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 44652#L476-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 44653#L481-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 44858#L660 assume !(0 == ~M_E~0); 44859#L660-2 assume !(0 == ~T1_E~0); 44273#L665-1 assume !(0 == ~T2_E~0); 44274#L670-1 assume !(0 == ~T3_E~0); 44379#L675-1 assume !(0 == ~T4_E~0); 44380#L680-1 assume !(0 == ~T5_E~0); 44661#L685-1 assume !(0 == ~T6_E~0); 44662#L690-1 assume !(0 == ~E_1~0); 44536#L695-1 assume !(0 == ~E_2~0); 44537#L700-1 assume !(0 == ~E_3~0); 44825#L705-1 assume !(0 == ~E_4~0); 44446#L710-1 assume !(0 == ~E_5~0); 44447#L715-1 assume !(0 == ~E_6~0); 44311#L720-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 44312#L310 assume !(1 == ~m_pc~0); 44498#L310-2 is_master_triggered_~__retres1~0 := 0; 44493#L321 is_master_triggered_#res := is_master_triggered_~__retres1~0; 44494#L322 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 44633#L815 assume !(0 != activate_threads_~tmp~1); 44821#L815-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 44726#L329 assume !(1 == ~t1_pc~0); 44727#L329-2 is_transmit1_triggered_~__retres1~1 := 0; 44721#L340 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 44722#L341 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 44857#L823 assume !(0 != activate_threads_~tmp___0~0); 44925#L823-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 44905#L348 assume !(1 == ~t2_pc~0); 44906#L348-2 is_transmit2_triggered_~__retres1~2 := 0; 44903#L359 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 44904#L360 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 44455#L831 assume !(0 != activate_threads_~tmp___1~0); 44441#L831-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 44375#L367 assume !(1 == ~t3_pc~0); 44343#L367-2 is_transmit3_triggered_~__retres1~3 := 0; 44344#L378 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 44374#L379 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 44479#L839 assume !(0 != activate_threads_~tmp___2~0); 44672#L839-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 44585#L386 assume !(1 == ~t4_pc~0); 44586#L386-2 is_transmit4_triggered_~__retres1~4 := 0; 44584#L397 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 44484#L398 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 44485#L847 assume !(0 != activate_threads_~tmp___3~0); 44863#L847-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 44864#L405 assume !(1 == ~t5_pc~0); 44808#L405-2 is_transmit5_triggered_~__retres1~5 := 0; 44809#L416 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 44767#L417 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 44768#L855 assume !(0 != activate_threads_~tmp___4~0); 44869#L855-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 44422#L424 assume !(1 == ~t6_pc~0); 44423#L424-2 is_transmit6_triggered_~__retres1~6 := 0; 44418#L435 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 44419#L436 activate_threads_#t~ret14 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 44330#L863 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 44298#L863-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44299#L733 assume !(1 == ~M_E~0); 44915#L733-2 assume !(1 == ~T1_E~0); 44823#L738-1 assume !(1 == ~T2_E~0); 44444#L743-1 assume !(1 == ~T3_E~0); 44445#L748-1 assume !(1 == ~T4_E~0); 44306#L753-1 assume !(1 == ~T5_E~0); 44307#L758-1 assume !(1 == ~T6_E~0); 44391#L763-1 assume !(1 == ~E_1~0); 44392#L768-1 assume !(1 == ~E_2~0); 44656#L773-1 assume !(1 == ~E_3~0); 44657#L778-1 assume !(1 == ~E_4~0); 44528#L783-1 assume !(1 == ~E_5~0); 44529#L788-1 assume 1 == ~E_6~0;~E_6~0 := 2; 44820#L793-1 assume { :end_inline_reset_delta_events } true; 44544#L1014-3 [2018-11-18 15:29:28,178 INFO L796 eck$LassoCheckResult]: Loop: 44544#L1014-3 assume true; 44545#L1014-1 assume !false; 44563#L1015 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 44278#L635 assume true; 44526#L541-1 assume !false; 44527#L542 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 44641#L494 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 44354#L531 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 44351#L532 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 44352#L546 assume !(0 != eval_~tmp~0); 44826#L650 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 44372#L444-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 44373#L660-3 assume 0 == ~M_E~0;~M_E~0 := 1; 44861#L660-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 44289#L665-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 44290#L670-3 assume !(0 == ~T3_E~0); 44381#L675-3 assume !(0 == ~T4_E~0); 44382#L680-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 44665#L685-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 44666#L690-3 assume !(0 == ~E_1~0); 44516#L695-3 assume 0 == ~E_2~0;~E_2~0 := 1; 44517#L700-3 assume 0 == ~E_3~0;~E_3~0 := 1; 44593#L705-3 assume 0 == ~E_4~0;~E_4~0 := 1; 44438#L710-3 assume !(0 == ~E_5~0); 44439#L715-3 assume 0 == ~E_6~0;~E_6~0 := 1; 44280#L720-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 44281#L310-21 assume !(1 == ~m_pc~0); 44663#L310-23 is_master_triggered_~__retres1~0 := 0; 44667#L321-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 44623#L322-7 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 44577#L815-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 44556#L815-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 44557#L329-21 assume !(1 == ~t1_pc~0); 44833#L329-23 is_transmit1_triggered_~__retres1~1 := 0; 44712#L340-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 44713#L341-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 44798#L823-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 44799#L823-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 51130#L348-21 assume !(1 == ~t2_pc~0); 44961#L348-23 is_transmit2_triggered_~__retres1~2 := 0; 44896#L359-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 44897#L360-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 44410#L831-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 44411#L831-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 44308#L367-21 assume !(1 == ~t3_pc~0); 44275#L367-23 is_transmit3_triggered_~__retres1~3 := 0; 44276#L378-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 44335#L379-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 44456#L839-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 44615#L839-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 44532#L386-21 assume !(1 == ~t4_pc~0); 44533#L386-23 is_transmit4_triggered_~__retres1~4 := 0; 44538#L397-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 44574#L398-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 44687#L847-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 44835#L847-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 44782#L405-21 assume !(1 == ~t5_pc~0); 44776#L405-23 is_transmit5_triggered_~__retres1~5 := 0; 44777#L416-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 44758#L417-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 44759#L855-21 assume !(0 != activate_threads_~tmp___4~0); 44935#L855-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 44914#L424-21 assume 1 == ~t6_pc~0; 44888#L425-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 44405#L435-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 44406#L436-7 activate_threads_#t~ret14 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 44472#L863-21 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 44458#L863-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 44459#L733-3 assume !(1 == ~M_E~0); 44912#L733-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 44827#L738-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 44434#L743-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 44435#L748-3 assume !(1 == ~T4_E~0); 44271#L753-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 44272#L758-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 44377#L763-3 assume !(1 == ~E_1~0); 44378#L768-3 assume !(1 == ~E_2~0); 44659#L773-3 assume 1 == ~E_3~0;~E_3~0 := 2; 44660#L778-3 assume 1 == ~E_4~0;~E_4~0 := 2; 44534#L783-3 assume 1 == ~E_5~0;~E_5~0 := 2; 44535#L788-3 assume 1 == ~E_6~0;~E_6~0 := 2; 44824#L793-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 44765#L494-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 44361#L531-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 44356#L532-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 44357#L1033 assume !(0 == start_simulation_~tmp~3); 44784#L1033-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 50977#L494-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 50975#L531-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 50973#L532-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 50972#L988 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 44318#L995 stop_simulation_#res := stop_simulation_~__retres2~0; 44319#L996 start_simulation_#t~ret17 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 44448#L1046 assume !(0 != start_simulation_~tmp___0~1); 44544#L1014-3 [2018-11-18 15:29:28,178 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:28,178 INFO L82 PathProgramCache]: Analyzing trace with hash -1079395559, now seen corresponding path program 1 times [2018-11-18 15:29:28,178 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:28,178 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:28,179 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:28,179 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:28,179 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:28,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:28,206 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:29:28,206 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:29:28,207 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 15:29:28,207 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 15:29:28,207 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:28,207 INFO L82 PathProgramCache]: Analyzing trace with hash -1750453335, now seen corresponding path program 1 times [2018-11-18 15:29:28,207 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:28,207 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:28,208 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:28,208 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:28,208 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:28,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:28,246 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:29:28,247 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:29:28,247 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:29:28,247 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:29:28,247 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:29:28,247 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:29:28,247 INFO L87 Difference]: Start difference. First operand 6917 states and 9840 transitions. cyclomatic complexity: 2939 Second operand 3 states. [2018-11-18 15:29:28,296 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:29:28,296 INFO L93 Difference]: Finished difference Result 6917 states and 9701 transitions. [2018-11-18 15:29:28,298 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:29:28,298 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6917 states and 9701 transitions. [2018-11-18 15:29:28,314 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 6768 [2018-11-18 15:29:28,330 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6917 states to 6917 states and 9701 transitions. [2018-11-18 15:29:28,330 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6917 [2018-11-18 15:29:28,334 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6917 [2018-11-18 15:29:28,334 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6917 states and 9701 transitions. [2018-11-18 15:29:28,339 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:29:28,339 INFO L705 BuchiCegarLoop]: Abstraction has 6917 states and 9701 transitions. [2018-11-18 15:29:28,343 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6917 states and 9701 transitions. [2018-11-18 15:29:28,392 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6917 to 6917. [2018-11-18 15:29:28,392 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6917 states. [2018-11-18 15:29:28,400 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6917 states to 6917 states and 9701 transitions. [2018-11-18 15:29:28,400 INFO L728 BuchiCegarLoop]: Abstraction has 6917 states and 9701 transitions. [2018-11-18 15:29:28,400 INFO L608 BuchiCegarLoop]: Abstraction has 6917 states and 9701 transitions. [2018-11-18 15:29:28,400 INFO L442 BuchiCegarLoop]: ======== Iteration 14============ [2018-11-18 15:29:28,400 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6917 states and 9701 transitions. [2018-11-18 15:29:28,415 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 6768 [2018-11-18 15:29:28,415 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:29:28,415 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:29:28,416 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:28,416 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:28,416 INFO L794 eck$LassoCheckResult]: Stem: 58675#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 58550#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 58551#L977 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 58206#L444 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 58207#L451 assume 1 == ~m_i~0;~m_st~0 := 0; 58687#L451-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 58318#L456-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 58319#L461-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 58211#L466-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 58212#L471-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 58491#L476-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 58492#L481-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 58691#L660 assume !(0 == ~M_E~0); 58692#L660-2 assume !(0 == ~T1_E~0); 58114#L665-1 assume !(0 == ~T2_E~0); 58115#L670-1 assume !(0 == ~T3_E~0); 58220#L675-1 assume !(0 == ~T4_E~0); 58221#L680-1 assume !(0 == ~T5_E~0); 58501#L685-1 assume !(0 == ~T6_E~0); 58502#L690-1 assume !(0 == ~E_1~0); 58379#L695-1 assume !(0 == ~E_2~0); 58380#L700-1 assume !(0 == ~E_3~0); 58658#L705-1 assume !(0 == ~E_4~0); 58288#L710-1 assume !(0 == ~E_5~0); 58289#L715-1 assume !(0 == ~E_6~0); 58152#L720-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 58153#L310 assume !(1 == ~m_pc~0); 58340#L310-2 is_master_triggered_~__retres1~0 := 0; 58335#L321 is_master_triggered_#res := is_master_triggered_~__retres1~0; 58336#L322 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 58472#L815 assume !(0 != activate_threads_~tmp~1); 58654#L815-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 58557#L329 assume !(1 == ~t1_pc~0); 58558#L329-2 is_transmit1_triggered_~__retres1~1 := 0; 58552#L340 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 58553#L341 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 58690#L823 assume !(0 != activate_threads_~tmp___0~0); 58763#L823-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 58741#L348 assume !(1 == ~t2_pc~0); 58742#L348-2 is_transmit2_triggered_~__retres1~2 := 0; 58739#L359 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 58740#L360 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 58297#L831 assume !(0 != activate_threads_~tmp___1~0); 58283#L831-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 58216#L367 assume !(1 == ~t3_pc~0); 58184#L367-2 is_transmit3_triggered_~__retres1~3 := 0; 58185#L378 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 58215#L379 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 58321#L839 assume !(0 != activate_threads_~tmp___2~0); 58509#L839-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 58424#L386 assume !(1 == ~t4_pc~0); 58425#L386-2 is_transmit4_triggered_~__retres1~4 := 0; 58423#L397 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 58326#L398 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 58327#L847 assume !(0 != activate_threads_~tmp___3~0); 58697#L847-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 58698#L405 assume !(1 == ~t5_pc~0); 58638#L405-2 is_transmit5_triggered_~__retres1~5 := 0; 58639#L416 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 58598#L417 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 58599#L855 assume !(0 != activate_threads_~tmp___4~0); 58703#L855-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 58264#L424 assume !(1 == ~t6_pc~0); 58265#L424-2 is_transmit6_triggered_~__retres1~6 := 0; 58260#L435 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 58261#L436 activate_threads_#t~ret14 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 58171#L863 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 58139#L863-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 58140#L733 assume !(1 == ~M_E~0); 58752#L733-2 assume !(1 == ~T1_E~0); 58656#L738-1 assume !(1 == ~T2_E~0); 58286#L743-1 assume !(1 == ~T3_E~0); 58287#L748-1 assume !(1 == ~T4_E~0); 58147#L753-1 assume !(1 == ~T5_E~0); 58148#L758-1 assume !(1 == ~T6_E~0); 58232#L763-1 assume !(1 == ~E_1~0); 58233#L768-1 assume !(1 == ~E_2~0); 58496#L773-1 assume !(1 == ~E_3~0); 58497#L778-1 assume !(1 == ~E_4~0); 58370#L783-1 assume !(1 == ~E_5~0); 58371#L788-1 assume !(1 == ~E_6~0); 58652#L793-1 assume { :end_inline_reset_delta_events } true; 58653#L1014-3 [2018-11-18 15:29:28,417 INFO L796 eck$LassoCheckResult]: Loop: 58653#L1014-3 assume true; 60254#L1014-1 assume !false; 60125#L1015 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 60124#L635 assume true; 60123#L541-1 assume !false; 60122#L542 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 60121#L494 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 60114#L531 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 60112#L532 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 60109#L546 assume !(0 != eval_~tmp~0); 60110#L650 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 60429#L444-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 60427#L660-3 assume 0 == ~M_E~0;~M_E~0 := 1; 60425#L660-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 60423#L665-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 60421#L670-3 assume !(0 == ~T3_E~0); 60419#L675-3 assume !(0 == ~T4_E~0); 60417#L680-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 60415#L685-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 60412#L690-3 assume !(0 == ~E_1~0); 60410#L695-3 assume 0 == ~E_2~0;~E_2~0 := 1; 60408#L700-3 assume 0 == ~E_3~0;~E_3~0 := 1; 60406#L705-3 assume 0 == ~E_4~0;~E_4~0 := 1; 60404#L710-3 assume !(0 == ~E_5~0); 60402#L715-3 assume !(0 == ~E_6~0); 60400#L720-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 60398#L310-21 assume !(1 == ~m_pc~0); 60396#L310-23 is_master_triggered_~__retres1~0 := 0; 60394#L321-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 60392#L322-7 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 60390#L815-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 60388#L815-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 60386#L329-21 assume !(1 == ~t1_pc~0); 60383#L329-23 is_transmit1_triggered_~__retres1~1 := 0; 60381#L340-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 60379#L341-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 60377#L823-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 60375#L823-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 60374#L348-21 assume !(1 == ~t2_pc~0); 60373#L348-23 is_transmit2_triggered_~__retres1~2 := 0; 60372#L359-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 60371#L360-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 60370#L831-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 60369#L831-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 60368#L367-21 assume 1 == ~t3_pc~0; 60366#L368-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 60365#L378-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 60364#L379-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 60363#L839-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 60362#L839-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 60360#L386-21 assume !(1 == ~t4_pc~0); 60358#L386-23 is_transmit4_triggered_~__retres1~4 := 0; 60356#L397-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 60354#L398-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 60352#L847-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 60350#L847-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 60348#L405-21 assume !(1 == ~t5_pc~0); 60346#L405-23 is_transmit5_triggered_~__retres1~5 := 0; 60345#L416-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 60342#L417-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 60340#L855-21 assume !(0 != activate_threads_~tmp___4~0); 60338#L855-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 60336#L424-21 assume !(1 == ~t6_pc~0); 60333#L424-23 is_transmit6_triggered_~__retres1~6 := 0; 60331#L435-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 60329#L436-7 activate_threads_#t~ret14 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 60326#L863-21 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 60324#L863-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 60322#L733-3 assume !(1 == ~M_E~0); 60320#L733-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 60318#L738-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 60316#L743-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 60313#L748-3 assume !(1 == ~T4_E~0); 60311#L753-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 60309#L758-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 60307#L763-3 assume !(1 == ~E_1~0); 60305#L768-3 assume !(1 == ~E_2~0); 60303#L773-3 assume 1 == ~E_3~0;~E_3~0 := 2; 60301#L778-3 assume 1 == ~E_4~0;~E_4~0 := 2; 60299#L783-3 assume 1 == ~E_5~0;~E_5~0 := 2; 60297#L788-3 assume !(1 == ~E_6~0); 60295#L793-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 60293#L494-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 60285#L531-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 60283#L532-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 60280#L1033 assume !(0 == start_simulation_~tmp~3); 60277#L1033-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 60261#L494-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 60260#L531-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 60259#L532-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 60258#L988 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 60257#L995 stop_simulation_#res := stop_simulation_~__retres2~0; 60256#L996 start_simulation_#t~ret17 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 60255#L1046 assume !(0 != start_simulation_~tmp___0~1); 58653#L1014-3 [2018-11-18 15:29:28,417 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:28,417 INFO L82 PathProgramCache]: Analyzing trace with hash -1079395497, now seen corresponding path program 1 times [2018-11-18 15:29:28,417 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:28,417 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:28,417 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:28,418 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:28,418 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:28,424 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:28,484 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:29:28,484 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:29:28,484 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 15:29:28,484 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 15:29:28,485 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:28,485 INFO L82 PathProgramCache]: Analyzing trace with hash 1796198885, now seen corresponding path program 1 times [2018-11-18 15:29:28,485 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:28,485 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:28,485 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:28,486 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:28,486 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:28,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:28,507 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:29:28,507 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:29:28,507 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:29:28,507 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:29:28,507 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 15:29:28,508 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:29:28,508 INFO L87 Difference]: Start difference. First operand 6917 states and 9701 transitions. cyclomatic complexity: 2800 Second operand 5 states. [2018-11-18 15:29:28,642 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:29:28,642 INFO L93 Difference]: Finished difference Result 10141 states and 14164 transitions. [2018-11-18 15:29:28,643 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 15:29:28,643 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10141 states and 14164 transitions. [2018-11-18 15:29:28,666 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 9944 [2018-11-18 15:29:28,684 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10141 states to 10141 states and 14164 transitions. [2018-11-18 15:29:28,684 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10141 [2018-11-18 15:29:28,689 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10141 [2018-11-18 15:29:28,689 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10141 states and 14164 transitions. [2018-11-18 15:29:28,695 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:29:28,695 INFO L705 BuchiCegarLoop]: Abstraction has 10141 states and 14164 transitions. [2018-11-18 15:29:28,701 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10141 states and 14164 transitions. [2018-11-18 15:29:28,751 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10141 to 6941. [2018-11-18 15:29:28,751 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6941 states. [2018-11-18 15:29:28,761 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6941 states to 6941 states and 9636 transitions. [2018-11-18 15:29:28,761 INFO L728 BuchiCegarLoop]: Abstraction has 6941 states and 9636 transitions. [2018-11-18 15:29:28,761 INFO L608 BuchiCegarLoop]: Abstraction has 6941 states and 9636 transitions. [2018-11-18 15:29:28,761 INFO L442 BuchiCegarLoop]: ======== Iteration 15============ [2018-11-18 15:29:28,761 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6941 states and 9636 transitions. [2018-11-18 15:29:28,777 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 6792 [2018-11-18 15:29:28,777 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:29:28,777 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:29:28,778 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:28,778 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:28,779 INFO L794 eck$LassoCheckResult]: Stem: 75768#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 75642#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 75643#L977 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 75282#L444 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 75283#L451 assume 1 == ~m_i~0;~m_st~0 := 0; 75782#L451-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 75394#L456-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 75395#L461-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 75284#L466-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 75285#L471-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 75575#L476-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 75576#L481-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 75785#L660 assume !(0 == ~M_E~0); 75786#L660-2 assume !(0 == ~T1_E~0); 75187#L665-1 assume !(0 == ~T2_E~0); 75188#L670-1 assume !(0 == ~T3_E~0); 75293#L675-1 assume !(0 == ~T4_E~0); 75294#L680-1 assume !(0 == ~T5_E~0); 75584#L685-1 assume !(0 == ~T6_E~0); 75585#L690-1 assume !(0 == ~E_1~0); 75453#L695-1 assume !(0 == ~E_2~0); 75454#L700-1 assume !(0 == ~E_3~0); 75749#L705-1 assume !(0 == ~E_4~0); 75362#L710-1 assume !(0 == ~E_5~0); 75363#L715-1 assume !(0 == ~E_6~0); 75224#L720-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 75225#L310 assume !(1 == ~m_pc~0); 75416#L310-2 is_master_triggered_~__retres1~0 := 0; 75414#L321 is_master_triggered_#res := is_master_triggered_~__retres1~0; 75415#L322 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 75554#L815 assume !(0 != activate_threads_~tmp~1); 75744#L815-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 75646#L329 assume !(1 == ~t1_pc~0); 75647#L329-2 is_transmit1_triggered_~__retres1~1 := 0; 75644#L340 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 75645#L341 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 75784#L823 assume !(0 != activate_threads_~tmp___0~0); 75882#L823-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 75845#L348 assume !(1 == ~t2_pc~0); 75846#L348-2 is_transmit2_triggered_~__retres1~2 := 0; 75842#L359 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 75843#L360 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 75373#L831 assume !(0 != activate_threads_~tmp___1~0); 75357#L831-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 75289#L367 assume !(1 == ~t3_pc~0); 75257#L367-2 is_transmit3_triggered_~__retres1~3 := 0; 75258#L378 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 75288#L379 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 75399#L839 assume !(0 != activate_threads_~tmp___2~0); 75595#L839-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 75502#L386 assume !(1 == ~t4_pc~0); 75503#L386-2 is_transmit4_triggered_~__retres1~4 := 0; 75501#L397 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 75402#L398 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 75403#L847 assume !(0 != activate_threads_~tmp___3~0); 75791#L847-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 75792#L405 assume !(1 == ~t5_pc~0); 75732#L405-2 is_transmit5_triggered_~__retres1~5 := 0; 75733#L416 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 75688#L417 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 75689#L855 assume !(0 != activate_threads_~tmp___4~0); 75801#L855-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 75337#L424 assume !(1 == ~t6_pc~0); 75338#L424-2 is_transmit6_triggered_~__retres1~6 := 0; 75335#L435 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 75336#L436 activate_threads_#t~ret14 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 75243#L863 assume !(0 != activate_threads_~tmp___5~0); 75214#L863-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 75215#L733 assume !(1 == ~M_E~0); 75863#L733-2 assume !(1 == ~T1_E~0); 75746#L738-1 assume !(1 == ~T2_E~0); 75360#L743-1 assume !(1 == ~T3_E~0); 75361#L748-1 assume !(1 == ~T4_E~0); 75219#L753-1 assume !(1 == ~T5_E~0); 75220#L758-1 assume !(1 == ~T6_E~0); 75305#L763-1 assume !(1 == ~E_1~0); 75306#L768-1 assume !(1 == ~E_2~0); 75580#L773-1 assume !(1 == ~E_3~0); 75581#L778-1 assume !(1 == ~E_4~0); 75447#L783-1 assume !(1 == ~E_5~0); 75448#L788-1 assume !(1 == ~E_6~0); 75742#L793-1 assume { :end_inline_reset_delta_events } true; 75743#L1014-3 [2018-11-18 15:29:28,779 INFO L796 eck$LassoCheckResult]: Loop: 75743#L1014-3 assume true; 78089#L1014-1 assume !false; 77692#L1015 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 77690#L635 assume true; 77688#L541-1 assume !false; 77674#L542 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 77505#L494 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 77496#L531 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 77494#L532 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 77491#L546 assume !(0 != eval_~tmp~0); 77492#L650 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 78740#L444-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 78738#L660-3 assume 0 == ~M_E~0;~M_E~0 := 1; 78736#L660-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 78734#L665-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 78733#L670-3 assume !(0 == ~T3_E~0); 78732#L675-3 assume !(0 == ~T4_E~0); 78731#L680-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 78730#L685-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 78729#L690-3 assume !(0 == ~E_1~0); 78728#L695-3 assume 0 == ~E_2~0;~E_2~0 := 1; 78727#L700-3 assume 0 == ~E_3~0;~E_3~0 := 1; 78726#L705-3 assume 0 == ~E_4~0;~E_4~0 := 1; 78724#L710-3 assume !(0 == ~E_5~0); 78722#L715-3 assume !(0 == ~E_6~0); 78720#L720-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 78718#L310-21 assume !(1 == ~m_pc~0); 78716#L310-23 is_master_triggered_~__retres1~0 := 0; 78714#L321-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 78712#L322-7 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 78710#L815-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 78709#L815-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 78708#L329-21 assume !(1 == ~t1_pc~0); 78704#L329-23 is_transmit1_triggered_~__retres1~1 := 0; 78702#L340-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 78700#L341-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 78698#L823-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 78696#L823-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 78694#L348-21 assume !(1 == ~t2_pc~0); 78692#L348-23 is_transmit2_triggered_~__retres1~2 := 0; 78689#L359-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 78687#L360-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 78685#L831-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 78683#L831-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 78681#L367-21 assume !(1 == ~t3_pc~0); 78679#L367-23 is_transmit3_triggered_~__retres1~3 := 0; 78675#L378-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 78673#L379-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 78671#L839-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 78669#L839-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 78667#L386-21 assume !(1 == ~t4_pc~0); 78665#L386-23 is_transmit4_triggered_~__retres1~4 := 0; 78662#L397-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 78660#L398-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 78658#L847-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 78656#L847-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 78654#L405-21 assume !(1 == ~t5_pc~0); 78652#L405-23 is_transmit5_triggered_~__retres1~5 := 0; 78650#L416-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 78648#L417-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 78646#L855-21 assume !(0 != activate_threads_~tmp___4~0); 78644#L855-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 78642#L424-21 assume !(1 == ~t6_pc~0); 78638#L424-23 is_transmit6_triggered_~__retres1~6 := 0; 78636#L435-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 78634#L436-7 activate_threads_#t~ret14 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 78632#L863-21 assume !(0 != activate_threads_~tmp___5~0); 78630#L863-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 78627#L733-3 assume !(1 == ~M_E~0); 78625#L733-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 78623#L738-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 78621#L743-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 78619#L748-3 assume !(1 == ~T4_E~0); 78617#L753-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 78614#L758-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 78612#L763-3 assume !(1 == ~E_1~0); 78610#L768-3 assume !(1 == ~E_2~0); 78608#L773-3 assume 1 == ~E_3~0;~E_3~0 := 2; 78599#L778-3 assume 1 == ~E_4~0;~E_4~0 := 2; 78592#L783-3 assume 1 == ~E_5~0;~E_5~0 := 2; 78589#L788-3 assume !(1 == ~E_6~0); 78545#L793-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 78165#L494-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 78157#L531-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 78155#L532-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 78152#L1033 assume !(0 == start_simulation_~tmp~3); 78150#L1033-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 78127#L494-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 78122#L531-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 78117#L532-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 78111#L988 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 78107#L995 stop_simulation_#res := stop_simulation_~__retres2~0; 78101#L996 start_simulation_#t~ret17 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 78095#L1046 assume !(0 != start_simulation_~tmp___0~1); 75743#L1014-3 [2018-11-18 15:29:28,779 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:28,779 INFO L82 PathProgramCache]: Analyzing trace with hash -2100463851, now seen corresponding path program 1 times [2018-11-18 15:29:28,779 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:28,779 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:28,780 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:28,780 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:28,780 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:28,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:29:28,791 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:29:28,817 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:28,817 INFO L82 PathProgramCache]: Analyzing trace with hash -443611262, now seen corresponding path program 1 times [2018-11-18 15:29:28,818 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:28,818 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:28,818 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:28,818 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:28,818 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:28,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:28,846 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:29:28,846 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:29:28,846 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:29:28,847 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:29:28,847 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:29:28,847 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:29:28,847 INFO L87 Difference]: Start difference. First operand 6941 states and 9636 transitions. cyclomatic complexity: 2711 Second operand 3 states. [2018-11-18 15:29:28,927 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:29:28,927 INFO L93 Difference]: Finished difference Result 10352 states and 14202 transitions. [2018-11-18 15:29:28,929 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:29:28,929 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10352 states and 14202 transitions. [2018-11-18 15:29:28,957 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 10120 [2018-11-18 15:29:28,979 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10352 states to 10352 states and 14202 transitions. [2018-11-18 15:29:29,018 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10352 [2018-11-18 15:29:29,021 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10352 [2018-11-18 15:29:29,021 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10352 states and 14202 transitions. [2018-11-18 15:29:29,026 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:29:29,026 INFO L705 BuchiCegarLoop]: Abstraction has 10352 states and 14202 transitions. [2018-11-18 15:29:29,030 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10352 states and 14202 transitions. [2018-11-18 15:29:29,085 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10352 to 10352. [2018-11-18 15:29:29,085 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10352 states. [2018-11-18 15:29:29,096 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10352 states to 10352 states and 14202 transitions. [2018-11-18 15:29:29,096 INFO L728 BuchiCegarLoop]: Abstraction has 10352 states and 14202 transitions. [2018-11-18 15:29:29,096 INFO L608 BuchiCegarLoop]: Abstraction has 10352 states and 14202 transitions. [2018-11-18 15:29:29,096 INFO L442 BuchiCegarLoop]: ======== Iteration 16============ [2018-11-18 15:29:29,096 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10352 states and 14202 transitions. [2018-11-18 15:29:29,115 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 10120 [2018-11-18 15:29:29,115 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:29:29,116 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:29:29,117 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:29,117 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:29,117 INFO L794 eck$LassoCheckResult]: Stem: 93063#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 92934#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 92935#L977 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 92576#L444 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 92577#L451 assume 1 == ~m_i~0;~m_st~0 := 0; 93077#L451-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 92690#L456-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 92691#L461-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 92581#L466-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 92582#L471-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 92859#L476-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 92860#L481-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 93083#L660 assume 0 == ~M_E~0;~M_E~0 := 1; 93084#L660-2 assume !(0 == ~T1_E~0); 93087#L665-1 assume !(0 == ~T2_E~0); 92993#L670-1 assume !(0 == ~T3_E~0); 92590#L675-1 assume !(0 == ~T4_E~0); 92591#L680-1 assume !(0 == ~T5_E~0); 92872#L685-1 assume !(0 == ~T6_E~0); 92873#L690-1 assume !(0 == ~E_1~0); 92752#L695-1 assume !(0 == ~E_2~0); 92753#L700-1 assume !(0 == ~E_3~0); 93249#L705-1 assume !(0 == ~E_4~0); 93248#L710-1 assume !(0 == ~E_5~0); 93247#L715-1 assume !(0 == ~E_6~0); 92522#L720-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 92523#L310 assume !(1 == ~m_pc~0); 92895#L310-2 is_master_triggered_~__retres1~0 := 0; 92896#L321 is_master_triggered_#res := is_master_triggered_~__retres1~0; 93246#L322 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 93245#L815 assume !(0 != activate_threads_~tmp~1); 93244#L815-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 92941#L329 assume !(1 == ~t1_pc~0); 92942#L329-2 is_transmit1_triggered_~__retres1~1 := 0; 92957#L340 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 93241#L341 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 93178#L823 assume !(0 != activate_threads_~tmp___0~0); 93179#L823-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 93141#L348 assume !(1 == ~t2_pc~0); 93142#L348-2 is_transmit2_triggered_~__retres1~2 := 0; 93139#L359 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 93140#L360 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 93240#L831 assume !(0 != activate_threads_~tmp___1~0); 93239#L831-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 93238#L367 assume !(1 == ~t3_pc~0); 93236#L367-2 is_transmit3_triggered_~__retres1~3 := 0; 93235#L378 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 92693#L379 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 92694#L839 assume !(0 != activate_threads_~tmp___2~0); 92885#L839-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 92799#L386 assume !(1 == ~t4_pc~0); 92800#L386-2 is_transmit4_triggered_~__retres1~4 := 0; 92797#L397 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 92798#L398 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 93231#L847 assume !(0 != activate_threads_~tmp___3~0); 93230#L847-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 93229#L405 assume !(1 == ~t5_pc~0); 93228#L405-2 is_transmit5_triggered_~__retres1~5 := 0; 93227#L416 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 93226#L417 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 93225#L855 assume !(0 != activate_threads_~tmp___4~0); 93224#L855-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 93223#L424 assume !(1 == ~t6_pc~0); 93221#L424-2 is_transmit6_triggered_~__retres1~6 := 0; 93220#L435 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 93219#L436 activate_threads_#t~ret14 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 92541#L863 assume !(0 != activate_threads_~tmp___5~0); 92509#L863-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 92510#L733 assume 1 == ~M_E~0;~M_E~0 := 2; 93159#L733-2 assume !(1 == ~T1_E~0); 93045#L738-1 assume !(1 == ~T2_E~0); 92656#L743-1 assume !(1 == ~T3_E~0); 92657#L748-1 assume !(1 == ~T4_E~0); 92517#L753-1 assume !(1 == ~T5_E~0); 92518#L758-1 assume !(1 == ~T6_E~0); 92602#L763-1 assume !(1 == ~E_1~0); 92603#L768-1 assume !(1 == ~E_2~0); 92863#L773-1 assume !(1 == ~E_3~0); 92864#L778-1 assume !(1 == ~E_4~0); 92743#L783-1 assume !(1 == ~E_5~0); 92744#L788-1 assume !(1 == ~E_6~0); 93040#L793-1 assume { :end_inline_reset_delta_events } true; 93041#L1014-3 [2018-11-18 15:29:29,117 INFO L796 eck$LassoCheckResult]: Loop: 93041#L1014-3 assume true; 98830#L1014-1 assume !false; 98819#L1015 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 98818#L635 assume true; 98817#L541-1 assume !false; 98816#L542 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 98815#L494 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 98808#L531 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 98645#L532 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 98635#L546 assume !(0 != eval_~tmp~0); 98636#L650 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 99018#L444-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 99015#L660-3 assume 0 == ~M_E~0;~M_E~0 := 1; 99013#L660-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 99011#L665-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 99009#L670-3 assume !(0 == ~T3_E~0); 99007#L675-3 assume !(0 == ~T4_E~0); 99005#L680-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 99003#L685-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 99001#L690-3 assume !(0 == ~E_1~0); 98999#L695-3 assume 0 == ~E_2~0;~E_2~0 := 1; 98997#L700-3 assume 0 == ~E_3~0;~E_3~0 := 1; 98995#L705-3 assume 0 == ~E_4~0;~E_4~0 := 1; 98993#L710-3 assume !(0 == ~E_5~0); 98991#L715-3 assume !(0 == ~E_6~0); 98989#L720-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 98987#L310-21 assume !(1 == ~m_pc~0); 98985#L310-23 is_master_triggered_~__retres1~0 := 0; 98983#L321-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 98981#L322-7 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 98978#L815-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 98976#L815-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 98974#L329-21 assume !(1 == ~t1_pc~0); 98971#L329-23 is_transmit1_triggered_~__retres1~1 := 0; 98969#L340-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 98967#L341-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 98965#L823-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 98963#L823-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 98961#L348-21 assume !(1 == ~t2_pc~0); 98959#L348-23 is_transmit2_triggered_~__retres1~2 := 0; 98957#L359-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 98955#L360-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 98953#L831-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 98950#L831-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 98948#L367-21 assume 1 == ~t3_pc~0; 98945#L368-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 98943#L378-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 98941#L379-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 98939#L839-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 98937#L839-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 98935#L386-21 assume !(1 == ~t4_pc~0); 98933#L386-23 is_transmit4_triggered_~__retres1~4 := 0; 98931#L397-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 98929#L398-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 98927#L847-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 98925#L847-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 98923#L405-21 assume !(1 == ~t5_pc~0); 98921#L405-23 is_transmit5_triggered_~__retres1~5 := 0; 98919#L416-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 98917#L417-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 98914#L855-21 assume !(0 != activate_threads_~tmp___4~0); 98912#L855-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 98910#L424-21 assume !(1 == ~t6_pc~0); 98907#L424-23 is_transmit6_triggered_~__retres1~6 := 0; 98905#L435-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 98903#L436-7 activate_threads_#t~ret14 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 98902#L863-21 assume !(0 != activate_threads_~tmp___5~0); 98901#L863-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 98899#L733-3 assume 1 == ~M_E~0;~M_E~0 := 2; 98896#L733-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 98894#L738-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 98892#L743-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 98890#L748-3 assume !(1 == ~T4_E~0); 98888#L753-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 98885#L758-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 98883#L763-3 assume !(1 == ~E_1~0); 98881#L768-3 assume !(1 == ~E_2~0); 98879#L773-3 assume 1 == ~E_3~0;~E_3~0 := 2; 98877#L778-3 assume 1 == ~E_4~0;~E_4~0 := 2; 98875#L783-3 assume 1 == ~E_5~0;~E_5~0 := 2; 98873#L788-3 assume !(1 == ~E_6~0); 98870#L793-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 98868#L494-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 98860#L531-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 98858#L532-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 98855#L1033 assume !(0 == start_simulation_~tmp~3); 98852#L1033-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 98837#L494-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 98836#L531-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 98835#L532-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 98834#L988 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 98833#L995 stop_simulation_#res := stop_simulation_~__retres2~0; 98832#L996 start_simulation_#t~ret17 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 98831#L1046 assume !(0 != start_simulation_~tmp___0~1); 93041#L1014-3 [2018-11-18 15:29:29,117 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:29,117 INFO L82 PathProgramCache]: Analyzing trace with hash 1297162905, now seen corresponding path program 1 times [2018-11-18 15:29:29,118 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:29,118 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:29,118 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:29,118 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:29,118 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:29,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:29,141 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:29:29,142 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:29:29,142 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 15:29:29,142 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 15:29:29,142 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:29,142 INFO L82 PathProgramCache]: Analyzing trace with hash 1224686181, now seen corresponding path program 1 times [2018-11-18 15:29:29,142 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:29,142 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:29,143 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:29,143 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:29,143 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:29,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:29,167 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:29:29,167 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:29:29,167 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:29:29,167 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:29:29,167 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:29:29,168 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:29:29,168 INFO L87 Difference]: Start difference. First operand 10352 states and 14202 transitions. cyclomatic complexity: 3866 Second operand 3 states. [2018-11-18 15:29:29,223 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:29:29,223 INFO L93 Difference]: Finished difference Result 6941 states and 9534 transitions. [2018-11-18 15:29:29,224 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:29:29,224 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6941 states and 9534 transitions. [2018-11-18 15:29:29,240 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 6792 [2018-11-18 15:29:29,252 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6941 states to 6941 states and 9534 transitions. [2018-11-18 15:29:29,252 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6941 [2018-11-18 15:29:29,255 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6941 [2018-11-18 15:29:29,255 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6941 states and 9534 transitions. [2018-11-18 15:29:29,259 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:29:29,259 INFO L705 BuchiCegarLoop]: Abstraction has 6941 states and 9534 transitions. [2018-11-18 15:29:29,263 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6941 states and 9534 transitions. [2018-11-18 15:29:29,300 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6941 to 6941. [2018-11-18 15:29:29,300 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6941 states. [2018-11-18 15:29:29,308 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6941 states to 6941 states and 9534 transitions. [2018-11-18 15:29:29,308 INFO L728 BuchiCegarLoop]: Abstraction has 6941 states and 9534 transitions. [2018-11-18 15:29:29,308 INFO L608 BuchiCegarLoop]: Abstraction has 6941 states and 9534 transitions. [2018-11-18 15:29:29,308 INFO L442 BuchiCegarLoop]: ======== Iteration 17============ [2018-11-18 15:29:29,308 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6941 states and 9534 transitions. [2018-11-18 15:29:29,321 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 6792 [2018-11-18 15:29:29,321 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:29:29,321 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:29:29,322 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:29,323 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:29,323 INFO L794 eck$LassoCheckResult]: Stem: 110361#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 110238#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 110239#L977 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 109877#L444 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 109878#L451 assume 1 == ~m_i~0;~m_st~0 := 0; 110374#L451-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 109991#L456-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 109992#L461-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 109882#L466-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 109883#L471-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 110167#L476-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 110168#L481-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 110378#L660 assume !(0 == ~M_E~0); 110379#L660-2 assume !(0 == ~T1_E~0); 109784#L665-1 assume !(0 == ~T2_E~0); 109785#L670-1 assume !(0 == ~T3_E~0); 109891#L675-1 assume !(0 == ~T4_E~0); 109892#L680-1 assume !(0 == ~T5_E~0); 110179#L685-1 assume !(0 == ~T6_E~0); 110180#L690-1 assume !(0 == ~E_1~0); 110051#L695-1 assume !(0 == ~E_2~0); 110052#L700-1 assume !(0 == ~E_3~0); 110344#L705-1 assume !(0 == ~E_4~0); 109959#L710-1 assume !(0 == ~E_5~0); 109960#L715-1 assume !(0 == ~E_6~0); 109823#L720-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 109824#L310 assume !(1 == ~m_pc~0); 110013#L310-2 is_master_triggered_~__retres1~0 := 0; 110008#L321 is_master_triggered_#res := is_master_triggered_~__retres1~0; 110009#L322 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 110148#L815 assume !(0 != activate_threads_~tmp~1); 110340#L815-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 110245#L329 assume !(1 == ~t1_pc~0); 110246#L329-2 is_transmit1_triggered_~__retres1~1 := 0; 110240#L340 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 110241#L341 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 110377#L823 assume !(0 != activate_threads_~tmp___0~0); 110464#L823-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 110434#L348 assume !(1 == ~t2_pc~0); 110435#L348-2 is_transmit2_triggered_~__retres1~2 := 0; 110432#L359 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 110433#L360 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 109969#L831 assume !(0 != activate_threads_~tmp___1~0); 109954#L831-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 109887#L367 assume !(1 == ~t3_pc~0); 109855#L367-2 is_transmit3_triggered_~__retres1~3 := 0; 109856#L378 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 109886#L379 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 109994#L839 assume !(0 != activate_threads_~tmp___2~0); 110190#L839-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 110100#L386 assume !(1 == ~t4_pc~0); 110101#L386-2 is_transmit4_triggered_~__retres1~4 := 0; 110099#L397 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 109999#L398 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 110000#L847 assume !(0 != activate_threads_~tmp___3~0); 110385#L847-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 110386#L405 assume !(1 == ~t5_pc~0); 110325#L405-2 is_transmit5_triggered_~__retres1~5 := 0; 110326#L416 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 110287#L417 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 110288#L855 assume !(0 != activate_threads_~tmp___4~0); 110392#L855-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 109934#L424 assume !(1 == ~t6_pc~0); 109935#L424-2 is_transmit6_triggered_~__retres1~6 := 0; 109930#L435 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 109931#L436 activate_threads_#t~ret14 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 109842#L863 assume !(0 != activate_threads_~tmp___5~0); 109810#L863-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 109811#L733 assume !(1 == ~M_E~0); 110449#L733-2 assume !(1 == ~T1_E~0); 110342#L738-1 assume !(1 == ~T2_E~0); 109957#L743-1 assume !(1 == ~T3_E~0); 109958#L748-1 assume !(1 == ~T4_E~0); 109818#L753-1 assume !(1 == ~T5_E~0); 109819#L758-1 assume !(1 == ~T6_E~0); 109903#L763-1 assume !(1 == ~E_1~0); 109904#L768-1 assume !(1 == ~E_2~0); 110171#L773-1 assume !(1 == ~E_3~0); 110172#L778-1 assume !(1 == ~E_4~0); 110043#L783-1 assume !(1 == ~E_5~0); 110044#L788-1 assume !(1 == ~E_6~0); 110338#L793-1 assume { :end_inline_reset_delta_events } true; 110339#L1014-3 [2018-11-18 15:29:29,323 INFO L796 eck$LassoCheckResult]: Loop: 110339#L1014-3 assume true; 114552#L1014-1 assume !false; 114426#L1015 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 114425#L635 assume true; 114424#L541-1 assume !false; 114423#L542 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 114422#L494 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 114408#L531 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 114406#L532 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 114403#L546 assume !(0 != eval_~tmp~0); 114404#L650 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 114725#L444-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 114723#L660-3 assume !(0 == ~M_E~0); 114721#L660-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 114719#L665-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 114717#L670-3 assume !(0 == ~T3_E~0); 114716#L675-3 assume !(0 == ~T4_E~0); 114715#L680-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 114714#L685-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 114713#L690-3 assume !(0 == ~E_1~0); 114712#L695-3 assume 0 == ~E_2~0;~E_2~0 := 1; 114711#L700-3 assume 0 == ~E_3~0;~E_3~0 := 1; 114710#L705-3 assume 0 == ~E_4~0;~E_4~0 := 1; 114709#L710-3 assume !(0 == ~E_5~0); 114708#L715-3 assume !(0 == ~E_6~0); 114707#L720-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 114706#L310-21 assume !(1 == ~m_pc~0); 114705#L310-23 is_master_triggered_~__retres1~0 := 0; 114704#L321-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 114703#L322-7 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 114701#L815-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 114699#L815-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 114697#L329-21 assume !(1 == ~t1_pc~0); 114694#L329-23 is_transmit1_triggered_~__retres1~1 := 0; 114692#L340-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 114690#L341-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 114687#L823-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 114685#L823-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 114683#L348-21 assume !(1 == ~t2_pc~0); 114681#L348-23 is_transmit2_triggered_~__retres1~2 := 0; 114679#L359-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 114677#L360-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 114675#L831-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 114673#L831-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 114671#L367-21 assume !(1 == ~t3_pc~0); 114669#L367-23 is_transmit3_triggered_~__retres1~3 := 0; 114666#L378-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 114664#L379-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 114662#L839-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 114659#L839-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 114657#L386-21 assume !(1 == ~t4_pc~0); 114655#L386-23 is_transmit4_triggered_~__retres1~4 := 0; 114653#L397-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 114651#L398-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 114649#L847-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 114647#L847-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 114645#L405-21 assume !(1 == ~t5_pc~0); 114643#L405-23 is_transmit5_triggered_~__retres1~5 := 0; 114641#L416-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 114639#L417-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 114637#L855-21 assume !(0 != activate_threads_~tmp___4~0); 114635#L855-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 114633#L424-21 assume !(1 == ~t6_pc~0); 114630#L424-23 is_transmit6_triggered_~__retres1~6 := 0; 114628#L435-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 114626#L436-7 activate_threads_#t~ret14 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 114623#L863-21 assume !(0 != activate_threads_~tmp___5~0); 114621#L863-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 114619#L733-3 assume !(1 == ~M_E~0); 114617#L733-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 114615#L738-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 114613#L743-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 114611#L748-3 assume !(1 == ~T4_E~0); 114609#L753-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 114607#L758-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 114605#L763-3 assume !(1 == ~E_1~0); 114603#L768-3 assume !(1 == ~E_2~0); 114601#L773-3 assume 1 == ~E_3~0;~E_3~0 := 2; 114599#L778-3 assume 1 == ~E_4~0;~E_4~0 := 2; 114597#L783-3 assume 1 == ~E_5~0;~E_5~0 := 2; 114595#L788-3 assume !(1 == ~E_6~0); 114593#L793-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 114591#L494-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 114583#L531-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 114581#L532-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 114579#L1033 assume !(0 == start_simulation_~tmp~3); 114575#L1033-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 114562#L494-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 114560#L531-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 114558#L532-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 114556#L988 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 114555#L995 stop_simulation_#res := stop_simulation_~__retres2~0; 114554#L996 start_simulation_#t~ret17 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 114553#L1046 assume !(0 != start_simulation_~tmp___0~1); 110339#L1014-3 [2018-11-18 15:29:29,323 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:29,323 INFO L82 PathProgramCache]: Analyzing trace with hash -2100463851, now seen corresponding path program 2 times [2018-11-18 15:29:29,323 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:29,323 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:29,324 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:29,324 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:29,324 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:29,329 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:29:29,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:29:29,348 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:29,348 INFO L82 PathProgramCache]: Analyzing trace with hash 1123146688, now seen corresponding path program 1 times [2018-11-18 15:29:29,349 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:29,349 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:29,349 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:29,349 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:29:29,349 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:29,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:29,379 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:29:29,379 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:29:29,379 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:29:29,379 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:29:29,379 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:29:29,379 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:29:29,380 INFO L87 Difference]: Start difference. First operand 6941 states and 9534 transitions. cyclomatic complexity: 2609 Second operand 3 states. [2018-11-18 15:29:29,449 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:29:29,450 INFO L93 Difference]: Finished difference Result 10324 states and 14083 transitions. [2018-11-18 15:29:29,451 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:29:29,451 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10324 states and 14083 transitions. [2018-11-18 15:29:29,474 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 10092 [2018-11-18 15:29:29,492 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10324 states to 10324 states and 14083 transitions. [2018-11-18 15:29:29,492 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10324 [2018-11-18 15:29:29,497 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10324 [2018-11-18 15:29:29,497 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10324 states and 14083 transitions. [2018-11-18 15:29:29,504 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:29:29,504 INFO L705 BuchiCegarLoop]: Abstraction has 10324 states and 14083 transitions. [2018-11-18 15:29:29,509 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10324 states and 14083 transitions. [2018-11-18 15:29:29,563 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10324 to 10316. [2018-11-18 15:29:29,563 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10316 states. [2018-11-18 15:29:29,575 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10316 states to 10316 states and 14075 transitions. [2018-11-18 15:29:29,575 INFO L728 BuchiCegarLoop]: Abstraction has 10316 states and 14075 transitions. [2018-11-18 15:29:29,575 INFO L608 BuchiCegarLoop]: Abstraction has 10316 states and 14075 transitions. [2018-11-18 15:29:29,575 INFO L442 BuchiCegarLoop]: ======== Iteration 18============ [2018-11-18 15:29:29,575 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10316 states and 14075 transitions. [2018-11-18 15:29:29,595 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 10084 [2018-11-18 15:29:29,595 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:29:29,595 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:29:29,596 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:29,597 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:29,597 INFO L794 eck$LassoCheckResult]: Stem: 127629#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 127511#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 127512#L977 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 127148#L444 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 127149#L451 assume 1 == ~m_i~0;~m_st~0 := 0; 127642#L451-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 127262#L456-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 127263#L461-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 127153#L466-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 127154#L471-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 127440#L476-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 127441#L481-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 127646#L660 assume !(0 == ~M_E~0); 127647#L660-2 assume !(0 == ~T1_E~0); 127055#L665-1 assume !(0 == ~T2_E~0); 127056#L670-1 assume !(0 == ~T3_E~0); 127162#L675-1 assume !(0 == ~T4_E~0); 127163#L680-1 assume !(0 == ~T5_E~0); 127454#L685-1 assume !(0 == ~T6_E~0); 127455#L690-1 assume !(0 == ~E_1~0); 127324#L695-1 assume 0 == ~E_2~0;~E_2~0 := 1; 127325#L700-1 assume !(0 == ~E_3~0); 127796#L705-1 assume !(0 == ~E_4~0); 127230#L710-1 assume !(0 == ~E_5~0); 127231#L715-1 assume !(0 == ~E_6~0); 127654#L720-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 127286#L310 assume !(1 == ~m_pc~0); 127287#L310-2 is_master_triggered_~__retres1~0 := 0; 127281#L321 is_master_triggered_#res := is_master_triggered_~__retres1~0; 127282#L322 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 127421#L815 assume !(0 != activate_threads_~tmp~1); 127606#L815-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 127607#L329 assume !(1 == ~t1_pc~0); 127790#L329-2 is_transmit1_triggered_~__retres1~1 := 0; 127513#L340 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 127514#L341 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 127645#L823 assume !(0 != activate_threads_~tmp___0~0); 127729#L823-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 127730#L348 assume !(1 == ~t2_pc~0); 127705#L348-2 is_transmit2_triggered_~__retres1~2 := 0; 127706#L359 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 127743#L360 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 127240#L831 assume !(0 != activate_threads_~tmp___1~0); 127225#L831-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 127158#L367 assume !(1 == ~t3_pc~0); 127126#L367-2 is_transmit3_triggered_~__retres1~3 := 0; 127127#L378 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 127157#L379 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 127463#L839 assume !(0 != activate_threads_~tmp___2~0); 127464#L839-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 127782#L386 assume !(1 == ~t4_pc~0); 127781#L386-2 is_transmit4_triggered_~__retres1~4 := 0; 127780#L397 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 127272#L398 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 127273#L847 assume !(0 != activate_threads_~tmp___3~0); 127651#L847-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 127652#L405 assume !(1 == ~t5_pc~0); 127777#L405-2 is_transmit5_triggered_~__retres1~5 := 0; 127723#L416 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 127560#L417 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 127561#L855 assume !(0 != activate_threads_~tmp___4~0); 127658#L855-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 127206#L424 assume !(1 == ~t6_pc~0); 127207#L424-2 is_transmit6_triggered_~__retres1~6 := 0; 127202#L435 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 127203#L436 activate_threads_#t~ret14 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 127113#L863 assume !(0 != activate_threads_~tmp___5~0); 127080#L863-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 127081#L733 assume !(1 == ~M_E~0); 127713#L733-2 assume !(1 == ~T1_E~0); 127609#L738-1 assume !(1 == ~T2_E~0); 127228#L743-1 assume !(1 == ~T3_E~0); 127229#L748-1 assume !(1 == ~T4_E~0); 127088#L753-1 assume !(1 == ~T5_E~0); 127089#L758-1 assume !(1 == ~T6_E~0); 127174#L763-1 assume !(1 == ~E_1~0); 127175#L768-1 assume 1 == ~E_2~0;~E_2~0 := 2; 127446#L773-1 assume !(1 == ~E_3~0); 127447#L778-1 assume !(1 == ~E_4~0); 127316#L783-1 assume !(1 == ~E_5~0); 127317#L788-1 assume !(1 == ~E_6~0); 127604#L793-1 assume { :end_inline_reset_delta_events } true; 127605#L1014-3 [2018-11-18 15:29:29,597 INFO L796 eck$LassoCheckResult]: Loop: 127605#L1014-3 assume true; 130945#L1014-1 assume !false; 130935#L1015 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 130930#L635 assume true; 130926#L541-1 assume !false; 130922#L542 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 129029#L494 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 129022#L531 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 129018#L532 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 129015#L546 assume !(0 != eval_~tmp~0); 129016#L650 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 131497#L444-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 131494#L660-3 assume !(0 == ~M_E~0); 131491#L660-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 131488#L665-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 131485#L670-3 assume !(0 == ~T3_E~0); 131482#L675-3 assume !(0 == ~T4_E~0); 131479#L680-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 131476#L685-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 131473#L690-3 assume !(0 == ~E_1~0); 131471#L695-3 assume !(0 == ~E_2~0); 131468#L700-3 assume 0 == ~E_3~0;~E_3~0 := 1; 131464#L705-3 assume 0 == ~E_4~0;~E_4~0 := 1; 131461#L710-3 assume !(0 == ~E_5~0); 131458#L715-3 assume !(0 == ~E_6~0); 131455#L720-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 131452#L310-21 assume !(1 == ~m_pc~0); 131449#L310-23 is_master_triggered_~__retres1~0 := 0; 131446#L321-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 131443#L322-7 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 131440#L815-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 131437#L815-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 131433#L329-21 assume !(1 == ~t1_pc~0); 131429#L329-23 is_transmit1_triggered_~__retres1~1 := 0; 131426#L340-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 131423#L341-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 131421#L823-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 131419#L823-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 131417#L348-21 assume !(1 == ~t2_pc~0); 131414#L348-23 is_transmit2_triggered_~__retres1~2 := 0; 131411#L359-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 131408#L360-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 131405#L831-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 131402#L831-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 131399#L367-21 assume 1 == ~t3_pc~0; 131394#L368-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 131391#L378-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 131388#L379-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 131385#L839-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 131383#L839-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 131380#L386-21 assume !(1 == ~t4_pc~0); 131377#L386-23 is_transmit4_triggered_~__retres1~4 := 0; 131374#L397-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 131371#L398-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 131367#L847-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 131364#L847-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 131361#L405-21 assume !(1 == ~t5_pc~0); 131358#L405-23 is_transmit5_triggered_~__retres1~5 := 0; 131355#L416-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 131352#L417-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 131348#L855-21 assume !(0 != activate_threads_~tmp___4~0); 131345#L855-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 131341#L424-21 assume !(1 == ~t6_pc~0); 131337#L424-23 is_transmit6_triggered_~__retres1~6 := 0; 131334#L435-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 131331#L436-7 activate_threads_#t~ret14 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 131328#L863-21 assume !(0 != activate_threads_~tmp___5~0); 131324#L863-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 131322#L733-3 assume !(1 == ~M_E~0); 131319#L733-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 131316#L738-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 131313#L743-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 131309#L748-3 assume !(1 == ~T4_E~0); 131304#L753-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 131300#L758-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 131296#L763-3 assume !(1 == ~E_1~0); 131292#L768-3 assume !(1 == ~E_2~0); 131288#L773-3 assume 1 == ~E_3~0;~E_3~0 := 2; 131284#L778-3 assume 1 == ~E_4~0;~E_4~0 := 2; 131278#L783-3 assume 1 == ~E_5~0;~E_5~0 := 2; 131272#L788-3 assume !(1 == ~E_6~0); 131266#L793-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 131074#L494-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 131066#L531-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 131064#L532-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 131061#L1033 assume !(0 == start_simulation_~tmp~3); 131059#L1033-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 131009#L494-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 131003#L531-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 130996#L532-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 130990#L988 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 130985#L995 stop_simulation_#res := stop_simulation_~__retres2~0; 130980#L996 start_simulation_#t~ret17 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 130974#L1046 assume !(0 != start_simulation_~tmp___0~1); 127605#L1014-3 [2018-11-18 15:29:29,597 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:29,597 INFO L82 PathProgramCache]: Analyzing trace with hash 1457972889, now seen corresponding path program 1 times [2018-11-18 15:29:29,597 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:29,597 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:29,598 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:29,598 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:29,598 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:29,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:29,621 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:29:29,622 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:29:29,622 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 15:29:29,622 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 15:29:29,622 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:29,622 INFO L82 PathProgramCache]: Analyzing trace with hash -554260705, now seen corresponding path program 1 times [2018-11-18 15:29:29,622 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:29,622 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:29,623 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:29,623 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:29,623 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:29,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:29,650 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:29:29,650 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:29:29,650 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 15:29:29,650 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:29:29,650 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:29:29,650 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:29:29,651 INFO L87 Difference]: Start difference. First operand 10316 states and 14075 transitions. cyclomatic complexity: 3775 Second operand 3 states. [2018-11-18 15:29:29,694 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:29:29,694 INFO L93 Difference]: Finished difference Result 6941 states and 9432 transitions. [2018-11-18 15:29:29,696 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:29:29,696 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6941 states and 9432 transitions. [2018-11-18 15:29:29,711 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 6792 [2018-11-18 15:29:29,724 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6941 states to 6941 states and 9432 transitions. [2018-11-18 15:29:29,724 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6941 [2018-11-18 15:29:29,727 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6941 [2018-11-18 15:29:29,727 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6941 states and 9432 transitions. [2018-11-18 15:29:29,732 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:29:29,732 INFO L705 BuchiCegarLoop]: Abstraction has 6941 states and 9432 transitions. [2018-11-18 15:29:29,736 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6941 states and 9432 transitions. [2018-11-18 15:29:29,770 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6941 to 6941. [2018-11-18 15:29:29,771 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6941 states. [2018-11-18 15:29:29,779 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6941 states to 6941 states and 9432 transitions. [2018-11-18 15:29:29,779 INFO L728 BuchiCegarLoop]: Abstraction has 6941 states and 9432 transitions. [2018-11-18 15:29:29,779 INFO L608 BuchiCegarLoop]: Abstraction has 6941 states and 9432 transitions. [2018-11-18 15:29:29,779 INFO L442 BuchiCegarLoop]: ======== Iteration 19============ [2018-11-18 15:29:29,779 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6941 states and 9432 transitions. [2018-11-18 15:29:29,793 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 6792 [2018-11-18 15:29:29,793 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:29:29,793 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:29:29,794 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:29,794 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:29,794 INFO L794 eck$LassoCheckResult]: Stem: 144881#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 144761#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 144762#L977 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 144416#L444 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 144417#L451 assume 1 == ~m_i~0;~m_st~0 := 0; 144893#L451-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 144530#L456-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 144531#L461-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 144421#L466-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 144422#L471-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 144699#L476-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 144700#L481-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 144897#L660 assume !(0 == ~M_E~0); 144898#L660-2 assume !(0 == ~T1_E~0); 144321#L665-1 assume !(0 == ~T2_E~0); 144322#L670-1 assume !(0 == ~T3_E~0); 144430#L675-1 assume !(0 == ~T4_E~0); 144431#L680-1 assume !(0 == ~T5_E~0); 144711#L685-1 assume !(0 == ~T6_E~0); 144712#L690-1 assume !(0 == ~E_1~0); 144590#L695-1 assume !(0 == ~E_2~0); 144591#L700-1 assume !(0 == ~E_3~0); 144864#L705-1 assume !(0 == ~E_4~0); 144498#L710-1 assume !(0 == ~E_5~0); 144499#L715-1 assume !(0 == ~E_6~0); 144360#L720-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 144361#L310 assume !(1 == ~m_pc~0); 144552#L310-2 is_master_triggered_~__retres1~0 := 0; 144547#L321 is_master_triggered_#res := is_master_triggered_~__retres1~0; 144548#L322 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 144679#L815 assume !(0 != activate_threads_~tmp~1); 144860#L815-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 144768#L329 assume !(1 == ~t1_pc~0); 144769#L329-2 is_transmit1_triggered_~__retres1~1 := 0; 144763#L340 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 144764#L341 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 144896#L823 assume !(0 != activate_threads_~tmp___0~0); 144983#L823-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 144956#L348 assume !(1 == ~t2_pc~0); 144957#L348-2 is_transmit2_triggered_~__retres1~2 := 0; 144954#L359 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 144955#L360 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 144508#L831 assume !(0 != activate_threads_~tmp___1~0); 144493#L831-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 144426#L367 assume !(1 == ~t3_pc~0); 144393#L367-2 is_transmit3_triggered_~__retres1~3 := 0; 144394#L378 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 144425#L379 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 144533#L839 assume !(0 != activate_threads_~tmp___2~0); 144720#L839-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 144636#L386 assume !(1 == ~t4_pc~0); 144637#L386-2 is_transmit4_triggered_~__retres1~4 := 0; 144635#L397 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 144538#L398 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 144539#L847 assume !(0 != activate_threads_~tmp___3~0); 144903#L847-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 144904#L405 assume !(1 == ~t5_pc~0); 144844#L405-2 is_transmit5_triggered_~__retres1~5 := 0; 144845#L416 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 144809#L417 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 144810#L855 assume !(0 != activate_threads_~tmp___4~0); 144913#L855-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 144474#L424 assume !(1 == ~t6_pc~0); 144475#L424-2 is_transmit6_triggered_~__retres1~6 := 0; 144470#L435 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 144471#L436 activate_threads_#t~ret14 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 144379#L863 assume !(0 != activate_threads_~tmp___5~0); 144347#L863-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 144348#L733 assume !(1 == ~M_E~0); 144969#L733-2 assume !(1 == ~T1_E~0); 144862#L738-1 assume !(1 == ~T2_E~0); 144496#L743-1 assume !(1 == ~T3_E~0); 144497#L748-1 assume !(1 == ~T4_E~0); 144355#L753-1 assume !(1 == ~T5_E~0); 144356#L758-1 assume !(1 == ~T6_E~0); 144442#L763-1 assume !(1 == ~E_1~0); 144443#L768-1 assume !(1 == ~E_2~0); 144703#L773-1 assume !(1 == ~E_3~0); 144704#L778-1 assume !(1 == ~E_4~0); 144581#L783-1 assume !(1 == ~E_5~0); 144582#L788-1 assume !(1 == ~E_6~0); 144858#L793-1 assume { :end_inline_reset_delta_events } true; 144859#L1014-3 [2018-11-18 15:29:29,794 INFO L796 eck$LassoCheckResult]: Loop: 144859#L1014-3 assume true; 147476#L1014-1 assume !false; 147454#L1015 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 147448#L635 assume true; 147441#L541-1 assume !false; 147435#L542 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 146844#L494 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 146837#L531 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 146833#L532 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 146830#L546 assume !(0 != eval_~tmp~0); 146831#L650 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 147713#L444-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 147711#L660-3 assume !(0 == ~M_E~0); 147709#L660-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 147706#L665-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 147704#L670-3 assume !(0 == ~T3_E~0); 147702#L675-3 assume !(0 == ~T4_E~0); 147700#L680-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 147698#L685-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 147696#L690-3 assume !(0 == ~E_1~0); 147694#L695-3 assume !(0 == ~E_2~0); 147692#L700-3 assume 0 == ~E_3~0;~E_3~0 := 1; 147690#L705-3 assume 0 == ~E_4~0;~E_4~0 := 1; 147688#L710-3 assume !(0 == ~E_5~0); 147686#L715-3 assume !(0 == ~E_6~0); 147684#L720-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 147682#L310-21 assume !(1 == ~m_pc~0); 147679#L310-23 is_master_triggered_~__retres1~0 := 0; 147677#L321-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 147675#L322-7 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 147673#L815-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 147671#L815-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 147669#L329-21 assume !(1 == ~t1_pc~0); 147666#L329-23 is_transmit1_triggered_~__retres1~1 := 0; 147664#L340-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 147662#L341-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 147660#L823-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 147658#L823-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 147656#L348-21 assume !(1 == ~t2_pc~0); 147654#L348-23 is_transmit2_triggered_~__retres1~2 := 0; 147652#L359-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 147650#L360-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 147648#L831-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 147646#L831-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 147643#L367-21 assume 1 == ~t3_pc~0; 147640#L368-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 147638#L378-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 147636#L379-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 147634#L839-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 147632#L839-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 147630#L386-21 assume !(1 == ~t4_pc~0); 147628#L386-23 is_transmit4_triggered_~__retres1~4 := 0; 147626#L397-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 147624#L398-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 147622#L847-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 147620#L847-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 147618#L405-21 assume !(1 == ~t5_pc~0); 147616#L405-23 is_transmit5_triggered_~__retres1~5 := 0; 147614#L416-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 147612#L417-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 147610#L855-21 assume !(0 != activate_threads_~tmp___4~0); 147608#L855-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 147606#L424-21 assume !(1 == ~t6_pc~0); 147604#L424-23 is_transmit6_triggered_~__retres1~6 := 0; 147603#L435-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 147602#L436-7 activate_threads_#t~ret14 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 147601#L863-21 assume !(0 != activate_threads_~tmp___5~0); 147600#L863-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 147599#L733-3 assume !(1 == ~M_E~0); 147598#L733-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 147597#L738-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 147595#L743-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 147593#L748-3 assume !(1 == ~T4_E~0); 147591#L753-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 147589#L758-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 147587#L763-3 assume !(1 == ~E_1~0); 147585#L768-3 assume !(1 == ~E_2~0); 147583#L773-3 assume 1 == ~E_3~0;~E_3~0 := 2; 147581#L778-3 assume 1 == ~E_4~0;~E_4~0 := 2; 147579#L783-3 assume 1 == ~E_5~0;~E_5~0 := 2; 147577#L788-3 assume !(1 == ~E_6~0); 147575#L793-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 147573#L494-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 147565#L531-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 147563#L532-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 147560#L1033 assume !(0 == start_simulation_~tmp~3); 147556#L1033-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 147532#L494-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 147530#L531-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 147528#L532-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 147526#L988 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 147524#L995 stop_simulation_#res := stop_simulation_~__retres2~0; 147496#L996 start_simulation_#t~ret17 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 147489#L1046 assume !(0 != start_simulation_~tmp___0~1); 144859#L1014-3 [2018-11-18 15:29:29,794 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:29,795 INFO L82 PathProgramCache]: Analyzing trace with hash -2100463851, now seen corresponding path program 3 times [2018-11-18 15:29:29,795 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:29,795 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:29,795 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:29,795 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:29,796 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:29,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:29:29,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:29:29,819 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:29,819 INFO L82 PathProgramCache]: Analyzing trace with hash -554260705, now seen corresponding path program 2 times [2018-11-18 15:29:29,819 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:29,820 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:29,820 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:29,820 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:29:29,820 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:29,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:29,864 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:29:29,864 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:29:29,864 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 15:29:29,865 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:29:29,865 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 15:29:29,865 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:29:29,865 INFO L87 Difference]: Start difference. First operand 6941 states and 9432 transitions. cyclomatic complexity: 2507 Second operand 5 states. [2018-11-18 15:29:29,946 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:29:29,947 INFO L93 Difference]: Finished difference Result 12453 states and 16704 transitions. [2018-11-18 15:29:29,948 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-18 15:29:29,948 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12453 states and 16704 transitions. [2018-11-18 15:29:30,016 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 12240 [2018-11-18 15:29:30,050 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12453 states to 12453 states and 16704 transitions. [2018-11-18 15:29:30,050 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12453 [2018-11-18 15:29:30,056 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12453 [2018-11-18 15:29:30,057 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12453 states and 16704 transitions. [2018-11-18 15:29:30,064 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:29:30,065 INFO L705 BuchiCegarLoop]: Abstraction has 12453 states and 16704 transitions. [2018-11-18 15:29:30,071 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12453 states and 16704 transitions. [2018-11-18 15:29:30,137 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12453 to 6989. [2018-11-18 15:29:30,137 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 6989 states. [2018-11-18 15:29:30,149 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6989 states to 6989 states and 9480 transitions. [2018-11-18 15:29:30,149 INFO L728 BuchiCegarLoop]: Abstraction has 6989 states and 9480 transitions. [2018-11-18 15:29:30,149 INFO L608 BuchiCegarLoop]: Abstraction has 6989 states and 9480 transitions. [2018-11-18 15:29:30,149 INFO L442 BuchiCegarLoop]: ======== Iteration 20============ [2018-11-18 15:29:30,149 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6989 states and 9480 transitions. [2018-11-18 15:29:30,165 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 6840 [2018-11-18 15:29:30,166 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:29:30,166 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:29:30,167 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:30,167 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:30,167 INFO L794 eck$LassoCheckResult]: Stem: 164320#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 164190#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 164191#L977 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 163826#L444 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 163827#L451 assume 1 == ~m_i~0;~m_st~0 := 0; 164335#L451-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 163940#L456-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 163941#L461-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 163831#L466-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 163832#L471-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 164122#L476-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 164123#L481-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 164339#L660 assume !(0 == ~M_E~0); 164340#L660-2 assume !(0 == ~T1_E~0); 163731#L665-1 assume !(0 == ~T2_E~0); 163732#L670-1 assume !(0 == ~T3_E~0); 163840#L675-1 assume !(0 == ~T4_E~0); 163841#L680-1 assume !(0 == ~T5_E~0); 164133#L685-1 assume !(0 == ~T6_E~0); 164134#L690-1 assume !(0 == ~E_1~0); 164000#L695-1 assume !(0 == ~E_2~0); 164001#L700-1 assume !(0 == ~E_3~0); 164298#L705-1 assume !(0 == ~E_4~0); 163908#L710-1 assume !(0 == ~E_5~0); 163909#L715-1 assume !(0 == ~E_6~0); 163771#L720-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 163772#L310 assume !(1 == ~m_pc~0); 163962#L310-2 is_master_triggered_~__retres1~0 := 0; 163957#L321 is_master_triggered_#res := is_master_triggered_~__retres1~0; 163958#L322 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 164101#L815 assume !(0 != activate_threads_~tmp~1); 164293#L815-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 164197#L329 assume !(1 == ~t1_pc~0); 164198#L329-2 is_transmit1_triggered_~__retres1~1 := 0; 164192#L340 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 164193#L341 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 164338#L823 assume !(0 != activate_threads_~tmp___0~0); 164438#L823-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 164402#L348 assume !(1 == ~t2_pc~0); 164403#L348-2 is_transmit2_triggered_~__retres1~2 := 0; 164399#L359 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 164400#L360 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 163917#L831 assume !(0 != activate_threads_~tmp___1~0); 163903#L831-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 163836#L367 assume !(1 == ~t3_pc~0); 163804#L367-2 is_transmit3_triggered_~__retres1~3 := 0; 163805#L378 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 163835#L379 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 163943#L839 assume !(0 != activate_threads_~tmp___2~0); 164143#L839-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 164055#L386 assume !(1 == ~t4_pc~0); 164056#L386-2 is_transmit4_triggered_~__retres1~4 := 0; 164054#L397 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 163948#L398 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 163949#L847 assume !(0 != activate_threads_~tmp___3~0); 164347#L847-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 164348#L405 assume !(1 == ~t5_pc~0); 164275#L405-2 is_transmit5_triggered_~__retres1~5 := 0; 164276#L416 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 164238#L417 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 164239#L855 assume !(0 != activate_threads_~tmp___4~0); 164357#L855-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 163884#L424 assume !(1 == ~t6_pc~0); 163885#L424-2 is_transmit6_triggered_~__retres1~6 := 0; 163880#L435 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 163881#L436 activate_threads_#t~ret14 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 163790#L863 assume !(0 != activate_threads_~tmp___5~0); 163757#L863-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 163758#L733 assume !(1 == ~M_E~0); 164415#L733-2 assume !(1 == ~T1_E~0); 164295#L738-1 assume !(1 == ~T2_E~0); 163906#L743-1 assume !(1 == ~T3_E~0); 163907#L748-1 assume !(1 == ~T4_E~0); 163765#L753-1 assume !(1 == ~T5_E~0); 163766#L758-1 assume !(1 == ~T6_E~0); 163852#L763-1 assume !(1 == ~E_1~0); 163853#L768-1 assume !(1 == ~E_2~0); 164126#L773-1 assume !(1 == ~E_3~0); 164127#L778-1 assume !(1 == ~E_4~0); 163991#L783-1 assume !(1 == ~E_5~0); 163992#L788-1 assume !(1 == ~E_6~0); 164291#L793-1 assume { :end_inline_reset_delta_events } true; 164292#L1014-3 [2018-11-18 15:29:30,167 INFO L796 eck$LassoCheckResult]: Loop: 164292#L1014-3 assume true; 169216#L1014-1 assume !false; 169197#L1015 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 169195#L635 assume true; 169184#L541-1 assume !false; 169183#L542 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 169182#L494 assume !(0 == ~m_st~0); 169178#L498 assume !(0 == ~t1_st~0); 169179#L502 assume !(0 == ~t2_st~0); 169181#L506 assume !(0 == ~t3_st~0); 169175#L510 assume !(0 == ~t4_st~0); 169177#L514 assume !(0 == ~t5_st~0); 169180#L518 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7 := 0; 166403#L531 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 166399#L532 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 166400#L546 assume !(0 != eval_~tmp~0); 169434#L650 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 169433#L444-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 169432#L660-3 assume !(0 == ~M_E~0); 169431#L660-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 169430#L665-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 169429#L670-3 assume !(0 == ~T3_E~0); 169428#L675-3 assume !(0 == ~T4_E~0); 169427#L680-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 169426#L685-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 169425#L690-3 assume !(0 == ~E_1~0); 169424#L695-3 assume !(0 == ~E_2~0); 169423#L700-3 assume 0 == ~E_3~0;~E_3~0 := 1; 169422#L705-3 assume 0 == ~E_4~0;~E_4~0 := 1; 169421#L710-3 assume !(0 == ~E_5~0); 169420#L715-3 assume !(0 == ~E_6~0); 169419#L720-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 169418#L310-21 assume !(1 == ~m_pc~0); 169417#L310-23 is_master_triggered_~__retres1~0 := 0; 169416#L321-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 169415#L322-7 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 169414#L815-21 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 169413#L815-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 169412#L329-21 assume !(1 == ~t1_pc~0); 169410#L329-23 is_transmit1_triggered_~__retres1~1 := 0; 169409#L340-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 169408#L341-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 169407#L823-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 169406#L823-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 169405#L348-21 assume !(1 == ~t2_pc~0); 169404#L348-23 is_transmit2_triggered_~__retres1~2 := 0; 169403#L359-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 169402#L360-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 169401#L831-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 169400#L831-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 169399#L367-21 assume !(1 == ~t3_pc~0); 169398#L367-23 is_transmit3_triggered_~__retres1~3 := 0; 169396#L378-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 169395#L379-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 169394#L839-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 169393#L839-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 169392#L386-21 assume !(1 == ~t4_pc~0); 169391#L386-23 is_transmit4_triggered_~__retres1~4 := 0; 169390#L397-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 169389#L398-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 169388#L847-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 169387#L847-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 169386#L405-21 assume !(1 == ~t5_pc~0); 169385#L405-23 is_transmit5_triggered_~__retres1~5 := 0; 169384#L416-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 169383#L417-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 169382#L855-21 assume !(0 != activate_threads_~tmp___4~0); 169381#L855-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 169380#L424-21 assume !(1 == ~t6_pc~0); 169378#L424-23 is_transmit6_triggered_~__retres1~6 := 0; 169377#L435-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 169376#L436-7 activate_threads_#t~ret14 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 169375#L863-21 assume !(0 != activate_threads_~tmp___5~0); 169374#L863-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 169373#L733-3 assume !(1 == ~M_E~0); 169372#L733-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 169371#L738-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 169370#L743-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 169369#L748-3 assume !(1 == ~T4_E~0); 169368#L753-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 169367#L758-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 169366#L763-3 assume !(1 == ~E_1~0); 169365#L768-3 assume !(1 == ~E_2~0); 169364#L773-3 assume 1 == ~E_3~0;~E_3~0 := 2; 169363#L778-3 assume 1 == ~E_4~0;~E_4~0 := 2; 169362#L783-3 assume 1 == ~E_5~0;~E_5~0 := 2; 169361#L788-3 assume !(1 == ~E_6~0); 169360#L793-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 169359#L494-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 169264#L531-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 169259#L532-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 169252#L1033 assume !(0 == start_simulation_~tmp~3); 169246#L1033-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 169240#L494-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 169238#L531-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 169227#L532-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 169225#L988 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 169223#L995 stop_simulation_#res := stop_simulation_~__retres2~0; 169221#L996 start_simulation_#t~ret17 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 169219#L1046 assume !(0 != start_simulation_~tmp___0~1); 164292#L1014-3 [2018-11-18 15:29:30,167 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:30,168 INFO L82 PathProgramCache]: Analyzing trace with hash -2100463851, now seen corresponding path program 4 times [2018-11-18 15:29:30,168 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:30,168 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:30,168 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:30,168 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:29:30,168 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:30,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:29:30,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:29:30,191 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:30,191 INFO L82 PathProgramCache]: Analyzing trace with hash 1719234957, now seen corresponding path program 1 times [2018-11-18 15:29:30,191 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:30,192 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:30,192 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:30,192 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:29:30,192 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:30,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:30,233 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:29:30,234 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:29:30,234 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 15:29:30,234 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:29:30,234 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 15:29:30,234 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 15:29:30,234 INFO L87 Difference]: Start difference. First operand 6989 states and 9480 transitions. cyclomatic complexity: 2507 Second operand 5 states. [2018-11-18 15:29:30,380 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:29:30,380 INFO L93 Difference]: Finished difference Result 9637 states and 13143 transitions. [2018-11-18 15:29:30,380 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 15:29:30,381 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9637 states and 13143 transitions. [2018-11-18 15:29:30,401 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 9440 [2018-11-18 15:29:30,423 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9637 states to 9637 states and 13143 transitions. [2018-11-18 15:29:30,423 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9637 [2018-11-18 15:29:30,428 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9637 [2018-11-18 15:29:30,428 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9637 states and 13143 transitions. [2018-11-18 15:29:30,434 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:29:30,434 INFO L705 BuchiCegarLoop]: Abstraction has 9637 states and 13143 transitions. [2018-11-18 15:29:30,439 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9637 states and 13143 transitions. [2018-11-18 15:29:30,489 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9637 to 7013. [2018-11-18 15:29:30,489 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 7013 states. [2018-11-18 15:29:30,498 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7013 states to 7013 states and 9415 transitions. [2018-11-18 15:29:30,498 INFO L728 BuchiCegarLoop]: Abstraction has 7013 states and 9415 transitions. [2018-11-18 15:29:30,498 INFO L608 BuchiCegarLoop]: Abstraction has 7013 states and 9415 transitions. [2018-11-18 15:29:30,498 INFO L442 BuchiCegarLoop]: ======== Iteration 21============ [2018-11-18 15:29:30,498 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7013 states and 9415 transitions. [2018-11-18 15:29:30,514 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 6864 [2018-11-18 15:29:30,514 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:29:30,514 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:29:30,515 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:30,516 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:30,516 INFO L794 eck$LassoCheckResult]: Stem: 181038#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 180884#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 180885#L977 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 180473#L444 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 180474#L451 assume 1 == ~m_i~0;~m_st~0 := 0; 181054#L451-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 180609#L456-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 180610#L461-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 180478#L466-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 180479#L471-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 180807#L476-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 180808#L481-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 181063#L660 assume !(0 == ~M_E~0); 181064#L660-2 assume !(0 == ~T1_E~0); 180370#L665-1 assume !(0 == ~T2_E~0); 180371#L670-1 assume !(0 == ~T3_E~0); 180487#L675-1 assume !(0 == ~T4_E~0); 180488#L680-1 assume !(0 == ~T5_E~0); 180822#L685-1 assume !(0 == ~T6_E~0); 180823#L690-1 assume !(0 == ~E_1~0); 180670#L695-1 assume !(0 == ~E_2~0); 180671#L700-1 assume !(0 == ~E_3~0); 181010#L705-1 assume !(0 == ~E_4~0); 180565#L710-1 assume !(0 == ~E_5~0); 180566#L715-1 assume !(0 == ~E_6~0); 180411#L720-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 180412#L310 assume !(1 == ~m_pc~0); 180633#L310-2 is_master_triggered_~__retres1~0 := 0; 180628#L321 is_master_triggered_#res := is_master_triggered_~__retres1~0; 180629#L322 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 180781#L815 assume !(0 != activate_threads_~tmp~1); 181004#L815-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 180891#L329 assume !(1 == ~t1_pc~0); 180892#L329-2 is_transmit1_triggered_~__retres1~1 := 0; 180886#L340 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 180887#L341 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 181062#L823 assume !(0 != activate_threads_~tmp___0~0); 181189#L823-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 181140#L348 assume !(1 == ~t2_pc~0); 181141#L348-2 is_transmit2_triggered_~__retres1~2 := 0; 181135#L359 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 181136#L360 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 180575#L831 assume !(0 != activate_threads_~tmp___1~0); 180560#L831-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 180483#L367 assume !(1 == ~t3_pc~0); 180449#L367-2 is_transmit3_triggered_~__retres1~3 := 0; 180450#L378 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 180482#L379 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 180614#L839 assume !(0 != activate_threads_~tmp___2~0); 180834#L839-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 180729#L386 assume !(1 == ~t4_pc~0); 180730#L386-2 is_transmit4_triggered_~__retres1~4 := 0; 180728#L397 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 180619#L398 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 180620#L847 assume !(0 != activate_threads_~tmp___3~0); 181075#L847-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 181076#L405 assume !(1 == ~t5_pc~0); 180983#L405-2 is_transmit5_triggered_~__retres1~5 := 0; 180984#L416 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 180934#L417 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 180935#L855 assume !(0 != activate_threads_~tmp___4~0); 181087#L855-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 180534#L424 assume !(1 == ~t6_pc~0); 180535#L424-2 is_transmit6_triggered_~__retres1~6 := 0; 180530#L435 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 180531#L436 activate_threads_#t~ret14 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 180432#L863 assume !(0 != activate_threads_~tmp___5~0); 180396#L863-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 180397#L733 assume !(1 == ~M_E~0); 181156#L733-2 assume !(1 == ~T1_E~0); 181007#L738-1 assume !(1 == ~T2_E~0); 180563#L743-1 assume !(1 == ~T3_E~0); 180564#L748-1 assume !(1 == ~T4_E~0); 180405#L753-1 assume !(1 == ~T5_E~0); 180406#L758-1 assume !(1 == ~T6_E~0); 180499#L763-1 assume !(1 == ~E_1~0); 180500#L768-1 assume !(1 == ~E_2~0); 180813#L773-1 assume !(1 == ~E_3~0); 180814#L778-1 assume !(1 == ~E_4~0); 180662#L783-1 assume !(1 == ~E_5~0); 180663#L788-1 assume !(1 == ~E_6~0); 181002#L793-1 assume { :end_inline_reset_delta_events } true; 181003#L1014-3 [2018-11-18 15:29:30,516 INFO L796 eck$LassoCheckResult]: Loop: 181003#L1014-3 assume true; 185280#L1014-1 assume !false; 185273#L1015 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 182922#L635 assume true; 182916#L541-1 assume !false; 182914#L542 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 182912#L494 assume !(0 == ~m_st~0); 182907#L498 assume !(0 == ~t1_st~0); 182908#L502 assume !(0 == ~t2_st~0); 182910#L506 assume !(0 == ~t3_st~0); 182905#L510 assume !(0 == ~t4_st~0); 182906#L514 assume !(0 == ~t5_st~0); 182909#L518 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7 := 0; 182911#L531 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 182852#L532 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 182853#L546 assume !(0 != eval_~tmp~0); 185512#L650 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 185511#L444-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 185510#L660-3 assume !(0 == ~M_E~0); 185509#L660-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 185508#L665-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 185507#L670-3 assume !(0 == ~T3_E~0); 185506#L675-3 assume !(0 == ~T4_E~0); 185505#L680-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 185504#L685-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 185503#L690-3 assume !(0 == ~E_1~0); 185502#L695-3 assume !(0 == ~E_2~0); 185501#L700-3 assume 0 == ~E_3~0;~E_3~0 := 1; 185500#L705-3 assume 0 == ~E_4~0;~E_4~0 := 1; 185499#L710-3 assume !(0 == ~E_5~0); 185498#L715-3 assume !(0 == ~E_6~0); 185497#L720-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 185496#L310-21 assume !(1 == ~m_pc~0); 185495#L310-23 is_master_triggered_~__retres1~0 := 0; 185494#L321-7 is_master_triggered_#res := is_master_triggered_~__retres1~0; 185493#L322-7 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 185492#L815-21 assume !(0 != activate_threads_~tmp~1); 185491#L815-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 185489#L329-21 assume !(1 == ~t1_pc~0); 185486#L329-23 is_transmit1_triggered_~__retres1~1 := 0; 185484#L340-7 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 185482#L341-7 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 185480#L823-21 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 185478#L823-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 185475#L348-21 assume !(1 == ~t2_pc~0); 185473#L348-23 is_transmit2_triggered_~__retres1~2 := 0; 185471#L359-7 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 185469#L360-7 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 185466#L831-21 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 185462#L831-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 185459#L367-21 assume !(1 == ~t3_pc~0); 185456#L367-23 is_transmit3_triggered_~__retres1~3 := 0; 185452#L378-7 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 185449#L379-7 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 185446#L839-21 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 185442#L839-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 185439#L386-21 assume !(1 == ~t4_pc~0); 185435#L386-23 is_transmit4_triggered_~__retres1~4 := 0; 185432#L397-7 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 185429#L398-7 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 185426#L847-21 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 185422#L847-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 185419#L405-21 assume !(1 == ~t5_pc~0); 185416#L405-23 is_transmit5_triggered_~__retres1~5 := 0; 185413#L416-7 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 185410#L417-7 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 185407#L855-21 assume !(0 != activate_threads_~tmp___4~0); 185404#L855-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 185400#L424-21 assume !(1 == ~t6_pc~0); 185396#L424-23 is_transmit6_triggered_~__retres1~6 := 0; 185393#L435-7 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 185388#L436-7 activate_threads_#t~ret14 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 185384#L863-21 assume !(0 != activate_threads_~tmp___5~0); 185381#L863-23 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 185378#L733-3 assume !(1 == ~M_E~0); 185376#L733-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 185374#L738-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 185372#L743-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 185370#L748-3 assume !(1 == ~T4_E~0); 185367#L753-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 185364#L758-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 185361#L763-3 assume !(1 == ~E_1~0); 185358#L768-3 assume !(1 == ~E_2~0); 185355#L773-3 assume 1 == ~E_3~0;~E_3~0 := 2; 185352#L778-3 assume 1 == ~E_4~0;~E_4~0 := 2; 185349#L783-3 assume 1 == ~E_5~0;~E_5~0 := 2; 185346#L788-3 assume !(1 == ~E_6~0); 185342#L793-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 185333#L494-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 185323#L531-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 185319#L532-1 start_simulation_#t~ret16 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret16;havoc start_simulation_#t~ret16; 185314#L1033 assume !(0 == start_simulation_~tmp~3); 185310#L1033-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret15, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 185298#L494-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 185297#L531-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 185295#L532-2 stop_simulation_#t~ret15 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret15;havoc stop_simulation_#t~ret15; 185293#L988 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 185291#L995 stop_simulation_#res := stop_simulation_~__retres2~0; 185289#L996 start_simulation_#t~ret17 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret17;havoc start_simulation_#t~ret17; 185285#L1046 assume !(0 != start_simulation_~tmp___0~1); 181003#L1014-3 [2018-11-18 15:29:30,516 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:30,516 INFO L82 PathProgramCache]: Analyzing trace with hash -2100463851, now seen corresponding path program 5 times [2018-11-18 15:29:30,516 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:30,516 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:30,517 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:30,517 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:30,517 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:30,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:29:30,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:29:30,540 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:30,540 INFO L82 PathProgramCache]: Analyzing trace with hash 1664842059, now seen corresponding path program 1 times [2018-11-18 15:29:30,540 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:30,540 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:30,541 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:30,541 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:29:30,541 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:30,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:30,578 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:29:30,578 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:29:30,578 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:29:30,579 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 15:29:30,579 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:29:30,579 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:29:30,579 INFO L87 Difference]: Start difference. First operand 7013 states and 9415 transitions. cyclomatic complexity: 2418 Second operand 3 states. [2018-11-18 15:29:30,644 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:29:30,644 INFO L93 Difference]: Finished difference Result 11128 states and 14722 transitions. [2018-11-18 15:29:30,646 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:29:30,646 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11128 states and 14722 transitions. [2018-11-18 15:29:30,679 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 10928 [2018-11-18 15:29:30,706 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11128 states to 11128 states and 14722 transitions. [2018-11-18 15:29:30,706 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11128 [2018-11-18 15:29:30,711 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11128 [2018-11-18 15:29:30,712 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11128 states and 14722 transitions. [2018-11-18 15:29:30,719 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:29:30,719 INFO L705 BuchiCegarLoop]: Abstraction has 11128 states and 14722 transitions. [2018-11-18 15:29:30,725 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11128 states and 14722 transitions. [2018-11-18 15:29:30,787 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11128 to 11128. [2018-11-18 15:29:30,787 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 11128 states. [2018-11-18 15:29:30,800 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11128 states to 11128 states and 14722 transitions. [2018-11-18 15:29:30,800 INFO L728 BuchiCegarLoop]: Abstraction has 11128 states and 14722 transitions. [2018-11-18 15:29:30,800 INFO L608 BuchiCegarLoop]: Abstraction has 11128 states and 14722 transitions. [2018-11-18 15:29:30,800 INFO L442 BuchiCegarLoop]: ======== Iteration 22============ [2018-11-18 15:29:30,801 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11128 states and 14722 transitions. [2018-11-18 15:29:30,825 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 10928 [2018-11-18 15:29:30,825 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:29:30,825 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:29:30,826 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:30,826 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:30,826 INFO L794 eck$LassoCheckResult]: Stem: 199113#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 198983#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 198984#L977 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 198612#L444 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 198613#L451 assume 1 == ~m_i~0;~m_st~0 := 0; 199126#L451-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 198726#L456-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 198727#L461-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 198617#L466-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 198618#L471-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 198908#L476-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 198909#L481-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 199129#L660 assume !(0 == ~M_E~0); 199130#L660-2 assume !(0 == ~T1_E~0); 198517#L665-1 assume !(0 == ~T2_E~0); 198518#L670-1 assume !(0 == ~T3_E~0); 198626#L675-1 assume !(0 == ~T4_E~0); 198627#L680-1 assume !(0 == ~T5_E~0); 198922#L685-1 assume !(0 == ~T6_E~0); 198923#L690-1 assume !(0 == ~E_1~0); 198788#L695-1 assume !(0 == ~E_2~0); 198789#L700-1 assume !(0 == ~E_3~0); 199090#L705-1 assume !(0 == ~E_4~0); 198694#L710-1 assume !(0 == ~E_5~0); 198695#L715-1 assume !(0 == ~E_6~0); 198555#L720-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 198556#L310 assume !(1 == ~m_pc~0); 198751#L310-2 is_master_triggered_~__retres1~0 := 0; 198749#L321 is_master_triggered_#res := is_master_triggered_~__retres1~0; 198750#L322 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 198887#L815 assume !(0 != activate_threads_~tmp~1); 199086#L815-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 198987#L329 assume !(1 == ~t1_pc~0); 198988#L329-2 is_transmit1_triggered_~__retres1~1 := 0; 198985#L340 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 198986#L341 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 199128#L823 assume !(0 != activate_threads_~tmp___0~0); 199211#L823-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 199183#L348 assume !(1 == ~t2_pc~0); 199184#L348-2 is_transmit2_triggered_~__retres1~2 := 0; 199180#L359 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 199181#L360 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 198703#L831 assume !(0 != activate_threads_~tmp___1~0); 198689#L831-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 198622#L367 assume !(1 == ~t3_pc~0); 198588#L367-2 is_transmit3_triggered_~__retres1~3 := 0; 198589#L378 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 198621#L379 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 198731#L839 assume !(0 != activate_threads_~tmp___2~0); 198935#L839-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 198841#L386 assume !(1 == ~t4_pc~0); 198842#L386-2 is_transmit4_triggered_~__retres1~4 := 0; 198840#L397 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 198737#L398 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 198738#L847 assume !(0 != activate_threads_~tmp___3~0); 199135#L847-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 199136#L405 assume !(1 == ~t5_pc~0); 199072#L405-2 is_transmit5_triggered_~__retres1~5 := 0; 199073#L416 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 199030#L417 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 199031#L855 assume !(0 != activate_threads_~tmp___4~0); 199142#L855-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 198670#L424 assume !(1 == ~t6_pc~0); 198671#L424-2 is_transmit6_triggered_~__retres1~6 := 0; 198668#L435 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 198669#L436 activate_threads_#t~ret14 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 198574#L863 assume !(0 != activate_threads_~tmp___5~0); 198545#L863-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 198546#L733 assume !(1 == ~M_E~0); 199196#L733-2 assume !(1 == ~T1_E~0); 199088#L738-1 assume !(1 == ~T2_E~0); 198692#L743-1 assume !(1 == ~T3_E~0); 198693#L748-1 assume !(1 == ~T4_E~0); 198550#L753-1 assume !(1 == ~T5_E~0); 198551#L758-1 assume !(1 == ~T6_E~0); 198638#L763-1 assume !(1 == ~E_1~0); 198639#L768-1 assume !(1 == ~E_2~0); 198914#L773-1 assume !(1 == ~E_3~0); 198915#L778-1 assume !(1 == ~E_4~0); 198782#L783-1 assume !(1 == ~E_5~0); 198783#L788-1 assume !(1 == ~E_6~0); 199084#L793-1 assume { :end_inline_reset_delta_events } true; 199085#L1014-3 assume true; 200442#L1014-1 assume !false; 200433#L1015 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 200428#L635 [2018-11-18 15:29:30,826 INFO L796 eck$LassoCheckResult]: Loop: 200428#L635 assume true; 200423#L541-1 assume !false; 200418#L542 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 200411#L494 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 200406#L531 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 200403#L532 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 200089#L546 assume 0 != eval_~tmp~0; 200079#L546-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 200071#L554 assume !(0 != eval_~tmp_ndt_1~0); 199601#L551 assume !(0 == ~t1_st~0); 199599#L565 assume !(0 == ~t2_st~0); 199595#L579 assume !(0 == ~t3_st~0); 199590#L593 assume !(0 == ~t4_st~0); 199589#L607 assume !(0 == ~t5_st~0); 200434#L621 assume !(0 == ~t6_st~0); 200428#L635 [2018-11-18 15:29:30,826 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:30,826 INFO L82 PathProgramCache]: Analyzing trace with hash -1539676155, now seen corresponding path program 1 times [2018-11-18 15:29:30,827 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:30,827 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:30,827 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:30,827 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:30,827 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:30,832 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:29:30,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:29:30,852 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:30,852 INFO L82 PathProgramCache]: Analyzing trace with hash -154661723, now seen corresponding path program 1 times [2018-11-18 15:29:30,852 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:30,852 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:30,853 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:30,853 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:30,853 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:30,854 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:29:30,856 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:29:30,857 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:30,857 INFO L82 PathProgramCache]: Analyzing trace with hash -541582303, now seen corresponding path program 1 times [2018-11-18 15:29:30,857 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:30,857 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:30,858 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:30,858 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:30,858 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:30,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:30,904 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:29:30,904 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:29:30,904 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:29:30,997 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:29:30,997 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:29:30,997 INFO L87 Difference]: Start difference. First operand 11128 states and 14722 transitions. cyclomatic complexity: 3618 Second operand 3 states. [2018-11-18 15:29:31,164 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:29:31,165 INFO L93 Difference]: Finished difference Result 20946 states and 27453 transitions. [2018-11-18 15:29:31,167 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:29:31,167 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 20946 states and 27453 transitions. [2018-11-18 15:29:31,217 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 20552 [2018-11-18 15:29:31,259 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 20946 states to 20946 states and 27453 transitions. [2018-11-18 15:29:31,259 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20946 [2018-11-18 15:29:31,272 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20946 [2018-11-18 15:29:31,272 INFO L73 IsDeterministic]: Start isDeterministic. Operand 20946 states and 27453 transitions. [2018-11-18 15:29:31,284 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:29:31,284 INFO L705 BuchiCegarLoop]: Abstraction has 20946 states and 27453 transitions. [2018-11-18 15:29:31,294 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20946 states and 27453 transitions. [2018-11-18 15:29:31,413 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20946 to 19714. [2018-11-18 15:29:31,413 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19714 states. [2018-11-18 15:29:31,437 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19714 states to 19714 states and 25917 transitions. [2018-11-18 15:29:31,437 INFO L728 BuchiCegarLoop]: Abstraction has 19714 states and 25917 transitions. [2018-11-18 15:29:31,438 INFO L608 BuchiCegarLoop]: Abstraction has 19714 states and 25917 transitions. [2018-11-18 15:29:31,438 INFO L442 BuchiCegarLoop]: ======== Iteration 23============ [2018-11-18 15:29:31,438 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19714 states and 25917 transitions. [2018-11-18 15:29:31,488 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 19320 [2018-11-18 15:29:31,488 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:29:31,488 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:29:31,489 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:31,489 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:31,489 INFO L794 eck$LassoCheckResult]: Stem: 231192#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 231062#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 231063#L977 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 230693#L444 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 230694#L451 assume 1 == ~m_i~0;~m_st~0 := 0; 231207#L451-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 230806#L456-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 230807#L461-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 230698#L466-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 230699#L471-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 230985#L476-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 230986#L481-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 231211#L660 assume !(0 == ~M_E~0); 231212#L660-2 assume !(0 == ~T1_E~0); 230599#L665-1 assume !(0 == ~T2_E~0); 230600#L670-1 assume !(0 == ~T3_E~0); 230707#L675-1 assume !(0 == ~T4_E~0); 230708#L680-1 assume !(0 == ~T5_E~0); 230998#L685-1 assume !(0 == ~T6_E~0); 230999#L690-1 assume !(0 == ~E_1~0); 230866#L695-1 assume !(0 == ~E_2~0); 230867#L700-1 assume !(0 == ~E_3~0); 231173#L705-1 assume !(0 == ~E_4~0); 230775#L710-1 assume !(0 == ~E_5~0); 230776#L715-1 assume !(0 == ~E_6~0); 230637#L720-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 230638#L310 assume !(1 == ~m_pc~0); 230829#L310-2 is_master_triggered_~__retres1~0 := 0; 230827#L321 is_master_triggered_#res := is_master_triggered_~__retres1~0; 230828#L322 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 230965#L815 assume !(0 != activate_threads_~tmp~1); 231168#L815-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 231066#L329 assume !(1 == ~t1_pc~0); 231067#L329-2 is_transmit1_triggered_~__retres1~1 := 0; 231064#L340 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 231065#L341 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 231210#L823 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 231311#L823-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 238330#L348 assume !(1 == ~t2_pc~0); 238329#L348-2 is_transmit2_triggered_~__retres1~2 := 0; 238328#L359 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 238327#L360 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 238326#L831 assume !(0 != activate_threads_~tmp___1~0); 238325#L831-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 238324#L367 assume !(1 == ~t3_pc~0); 238322#L367-2 is_transmit3_triggered_~__retres1~3 := 0; 238321#L378 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 238320#L379 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 238319#L839 assume !(0 != activate_threads_~tmp___2~0); 238318#L839-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 238317#L386 assume !(1 == ~t4_pc~0); 238316#L386-2 is_transmit4_triggered_~__retres1~4 := 0; 238315#L397 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 238314#L398 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 238313#L847 assume !(0 != activate_threads_~tmp___3~0); 238312#L847-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 231304#L405 assume !(1 == ~t5_pc~0); 231149#L405-2 is_transmit5_triggered_~__retres1~5 := 0; 231150#L416 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 238299#L417 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 238297#L855 assume !(0 != activate_threads_~tmp___4~0); 231229#L855-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 230750#L424 assume !(1 == ~t6_pc~0); 230751#L424-2 is_transmit6_triggered_~__retres1~6 := 0; 230748#L435 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 230749#L436 activate_threads_#t~ret14 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 230656#L863 assume !(0 != activate_threads_~tmp___5~0); 230657#L863-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 238277#L733 assume !(1 == ~M_E~0); 238274#L733-2 assume !(1 == ~T1_E~0); 238273#L738-1 assume !(1 == ~T2_E~0); 230773#L743-1 assume !(1 == ~T3_E~0); 230774#L748-1 assume !(1 == ~T4_E~0); 230632#L753-1 assume !(1 == ~T5_E~0); 230633#L758-1 assume !(1 == ~T6_E~0); 230719#L763-1 assume !(1 == ~E_1~0); 230720#L768-1 assume !(1 == ~E_2~0); 230988#L773-1 assume !(1 == ~E_3~0); 230989#L778-1 assume !(1 == ~E_4~0); 230860#L783-1 assume !(1 == ~E_5~0); 230861#L788-1 assume !(1 == ~E_6~0); 231166#L793-1 assume { :end_inline_reset_delta_events } true; 231167#L1014-3 assume true; 239691#L1014-1 assume !false; 239588#L1015 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 239585#L635 [2018-11-18 15:29:31,490 INFO L796 eck$LassoCheckResult]: Loop: 239585#L635 assume true; 239583#L541-1 assume !false; 239581#L542 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 239578#L494 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 239576#L531 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 239575#L532 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 239573#L546 assume 0 != eval_~tmp~0; 239570#L546-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 239567#L554 assume !(0 != eval_~tmp_ndt_1~0); 239568#L551 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 238131#L568 assume !(0 != eval_~tmp_ndt_2~0); 239624#L565 assume !(0 == ~t2_st~0); 239620#L579 assume !(0 == ~t3_st~0); 239615#L593 assume !(0 == ~t4_st~0); 239611#L607 assume !(0 == ~t5_st~0); 239589#L621 assume !(0 == ~t6_st~0); 239585#L635 [2018-11-18 15:29:31,490 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:31,490 INFO L82 PathProgramCache]: Analyzing trace with hash 1628307393, now seen corresponding path program 1 times [2018-11-18 15:29:31,490 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:31,490 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:31,491 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:31,491 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:31,491 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:31,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:31,516 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:29:31,516 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:29:31,516 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:29:31,517 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 15:29:31,517 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:31,517 INFO L82 PathProgramCache]: Analyzing trace with hash -354681309, now seen corresponding path program 1 times [2018-11-18 15:29:31,517 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:31,517 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:31,518 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:31,518 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:31,518 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:31,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:29:31,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:29:31,635 WARN L180 SmtUtils]: Spent 110.00 ms on a formula simplification. DAG size of input: 38 DAG size of output: 36 [2018-11-18 15:29:31,666 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:29:31,666 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:29:31,667 INFO L87 Difference]: Start difference. First operand 19714 states and 25917 transitions. cyclomatic complexity: 6227 Second operand 3 states. [2018-11-18 15:29:31,709 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:29:31,709 INFO L93 Difference]: Finished difference Result 19632 states and 25809 transitions. [2018-11-18 15:29:31,710 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:29:31,710 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19632 states and 25809 transitions. [2018-11-18 15:29:31,810 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 19320 [2018-11-18 15:29:31,831 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19632 states to 19632 states and 25809 transitions. [2018-11-18 15:29:31,831 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19632 [2018-11-18 15:29:31,838 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19632 [2018-11-18 15:29:31,839 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19632 states and 25809 transitions. [2018-11-18 15:29:31,849 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:29:31,849 INFO L705 BuchiCegarLoop]: Abstraction has 19632 states and 25809 transitions. [2018-11-18 15:29:31,858 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19632 states and 25809 transitions. [2018-11-18 15:29:31,965 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19632 to 19632. [2018-11-18 15:29:31,965 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19632 states. [2018-11-18 15:29:31,980 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19632 states to 19632 states and 25809 transitions. [2018-11-18 15:29:31,980 INFO L728 BuchiCegarLoop]: Abstraction has 19632 states and 25809 transitions. [2018-11-18 15:29:31,980 INFO L608 BuchiCegarLoop]: Abstraction has 19632 states and 25809 transitions. [2018-11-18 15:29:31,980 INFO L442 BuchiCegarLoop]: ======== Iteration 24============ [2018-11-18 15:29:31,980 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 19632 states and 25809 transitions. [2018-11-18 15:29:32,012 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 19320 [2018-11-18 15:29:32,012 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:29:32,012 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:29:32,012 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:32,012 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:32,013 INFO L794 eck$LassoCheckResult]: Stem: 270540#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 270407#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 270408#L977 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 270047#L444 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 270048#L451 assume 1 == ~m_i~0;~m_st~0 := 0; 270553#L451-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 270161#L456-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 270162#L461-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 270049#L466-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 270050#L471-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 270337#L476-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 270338#L481-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 270557#L660 assume !(0 == ~M_E~0); 270558#L660-2 assume !(0 == ~T1_E~0); 269953#L665-1 assume !(0 == ~T2_E~0); 269954#L670-1 assume !(0 == ~T3_E~0); 270058#L675-1 assume !(0 == ~T4_E~0); 270059#L680-1 assume !(0 == ~T5_E~0); 270350#L685-1 assume !(0 == ~T6_E~0); 270351#L690-1 assume !(0 == ~E_1~0); 270222#L695-1 assume !(0 == ~E_2~0); 270223#L700-1 assume !(0 == ~E_3~0); 270519#L705-1 assume !(0 == ~E_4~0); 270128#L710-1 assume !(0 == ~E_5~0); 270129#L715-1 assume !(0 == ~E_6~0); 269989#L720-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 269990#L310 assume !(1 == ~m_pc~0); 270184#L310-2 is_master_triggered_~__retres1~0 := 0; 270182#L321 is_master_triggered_#res := is_master_triggered_~__retres1~0; 270183#L322 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 270317#L815 assume !(0 != activate_threads_~tmp~1); 270515#L815-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 270411#L329 assume !(1 == ~t1_pc~0); 270412#L329-2 is_transmit1_triggered_~__retres1~1 := 0; 270409#L340 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 270410#L341 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 270556#L823 assume !(0 != activate_threads_~tmp___0~0); 270651#L823-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 270615#L348 assume !(1 == ~t2_pc~0); 270616#L348-2 is_transmit2_triggered_~__retres1~2 := 0; 270612#L359 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 270613#L360 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 270137#L831 assume !(0 != activate_threads_~tmp___1~0); 270123#L831-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 270054#L367 assume !(1 == ~t3_pc~0); 270022#L367-2 is_transmit3_triggered_~__retres1~3 := 0; 270023#L378 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 270053#L379 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 270166#L839 assume !(0 != activate_threads_~tmp___2~0); 270363#L839-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 270270#L386 assume !(1 == ~t4_pc~0); 270271#L386-2 is_transmit4_triggered_~__retres1~4 := 0; 270269#L397 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 270170#L398 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 270171#L847 assume !(0 != activate_threads_~tmp___3~0); 270564#L847-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 270565#L405 assume !(1 == ~t5_pc~0); 270501#L405-2 is_transmit5_triggered_~__retres1~5 := 0; 270502#L416 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 270455#L417 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 270456#L855 assume !(0 != activate_threads_~tmp___4~0); 270572#L855-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 270102#L424 assume !(1 == ~t6_pc~0); 270103#L424-2 is_transmit6_triggered_~__retres1~6 := 0; 270100#L435 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 270101#L436 activate_threads_#t~ret14 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 270009#L863 assume !(0 != activate_threads_~tmp___5~0); 269979#L863-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 269980#L733 assume !(1 == ~M_E~0); 270633#L733-2 assume !(1 == ~T1_E~0); 270517#L738-1 assume !(1 == ~T2_E~0); 270126#L743-1 assume !(1 == ~T3_E~0); 270127#L748-1 assume !(1 == ~T4_E~0); 269984#L753-1 assume !(1 == ~T5_E~0); 269985#L758-1 assume !(1 == ~T6_E~0); 270070#L763-1 assume !(1 == ~E_1~0); 270071#L768-1 assume !(1 == ~E_2~0); 270342#L773-1 assume !(1 == ~E_3~0); 270343#L778-1 assume !(1 == ~E_4~0); 270215#L783-1 assume !(1 == ~E_5~0); 270216#L788-1 assume !(1 == ~E_6~0); 270513#L793-1 assume { :end_inline_reset_delta_events } true; 270514#L1014-3 assume true; 270973#L1014-1 assume !false; 270967#L1015 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 270968#L635 [2018-11-18 15:29:32,013 INFO L796 eck$LassoCheckResult]: Loop: 270968#L635 assume true; 270940#L541-1 assume !false; 270941#L542 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 270923#L494 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 270925#L531 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 270905#L532 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 270906#L546 assume 0 != eval_~tmp~0; 270889#L546-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 270891#L554 assume !(0 != eval_~tmp_ndt_1~0); 272004#L551 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 272056#L568 assume !(0 != eval_~tmp_ndt_2~0); 272082#L565 assume !(0 == ~t2_st~0); 272215#L579 assume !(0 == ~t3_st~0); 272211#L593 assume !(0 == ~t4_st~0); 272208#L607 assume !(0 == ~t5_st~0); 270969#L621 assume !(0 == ~t6_st~0); 270968#L635 [2018-11-18 15:29:32,013 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:32,013 INFO L82 PathProgramCache]: Analyzing trace with hash -1539676155, now seen corresponding path program 2 times [2018-11-18 15:29:32,013 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:32,013 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:32,014 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:32,014 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:32,014 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:32,019 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:29:32,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:29:32,039 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:32,039 INFO L82 PathProgramCache]: Analyzing trace with hash -354681309, now seen corresponding path program 2 times [2018-11-18 15:29:32,040 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:32,040 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:32,040 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:32,040 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:29:32,040 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:32,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:29:32,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:29:32,044 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:32,044 INFO L82 PathProgramCache]: Analyzing trace with hash 535682599, now seen corresponding path program 1 times [2018-11-18 15:29:32,044 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:32,045 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:32,045 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:32,045 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:29:32,045 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:32,050 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:32,099 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:29:32,099 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:29:32,099 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:29:32,186 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:29:32,186 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:29:32,186 INFO L87 Difference]: Start difference. First operand 19632 states and 25809 transitions. cyclomatic complexity: 6201 Second operand 3 states. [2018-11-18 15:29:32,257 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:29:32,257 INFO L93 Difference]: Finished difference Result 24724 states and 32241 transitions. [2018-11-18 15:29:32,257 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:29:32,257 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 24724 states and 32241 transitions. [2018-11-18 15:29:32,312 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 23932 [2018-11-18 15:29:32,349 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 24724 states to 24724 states and 32241 transitions. [2018-11-18 15:29:32,350 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 24724 [2018-11-18 15:29:32,360 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 24724 [2018-11-18 15:29:32,361 INFO L73 IsDeterministic]: Start isDeterministic. Operand 24724 states and 32241 transitions. [2018-11-18 15:29:32,369 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:29:32,370 INFO L705 BuchiCegarLoop]: Abstraction has 24724 states and 32241 transitions. [2018-11-18 15:29:32,379 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24724 states and 32241 transitions. [2018-11-18 15:29:32,471 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24724 to 23700. [2018-11-18 15:29:32,472 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 23700 states. [2018-11-18 15:29:32,491 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23700 states to 23700 states and 30961 transitions. [2018-11-18 15:29:32,492 INFO L728 BuchiCegarLoop]: Abstraction has 23700 states and 30961 transitions. [2018-11-18 15:29:32,492 INFO L608 BuchiCegarLoop]: Abstraction has 23700 states and 30961 transitions. [2018-11-18 15:29:32,492 INFO L442 BuchiCegarLoop]: ======== Iteration 25============ [2018-11-18 15:29:32,492 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23700 states and 30961 transitions. [2018-11-18 15:29:32,532 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 22908 [2018-11-18 15:29:32,532 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:29:32,532 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:29:32,533 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:32,533 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:32,533 INFO L794 eck$LassoCheckResult]: Stem: 314907#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 314781#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 314782#L977 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 314408#L444 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 314409#L451 assume 1 == ~m_i~0;~m_st~0 := 0; 314922#L451-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 314524#L456-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 314525#L461-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 314413#L466-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 314414#L471-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 314708#L476-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 314709#L481-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 314926#L660 assume !(0 == ~M_E~0); 314927#L660-2 assume !(0 == ~T1_E~0); 314315#L665-1 assume !(0 == ~T2_E~0); 314316#L670-1 assume !(0 == ~T3_E~0); 314422#L675-1 assume !(0 == ~T4_E~0); 314423#L680-1 assume !(0 == ~T5_E~0); 314722#L685-1 assume !(0 == ~T6_E~0); 314723#L690-1 assume !(0 == ~E_1~0); 314588#L695-1 assume !(0 == ~E_2~0); 314589#L700-1 assume !(0 == ~E_3~0); 314888#L705-1 assume !(0 == ~E_4~0); 314491#L710-1 assume !(0 == ~E_5~0); 314492#L715-1 assume !(0 == ~E_6~0); 314353#L720-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 314354#L310 assume !(1 == ~m_pc~0); 314549#L310-2 is_master_triggered_~__retres1~0 := 0; 314544#L321 is_master_triggered_#res := is_master_triggered_~__retres1~0; 314545#L322 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 314686#L815 assume !(0 != activate_threads_~tmp~1); 314884#L815-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 314788#L329 assume !(1 == ~t1_pc~0); 314789#L329-2 is_transmit1_triggered_~__retres1~1 := 0; 314783#L340 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 314784#L341 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 314925#L823 assume !(0 != activate_threads_~tmp___0~0); 315021#L823-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 314984#L348 assume !(1 == ~t2_pc~0); 314985#L348-2 is_transmit2_triggered_~__retres1~2 := 0; 314982#L359 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 314983#L360 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 314500#L831 assume !(0 != activate_threads_~tmp___1~0); 314486#L831-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 314418#L367 assume !(1 == ~t3_pc~0); 314385#L367-2 is_transmit3_triggered_~__retres1~3 := 0; 314386#L378 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 314417#L379 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 314528#L839 assume !(0 != activate_threads_~tmp___2~0); 314734#L839-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 314637#L386 assume !(1 == ~t4_pc~0); 314638#L386-2 is_transmit4_triggered_~__retres1~4 := 0; 314636#L397 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 314535#L398 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 314536#L847 assume !(0 != activate_threads_~tmp___3~0); 314934#L847-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 314935#L405 assume !(1 == ~t5_pc~0); 314870#L405-2 is_transmit5_triggered_~__retres1~5 := 0; 314871#L416 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 314831#L417 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 314832#L855 assume !(0 != activate_threads_~tmp___4~0); 314942#L855-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 314465#L424 assume !(1 == ~t6_pc~0); 314466#L424-2 is_transmit6_triggered_~__retres1~6 := 0; 314461#L435 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 314462#L436 activate_threads_#t~ret14 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 314372#L863 assume !(0 != activate_threads_~tmp___5~0); 314340#L863-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 314341#L733 assume !(1 == ~M_E~0); 315002#L733-2 assume !(1 == ~T1_E~0); 314886#L738-1 assume !(1 == ~T2_E~0); 314489#L743-1 assume !(1 == ~T3_E~0); 314490#L748-1 assume !(1 == ~T4_E~0); 314348#L753-1 assume !(1 == ~T5_E~0); 314349#L758-1 assume !(1 == ~T6_E~0); 314433#L763-1 assume !(1 == ~E_1~0); 314434#L768-1 assume !(1 == ~E_2~0); 314712#L773-1 assume !(1 == ~E_3~0); 314713#L778-1 assume !(1 == ~E_4~0); 314579#L783-1 assume !(1 == ~E_5~0); 314580#L788-1 assume !(1 == ~E_6~0); 314882#L793-1 assume { :end_inline_reset_delta_events } true; 314883#L1014-3 assume true; 324897#L1014-1 assume !false; 324873#L1015 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 324866#L635 [2018-11-18 15:29:32,534 INFO L796 eck$LassoCheckResult]: Loop: 324866#L635 assume true; 324859#L541-1 assume !false; 324853#L542 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 324846#L494 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 324841#L531 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 324836#L532 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 324710#L546 assume 0 != eval_~tmp~0; 324687#L546-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 324689#L554 assume !(0 != eval_~tmp_ndt_1~0); 324476#L551 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 321937#L568 assume !(0 != eval_~tmp_ndt_2~0); 321939#L565 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 321930#L582 assume !(0 != eval_~tmp_ndt_3~0); 321932#L579 assume !(0 == ~t3_st~0); 324903#L593 assume !(0 == ~t4_st~0); 324900#L607 assume !(0 == ~t5_st~0); 324874#L621 assume !(0 == ~t6_st~0); 324866#L635 [2018-11-18 15:29:32,534 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:32,534 INFO L82 PathProgramCache]: Analyzing trace with hash -1539676155, now seen corresponding path program 3 times [2018-11-18 15:29:32,534 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:32,534 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:32,535 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:32,535 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:32,535 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:32,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:29:32,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:29:32,566 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:32,566 INFO L82 PathProgramCache]: Analyzing trace with hash 231893060, now seen corresponding path program 1 times [2018-11-18 15:29:32,566 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:32,567 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:32,567 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:32,567 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:29:32,567 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:32,569 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:29:32,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:29:32,572 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:32,572 INFO L82 PathProgramCache]: Analyzing trace with hash 2063370432, now seen corresponding path program 1 times [2018-11-18 15:29:32,572 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:32,572 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:32,572 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:32,573 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:32,573 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:32,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:32,609 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:29:32,609 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:29:32,609 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:29:32,687 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:29:32,687 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:29:32,687 INFO L87 Difference]: Start difference. First operand 23700 states and 30961 transitions. cyclomatic complexity: 7285 Second operand 3 states. [2018-11-18 15:29:32,771 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:29:32,771 INFO L93 Difference]: Finished difference Result 43908 states and 57105 transitions. [2018-11-18 15:29:32,773 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:29:32,773 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43908 states and 57105 transitions. [2018-11-18 15:29:32,869 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 42412 [2018-11-18 15:29:32,934 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43908 states to 43908 states and 57105 transitions. [2018-11-18 15:29:32,934 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 43908 [2018-11-18 15:29:32,952 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 43908 [2018-11-18 15:29:32,952 INFO L73 IsDeterministic]: Start isDeterministic. Operand 43908 states and 57105 transitions. [2018-11-18 15:29:32,969 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:29:32,969 INFO L705 BuchiCegarLoop]: Abstraction has 43908 states and 57105 transitions. [2018-11-18 15:29:32,986 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43908 states and 57105 transitions. [2018-11-18 15:29:33,270 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43908 to 41708. [2018-11-18 15:29:33,270 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 41708 states. [2018-11-18 15:29:33,307 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41708 states to 41708 states and 54465 transitions. [2018-11-18 15:29:33,307 INFO L728 BuchiCegarLoop]: Abstraction has 41708 states and 54465 transitions. [2018-11-18 15:29:33,307 INFO L608 BuchiCegarLoop]: Abstraction has 41708 states and 54465 transitions. [2018-11-18 15:29:33,307 INFO L442 BuchiCegarLoop]: ======== Iteration 26============ [2018-11-18 15:29:33,307 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 41708 states and 54465 transitions. [2018-11-18 15:29:33,383 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 40212 [2018-11-18 15:29:33,383 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:29:33,383 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:29:33,384 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:33,384 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:33,384 INFO L794 eck$LassoCheckResult]: Stem: 382538#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 382401#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 382402#L977 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 382025#L444 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 382026#L451 assume 1 == ~m_i~0;~m_st~0 := 0; 382553#L451-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 382143#L456-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 382144#L461-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 382030#L466-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 382031#L471-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 382330#L476-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 382331#L481-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 382559#L660 assume !(0 == ~M_E~0); 382560#L660-2 assume !(0 == ~T1_E~0); 381931#L665-1 assume !(0 == ~T2_E~0); 381932#L670-1 assume !(0 == ~T3_E~0); 382039#L675-1 assume !(0 == ~T4_E~0); 382040#L680-1 assume !(0 == ~T5_E~0); 382343#L685-1 assume !(0 == ~T6_E~0); 382344#L690-1 assume !(0 == ~E_1~0); 382204#L695-1 assume !(0 == ~E_2~0); 382205#L700-1 assume !(0 == ~E_3~0); 382517#L705-1 assume !(0 == ~E_4~0); 382110#L710-1 assume !(0 == ~E_5~0); 382111#L715-1 assume !(0 == ~E_6~0); 381970#L720-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 381971#L310 assume !(1 == ~m_pc~0); 382166#L310-2 is_master_triggered_~__retres1~0 := 0; 382161#L321 is_master_triggered_#res := is_master_triggered_~__retres1~0; 382162#L322 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 382304#L815 assume !(0 != activate_threads_~tmp~1); 382511#L815-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 382408#L329 assume !(1 == ~t1_pc~0); 382409#L329-2 is_transmit1_triggered_~__retres1~1 := 0; 382403#L340 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 382404#L341 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 382558#L823 assume !(0 != activate_threads_~tmp___0~0); 382675#L823-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 382629#L348 assume !(1 == ~t2_pc~0); 382630#L348-2 is_transmit2_triggered_~__retres1~2 := 0; 382627#L359 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 382628#L360 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 382122#L831 assume !(0 != activate_threads_~tmp___1~0); 382105#L831-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 382035#L367 assume !(1 == ~t3_pc~0); 382002#L367-2 is_transmit3_triggered_~__retres1~3 := 0; 382003#L378 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 382034#L379 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 382146#L839 assume !(0 != activate_threads_~tmp___2~0); 382355#L839-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 382250#L386 assume !(1 == ~t4_pc~0); 382251#L386-2 is_transmit4_triggered_~__retres1~4 := 0; 382249#L397 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 382152#L398 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 382153#L847 assume !(0 != activate_threads_~tmp___3~0); 382570#L847-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 382571#L405 assume !(1 == ~t5_pc~0); 382494#L405-2 is_transmit5_triggered_~__retres1~5 := 0; 382495#L416 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 382452#L417 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 382453#L855 assume !(0 != activate_threads_~tmp___4~0); 382582#L855-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 382082#L424 assume !(1 == ~t6_pc~0); 382083#L424-2 is_transmit6_triggered_~__retres1~6 := 0; 382078#L435 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 382079#L436 activate_threads_#t~ret14 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 381989#L863 assume !(0 != activate_threads_~tmp___5~0); 381956#L863-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 381957#L733 assume !(1 == ~M_E~0); 382651#L733-2 assume !(1 == ~T1_E~0); 382514#L738-1 assume !(1 == ~T2_E~0); 382108#L743-1 assume !(1 == ~T3_E~0); 382109#L748-1 assume !(1 == ~T4_E~0); 381964#L753-1 assume !(1 == ~T5_E~0); 381965#L758-1 assume !(1 == ~T6_E~0); 382050#L763-1 assume !(1 == ~E_1~0); 382051#L768-1 assume !(1 == ~E_2~0); 382333#L773-1 assume !(1 == ~E_3~0); 382334#L778-1 assume !(1 == ~E_4~0); 382195#L783-1 assume !(1 == ~E_5~0); 382196#L788-1 assume !(1 == ~E_6~0); 382509#L793-1 assume { :end_inline_reset_delta_events } true; 382510#L1014-3 assume true; 391060#L1014-1 assume !false; 391029#L1015 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 391027#L635 [2018-11-18 15:29:33,384 INFO L796 eck$LassoCheckResult]: Loop: 391027#L635 assume true; 391024#L541-1 assume !false; 391022#L542 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 391019#L494 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 391017#L531 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 391015#L532 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 391014#L546 assume 0 != eval_~tmp~0; 391011#L546-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 391008#L554 assume !(0 != eval_~tmp_ndt_1~0); 391006#L551 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 391003#L568 assume !(0 != eval_~tmp_ndt_2~0); 391001#L565 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 390998#L582 assume !(0 != eval_~tmp_ndt_3~0); 390996#L579 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 389227#L596 assume !(0 != eval_~tmp_ndt_4~0); 390991#L593 assume !(0 == ~t4_st~0); 390987#L607 assume !(0 == ~t5_st~0); 390983#L621 assume !(0 == ~t6_st~0); 391027#L635 [2018-11-18 15:29:33,385 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:33,385 INFO L82 PathProgramCache]: Analyzing trace with hash -1539676155, now seen corresponding path program 4 times [2018-11-18 15:29:33,385 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:33,385 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:33,386 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:33,386 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:33,386 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:33,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:29:33,395 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:29:33,409 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:33,409 INFO L82 PathProgramCache]: Analyzing trace with hash -1593270652, now seen corresponding path program 1 times [2018-11-18 15:29:33,409 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:33,409 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:33,410 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:33,410 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:29:33,410 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:33,411 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:29:33,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:29:33,415 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:33,415 INFO L82 PathProgramCache]: Analyzing trace with hash -652046968, now seen corresponding path program 1 times [2018-11-18 15:29:33,415 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:33,415 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:33,415 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:33,416 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:33,416 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:33,420 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:33,463 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:29:33,463 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:29:33,464 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:29:33,585 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:29:33,585 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:29:33,586 INFO L87 Difference]: Start difference. First operand 41708 states and 54465 transitions. cyclomatic complexity: 12781 Second operand 3 states. [2018-11-18 15:29:33,751 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:29:33,751 INFO L93 Difference]: Finished difference Result 53622 states and 69697 transitions. [2018-11-18 15:29:33,753 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:29:33,754 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 53622 states and 69697 transitions. [2018-11-18 15:29:33,911 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 50682 [2018-11-18 15:29:33,989 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 53622 states to 53622 states and 69697 transitions. [2018-11-18 15:29:33,989 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 53622 [2018-11-18 15:29:34,011 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 53622 [2018-11-18 15:29:34,011 INFO L73 IsDeterministic]: Start isDeterministic. Operand 53622 states and 69697 transitions. [2018-11-18 15:29:34,029 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:29:34,029 INFO L705 BuchiCegarLoop]: Abstraction has 53622 states and 69697 transitions. [2018-11-18 15:29:34,048 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53622 states and 69697 transitions. [2018-11-18 15:29:34,267 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53622 to 51994. [2018-11-18 15:29:34,267 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 51994 states. [2018-11-18 15:29:34,317 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51994 states to 51994 states and 67805 transitions. [2018-11-18 15:29:34,317 INFO L728 BuchiCegarLoop]: Abstraction has 51994 states and 67805 transitions. [2018-11-18 15:29:34,317 INFO L608 BuchiCegarLoop]: Abstraction has 51994 states and 67805 transitions. [2018-11-18 15:29:34,317 INFO L442 BuchiCegarLoop]: ======== Iteration 27============ [2018-11-18 15:29:34,317 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51994 states and 67805 transitions. [2018-11-18 15:29:34,424 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 49054 [2018-11-18 15:29:34,424 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:29:34,424 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:29:34,425 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:34,425 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:34,425 INFO L794 eck$LassoCheckResult]: Stem: 477876#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 477742#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 477743#L977 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 477362#L444 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 477363#L451 assume 1 == ~m_i~0;~m_st~0 := 0; 477891#L451-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 477483#L456-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 477484#L461-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 477366#L466-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 477367#L471-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 477671#L476-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 477672#L481-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 477897#L660 assume !(0 == ~M_E~0); 477898#L660-2 assume !(0 == ~T1_E~0); 477269#L665-1 assume !(0 == ~T2_E~0); 477270#L670-1 assume !(0 == ~T3_E~0); 477375#L675-1 assume !(0 == ~T4_E~0); 477376#L680-1 assume !(0 == ~T5_E~0); 477682#L685-1 assume !(0 == ~T6_E~0); 477683#L690-1 assume !(0 == ~E_1~0); 477544#L695-1 assume !(0 == ~E_2~0); 477545#L700-1 assume !(0 == ~E_3~0); 477859#L705-1 assume !(0 == ~E_4~0); 477445#L710-1 assume !(0 == ~E_5~0); 477446#L715-1 assume !(0 == ~E_6~0); 477308#L720-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 477309#L310 assume !(1 == ~m_pc~0); 477505#L310-2 is_master_triggered_~__retres1~0 := 0; 477500#L321 is_master_triggered_#res := is_master_triggered_~__retres1~0; 477501#L322 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 477647#L815 assume !(0 != activate_threads_~tmp~1); 477854#L815-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 477749#L329 assume !(1 == ~t1_pc~0); 477750#L329-2 is_transmit1_triggered_~__retres1~1 := 0; 477744#L340 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 477745#L341 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 477896#L823 assume !(0 != activate_threads_~tmp___0~0); 477995#L823-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 477960#L348 assume !(1 == ~t2_pc~0); 477961#L348-2 is_transmit2_triggered_~__retres1~2 := 0; 477957#L359 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 477958#L360 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 477456#L831 assume !(0 != activate_threads_~tmp___1~0); 477440#L831-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 477371#L367 assume !(1 == ~t3_pc~0); 477342#L367-2 is_transmit3_triggered_~__retres1~3 := 0; 477343#L378 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 477370#L379 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 477486#L839 assume !(0 != activate_threads_~tmp___2~0); 477695#L839-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 477599#L386 assume !(1 == ~t4_pc~0); 477600#L386-2 is_transmit4_triggered_~__retres1~4 := 0; 477598#L397 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 477491#L398 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 477492#L847 assume !(0 != activate_threads_~tmp___3~0); 477907#L847-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 477908#L405 assume !(1 == ~t5_pc~0); 477836#L405-2 is_transmit5_triggered_~__retres1~5 := 0; 477837#L416 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 477794#L417 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 477795#L855 assume !(0 != activate_threads_~tmp___4~0); 477914#L855-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 477418#L424 assume !(1 == ~t6_pc~0); 477419#L424-2 is_transmit6_triggered_~__retres1~6 := 0; 477414#L435 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 477415#L436 activate_threads_#t~ret14 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 477327#L863 assume !(0 != activate_threads_~tmp___5~0); 477294#L863-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 477295#L733 assume !(1 == ~M_E~0); 477978#L733-2 assume !(1 == ~T1_E~0); 477856#L738-1 assume !(1 == ~T2_E~0); 477443#L743-1 assume !(1 == ~T3_E~0); 477444#L748-1 assume !(1 == ~T4_E~0); 477303#L753-1 assume !(1 == ~T5_E~0); 477304#L758-1 assume !(1 == ~T6_E~0); 477386#L763-1 assume !(1 == ~E_1~0); 477387#L768-1 assume !(1 == ~E_2~0); 477675#L773-1 assume !(1 == ~E_3~0); 477676#L778-1 assume !(1 == ~E_4~0); 477535#L783-1 assume !(1 == ~E_5~0); 477536#L788-1 assume !(1 == ~E_6~0); 477852#L793-1 assume { :end_inline_reset_delta_events } true; 477853#L1014-3 assume true; 522889#L1014-1 assume !false; 494041#L1015 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 494040#L635 [2018-11-18 15:29:34,426 INFO L796 eck$LassoCheckResult]: Loop: 494040#L635 assume true; 494038#L541-1 assume !false; 494036#L542 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 494033#L494 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 494031#L531 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 494030#L532 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 494025#L546 assume 0 != eval_~tmp~0; 494022#L546-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 494019#L554 assume !(0 != eval_~tmp_ndt_1~0); 494017#L551 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 494013#L568 assume !(0 != eval_~tmp_ndt_2~0); 494011#L565 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 494008#L582 assume !(0 != eval_~tmp_ndt_3~0); 494006#L579 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 493986#L596 assume !(0 != eval_~tmp_ndt_4~0); 494003#L593 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 494051#L610 assume !(0 != eval_~tmp_ndt_5~0); 494049#L607 assume !(0 == ~t5_st~0); 494042#L621 assume !(0 == ~t6_st~0); 494040#L635 [2018-11-18 15:29:34,426 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:34,426 INFO L82 PathProgramCache]: Analyzing trace with hash -1539676155, now seen corresponding path program 5 times [2018-11-18 15:29:34,426 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:34,426 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:34,427 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:34,427 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:34,427 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:34,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:29:34,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:29:34,452 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:34,452 INFO L82 PathProgramCache]: Analyzing trace with hash 2142029795, now seen corresponding path program 1 times [2018-11-18 15:29:34,452 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:34,452 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:34,453 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:34,453 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:29:34,453 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:34,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:29:34,456 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:29:34,458 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:34,458 INFO L82 PathProgramCache]: Analyzing trace with hash 1255192927, now seen corresponding path program 1 times [2018-11-18 15:29:34,458 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:34,458 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:34,459 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:34,459 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:34,459 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:34,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:34,501 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:29:34,501 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:29:34,501 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 15:29:34,649 WARN L180 SmtUtils]: Spent 147.00 ms on a formula simplification. DAG size of input: 47 DAG size of output: 45 [2018-11-18 15:29:34,710 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:29:34,711 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:29:34,711 INFO L87 Difference]: Start difference. First operand 51994 states and 67805 transitions. cyclomatic complexity: 15835 Second operand 3 states. [2018-11-18 15:29:35,143 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:29:35,144 INFO L93 Difference]: Finished difference Result 68365 states and 88733 transitions. [2018-11-18 15:29:35,146 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:29:35,146 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 68365 states and 88733 transitions. [2018-11-18 15:29:35,342 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 63265 [2018-11-18 15:29:35,469 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 68365 states to 68365 states and 88733 transitions. [2018-11-18 15:29:35,469 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 68365 [2018-11-18 15:29:35,495 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 68365 [2018-11-18 15:29:35,495 INFO L73 IsDeterministic]: Start isDeterministic. Operand 68365 states and 88733 transitions. [2018-11-18 15:29:35,521 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:29:35,522 INFO L705 BuchiCegarLoop]: Abstraction has 68365 states and 88733 transitions. [2018-11-18 15:29:35,549 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 68365 states and 88733 transitions. [2018-11-18 15:29:35,834 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 68365 to 66505. [2018-11-18 15:29:35,834 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 66505 states. [2018-11-18 15:29:35,904 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66505 states to 66505 states and 86501 transitions. [2018-11-18 15:29:35,904 INFO L728 BuchiCegarLoop]: Abstraction has 66505 states and 86501 transitions. [2018-11-18 15:29:35,904 INFO L608 BuchiCegarLoop]: Abstraction has 66505 states and 86501 transitions. [2018-11-18 15:29:35,904 INFO L442 BuchiCegarLoop]: ======== Iteration 28============ [2018-11-18 15:29:35,904 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 66505 states and 86501 transitions. [2018-11-18 15:29:36,028 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 61405 [2018-11-18 15:29:36,028 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:29:36,028 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:29:36,029 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:36,029 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:36,029 INFO L794 eck$LassoCheckResult]: Stem: 598246#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 598107#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 598108#L977 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 597730#L444 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 597731#L451 assume 1 == ~m_i~0;~m_st~0 := 0; 598263#L451-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 597848#L456-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 597849#L461-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 597734#L466-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 597735#L471-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 598038#L476-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 598039#L481-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 598269#L660 assume !(0 == ~M_E~0); 598270#L660-2 assume !(0 == ~T1_E~0); 597636#L665-1 assume !(0 == ~T2_E~0); 597637#L670-1 assume !(0 == ~T3_E~0); 597743#L675-1 assume !(0 == ~T4_E~0); 597744#L680-1 assume !(0 == ~T5_E~0); 598048#L685-1 assume !(0 == ~T6_E~0); 598049#L690-1 assume !(0 == ~E_1~0); 597908#L695-1 assume !(0 == ~E_2~0); 597909#L700-1 assume !(0 == ~E_3~0); 598222#L705-1 assume !(0 == ~E_4~0); 597812#L710-1 assume !(0 == ~E_5~0); 597813#L715-1 assume !(0 == ~E_6~0); 597676#L720-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 597677#L310 assume !(1 == ~m_pc~0); 597870#L310-2 is_master_triggered_~__retres1~0 := 0; 597865#L321 is_master_triggered_#res := is_master_triggered_~__retres1~0; 597866#L322 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 598010#L815 assume !(0 != activate_threads_~tmp~1); 598218#L815-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 598114#L329 assume !(1 == ~t1_pc~0); 598115#L329-2 is_transmit1_triggered_~__retres1~1 := 0; 598109#L340 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 598110#L341 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 598268#L823 assume !(0 != activate_threads_~tmp___0~0); 598372#L823-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 598338#L348 assume !(1 == ~t2_pc~0); 598339#L348-2 is_transmit2_triggered_~__retres1~2 := 0; 598335#L359 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 598336#L360 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 597823#L831 assume !(0 != activate_threads_~tmp___1~0); 597807#L831-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 597739#L367 assume !(1 == ~t3_pc~0); 597708#L367-2 is_transmit3_triggered_~__retres1~3 := 0; 597709#L378 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 597738#L379 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 597851#L839 assume !(0 != activate_threads_~tmp___2~0); 598060#L839-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 597958#L386 assume !(1 == ~t4_pc~0); 597959#L386-2 is_transmit4_triggered_~__retres1~4 := 0; 597957#L397 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 597856#L398 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 597857#L847 assume !(0 != activate_threads_~tmp___3~0); 598281#L847-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 598282#L405 assume !(1 == ~t5_pc~0); 598198#L405-2 is_transmit5_triggered_~__retres1~5 := 0; 598199#L416 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 598156#L417 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 598157#L855 assume !(0 != activate_threads_~tmp___4~0); 598293#L855-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 597787#L424 assume !(1 == ~t6_pc~0); 597788#L424-2 is_transmit6_triggered_~__retres1~6 := 0; 597783#L435 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 597784#L436 activate_threads_#t~ret14 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 597695#L863 assume !(0 != activate_threads_~tmp___5~0); 597663#L863-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 597664#L733 assume !(1 == ~M_E~0); 598357#L733-2 assume !(1 == ~T1_E~0); 598220#L738-1 assume !(1 == ~T2_E~0); 597810#L743-1 assume !(1 == ~T3_E~0); 597811#L748-1 assume !(1 == ~T4_E~0); 597671#L753-1 assume !(1 == ~T5_E~0); 597672#L758-1 assume !(1 == ~T6_E~0); 597754#L763-1 assume !(1 == ~E_1~0); 597755#L768-1 assume !(1 == ~E_2~0); 598041#L773-1 assume !(1 == ~E_3~0); 598042#L778-1 assume !(1 == ~E_4~0); 597899#L783-1 assume !(1 == ~E_5~0); 597900#L788-1 assume !(1 == ~E_6~0); 598216#L793-1 assume { :end_inline_reset_delta_events } true; 598217#L1014-3 assume true; 663179#L1014-1 assume !false; 663161#L1015 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 663158#L635 [2018-11-18 15:29:36,030 INFO L796 eck$LassoCheckResult]: Loop: 663158#L635 assume true; 663156#L541-1 assume !false; 663154#L542 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 663151#L494 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 663150#L531 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 663148#L532 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 663147#L546 assume 0 != eval_~tmp~0; 663146#L546-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 663145#L554 assume !(0 != eval_~tmp_ndt_1~0); 617800#L551 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 617794#L568 assume !(0 != eval_~tmp_ndt_2~0); 617787#L565 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 617777#L582 assume !(0 != eval_~tmp_ndt_3~0); 617778#L579 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 635812#L596 assume !(0 != eval_~tmp_ndt_4~0); 635831#L593 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 650901#L610 assume !(0 != eval_~tmp_ndt_5~0); 650902#L607 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 660303#L624 assume !(0 != eval_~tmp_ndt_6~0); 660304#L621 assume !(0 == ~t6_st~0); 663158#L635 [2018-11-18 15:29:36,030 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:36,030 INFO L82 PathProgramCache]: Analyzing trace with hash -1539676155, now seen corresponding path program 6 times [2018-11-18 15:29:36,030 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:36,030 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:36,031 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:36,031 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:36,031 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:36,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:29:36,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:29:36,054 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:36,054 INFO L82 PathProgramCache]: Analyzing trace with hash 1978221285, now seen corresponding path program 1 times [2018-11-18 15:29:36,054 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:36,054 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:36,055 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:36,055 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 15:29:36,055 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:36,056 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:29:36,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:29:36,059 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:36,060 INFO L82 PathProgramCache]: Analyzing trace with hash 256082153, now seen corresponding path program 1 times [2018-11-18 15:29:36,060 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:36,060 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:36,060 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:36,060 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:36,060 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:36,065 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 15:29:36,097 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 15:29:36,097 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 15:29:36,097 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 15:29:36,185 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 15:29:36,186 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 15:29:36,186 INFO L87 Difference]: Start difference. First operand 66505 states and 86501 transitions. cyclomatic complexity: 20020 Second operand 3 states. [2018-11-18 15:29:36,423 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 15:29:36,423 INFO L93 Difference]: Finished difference Result 124952 states and 161906 transitions. [2018-11-18 15:29:36,423 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 15:29:36,424 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 124952 states and 161906 transitions. [2018-11-18 15:29:37,004 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 114840 [2018-11-18 15:29:37,156 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 124952 states to 124952 states and 161906 transitions. [2018-11-18 15:29:37,156 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 124952 [2018-11-18 15:29:37,193 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 124952 [2018-11-18 15:29:37,193 INFO L73 IsDeterministic]: Start isDeterministic. Operand 124952 states and 161906 transitions. [2018-11-18 15:29:37,229 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 15:29:37,229 INFO L705 BuchiCegarLoop]: Abstraction has 124952 states and 161906 transitions. [2018-11-18 15:29:37,265 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 124952 states and 161906 transitions. [2018-11-18 15:29:37,829 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 124952 to 124952. [2018-11-18 15:29:37,829 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 124952 states. [2018-11-18 15:29:37,966 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 124952 states to 124952 states and 161906 transitions. [2018-11-18 15:29:37,966 INFO L728 BuchiCegarLoop]: Abstraction has 124952 states and 161906 transitions. [2018-11-18 15:29:37,966 INFO L608 BuchiCegarLoop]: Abstraction has 124952 states and 161906 transitions. [2018-11-18 15:29:37,966 INFO L442 BuchiCegarLoop]: ======== Iteration 29============ [2018-11-18 15:29:37,966 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 124952 states and 161906 transitions. [2018-11-18 15:29:38,212 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 114840 [2018-11-18 15:29:38,212 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 15:29:38,212 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 15:29:38,212 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:38,213 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 15:29:38,213 INFO L794 eck$LassoCheckResult]: Stem: 789718#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 789574#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~8;havoc main_~__retres1~8;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 789575#L977 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret16, start_simulation_#t~ret17, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 789193#L444 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 789194#L451 assume 1 == ~m_i~0;~m_st~0 := 0; 789737#L451-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 789307#L456-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 789308#L461-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 789197#L466-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 789198#L471-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 789503#L476-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 789504#L481-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 789741#L660 assume !(0 == ~M_E~0); 789742#L660-2 assume !(0 == ~T1_E~0); 789101#L665-1 assume !(0 == ~T2_E~0); 789102#L670-1 assume !(0 == ~T3_E~0); 789206#L675-1 assume !(0 == ~T4_E~0); 789207#L680-1 assume !(0 == ~T5_E~0); 789513#L685-1 assume !(0 == ~T6_E~0); 789514#L690-1 assume !(0 == ~E_1~0); 789372#L695-1 assume !(0 == ~E_2~0); 789373#L700-1 assume !(0 == ~E_3~0); 789693#L705-1 assume !(0 == ~E_4~0); 789274#L710-1 assume !(0 == ~E_5~0); 789275#L715-1 assume !(0 == ~E_6~0); 789139#L720-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8, activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 789140#L310 assume !(1 == ~m_pc~0); 789332#L310-2 is_master_triggered_~__retres1~0 := 0; 789327#L321 is_master_triggered_#res := is_master_triggered_~__retres1~0; 789328#L322 activate_threads_#t~ret8 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret8;havoc activate_threads_#t~ret8; 789479#L815 assume !(0 != activate_threads_~tmp~1); 789687#L815-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 789578#L329 assume !(1 == ~t1_pc~0); 789579#L329-2 is_transmit1_triggered_~__retres1~1 := 0; 789576#L340 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 789577#L341 activate_threads_#t~ret9 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 789740#L823 assume !(0 != activate_threads_~tmp___0~0); 789861#L823-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 789814#L348 assume !(1 == ~t2_pc~0); 789815#L348-2 is_transmit2_triggered_~__retres1~2 := 0; 789811#L359 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 789812#L360 activate_threads_#t~ret10 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 789285#L831 assume !(0 != activate_threads_~tmp___1~0); 789269#L831-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 789202#L367 assume !(1 == ~t3_pc~0); 789171#L367-2 is_transmit3_triggered_~__retres1~3 := 0; 789172#L378 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 789201#L379 activate_threads_#t~ret11 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 789310#L839 assume !(0 != activate_threads_~tmp___2~0); 789523#L839-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 789428#L386 assume !(1 == ~t4_pc~0); 789429#L386-2 is_transmit4_triggered_~__retres1~4 := 0; 789427#L397 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 789318#L398 activate_threads_#t~ret12 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 789319#L847 assume !(0 != activate_threads_~tmp___3~0); 789756#L847-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 789757#L405 assume !(1 == ~t5_pc~0); 789668#L405-2 is_transmit5_triggered_~__retres1~5 := 0; 789669#L416 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 789623#L417 activate_threads_#t~ret13 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 789624#L855 assume !(0 != activate_threads_~tmp___4~0); 789769#L855-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 789249#L424 assume !(1 == ~t6_pc~0); 789250#L424-2 is_transmit6_triggered_~__retres1~6 := 0; 789245#L435 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 789246#L436 activate_threads_#t~ret14 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 789158#L863 assume !(0 != activate_threads_~tmp___5~0); 789126#L863-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 789127#L733 assume !(1 == ~M_E~0); 789837#L733-2 assume !(1 == ~T1_E~0); 789690#L738-1 assume !(1 == ~T2_E~0); 789272#L743-1 assume !(1 == ~T3_E~0); 789273#L748-1 assume !(1 == ~T4_E~0); 789134#L753-1 assume !(1 == ~T5_E~0); 789135#L758-1 assume !(1 == ~T6_E~0); 789217#L763-1 assume !(1 == ~E_1~0); 789218#L768-1 assume !(1 == ~E_2~0); 789506#L773-1 assume !(1 == ~E_3~0); 789507#L778-1 assume !(1 == ~E_4~0); 789365#L783-1 assume !(1 == ~E_5~0); 789366#L788-1 assume !(1 == ~E_6~0); 789685#L793-1 assume { :end_inline_reset_delta_events } true; 789686#L1014-3 assume true; 828291#L1014-1 assume !false; 828280#L1015 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_~tmp~0;havoc eval_~tmp~0; 828278#L635 [2018-11-18 15:29:38,213 INFO L796 eck$LassoCheckResult]: Loop: 828278#L635 assume true; 828276#L541-1 assume !false; 828274#L542 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~7;havoc exists_runnable_thread_~__retres1~7; 828271#L494 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7 := 1; 828269#L531 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~7; 828267#L532 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 828264#L546 assume 0 != eval_~tmp~0; 828262#L546-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 828257#L554 assume !(0 != eval_~tmp_ndt_1~0); 828255#L551 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 828252#L568 assume !(0 != eval_~tmp_ndt_2~0); 828250#L565 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 828249#L582 assume !(0 != eval_~tmp_ndt_3~0); 812441#L579 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 812438#L596 assume !(0 != eval_~tmp_ndt_4~0); 812436#L593 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 812434#L610 assume !(0 != eval_~tmp_ndt_5~0); 812435#L607 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 828286#L624 assume !(0 != eval_~tmp_ndt_6~0); 828284#L621 assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0;eval_~tmp_ndt_7~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 828281#L638 assume !(0 != eval_~tmp_ndt_7~0); 828278#L635 [2018-11-18 15:29:38,213 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:38,213 INFO L82 PathProgramCache]: Analyzing trace with hash -1539676155, now seen corresponding path program 7 times [2018-11-18 15:29:38,213 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:38,214 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:38,214 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:38,214 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:38,214 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:38,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:29:38,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:29:38,237 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:38,237 INFO L82 PathProgramCache]: Analyzing trace with hash 1195318146, now seen corresponding path program 1 times [2018-11-18 15:29:38,238 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:38,238 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:38,238 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:38,238 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:38,238 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:38,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:29:38,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:29:38,243 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 15:29:38,243 INFO L82 PathProgramCache]: Analyzing trace with hash -651387394, now seen corresponding path program 1 times [2018-11-18 15:29:38,243 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 15:29:38,243 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 15:29:38,244 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:38,244 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 15:29:38,244 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 15:29:38,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:29:38,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 15:29:39,072 WARN L180 SmtUtils]: Spent 693.00 ms on a formula simplification. DAG size of input: 219 DAG size of output: 146 [2018-11-18 15:29:39,200 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 18.11 03:29:39 BoogieIcfgContainer [2018-11-18 15:29:39,200 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2018-11-18 15:29:39,201 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-18 15:29:39,201 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-18 15:29:39,201 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-18 15:29:39,201 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 03:29:26" (3/4) ... [2018-11-18 15:29:39,206 INFO L141 WitnessPrinter]: Generating witness for non-termination counterexample [2018-11-18 15:29:39,258 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_c6703cb5-0709-4fd4-a613-f346af7a7a19/bin-2019/uautomizer/witness.graphml [2018-11-18 15:29:39,258 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-18 15:29:39,259 INFO L168 Benchmark]: Toolchain (without parser) took 14525.35 ms. Allocated memory was 1.0 GB in the beginning and 2.2 GB in the end (delta: 1.2 GB). Free memory was 959.1 MB in the beginning and 1.4 GB in the end (delta: -410.3 MB). Peak memory consumption was 790.3 MB. Max. memory is 11.5 GB. [2018-11-18 15:29:39,259 INFO L168 Benchmark]: CDTParser took 0.11 ms. Allocated memory is still 1.0 GB. Free memory is still 985.4 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-18 15:29:39,259 INFO L168 Benchmark]: CACSL2BoogieTranslator took 232.77 ms. Allocated memory is still 1.0 GB. Free memory was 959.1 MB in the beginning and 937.7 MB in the end (delta: 21.5 MB). Peak memory consumption was 21.5 MB. Max. memory is 11.5 GB. [2018-11-18 15:29:39,260 INFO L168 Benchmark]: Boogie Procedure Inliner took 87.20 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 154.7 MB). Free memory was 937.7 MB in the beginning and 1.1 GB in the end (delta: -208.6 MB). Peak memory consumption was 14.9 MB. Max. memory is 11.5 GB. [2018-11-18 15:29:39,260 INFO L168 Benchmark]: Boogie Preprocessor took 45.79 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.5 MB). Peak memory consumption was 6.5 MB. Max. memory is 11.5 GB. [2018-11-18 15:29:39,260 INFO L168 Benchmark]: RCFGBuilder took 937.13 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 137.6 MB). Peak memory consumption was 137.6 MB. Max. memory is 11.5 GB. [2018-11-18 15:29:39,260 INFO L168 Benchmark]: BuchiAutomizer took 13161.92 ms. Allocated memory was 1.2 GB in the beginning and 2.2 GB in the end (delta: 1.0 GB). Free memory was 1.0 GB in the beginning and 1.4 GB in the end (delta: -390.0 MB). Peak memory consumption was 1.7 GB. Max. memory is 11.5 GB. [2018-11-18 15:29:39,260 INFO L168 Benchmark]: Witness Printer took 57.37 ms. Allocated memory is still 2.2 GB. Free memory was 1.4 GB in the beginning and 1.4 GB in the end (delta: 22.7 MB). Peak memory consumption was 22.7 MB. Max. memory is 11.5 GB. [2018-11-18 15:29:39,262 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.11 ms. Allocated memory is still 1.0 GB. Free memory is still 985.4 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 232.77 ms. Allocated memory is still 1.0 GB. Free memory was 959.1 MB in the beginning and 937.7 MB in the end (delta: 21.5 MB). Peak memory consumption was 21.5 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 87.20 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 154.7 MB). Free memory was 937.7 MB in the beginning and 1.1 GB in the end (delta: -208.6 MB). Peak memory consumption was 14.9 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 45.79 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.5 MB). Peak memory consumption was 6.5 MB. Max. memory is 11.5 GB. * RCFGBuilder took 937.13 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 137.6 MB). Peak memory consumption was 137.6 MB. Max. memory is 11.5 GB. * BuchiAutomizer took 13161.92 ms. Allocated memory was 1.2 GB in the beginning and 2.2 GB in the end (delta: 1.0 GB). Free memory was 1.0 GB in the beginning and 1.4 GB in the end (delta: -390.0 MB). Peak memory consumption was 1.7 GB. Max. memory is 11.5 GB. * Witness Printer took 57.37 ms. Allocated memory is still 2.2 GB. Free memory was 1.4 GB in the beginning and 1.4 GB in the end (delta: 22.7 MB). Peak memory consumption was 22.7 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 28 terminating modules (28 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.28 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 124952 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 13.1s and 29 iterations. TraceHistogramMax:1. Analysis of lassos took 3.7s. Construction of modules took 0.9s. Büchi inclusion checks took 1.5s. Highest rank in rank-based complementation 0. Minimization of det autom 28. Minimization of nondet autom 0. Automata minimization 3.0s AutomataMinimizationTime, 28 MinimizatonAttempts, 19333 StatesRemovedByMinimization, 13 NontrivialMinimizations. Non-live state removal took 2.4s Buchi closure took 0.1s. Biggest automaton had 124952 states and ocurred in iteration 28. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 26340 SDtfs, 25650 SDslu, 16291 SDs, 0 SdLazy, 516 SolverSat, 343 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.9s Time LassoAnalysisResults: nont1 unkn0 SFLI5 SFLT0 conc6 concLT0 SILN1 SILU0 SILI16 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 541]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {__retres1=0, t3_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@34eb5a8e=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@31f79027=0, tmp=1, t5_i=1, __retres1=0, kernel_st=1, \result=0, t2_st=0, t4_i=1, E_3=2, t4_pc=0, E_5=2, T6_E=2, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4a7910be=0, E_1=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1b81961f=0, tmp_ndt_2=0, \result=0, __retres1=0, \result=0, tmp_ndt_4=0, tmp_ndt_6=0, m_st=0, t6_pc=0, tmp___2=0, tmp___0=0, t3_pc=0, tmp=0, __retres1=0, \result=0, t6_i=1, m_pc=0, tmp___4=0, \result=0, __retres1=0, t6_st=0, E_6=2, \result=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@679c882f=0, \result=0, T2_E=2, tmp___0=0, t1_pc=0, __retres1=1, t5_st=0, E_2=2, E_4=2, T1_E=2, tmp_ndt_1=0, M_E=2, tmp=0, tmp_ndt_3=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@27bd5548=0, __retres1=0, T5_E=2, t2_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@10522a3e=0, T4_E=2, t3_i=1, t4_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5d0823c2=0, m_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5d45fcd2=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@12a71a41=0, t1_st=0, tmp_ndt_5=0, t5_pc=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@485c9788=0, t2_pc=0, tmp_ndt_7=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3a8d4f67=0, tmp___3=0, tmp___1=0, T3_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@50d46901=0, t1_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4092f582=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1ff19a7b=0, \result=1, tmp___5=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1549a47b=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@57c1cf4f=0} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 541]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int t4_pc = 0; [L20] int t5_pc = 0; [L21] int t6_pc = 0; [L22] int m_st ; [L23] int t1_st ; [L24] int t2_st ; [L25] int t3_st ; [L26] int t4_st ; [L27] int t5_st ; [L28] int t6_st ; [L29] int m_i ; [L30] int t1_i ; [L31] int t2_i ; [L32] int t3_i ; [L33] int t4_i ; [L34] int t5_i ; [L35] int t6_i ; [L36] int M_E = 2; [L37] int T1_E = 2; [L38] int T2_E = 2; [L39] int T3_E = 2; [L40] int T4_E = 2; [L41] int T5_E = 2; [L42] int T6_E = 2; [L43] int E_1 = 2; [L44] int E_2 = 2; [L45] int E_3 = 2; [L46] int E_4 = 2; [L47] int E_5 = 2; [L48] int E_6 = 2; [L1059] int __retres1 ; [L1063] CALL init_model() [L969] m_i = 1 [L970] t1_i = 1 [L971] t2_i = 1 [L972] t3_i = 1 [L973] t4_i = 1 [L974] t5_i = 1 [L975] RET t6_i = 1 [L1063] init_model() [L1064] CALL start_simulation() [L1000] int kernel_st ; [L1001] int tmp ; [L1002] int tmp___0 ; [L1006] kernel_st = 0 [L1007] FCALL update_channels() [L1008] CALL init_threads() [L451] COND TRUE m_i == 1 [L452] m_st = 0 [L456] COND TRUE t1_i == 1 [L457] t1_st = 0 [L461] COND TRUE t2_i == 1 [L462] t2_st = 0 [L466] COND TRUE t3_i == 1 [L467] t3_st = 0 [L471] COND TRUE t4_i == 1 [L472] t4_st = 0 [L476] COND TRUE t5_i == 1 [L477] t5_st = 0 [L481] COND TRUE t6_i == 1 [L482] RET t6_st = 0 [L1008] init_threads() [L1009] CALL fire_delta_events() [L660] COND FALSE !(M_E == 0) [L665] COND FALSE !(T1_E == 0) [L670] COND FALSE !(T2_E == 0) [L675] COND FALSE !(T3_E == 0) [L680] COND FALSE !(T4_E == 0) [L685] COND FALSE !(T5_E == 0) [L690] COND FALSE !(T6_E == 0) [L695] COND FALSE !(E_1 == 0) [L700] COND FALSE !(E_2 == 0) [L705] COND FALSE !(E_3 == 0) [L710] COND FALSE !(E_4 == 0) [L715] COND FALSE !(E_5 == 0) [L720] COND FALSE, RET !(E_6 == 0) [L1009] fire_delta_events() [L1010] CALL activate_threads() [L803] int tmp ; [L804] int tmp___0 ; [L805] int tmp___1 ; [L806] int tmp___2 ; [L807] int tmp___3 ; [L808] int tmp___4 ; [L809] int tmp___5 ; [L813] CALL, EXPR is_master_triggered() [L307] int __retres1 ; [L310] COND FALSE !(m_pc == 1) [L320] __retres1 = 0 [L322] RET return (__retres1); [L813] EXPR is_master_triggered() [L813] tmp = is_master_triggered() [L815] COND FALSE !(\read(tmp)) [L821] CALL, EXPR is_transmit1_triggered() [L326] int __retres1 ; [L329] COND FALSE !(t1_pc == 1) [L339] __retres1 = 0 [L341] RET return (__retres1); [L821] EXPR is_transmit1_triggered() [L821] tmp___0 = is_transmit1_triggered() [L823] COND FALSE !(\read(tmp___0)) [L829] CALL, EXPR is_transmit2_triggered() [L345] int __retres1 ; [L348] COND FALSE !(t2_pc == 1) [L358] __retres1 = 0 [L360] RET return (__retres1); [L829] EXPR is_transmit2_triggered() [L829] tmp___1 = is_transmit2_triggered() [L831] COND FALSE !(\read(tmp___1)) [L837] CALL, EXPR is_transmit3_triggered() [L364] int __retres1 ; [L367] COND FALSE !(t3_pc == 1) [L377] __retres1 = 0 [L379] RET return (__retres1); [L837] EXPR is_transmit3_triggered() [L837] tmp___2 = is_transmit3_triggered() [L839] COND FALSE !(\read(tmp___2)) [L845] CALL, EXPR is_transmit4_triggered() [L383] int __retres1 ; [L386] COND FALSE !(t4_pc == 1) [L396] __retres1 = 0 [L398] RET return (__retres1); [L845] EXPR is_transmit4_triggered() [L845] tmp___3 = is_transmit4_triggered() [L847] COND FALSE !(\read(tmp___3)) [L853] CALL, EXPR is_transmit5_triggered() [L402] int __retres1 ; [L405] COND FALSE !(t5_pc == 1) [L415] __retres1 = 0 [L417] RET return (__retres1); [L853] EXPR is_transmit5_triggered() [L853] tmp___4 = is_transmit5_triggered() [L855] COND FALSE !(\read(tmp___4)) [L861] CALL, EXPR is_transmit6_triggered() [L421] int __retres1 ; [L424] COND FALSE !(t6_pc == 1) [L434] __retres1 = 0 [L436] RET return (__retres1); [L861] EXPR is_transmit6_triggered() [L861] tmp___5 = is_transmit6_triggered() [L863] COND FALSE, RET !(\read(tmp___5)) [L1010] activate_threads() [L1011] CALL reset_delta_events() [L733] COND FALSE !(M_E == 1) [L738] COND FALSE !(T1_E == 1) [L743] COND FALSE !(T2_E == 1) [L748] COND FALSE !(T3_E == 1) [L753] COND FALSE !(T4_E == 1) [L758] COND FALSE !(T5_E == 1) [L763] COND FALSE !(T6_E == 1) [L768] COND FALSE !(E_1 == 1) [L773] COND FALSE !(E_2 == 1) [L778] COND FALSE !(E_3 == 1) [L783] COND FALSE !(E_4 == 1) [L788] COND FALSE !(E_5 == 1) [L793] COND FALSE, RET !(E_6 == 1) [L1011] reset_delta_events() [L1014] COND TRUE 1 [L1017] kernel_st = 1 [L1018] CALL eval() [L537] int tmp ; Loop: [L541] COND TRUE 1 [L544] CALL, EXPR exists_runnable_thread() [L491] int __retres1 ; [L494] COND TRUE m_st == 0 [L495] __retres1 = 1 [L532] RET return (__retres1); [L544] EXPR exists_runnable_thread() [L544] tmp = exists_runnable_thread() [L546] COND TRUE \read(tmp) [L551] COND TRUE m_st == 0 [L552] int tmp_ndt_1; [L553] tmp_ndt_1 = __VERIFIER_nondet_int() [L554] COND FALSE !(\read(tmp_ndt_1)) [L565] COND TRUE t1_st == 0 [L566] int tmp_ndt_2; [L567] tmp_ndt_2 = __VERIFIER_nondet_int() [L568] COND FALSE !(\read(tmp_ndt_2)) [L579] COND TRUE t2_st == 0 [L580] int tmp_ndt_3; [L581] tmp_ndt_3 = __VERIFIER_nondet_int() [L582] COND FALSE !(\read(tmp_ndt_3)) [L593] COND TRUE t3_st == 0 [L594] int tmp_ndt_4; [L595] tmp_ndt_4 = __VERIFIER_nondet_int() [L596] COND FALSE !(\read(tmp_ndt_4)) [L607] COND TRUE t4_st == 0 [L608] int tmp_ndt_5; [L609] tmp_ndt_5 = __VERIFIER_nondet_int() [L610] COND FALSE !(\read(tmp_ndt_5)) [L621] COND TRUE t5_st == 0 [L622] int tmp_ndt_6; [L623] tmp_ndt_6 = __VERIFIER_nondet_int() [L624] COND FALSE !(\read(tmp_ndt_6)) [L635] COND TRUE t6_st == 0 [L636] int tmp_ndt_7; [L637] tmp_ndt_7 = __VERIFIER_nondet_int() [L638] COND FALSE !(\read(tmp_ndt_7)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...