./Ultimate.py --spec ../../sv-benchmarks/c/Termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.07_false-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 5842f4b8 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_eeb28a43-bad7-4f07-a222-3d03d3a88e9c/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_eeb28a43-bad7-4f07-a222-3d03d3a88e9c/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_eeb28a43-bad7-4f07-a222-3d03d3a88e9c/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_eeb28a43-bad7-4f07-a222-3d03d3a88e9c/bin-2019/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.07_false-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_eeb28a43-bad7-4f07-a222-3d03d3a88e9c/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_eeb28a43-bad7-4f07-a222-3d03d3a88e9c/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 7065f281083809b042f9cd06530419b32b632e49 .............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.1.23-5842f4b [2018-11-18 10:50:49,359 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-18 10:50:49,361 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-18 10:50:49,369 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-18 10:50:49,369 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-18 10:50:49,369 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-18 10:50:49,370 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-18 10:50:49,371 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-18 10:50:49,373 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-18 10:50:49,373 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-18 10:50:49,374 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-18 10:50:49,374 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-18 10:50:49,375 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-18 10:50:49,375 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-18 10:50:49,377 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-18 10:50:49,377 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-18 10:50:49,378 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-18 10:50:49,379 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-18 10:50:49,380 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-18 10:50:49,381 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-18 10:50:49,382 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-18 10:50:49,383 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-18 10:50:49,385 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-18 10:50:49,385 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-18 10:50:49,385 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-18 10:50:49,386 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-18 10:50:49,386 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-18 10:50:49,387 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-18 10:50:49,387 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-18 10:50:49,389 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-18 10:50:49,389 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-18 10:50:49,389 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-18 10:50:49,390 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-18 10:50:49,390 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-18 10:50:49,390 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-18 10:50:49,391 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-18 10:50:49,391 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_eeb28a43-bad7-4f07-a222-3d03d3a88e9c/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2018-11-18 10:50:49,401 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-18 10:50:49,402 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-18 10:50:49,402 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-18 10:50:49,403 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-18 10:50:49,403 INFO L133 SettingsManager]: * Use SBE=true [2018-11-18 10:50:49,403 INFO L131 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2018-11-18 10:50:49,403 INFO L133 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2018-11-18 10:50:49,403 INFO L133 SettingsManager]: * Use old map elimination=false [2018-11-18 10:50:49,403 INFO L133 SettingsManager]: * Use external solver (rank synthesis)=false [2018-11-18 10:50:49,403 INFO L133 SettingsManager]: * Use only trivial implications for array writes=true [2018-11-18 10:50:49,403 INFO L133 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2018-11-18 10:50:49,403 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-18 10:50:49,405 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-18 10:50:49,405 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-11-18 10:50:49,405 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-18 10:50:49,405 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-18 10:50:49,405 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-18 10:50:49,405 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2018-11-18 10:50:49,405 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2018-11-18 10:50:49,405 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2018-11-18 10:50:49,406 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-18 10:50:49,406 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-18 10:50:49,406 INFO L133 SettingsManager]: * Assume nondeterminstic values are in range=false [2018-11-18 10:50:49,406 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-18 10:50:49,407 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2018-11-18 10:50:49,407 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-18 10:50:49,407 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-18 10:50:49,407 INFO L133 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2018-11-18 10:50:49,407 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-18 10:50:49,407 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-18 10:50:49,407 INFO L133 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2018-11-18 10:50:49,408 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-11-18 10:50:49,408 INFO L133 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_eeb28a43-bad7-4f07-a222-3d03d3a88e9c/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 7065f281083809b042f9cd06530419b32b632e49 [2018-11-18 10:50:49,431 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-18 10:50:49,440 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-18 10:50:49,442 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-18 10:50:49,444 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-18 10:50:49,444 INFO L276 PluginConnector]: CDTParser initialized [2018-11-18 10:50:49,444 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_eeb28a43-bad7-4f07-a222-3d03d3a88e9c/bin-2019/uautomizer/../../sv-benchmarks/c/systemc/transmitter.07_false-unreach-call_false-termination.cil.c [2018-11-18 10:50:49,481 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_eeb28a43-bad7-4f07-a222-3d03d3a88e9c/bin-2019/uautomizer/data/87c482a4f/2ea4180fbf3d4d1c81e0f07fd9548dd7/FLAG840bb7665 [2018-11-18 10:50:49,907 INFO L307 CDTParser]: Found 1 translation units. [2018-11-18 10:50:49,907 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_eeb28a43-bad7-4f07-a222-3d03d3a88e9c/sv-benchmarks/c/systemc/transmitter.07_false-unreach-call_false-termination.cil.c [2018-11-18 10:50:49,917 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_eeb28a43-bad7-4f07-a222-3d03d3a88e9c/bin-2019/uautomizer/data/87c482a4f/2ea4180fbf3d4d1c81e0f07fd9548dd7/FLAG840bb7665 [2018-11-18 10:50:49,927 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_eeb28a43-bad7-4f07-a222-3d03d3a88e9c/bin-2019/uautomizer/data/87c482a4f/2ea4180fbf3d4d1c81e0f07fd9548dd7 [2018-11-18 10:50:49,930 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-18 10:50:49,931 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-18 10:50:49,931 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-18 10:50:49,931 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-18 10:50:49,934 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-18 10:50:49,934 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 10:50:49" (1/1) ... [2018-11-18 10:50:49,936 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4959e04 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 10:50:49, skipping insertion in model container [2018-11-18 10:50:49,936 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 10:50:49" (1/1) ... [2018-11-18 10:50:49,943 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-18 10:50:49,971 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-18 10:50:50,119 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 10:50:50,122 INFO L191 MainTranslator]: Completed pre-run [2018-11-18 10:50:50,155 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 10:50:50,167 INFO L195 MainTranslator]: Completed translation [2018-11-18 10:50:50,167 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 10:50:50 WrapperNode [2018-11-18 10:50:50,167 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-18 10:50:50,168 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-18 10:50:50,168 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-18 10:50:50,168 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-18 10:50:50,173 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 10:50:50" (1/1) ... [2018-11-18 10:50:50,217 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 10:50:50" (1/1) ... [2018-11-18 10:50:50,259 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-18 10:50:50,260 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-18 10:50:50,260 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-18 10:50:50,260 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-18 10:50:50,266 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 10:50:50" (1/1) ... [2018-11-18 10:50:50,266 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 10:50:50" (1/1) ... [2018-11-18 10:50:50,270 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 10:50:50" (1/1) ... [2018-11-18 10:50:50,270 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 10:50:50" (1/1) ... [2018-11-18 10:50:50,284 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 10:50:50" (1/1) ... [2018-11-18 10:50:50,303 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 10:50:50" (1/1) ... [2018-11-18 10:50:50,307 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 10:50:50" (1/1) ... [2018-11-18 10:50:50,312 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-18 10:50:50,313 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-18 10:50:50,313 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-18 10:50:50,313 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-18 10:50:50,314 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 10:50:50" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_eeb28a43-bad7-4f07-a222-3d03d3a88e9c/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 10:50:50,373 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-18 10:50:50,373 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-18 10:50:51,339 INFO L278 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-18 10:50:51,339 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 10:50:51 BoogieIcfgContainer [2018-11-18 10:50:51,340 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-18 10:50:51,340 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2018-11-18 10:50:51,340 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2018-11-18 10:50:51,343 INFO L276 PluginConnector]: BuchiAutomizer initialized [2018-11-18 10:50:51,343 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-18 10:50:51,343 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 18.11 10:50:49" (1/3) ... [2018-11-18 10:50:51,344 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4f53b61e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 18.11 10:50:51, skipping insertion in model container [2018-11-18 10:50:51,344 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-18 10:50:51,344 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 10:50:50" (2/3) ... [2018-11-18 10:50:51,344 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4f53b61e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 18.11 10:50:51, skipping insertion in model container [2018-11-18 10:50:51,344 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-18 10:50:51,344 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 10:50:51" (3/3) ... [2018-11-18 10:50:51,345 INFO L375 chiAutomizerObserver]: Analyzing ICFG transmitter.07_false-unreach-call_false-termination.cil.c [2018-11-18 10:50:51,377 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-18 10:50:51,378 INFO L374 BuchiCegarLoop]: Interprodecural is true [2018-11-18 10:50:51,378 INFO L375 BuchiCegarLoop]: Hoare is false [2018-11-18 10:50:51,378 INFO L376 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2018-11-18 10:50:51,378 INFO L377 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-18 10:50:51,378 INFO L378 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-18 10:50:51,378 INFO L379 BuchiCegarLoop]: Difference is false [2018-11-18 10:50:51,378 INFO L380 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-18 10:50:51,378 INFO L383 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2018-11-18 10:50:51,403 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 786 states. [2018-11-18 10:50:51,437 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 681 [2018-11-18 10:50:51,437 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:50:51,437 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:50:51,445 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:51,445 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:51,446 INFO L442 BuchiCegarLoop]: ======== Iteration 1============ [2018-11-18 10:50:51,446 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 786 states. [2018-11-18 10:50:51,455 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 681 [2018-11-18 10:50:51,455 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:50:51,455 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:50:51,458 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:51,458 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:51,466 INFO L794 eck$LassoCheckResult]: Stem: 254#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 182#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 241#L1101true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 366#L504true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4#L511true assume !(1 == ~m_i~0);~m_st~0 := 2; 101#L511-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 616#L516-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 441#L521-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 367#L526-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 158#L531-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 780#L536-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 495#L541-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 348#L546-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 352#L744true assume !(0 == ~M_E~0); 356#L744-2true assume !(0 == ~T1_E~0); 228#L749-1true assume !(0 == ~T2_E~0); 84#L754-1true assume !(0 == ~T3_E~0); 690#L759-1true assume !(0 == ~T4_E~0); 418#L764-1true assume !(0 == ~T5_E~0); 206#L769-1true assume 0 == ~T6_E~0;~T6_E~0 := 1; 58#L774-1true assume !(0 == ~T7_E~0); 754#L779-1true assume !(0 == ~E_1~0); 584#L784-1true assume !(0 == ~E_2~0); 401#L789-1true assume !(0 == ~E_3~0); 112#L794-1true assume !(0 == ~E_4~0); 728#L799-1true assume !(0 == ~E_5~0); 647#L804-1true assume !(0 == ~E_6~0); 468#L809-1true assume 0 == ~E_7~0;~E_7~0 := 1; 289#L814-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 200#L351true assume 1 == ~m_pc~0; 274#L352true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 619#L362true is_master_triggered_#res := is_master_triggered_~__retres1~0; 678#L363true activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 360#L920true assume !(0 != activate_threads_~tmp~1); 361#L920-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 334#L370true assume !(1 == ~t1_pc~0); 340#L370-2true is_transmit1_triggered_~__retres1~1 := 0; 708#L381true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 767#L382true activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 145#L928true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 51#L928-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 445#L389true assume 1 == ~t2_pc~0; 483#L390true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 38#L400true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 103#L401true activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 654#L936true assume !(0 != activate_threads_~tmp___1~0); 655#L936-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 533#L408true assume !(1 == ~t3_pc~0); 537#L408-2true is_transmit3_triggered_~__retres1~3 := 0; 129#L419true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 106#L420true activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 384#L944true assume !(0 != activate_threads_~tmp___2~0); 379#L944-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 747#L427true assume 1 == ~t4_pc~0; 617#L428true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 371#L438true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 197#L439true activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 89#L952true assume !(0 != activate_threads_~tmp___3~0); 91#L952-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 70#L446true assume !(1 == ~t5_pc~0); 73#L446-2true is_transmit5_triggered_~__retres1~5 := 0; 455#L457true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 349#L458true activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 589#L960true assume !(0 != activate_threads_~tmp___4~0); 578#L960-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 159#L465true assume 1 == ~t6_pc~0; 34#L466true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 568#L476true is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 442#L477true activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 300#L968true assume !(0 != activate_threads_~tmp___5~0); 302#L968-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 266#L484true assume 1 == ~t7_pc~0; 142#L485true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 687#L495true is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 544#L496true activate_threads_#t~ret16 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 697#L976true assume !(0 != activate_threads_~tmp___6~0); 691#L976-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 508#L827true assume !(1 == ~M_E~0); 499#L827-2true assume !(1 == ~T1_E~0); 363#L832-1true assume !(1 == ~T2_E~0); 225#L837-1true assume !(1 == ~T3_E~0); 80#L842-1true assume !(1 == ~T4_E~0); 688#L847-1true assume 1 == ~T5_E~0;~T5_E~0 := 2; 414#L852-1true assume !(1 == ~T6_E~0); 204#L857-1true assume !(1 == ~T7_E~0); 52#L862-1true assume !(1 == ~E_1~0); 752#L867-1true assume !(1 == ~E_2~0); 580#L872-1true assume !(1 == ~E_3~0); 307#L877-1true assume !(1 == ~E_4~0); 114#L882-1true assume !(1 == ~E_5~0); 734#L887-1true assume 1 == ~E_6~0;~E_6~0 := 2; 656#L892-1true assume !(1 == ~E_7~0); 472#L897-1true assume { :end_inline_reset_delta_events } true; 428#L1138-3true [2018-11-18 10:50:51,467 INFO L796 eck$LassoCheckResult]: Loop: 428#L1138-3true assume true; 426#L1138-1true assume !false; 473#L1139true start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 449#L719true assume !true; 783#L734true assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 369#L504-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 358#L744-3true assume 0 == ~M_E~0;~M_E~0 := 1; 345#L744-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 231#L749-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 87#L754-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 682#L759-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 408#L764-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 201#L769-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 45#L774-3true assume !(0 == ~T7_E~0); 749#L779-3true assume 0 == ~E_1~0;~E_1~0 := 1; 574#L784-3true assume 0 == ~E_2~0;~E_2~0 := 1; 404#L789-3true assume 0 == ~E_3~0;~E_3~0 := 1; 113#L794-3true assume 0 == ~E_4~0;~E_4~0 := 1; 730#L799-3true assume 0 == ~E_5~0;~E_5~0 := 1; 650#L804-3true assume 0 == ~E_6~0;~E_6~0 := 1; 469#L809-3true assume 0 == ~E_7~0;~E_7~0 := 1; 293#L814-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 283#L351-24true assume 1 == ~m_pc~0; 242#L352-8true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 599#L362-8true is_master_triggered_#res := is_master_triggered_~__retres1~0; 660#L363-8true activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 328#L920-24true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 312#L920-26true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 407#L370-24true assume 1 == ~t1_pc~0; 389#L371-8true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 706#L381-8true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 763#L382-8true activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 12#L928-24true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 15#L928-26true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 410#L389-24true assume 1 == ~t2_pc~0; 474#L390-8true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 13#L400-8true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 93#L401-8true activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 527#L936-24true assume !(0 != activate_threads_~tmp___1~0); 509#L936-26true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 504#L408-24true assume 1 == ~t3_pc~0; 593#L409-8true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 125#L419-8true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 176#L420-8true activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 210#L944-24true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 212#L944-26true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 622#L427-24true assume 1 == ~t4_pc~0; 596#L428-8true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 209#L438-8true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 195#L439-8true activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 67#L952-24true assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 737#L952-26true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 731#L446-24true assume !(1 == ~t5_pc~0); 716#L446-26true is_transmit5_triggered_~__retres1~5 := 0; 453#L457-8true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 324#L458-8true activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 554#L960-24true assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 555#L960-26true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 44#L465-24true assume !(1 == ~t6_pc~0); 48#L465-26true is_transmit6_triggered_~__retres1~6 := 0; 551#L476-8true is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 437#L477-8true activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 263#L968-24true assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 240#L968-26true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 229#L484-24true assume !(1 == ~t7_pc~0); 232#L484-26true is_transmit7_triggered_~__retres1~7 := 0; 671#L495-8true is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 521#L496-8true activate_threads_#t~ret16 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 760#L976-24true assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 764#L976-26true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 501#L827-3true assume 1 == ~M_E~0;~M_E~0 := 2; 503#L827-5true assume !(1 == ~T1_E~0); 353#L832-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 227#L837-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 83#L842-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 689#L847-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 417#L852-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 205#L857-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 57#L862-3true assume 1 == ~E_1~0;~E_1~0 := 2; 753#L867-3true assume !(1 == ~E_2~0); 582#L872-3true assume 1 == ~E_3~0;~E_3~0 := 2; 310#L877-3true assume 1 == ~E_4~0;~E_4~0 := 2; 115#L882-3true assume 1 == ~E_5~0;~E_5~0 := 2; 726#L887-3true assume 1 == ~E_6~0;~E_6~0 := 2; 646#L892-3true assume 1 == ~E_7~0;~E_7~0 := 2; 467#L897-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 745#L559-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 720#L601-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 777#L602-1true start_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 528#L1157true assume !(0 == start_simulation_~tmp~3); 510#L1157-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 746#L559-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 722#L601-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 778#L602-2true stop_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 661#L1112true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 330#L1119true stop_simulation_#res := stop_simulation_~__retres2~0; 390#L1120true start_simulation_#t~ret19 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 150#L1170true assume !(0 != start_simulation_~tmp___0~1); 428#L1138-3true [2018-11-18 10:50:51,473 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:51,473 INFO L82 PathProgramCache]: Analyzing trace with hash -171938705, now seen corresponding path program 1 times [2018-11-18 10:50:51,475 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:51,475 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:51,509 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:51,510 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:50:51,510 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:51,536 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:50:51,590 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:50:51,592 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:50:51,593 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:50:51,597 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 10:50:51,597 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:51,597 INFO L82 PathProgramCache]: Analyzing trace with hash -975936999, now seen corresponding path program 1 times [2018-11-18 10:50:51,597 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:51,597 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:51,598 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:51,598 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:50:51,599 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:51,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:50:51,617 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:50:51,618 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:50:51,618 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 10:50:51,619 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 10:50:51,628 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 10:50:51,629 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:50:51,630 INFO L87 Difference]: Start difference. First operand 786 states. Second operand 3 states. [2018-11-18 10:50:51,667 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:50:51,668 INFO L93 Difference]: Finished difference Result 785 states and 1165 transitions. [2018-11-18 10:50:51,671 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 10:50:51,672 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 785 states and 1165 transitions. [2018-11-18 10:50:51,679 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 678 [2018-11-18 10:50:51,687 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 785 states to 779 states and 1159 transitions. [2018-11-18 10:50:51,688 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 779 [2018-11-18 10:50:51,690 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 779 [2018-11-18 10:50:51,690 INFO L73 IsDeterministic]: Start isDeterministic. Operand 779 states and 1159 transitions. [2018-11-18 10:50:51,694 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 10:50:51,694 INFO L705 BuchiCegarLoop]: Abstraction has 779 states and 1159 transitions. [2018-11-18 10:50:51,711 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 779 states and 1159 transitions. [2018-11-18 10:50:51,738 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 779 to 779. [2018-11-18 10:50:51,739 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 779 states. [2018-11-18 10:50:51,742 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 779 states to 779 states and 1159 transitions. [2018-11-18 10:50:51,743 INFO L728 BuchiCegarLoop]: Abstraction has 779 states and 1159 transitions. [2018-11-18 10:50:51,743 INFO L608 BuchiCegarLoop]: Abstraction has 779 states and 1159 transitions. [2018-11-18 10:50:51,743 INFO L442 BuchiCegarLoop]: ======== Iteration 2============ [2018-11-18 10:50:51,743 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 779 states and 1159 transitions. [2018-11-18 10:50:51,747 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 678 [2018-11-18 10:50:51,747 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:50:51,747 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:50:51,749 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:51,749 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:51,750 INFO L794 eck$LassoCheckResult]: Stem: 1956#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 1877#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1878#L1101 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 1940#L504 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1583#L511 assume 1 == ~m_i~0;~m_st~0 := 0; 1584#L511-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1750#L516-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2155#L521-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2091#L526-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1845#L531-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1846#L536-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2200#L541-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 2073#L546-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2074#L744 assume !(0 == ~M_E~0); 2078#L744-2 assume !(0 == ~T1_E~0); 1928#L749-1 assume !(0 == ~T2_E~0); 1730#L754-1 assume !(0 == ~T3_E~0); 1731#L759-1 assume !(0 == ~T4_E~0); 2133#L764-1 assume !(0 == ~T5_E~0); 1908#L769-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1685#L774-1 assume !(0 == ~T7_E~0); 1686#L779-1 assume !(0 == ~E_1~0); 2272#L784-1 assume !(0 == ~E_2~0); 2118#L789-1 assume !(0 == ~E_3~0); 1767#L794-1 assume !(0 == ~E_4~0); 1768#L799-1 assume !(0 == ~E_5~0); 2309#L804-1 assume !(0 == ~E_6~0); 2177#L809-1 assume 0 == ~E_7~0;~E_7~0 := 1; 1988#L814-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1901#L351 assume 1 == ~m_pc~0; 1902#L352 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 1885#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2303#L363 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2085#L920 assume !(0 != activate_threads_~tmp~1); 2086#L920-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2050#L370 assume !(1 == ~t1_pc~0); 2051#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 2060#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2337#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1831#L928 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1675#L928-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1676#L389 assume 1 == ~t2_pc~0; 2159#L390 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 1652#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1653#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1752#L936 assume !(0 != activate_threads_~tmp___1~0); 2313#L936-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2239#L408 assume !(1 == ~t3_pc~0); 2184#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 1804#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1755#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1756#L944 assume !(0 != activate_threads_~tmp___2~0); 2103#L944-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2104#L427 assume 1 == ~t4_pc~0; 2299#L428 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2095#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1898#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1737#L952 assume !(0 != activate_threads_~tmp___3~0); 1738#L952-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1706#L446 assume !(1 == ~t5_pc~0); 1707#L446-2 is_transmit5_triggered_~__retres1~5 := 0; 1712#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2075#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2076#L960 assume !(0 != activate_threads_~tmp___4~0); 2268#L960-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1847#L465 assume 1 == ~t6_pc~0; 1643#L466 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 1644#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2156#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1995#L968 assume !(0 != activate_threads_~tmp___5~0); 1996#L968-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1972#L484 assume 1 == ~t7_pc~0; 1827#L485 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 1828#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 2251#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2252#L976 assume !(0 != activate_threads_~tmp___6~0); 2320#L976-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2216#L827 assume !(1 == ~M_E~0); 2203#L827-2 assume !(1 == ~T1_E~0); 2088#L832-1 assume !(1 == ~T2_E~0); 1926#L837-1 assume !(1 == ~T3_E~0); 1723#L842-1 assume !(1 == ~T4_E~0); 1724#L847-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2129#L852-1 assume !(1 == ~T6_E~0); 1906#L857-1 assume !(1 == ~T7_E~0); 1677#L862-1 assume !(1 == ~E_1~0); 1678#L867-1 assume !(1 == ~E_2~0); 2270#L872-1 assume !(1 == ~E_3~0); 2004#L877-1 assume !(1 == ~E_4~0); 1771#L882-1 assume !(1 == ~E_5~0); 1772#L887-1 assume 1 == ~E_6~0;~E_6~0 := 2; 2314#L892-1 assume !(1 == ~E_7~0); 2182#L897-1 assume { :end_inline_reset_delta_events } true; 1835#L1138-3 [2018-11-18 10:50:51,750 INFO L796 eck$LassoCheckResult]: Loop: 1835#L1138-3 assume true; 2141#L1138-1 assume !false; 2142#L1139 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 1931#L719 assume true; 2163#L611-1 assume !false; 2067#L612 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 2068#L559 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 1851#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 2345#L602 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 1979#L616 assume !(0 != eval_~tmp~0); 1981#L734 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 2093#L504-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 2083#L744-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2069#L744-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1932#L749-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1734#L754-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1735#L759-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2122#L764-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1903#L769-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1667#L774-3 assume !(0 == ~T7_E~0); 1668#L779-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2265#L784-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2119#L789-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1769#L794-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1770#L799-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2312#L804-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2178#L809-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1992#L814-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1984#L351-24 assume 1 == ~m_pc~0; 1941#L352-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 1942#L362-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2280#L363-8 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 2040#L920-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2013#L920-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2014#L370-24 assume 1 == ~t1_pc~0; 2112#L371-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 2113#L381-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2336#L382-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1601#L928-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 1602#L928-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1607#L389-24 assume !(1 == ~t2_pc~0); 2124#L389-26 is_transmit2_triggered_~__retres1~2 := 0; 1603#L400-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1604#L401-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1741#L936-24 assume !(0 != activate_threads_~tmp___1~0); 2217#L936-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2209#L408-24 assume 1 == ~t3_pc~0; 2210#L409-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1796#L419-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1797#L420-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1867#L944-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1914#L944-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1916#L427-24 assume 1 == ~t4_pc~0; 2275#L428-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 1913#L438-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1896#L439-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1699#L952-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 1700#L952-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2349#L446-24 assume 1 == ~t5_pc~0; 2331#L447-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 2167#L457-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2032#L458-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2033#L960-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 2260#L960-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1666#L465-24 assume 1 == ~t6_pc~0; 1635#L466-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 1636#L476-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2152#L477-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1967#L968-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 1939#L968-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1929#L484-24 assume 1 == ~t7_pc~0; 1788#L485-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 1789#L495-8 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 2226#L496-8 activate_threads_#t~ret16 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2227#L976-24 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 2353#L976-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2207#L827-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2208#L827-5 assume !(1 == ~T1_E~0); 2079#L832-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1927#L837-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1728#L842-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1729#L847-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2132#L852-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1907#L857-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1683#L862-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1684#L867-3 assume !(1 == ~E_2~0); 2271#L872-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2009#L877-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1773#L882-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1774#L887-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2308#L892-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2175#L897-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 2176#L559-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 1840#L601-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 2347#L602-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 2231#L1157 assume !(0 == start_simulation_~tmp~3); 1951#L1157-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 2218#L559-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 1843#L601-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 2348#L602-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 2315#L1112 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2042#L1119 stop_simulation_#res := stop_simulation_~__retres2~0; 2043#L1120 start_simulation_#t~ret19 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 1834#L1170 assume !(0 != start_simulation_~tmp___0~1); 1835#L1138-3 [2018-11-18 10:50:51,751 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:51,751 INFO L82 PathProgramCache]: Analyzing trace with hash 598794861, now seen corresponding path program 1 times [2018-11-18 10:50:51,751 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:51,751 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:51,752 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:51,752 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:50:51,752 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:51,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:50:51,800 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:50:51,800 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:50:51,800 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:50:51,801 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 10:50:51,801 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:51,801 INFO L82 PathProgramCache]: Analyzing trace with hash 2140214550, now seen corresponding path program 1 times [2018-11-18 10:50:51,801 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:51,801 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:51,802 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:51,802 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:50:51,802 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:51,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:50:51,873 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:50:51,873 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:50:51,873 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:50:51,873 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 10:50:51,874 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 10:50:51,874 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:50:51,874 INFO L87 Difference]: Start difference. First operand 779 states and 1159 transitions. cyclomatic complexity: 381 Second operand 3 states. [2018-11-18 10:50:51,885 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:50:51,886 INFO L93 Difference]: Finished difference Result 779 states and 1158 transitions. [2018-11-18 10:50:51,886 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 10:50:51,887 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 779 states and 1158 transitions. [2018-11-18 10:50:51,890 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 678 [2018-11-18 10:50:51,893 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 779 states to 779 states and 1158 transitions. [2018-11-18 10:50:51,893 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 779 [2018-11-18 10:50:51,894 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 779 [2018-11-18 10:50:51,894 INFO L73 IsDeterministic]: Start isDeterministic. Operand 779 states and 1158 transitions. [2018-11-18 10:50:51,895 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 10:50:51,895 INFO L705 BuchiCegarLoop]: Abstraction has 779 states and 1158 transitions. [2018-11-18 10:50:51,896 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 779 states and 1158 transitions. [2018-11-18 10:50:51,905 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 779 to 779. [2018-11-18 10:50:51,905 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 779 states. [2018-11-18 10:50:51,907 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 779 states to 779 states and 1158 transitions. [2018-11-18 10:50:51,907 INFO L728 BuchiCegarLoop]: Abstraction has 779 states and 1158 transitions. [2018-11-18 10:50:51,907 INFO L608 BuchiCegarLoop]: Abstraction has 779 states and 1158 transitions. [2018-11-18 10:50:51,907 INFO L442 BuchiCegarLoop]: ======== Iteration 3============ [2018-11-18 10:50:51,907 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 779 states and 1158 transitions. [2018-11-18 10:50:51,909 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 678 [2018-11-18 10:50:51,910 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:50:51,910 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:50:51,911 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:51,911 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:51,912 INFO L794 eck$LassoCheckResult]: Stem: 3521#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 3442#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 3443#L1101 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 3505#L504 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3148#L511 assume 1 == ~m_i~0;~m_st~0 := 0; 3149#L511-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3315#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3720#L521-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3656#L526-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3410#L531-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3411#L536-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3765#L541-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3638#L546-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3639#L744 assume !(0 == ~M_E~0); 3643#L744-2 assume !(0 == ~T1_E~0); 3493#L749-1 assume !(0 == ~T2_E~0); 3295#L754-1 assume !(0 == ~T3_E~0); 3296#L759-1 assume !(0 == ~T4_E~0); 3698#L764-1 assume !(0 == ~T5_E~0); 3473#L769-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3250#L774-1 assume !(0 == ~T7_E~0); 3251#L779-1 assume !(0 == ~E_1~0); 3837#L784-1 assume !(0 == ~E_2~0); 3683#L789-1 assume !(0 == ~E_3~0); 3332#L794-1 assume !(0 == ~E_4~0); 3333#L799-1 assume !(0 == ~E_5~0); 3874#L804-1 assume !(0 == ~E_6~0); 3742#L809-1 assume 0 == ~E_7~0;~E_7~0 := 1; 3553#L814-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3466#L351 assume 1 == ~m_pc~0; 3467#L352 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 3450#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3868#L363 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 3650#L920 assume !(0 != activate_threads_~tmp~1); 3651#L920-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3615#L370 assume !(1 == ~t1_pc~0); 3616#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 3625#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3902#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3396#L928 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3240#L928-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3241#L389 assume 1 == ~t2_pc~0; 3724#L390 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 3217#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3218#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3317#L936 assume !(0 != activate_threads_~tmp___1~0); 3878#L936-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3804#L408 assume !(1 == ~t3_pc~0); 3749#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 3369#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3320#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3321#L944 assume !(0 != activate_threads_~tmp___2~0); 3668#L944-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3669#L427 assume 1 == ~t4_pc~0; 3864#L428 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3660#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3463#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3302#L952 assume !(0 != activate_threads_~tmp___3~0); 3303#L952-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3271#L446 assume !(1 == ~t5_pc~0); 3272#L446-2 is_transmit5_triggered_~__retres1~5 := 0; 3277#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3640#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3641#L960 assume !(0 != activate_threads_~tmp___4~0); 3833#L960-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 3412#L465 assume 1 == ~t6_pc~0; 3208#L466 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 3209#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 3721#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3560#L968 assume !(0 != activate_threads_~tmp___5~0); 3561#L968-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 3537#L484 assume 1 == ~t7_pc~0; 3392#L485 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 3393#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 3816#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3817#L976 assume !(0 != activate_threads_~tmp___6~0); 3885#L976-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3781#L827 assume !(1 == ~M_E~0); 3768#L827-2 assume !(1 == ~T1_E~0); 3653#L832-1 assume !(1 == ~T2_E~0); 3491#L837-1 assume !(1 == ~T3_E~0); 3288#L842-1 assume !(1 == ~T4_E~0); 3289#L847-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3694#L852-1 assume !(1 == ~T6_E~0); 3471#L857-1 assume !(1 == ~T7_E~0); 3242#L862-1 assume !(1 == ~E_1~0); 3243#L867-1 assume !(1 == ~E_2~0); 3835#L872-1 assume !(1 == ~E_3~0); 3569#L877-1 assume !(1 == ~E_4~0); 3336#L882-1 assume !(1 == ~E_5~0); 3337#L887-1 assume 1 == ~E_6~0;~E_6~0 := 2; 3879#L892-1 assume !(1 == ~E_7~0); 3747#L897-1 assume { :end_inline_reset_delta_events } true; 3400#L1138-3 [2018-11-18 10:50:51,912 INFO L796 eck$LassoCheckResult]: Loop: 3400#L1138-3 assume true; 3706#L1138-1 assume !false; 3707#L1139 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 3496#L719 assume true; 3728#L611-1 assume !false; 3632#L612 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 3633#L559 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 3416#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 3910#L602 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 3544#L616 assume !(0 != eval_~tmp~0); 3546#L734 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 3658#L504-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 3648#L744-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3634#L744-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3497#L749-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3299#L754-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3300#L759-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3687#L764-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3468#L769-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3232#L774-3 assume !(0 == ~T7_E~0); 3233#L779-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3830#L784-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3684#L789-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3334#L794-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3335#L799-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3877#L804-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3743#L809-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3557#L814-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3549#L351-24 assume 1 == ~m_pc~0; 3506#L352-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 3507#L362-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3845#L363-8 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 3605#L920-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 3578#L920-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3579#L370-24 assume 1 == ~t1_pc~0; 3677#L371-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 3678#L381-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3901#L382-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3166#L928-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 3167#L928-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3172#L389-24 assume !(1 == ~t2_pc~0); 3689#L389-26 is_transmit2_triggered_~__retres1~2 := 0; 3168#L400-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3169#L401-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3306#L936-24 assume !(0 != activate_threads_~tmp___1~0); 3782#L936-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3774#L408-24 assume 1 == ~t3_pc~0; 3775#L409-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 3361#L419-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3362#L420-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3432#L944-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 3479#L944-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3481#L427-24 assume 1 == ~t4_pc~0; 3840#L428-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3478#L438-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3461#L439-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3264#L952-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 3265#L952-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3914#L446-24 assume 1 == ~t5_pc~0; 3896#L447-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 3732#L457-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3597#L458-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3598#L960-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 3825#L960-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 3231#L465-24 assume 1 == ~t6_pc~0; 3200#L466-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 3201#L476-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 3717#L477-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3532#L968-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 3504#L968-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 3494#L484-24 assume 1 == ~t7_pc~0; 3353#L485-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 3354#L495-8 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 3791#L496-8 activate_threads_#t~ret16 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3792#L976-24 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 3918#L976-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3772#L827-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3773#L827-5 assume !(1 == ~T1_E~0); 3644#L832-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3492#L837-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3293#L842-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3294#L847-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3697#L852-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3472#L857-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3248#L862-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3249#L867-3 assume !(1 == ~E_2~0); 3836#L872-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3574#L877-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3338#L882-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3339#L887-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3873#L892-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3740#L897-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 3741#L559-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 3405#L601-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 3912#L602-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 3796#L1157 assume !(0 == start_simulation_~tmp~3); 3516#L1157-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 3783#L559-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 3408#L601-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 3913#L602-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 3880#L1112 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 3607#L1119 stop_simulation_#res := stop_simulation_~__retres2~0; 3608#L1120 start_simulation_#t~ret19 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 3399#L1170 assume !(0 != start_simulation_~tmp___0~1); 3400#L1138-3 [2018-11-18 10:50:51,913 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:51,913 INFO L82 PathProgramCache]: Analyzing trace with hash 1185071083, now seen corresponding path program 1 times [2018-11-18 10:50:51,913 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:51,913 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:51,914 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:51,914 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:50:51,914 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:51,920 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:50:51,953 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:50:51,953 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:50:51,953 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:50:51,954 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 10:50:51,954 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:51,954 INFO L82 PathProgramCache]: Analyzing trace with hash 2140214550, now seen corresponding path program 2 times [2018-11-18 10:50:51,954 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:51,954 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:51,955 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:51,955 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:50:51,955 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:51,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:50:52,024 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:50:52,024 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:50:52,024 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:50:52,025 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 10:50:52,025 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 10:50:52,025 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:50:52,025 INFO L87 Difference]: Start difference. First operand 779 states and 1158 transitions. cyclomatic complexity: 380 Second operand 3 states. [2018-11-18 10:50:52,054 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:50:52,054 INFO L93 Difference]: Finished difference Result 779 states and 1157 transitions. [2018-11-18 10:50:52,055 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 10:50:52,055 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 779 states and 1157 transitions. [2018-11-18 10:50:52,059 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 678 [2018-11-18 10:50:52,062 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 779 states to 779 states and 1157 transitions. [2018-11-18 10:50:52,062 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 779 [2018-11-18 10:50:52,063 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 779 [2018-11-18 10:50:52,063 INFO L73 IsDeterministic]: Start isDeterministic. Operand 779 states and 1157 transitions. [2018-11-18 10:50:52,064 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 10:50:52,064 INFO L705 BuchiCegarLoop]: Abstraction has 779 states and 1157 transitions. [2018-11-18 10:50:52,065 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 779 states and 1157 transitions. [2018-11-18 10:50:52,072 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 779 to 779. [2018-11-18 10:50:52,072 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 779 states. [2018-11-18 10:50:52,074 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 779 states to 779 states and 1157 transitions. [2018-11-18 10:50:52,074 INFO L728 BuchiCegarLoop]: Abstraction has 779 states and 1157 transitions. [2018-11-18 10:50:52,074 INFO L608 BuchiCegarLoop]: Abstraction has 779 states and 1157 transitions. [2018-11-18 10:50:52,074 INFO L442 BuchiCegarLoop]: ======== Iteration 4============ [2018-11-18 10:50:52,074 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 779 states and 1157 transitions. [2018-11-18 10:50:52,077 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 678 [2018-11-18 10:50:52,077 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:50:52,078 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:50:52,079 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:52,079 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:52,079 INFO L794 eck$LassoCheckResult]: Stem: 5088#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 5008#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 5009#L1101 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 5074#L504 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4713#L511 assume 1 == ~m_i~0;~m_st~0 := 0; 4714#L511-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4880#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5285#L521-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5221#L526-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4975#L531-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4976#L536-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5330#L541-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5203#L546-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5204#L744 assume !(0 == ~M_E~0); 5208#L744-2 assume !(0 == ~T1_E~0); 5059#L749-1 assume !(0 == ~T2_E~0); 4860#L754-1 assume !(0 == ~T3_E~0); 4861#L759-1 assume !(0 == ~T4_E~0); 5263#L764-1 assume !(0 == ~T5_E~0); 5038#L769-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4815#L774-1 assume !(0 == ~T7_E~0); 4816#L779-1 assume !(0 == ~E_1~0); 5402#L784-1 assume !(0 == ~E_2~0); 5248#L789-1 assume !(0 == ~E_3~0); 4897#L794-1 assume !(0 == ~E_4~0); 4898#L799-1 assume !(0 == ~E_5~0); 5440#L804-1 assume !(0 == ~E_6~0); 5307#L809-1 assume 0 == ~E_7~0;~E_7~0 := 1; 5119#L814-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5031#L351 assume 1 == ~m_pc~0; 5032#L352 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 5015#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5435#L363 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 5215#L920 assume !(0 != activate_threads_~tmp~1); 5216#L920-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5180#L370 assume !(1 == ~t1_pc~0); 5181#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 5190#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5467#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 4961#L928 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4805#L928-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4806#L389 assume 1 == ~t2_pc~0; 5289#L390 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4785#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4786#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 4882#L936 assume !(0 != activate_threads_~tmp___1~0); 5443#L936-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5369#L408 assume !(1 == ~t3_pc~0); 5314#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 4937#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4885#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4886#L944 assume !(0 != activate_threads_~tmp___2~0); 5233#L944-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5234#L427 assume 1 == ~t4_pc~0; 5429#L428 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5225#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5028#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4867#L952 assume !(0 != activate_threads_~tmp___3~0); 4868#L952-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4836#L446 assume !(1 == ~t5_pc~0); 4837#L446-2 is_transmit5_triggered_~__retres1~5 := 0; 4842#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5205#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5206#L960 assume !(0 != activate_threads_~tmp___4~0); 5398#L960-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 4977#L465 assume 1 == ~t6_pc~0; 4774#L466 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 4775#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 5286#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 5125#L968 assume !(0 != activate_threads_~tmp___5~0); 5126#L968-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 5103#L484 assume 1 == ~t7_pc~0; 4957#L485 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 4958#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 5381#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 5382#L976 assume !(0 != activate_threads_~tmp___6~0); 5450#L976-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5346#L827 assume !(1 == ~M_E~0); 5333#L827-2 assume !(1 == ~T1_E~0); 5218#L832-1 assume !(1 == ~T2_E~0); 5056#L837-1 assume !(1 == ~T3_E~0); 4853#L842-1 assume !(1 == ~T4_E~0); 4854#L847-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5261#L852-1 assume !(1 == ~T6_E~0); 5036#L857-1 assume !(1 == ~T7_E~0); 4809#L862-1 assume !(1 == ~E_1~0); 4810#L867-1 assume !(1 == ~E_2~0); 5400#L872-1 assume !(1 == ~E_3~0); 5134#L877-1 assume !(1 == ~E_4~0); 4901#L882-1 assume !(1 == ~E_5~0); 4902#L887-1 assume 1 == ~E_6~0;~E_6~0 := 2; 5444#L892-1 assume !(1 == ~E_7~0); 5312#L897-1 assume { :end_inline_reset_delta_events } true; 4965#L1138-3 [2018-11-18 10:50:52,080 INFO L796 eck$LassoCheckResult]: Loop: 4965#L1138-3 assume true; 5273#L1138-1 assume !false; 5274#L1139 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 5061#L719 assume true; 5293#L611-1 assume !false; 5197#L612 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 5198#L559 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 4981#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 5475#L602 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 5109#L616 assume !(0 != eval_~tmp~0); 5111#L734 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 5223#L504-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 5213#L744-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5199#L744-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5062#L749-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4865#L754-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4866#L759-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5252#L764-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5033#L769-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4797#L774-3 assume !(0 == ~T7_E~0); 4798#L779-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5395#L784-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5249#L789-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4899#L794-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4900#L799-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5442#L804-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5308#L809-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5122#L814-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5113#L351-24 assume !(1 == ~m_pc~0); 5072#L351-26 is_master_triggered_~__retres1~0 := 0; 5071#L362-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 5410#L363-8 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 5170#L920-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 5143#L920-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 5144#L370-24 assume 1 == ~t1_pc~0; 5242#L371-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 5243#L381-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5466#L382-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 4731#L928-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4732#L928-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4737#L389-24 assume !(1 == ~t2_pc~0); 5254#L389-26 is_transmit2_triggered_~__retres1~2 := 0; 4733#L400-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4734#L401-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 4871#L936-24 assume !(0 != activate_threads_~tmp___1~0); 5347#L936-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 5339#L408-24 assume 1 == ~t3_pc~0; 5340#L409-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 4926#L419-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4927#L420-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4997#L944-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 5044#L944-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5046#L427-24 assume 1 == ~t4_pc~0; 5405#L428-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5043#L438-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 5026#L439-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4829#L952-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 4830#L952-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5479#L446-24 assume 1 == ~t5_pc~0; 5461#L447-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 5297#L457-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 5162#L458-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5163#L960-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 5390#L960-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 4796#L465-24 assume 1 == ~t6_pc~0; 4765#L466-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 4766#L476-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 5282#L477-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 5097#L968-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 5069#L968-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 5058#L484-24 assume 1 == ~t7_pc~0; 4918#L485-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 4919#L495-8 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 5356#L496-8 activate_threads_#t~ret16 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 5357#L976-24 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 5483#L976-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5337#L827-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5338#L827-5 assume !(1 == ~T1_E~0); 5209#L832-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5057#L837-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4858#L842-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4859#L847-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5262#L852-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5037#L857-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4813#L862-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4814#L867-3 assume !(1 == ~E_2~0); 5401#L872-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5139#L877-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4903#L882-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4904#L887-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5438#L892-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5305#L897-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 5306#L559-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 4970#L601-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 5477#L602-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 5361#L1157 assume !(0 == start_simulation_~tmp~3); 5081#L1157-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 5348#L559-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 4973#L601-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 5478#L602-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 5445#L1112 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5172#L1119 stop_simulation_#res := stop_simulation_~__retres2~0; 5173#L1120 start_simulation_#t~ret19 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 4964#L1170 assume !(0 != start_simulation_~tmp___0~1); 4965#L1138-3 [2018-11-18 10:50:52,080 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:52,080 INFO L82 PathProgramCache]: Analyzing trace with hash -1151321427, now seen corresponding path program 1 times [2018-11-18 10:50:52,080 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:52,080 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:52,081 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:52,081 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:50:52,081 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:52,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:50:52,110 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:50:52,111 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:50:52,111 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:50:52,111 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 10:50:52,111 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:52,111 INFO L82 PathProgramCache]: Analyzing trace with hash -2075634891, now seen corresponding path program 1 times [2018-11-18 10:50:52,113 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:52,113 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:52,113 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:52,113 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:50:52,114 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:52,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:50:52,162 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:50:52,162 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:50:52,163 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:50:52,163 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 10:50:52,163 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 10:50:52,163 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:50:52,163 INFO L87 Difference]: Start difference. First operand 779 states and 1157 transitions. cyclomatic complexity: 379 Second operand 3 states. [2018-11-18 10:50:52,173 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:50:52,173 INFO L93 Difference]: Finished difference Result 779 states and 1156 transitions. [2018-11-18 10:50:52,176 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 10:50:52,176 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 779 states and 1156 transitions. [2018-11-18 10:50:52,179 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 678 [2018-11-18 10:50:52,182 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 779 states to 779 states and 1156 transitions. [2018-11-18 10:50:52,182 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 779 [2018-11-18 10:50:52,183 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 779 [2018-11-18 10:50:52,183 INFO L73 IsDeterministic]: Start isDeterministic. Operand 779 states and 1156 transitions. [2018-11-18 10:50:52,184 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 10:50:52,184 INFO L705 BuchiCegarLoop]: Abstraction has 779 states and 1156 transitions. [2018-11-18 10:50:52,185 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 779 states and 1156 transitions. [2018-11-18 10:50:52,192 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 779 to 779. [2018-11-18 10:50:52,192 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 779 states. [2018-11-18 10:50:52,194 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 779 states to 779 states and 1156 transitions. [2018-11-18 10:50:52,194 INFO L728 BuchiCegarLoop]: Abstraction has 779 states and 1156 transitions. [2018-11-18 10:50:52,194 INFO L608 BuchiCegarLoop]: Abstraction has 779 states and 1156 transitions. [2018-11-18 10:50:52,194 INFO L442 BuchiCegarLoop]: ======== Iteration 5============ [2018-11-18 10:50:52,194 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 779 states and 1156 transitions. [2018-11-18 10:50:52,196 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 678 [2018-11-18 10:50:52,197 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:50:52,197 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:50:52,198 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:52,198 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:52,198 INFO L794 eck$LassoCheckResult]: Stem: 6651#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 6572#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 6573#L1101 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 6635#L504 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6278#L511 assume 1 == ~m_i~0;~m_st~0 := 0; 6279#L511-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6445#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6850#L521-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6786#L526-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6540#L531-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6541#L536-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6895#L541-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6768#L546-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6769#L744 assume !(0 == ~M_E~0); 6773#L744-2 assume !(0 == ~T1_E~0); 6624#L749-1 assume !(0 == ~T2_E~0); 6425#L754-1 assume !(0 == ~T3_E~0); 6426#L759-1 assume !(0 == ~T4_E~0); 6828#L764-1 assume !(0 == ~T5_E~0); 6603#L769-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6380#L774-1 assume !(0 == ~T7_E~0); 6381#L779-1 assume !(0 == ~E_1~0); 6967#L784-1 assume !(0 == ~E_2~0); 6813#L789-1 assume !(0 == ~E_3~0); 6462#L794-1 assume !(0 == ~E_4~0); 6463#L799-1 assume !(0 == ~E_5~0); 7004#L804-1 assume !(0 == ~E_6~0); 6872#L809-1 assume 0 == ~E_7~0;~E_7~0 := 1; 6683#L814-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6596#L351 assume 1 == ~m_pc~0; 6597#L352 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 6580#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6998#L363 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 6780#L920 assume !(0 != activate_threads_~tmp~1); 6781#L920-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6745#L370 assume !(1 == ~t1_pc~0); 6746#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 6755#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7032#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 6526#L928 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 6370#L928-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6371#L389 assume 1 == ~t2_pc~0; 6854#L390 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 6347#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6348#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 6447#L936 assume !(0 != activate_threads_~tmp___1~0); 7008#L936-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6934#L408 assume !(1 == ~t3_pc~0); 6879#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 6499#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6450#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 6451#L944 assume !(0 != activate_threads_~tmp___2~0); 6798#L944-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6799#L427 assume 1 == ~t4_pc~0; 6994#L428 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 6790#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6593#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 6432#L952 assume !(0 != activate_threads_~tmp___3~0); 6433#L952-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 6401#L446 assume !(1 == ~t5_pc~0); 6402#L446-2 is_transmit5_triggered_~__retres1~5 := 0; 6407#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 6770#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 6771#L960 assume !(0 != activate_threads_~tmp___4~0); 6963#L960-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 6542#L465 assume 1 == ~t6_pc~0; 6338#L466 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 6339#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 6851#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 6690#L968 assume !(0 != activate_threads_~tmp___5~0); 6691#L968-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 6668#L484 assume 1 == ~t7_pc~0; 6522#L485 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 6523#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 6946#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 6947#L976 assume !(0 != activate_threads_~tmp___6~0); 7015#L976-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6911#L827 assume !(1 == ~M_E~0); 6898#L827-2 assume !(1 == ~T1_E~0); 6783#L832-1 assume !(1 == ~T2_E~0); 6621#L837-1 assume !(1 == ~T3_E~0); 6418#L842-1 assume !(1 == ~T4_E~0); 6419#L847-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6824#L852-1 assume !(1 == ~T6_E~0); 6601#L857-1 assume !(1 == ~T7_E~0); 6372#L862-1 assume !(1 == ~E_1~0); 6373#L867-1 assume !(1 == ~E_2~0); 6965#L872-1 assume !(1 == ~E_3~0); 6699#L877-1 assume !(1 == ~E_4~0); 6466#L882-1 assume !(1 == ~E_5~0); 6467#L887-1 assume 1 == ~E_6~0;~E_6~0 := 2; 7009#L892-1 assume !(1 == ~E_7~0); 6877#L897-1 assume { :end_inline_reset_delta_events } true; 6530#L1138-3 [2018-11-18 10:50:52,199 INFO L796 eck$LassoCheckResult]: Loop: 6530#L1138-3 assume true; 6836#L1138-1 assume !false; 6837#L1139 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 6626#L719 assume true; 6858#L611-1 assume !false; 6762#L612 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 6763#L559 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 6546#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 7040#L602 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 6674#L616 assume !(0 != eval_~tmp~0); 6676#L734 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 6788#L504-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 6778#L744-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6764#L744-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6627#L749-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6429#L754-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6430#L759-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6817#L764-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6598#L769-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6362#L774-3 assume !(0 == ~T7_E~0); 6363#L779-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6960#L784-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6814#L789-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6464#L794-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6465#L799-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7007#L804-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6873#L809-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6687#L814-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6679#L351-24 assume 1 == ~m_pc~0; 6636#L352-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 6637#L362-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6975#L363-8 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 6735#L920-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 6708#L920-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6709#L370-24 assume 1 == ~t1_pc~0; 6807#L371-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 6808#L381-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7031#L382-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 6296#L928-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 6297#L928-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6302#L389-24 assume !(1 == ~t2_pc~0); 6819#L389-26 is_transmit2_triggered_~__retres1~2 := 0; 6298#L400-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6299#L401-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 6436#L936-24 assume !(0 != activate_threads_~tmp___1~0); 6913#L936-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6904#L408-24 assume 1 == ~t3_pc~0; 6905#L409-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 6491#L419-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6492#L420-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 6562#L944-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 6609#L944-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6611#L427-24 assume 1 == ~t4_pc~0; 6970#L428-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 6608#L438-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6591#L439-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 6394#L952-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 6395#L952-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7044#L446-24 assume 1 == ~t5_pc~0; 7026#L447-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 6862#L457-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 6727#L458-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 6728#L960-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 6955#L960-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 6361#L465-24 assume 1 == ~t6_pc~0; 6330#L466-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 6331#L476-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 6847#L477-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 6662#L968-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 6634#L968-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 6623#L484-24 assume 1 == ~t7_pc~0; 6481#L485-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 6482#L495-8 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 6921#L496-8 activate_threads_#t~ret16 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 6922#L976-24 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 7048#L976-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6902#L827-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6903#L827-5 assume !(1 == ~T1_E~0); 6774#L832-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6622#L837-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6423#L842-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6424#L847-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6827#L852-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6602#L857-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6377#L862-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6378#L867-3 assume !(1 == ~E_2~0); 6966#L872-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6704#L877-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6468#L882-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6469#L887-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7003#L892-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6870#L897-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 6871#L559-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 6535#L601-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 7042#L602-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 6926#L1157 assume !(0 == start_simulation_~tmp~3); 6646#L1157-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 6912#L559-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 6538#L601-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 7043#L602-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 7010#L1112 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 6736#L1119 stop_simulation_#res := stop_simulation_~__retres2~0; 6737#L1120 start_simulation_#t~ret19 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 6529#L1170 assume !(0 != start_simulation_~tmp___0~1); 6530#L1138-3 [2018-11-18 10:50:52,199 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:52,199 INFO L82 PathProgramCache]: Analyzing trace with hash 1267163051, now seen corresponding path program 1 times [2018-11-18 10:50:52,199 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:52,199 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:52,200 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:52,200 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:50:52,200 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:52,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:50:52,231 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:50:52,232 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:50:52,232 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:50:52,232 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 10:50:52,232 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:52,232 INFO L82 PathProgramCache]: Analyzing trace with hash 2140214550, now seen corresponding path program 3 times [2018-11-18 10:50:52,233 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:52,233 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:52,233 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:52,233 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:50:52,233 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:52,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:50:52,280 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:50:52,280 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:50:52,280 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:50:52,280 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 10:50:52,280 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 10:50:52,280 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:50:52,281 INFO L87 Difference]: Start difference. First operand 779 states and 1156 transitions. cyclomatic complexity: 378 Second operand 3 states. [2018-11-18 10:50:52,289 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:50:52,289 INFO L93 Difference]: Finished difference Result 779 states and 1155 transitions. [2018-11-18 10:50:52,290 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 10:50:52,290 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 779 states and 1155 transitions. [2018-11-18 10:50:52,293 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 678 [2018-11-18 10:50:52,296 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 779 states to 779 states and 1155 transitions. [2018-11-18 10:50:52,296 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 779 [2018-11-18 10:50:52,297 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 779 [2018-11-18 10:50:52,297 INFO L73 IsDeterministic]: Start isDeterministic. Operand 779 states and 1155 transitions. [2018-11-18 10:50:52,298 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 10:50:52,298 INFO L705 BuchiCegarLoop]: Abstraction has 779 states and 1155 transitions. [2018-11-18 10:50:52,299 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 779 states and 1155 transitions. [2018-11-18 10:50:52,306 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 779 to 779. [2018-11-18 10:50:52,306 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 779 states. [2018-11-18 10:50:52,308 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 779 states to 779 states and 1155 transitions. [2018-11-18 10:50:52,308 INFO L728 BuchiCegarLoop]: Abstraction has 779 states and 1155 transitions. [2018-11-18 10:50:52,308 INFO L608 BuchiCegarLoop]: Abstraction has 779 states and 1155 transitions. [2018-11-18 10:50:52,308 INFO L442 BuchiCegarLoop]: ======== Iteration 6============ [2018-11-18 10:50:52,308 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 779 states and 1155 transitions. [2018-11-18 10:50:52,310 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 678 [2018-11-18 10:50:52,310 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:50:52,310 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:50:52,312 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:52,312 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:52,312 INFO L794 eck$LassoCheckResult]: Stem: 8216#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 8137#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 8138#L1101 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 8200#L504 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7843#L511 assume 1 == ~m_i~0;~m_st~0 := 0; 7844#L511-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8010#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8415#L521-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8351#L526-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8105#L531-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8106#L536-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8460#L541-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8333#L546-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8334#L744 assume !(0 == ~M_E~0); 8338#L744-2 assume !(0 == ~T1_E~0); 8188#L749-1 assume !(0 == ~T2_E~0); 7990#L754-1 assume !(0 == ~T3_E~0); 7991#L759-1 assume !(0 == ~T4_E~0); 8393#L764-1 assume !(0 == ~T5_E~0); 8168#L769-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7945#L774-1 assume !(0 == ~T7_E~0); 7946#L779-1 assume !(0 == ~E_1~0); 8532#L784-1 assume !(0 == ~E_2~0); 8378#L789-1 assume !(0 == ~E_3~0); 8027#L794-1 assume !(0 == ~E_4~0); 8028#L799-1 assume !(0 == ~E_5~0); 8569#L804-1 assume !(0 == ~E_6~0); 8437#L809-1 assume 0 == ~E_7~0;~E_7~0 := 1; 8248#L814-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8161#L351 assume 1 == ~m_pc~0; 8162#L352 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 8145#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8563#L363 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 8345#L920 assume !(0 != activate_threads_~tmp~1); 8346#L920-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8310#L370 assume !(1 == ~t1_pc~0); 8311#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 8320#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8597#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 8091#L928 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 7935#L928-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7936#L389 assume 1 == ~t2_pc~0; 8419#L390 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 7912#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7913#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 8012#L936 assume !(0 != activate_threads_~tmp___1~0); 8573#L936-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8499#L408 assume !(1 == ~t3_pc~0); 8444#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 8064#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 8015#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 8016#L944 assume !(0 != activate_threads_~tmp___2~0); 8363#L944-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 8364#L427 assume 1 == ~t4_pc~0; 8559#L428 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 8355#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 8158#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 7997#L952 assume !(0 != activate_threads_~tmp___3~0); 7998#L952-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7966#L446 assume !(1 == ~t5_pc~0); 7967#L446-2 is_transmit5_triggered_~__retres1~5 := 0; 7972#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 8335#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 8336#L960 assume !(0 != activate_threads_~tmp___4~0); 8528#L960-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 8107#L465 assume 1 == ~t6_pc~0; 7903#L466 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 7904#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 8416#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 8255#L968 assume !(0 != activate_threads_~tmp___5~0); 8256#L968-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 8232#L484 assume 1 == ~t7_pc~0; 8087#L485 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 8088#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 8511#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 8512#L976 assume !(0 != activate_threads_~tmp___6~0); 8580#L976-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8476#L827 assume !(1 == ~M_E~0); 8463#L827-2 assume !(1 == ~T1_E~0); 8348#L832-1 assume !(1 == ~T2_E~0); 8186#L837-1 assume !(1 == ~T3_E~0); 7983#L842-1 assume !(1 == ~T4_E~0); 7984#L847-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8389#L852-1 assume !(1 == ~T6_E~0); 8166#L857-1 assume !(1 == ~T7_E~0); 7937#L862-1 assume !(1 == ~E_1~0); 7938#L867-1 assume !(1 == ~E_2~0); 8530#L872-1 assume !(1 == ~E_3~0); 8264#L877-1 assume !(1 == ~E_4~0); 8031#L882-1 assume !(1 == ~E_5~0); 8032#L887-1 assume 1 == ~E_6~0;~E_6~0 := 2; 8574#L892-1 assume !(1 == ~E_7~0); 8442#L897-1 assume { :end_inline_reset_delta_events } true; 8095#L1138-3 [2018-11-18 10:50:52,312 INFO L796 eck$LassoCheckResult]: Loop: 8095#L1138-3 assume true; 8401#L1138-1 assume !false; 8402#L1139 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 8191#L719 assume true; 8423#L611-1 assume !false; 8327#L612 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 8328#L559 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 8111#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 8605#L602 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 8239#L616 assume !(0 != eval_~tmp~0); 8241#L734 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 8353#L504-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 8343#L744-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8329#L744-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8192#L749-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7994#L754-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7995#L759-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8382#L764-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8163#L769-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7927#L774-3 assume !(0 == ~T7_E~0); 7928#L779-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8525#L784-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8379#L789-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8029#L794-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8030#L799-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8572#L804-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8438#L809-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8252#L814-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8244#L351-24 assume 1 == ~m_pc~0; 8201#L352-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 8202#L362-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8540#L363-8 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 8300#L920-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 8273#L920-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8274#L370-24 assume 1 == ~t1_pc~0; 8372#L371-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 8373#L381-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8596#L382-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 7861#L928-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 7862#L928-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7867#L389-24 assume !(1 == ~t2_pc~0); 8384#L389-26 is_transmit2_triggered_~__retres1~2 := 0; 7863#L400-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7864#L401-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 8001#L936-24 assume !(0 != activate_threads_~tmp___1~0); 8477#L936-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8469#L408-24 assume 1 == ~t3_pc~0; 8470#L409-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 8056#L419-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 8057#L420-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 8127#L944-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 8174#L944-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 8176#L427-24 assume 1 == ~t4_pc~0; 8535#L428-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 8173#L438-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 8156#L439-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 7959#L952-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 7960#L952-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 8609#L446-24 assume !(1 == ~t5_pc~0); 8592#L446-26 is_transmit5_triggered_~__retres1~5 := 0; 8427#L457-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 8292#L458-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 8293#L960-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 8520#L960-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 7926#L465-24 assume 1 == ~t6_pc~0; 7895#L466-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 7896#L476-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 8412#L477-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 8227#L968-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 8199#L968-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 8189#L484-24 assume 1 == ~t7_pc~0; 8048#L485-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 8049#L495-8 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 8486#L496-8 activate_threads_#t~ret16 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 8487#L976-24 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 8613#L976-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8467#L827-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8468#L827-5 assume !(1 == ~T1_E~0); 8339#L832-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8187#L837-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7988#L842-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7989#L847-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8392#L852-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8167#L857-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7943#L862-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7944#L867-3 assume !(1 == ~E_2~0); 8531#L872-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8269#L877-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8033#L882-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8034#L887-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8568#L892-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8435#L897-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 8436#L559-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 8100#L601-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 8607#L602-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 8491#L1157 assume !(0 == start_simulation_~tmp~3); 8211#L1157-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 8478#L559-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 8103#L601-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 8608#L602-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 8575#L1112 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 8302#L1119 stop_simulation_#res := stop_simulation_~__retres2~0; 8303#L1120 start_simulation_#t~ret19 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 8094#L1170 assume !(0 != start_simulation_~tmp___0~1); 8095#L1138-3 [2018-11-18 10:50:52,312 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:52,312 INFO L82 PathProgramCache]: Analyzing trace with hash -1148673299, now seen corresponding path program 1 times [2018-11-18 10:50:52,313 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:52,313 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:52,313 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:52,313 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:50:52,313 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:52,317 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:50:52,350 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:50:52,350 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:50:52,350 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:50:52,350 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 10:50:52,351 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:52,351 INFO L82 PathProgramCache]: Analyzing trace with hash 832209781, now seen corresponding path program 1 times [2018-11-18 10:50:52,351 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:52,351 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:52,352 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:52,353 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:50:52,353 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:52,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:50:52,386 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:50:52,386 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:50:52,386 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:50:52,387 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 10:50:52,387 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 10:50:52,387 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:50:52,387 INFO L87 Difference]: Start difference. First operand 779 states and 1155 transitions. cyclomatic complexity: 377 Second operand 3 states. [2018-11-18 10:50:52,397 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:50:52,397 INFO L93 Difference]: Finished difference Result 779 states and 1154 transitions. [2018-11-18 10:50:52,398 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 10:50:52,398 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 779 states and 1154 transitions. [2018-11-18 10:50:52,401 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 678 [2018-11-18 10:50:52,404 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 779 states to 779 states and 1154 transitions. [2018-11-18 10:50:52,404 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 779 [2018-11-18 10:50:52,405 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 779 [2018-11-18 10:50:52,405 INFO L73 IsDeterministic]: Start isDeterministic. Operand 779 states and 1154 transitions. [2018-11-18 10:50:52,406 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 10:50:52,406 INFO L705 BuchiCegarLoop]: Abstraction has 779 states and 1154 transitions. [2018-11-18 10:50:52,407 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 779 states and 1154 transitions. [2018-11-18 10:50:52,414 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 779 to 779. [2018-11-18 10:50:52,414 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 779 states. [2018-11-18 10:50:52,415 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 779 states to 779 states and 1154 transitions. [2018-11-18 10:50:52,415 INFO L728 BuchiCegarLoop]: Abstraction has 779 states and 1154 transitions. [2018-11-18 10:50:52,415 INFO L608 BuchiCegarLoop]: Abstraction has 779 states and 1154 transitions. [2018-11-18 10:50:52,416 INFO L442 BuchiCegarLoop]: ======== Iteration 7============ [2018-11-18 10:50:52,416 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 779 states and 1154 transitions. [2018-11-18 10:50:52,418 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 678 [2018-11-18 10:50:52,418 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:50:52,418 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:50:52,419 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:52,419 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:52,419 INFO L794 eck$LassoCheckResult]: Stem: 9781#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 9702#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 9703#L1101 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 9765#L504 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9408#L511 assume 1 == ~m_i~0;~m_st~0 := 0; 9409#L511-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9575#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9980#L521-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9916#L526-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9670#L531-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9671#L536-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 10025#L541-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9898#L546-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9899#L744 assume !(0 == ~M_E~0); 9903#L744-2 assume !(0 == ~T1_E~0); 9753#L749-1 assume !(0 == ~T2_E~0); 9555#L754-1 assume !(0 == ~T3_E~0); 9556#L759-1 assume !(0 == ~T4_E~0); 9958#L764-1 assume !(0 == ~T5_E~0); 9733#L769-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9510#L774-1 assume !(0 == ~T7_E~0); 9511#L779-1 assume !(0 == ~E_1~0); 10097#L784-1 assume !(0 == ~E_2~0); 9943#L789-1 assume !(0 == ~E_3~0); 9592#L794-1 assume !(0 == ~E_4~0); 9593#L799-1 assume !(0 == ~E_5~0); 10134#L804-1 assume !(0 == ~E_6~0); 10002#L809-1 assume 0 == ~E_7~0;~E_7~0 := 1; 9813#L814-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9726#L351 assume 1 == ~m_pc~0; 9727#L352 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 9710#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10128#L363 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 9910#L920 assume !(0 != activate_threads_~tmp~1); 9911#L920-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9875#L370 assume !(1 == ~t1_pc~0); 9876#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 9885#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10162#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 9656#L928 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 9500#L928-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9501#L389 assume 1 == ~t2_pc~0; 9984#L390 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 9477#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9478#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 9577#L936 assume !(0 != activate_threads_~tmp___1~0); 10138#L936-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 10064#L408 assume !(1 == ~t3_pc~0); 10009#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 9629#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9580#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 9581#L944 assume !(0 != activate_threads_~tmp___2~0); 9928#L944-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9929#L427 assume 1 == ~t4_pc~0; 10124#L428 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 9920#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9723#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 9562#L952 assume !(0 != activate_threads_~tmp___3~0); 9563#L952-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 9531#L446 assume !(1 == ~t5_pc~0); 9532#L446-2 is_transmit5_triggered_~__retres1~5 := 0; 9537#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 9900#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 9901#L960 assume !(0 != activate_threads_~tmp___4~0); 10093#L960-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 9672#L465 assume 1 == ~t6_pc~0; 9468#L466 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 9469#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 9981#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 9820#L968 assume !(0 != activate_threads_~tmp___5~0); 9821#L968-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 9797#L484 assume 1 == ~t7_pc~0; 9652#L485 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 9653#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 10076#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 10077#L976 assume !(0 != activate_threads_~tmp___6~0); 10145#L976-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10041#L827 assume !(1 == ~M_E~0); 10028#L827-2 assume !(1 == ~T1_E~0); 9913#L832-1 assume !(1 == ~T2_E~0); 9751#L837-1 assume !(1 == ~T3_E~0); 9548#L842-1 assume !(1 == ~T4_E~0); 9549#L847-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9954#L852-1 assume !(1 == ~T6_E~0); 9731#L857-1 assume !(1 == ~T7_E~0); 9502#L862-1 assume !(1 == ~E_1~0); 9503#L867-1 assume !(1 == ~E_2~0); 10095#L872-1 assume !(1 == ~E_3~0); 9829#L877-1 assume !(1 == ~E_4~0); 9596#L882-1 assume !(1 == ~E_5~0); 9597#L887-1 assume 1 == ~E_6~0;~E_6~0 := 2; 10139#L892-1 assume !(1 == ~E_7~0); 10007#L897-1 assume { :end_inline_reset_delta_events } true; 9660#L1138-3 [2018-11-18 10:50:52,420 INFO L796 eck$LassoCheckResult]: Loop: 9660#L1138-3 assume true; 9966#L1138-1 assume !false; 9967#L1139 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 9756#L719 assume true; 9988#L611-1 assume !false; 9892#L612 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 9893#L559 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 9676#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 10170#L602 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 9804#L616 assume !(0 != eval_~tmp~0); 9806#L734 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 9918#L504-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 9908#L744-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9894#L744-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9757#L749-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9559#L754-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9560#L759-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9947#L764-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9728#L769-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9492#L774-3 assume !(0 == ~T7_E~0); 9493#L779-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10090#L784-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9944#L789-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9594#L794-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9595#L799-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10137#L804-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10003#L809-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9817#L814-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9809#L351-24 assume 1 == ~m_pc~0; 9766#L352-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 9767#L362-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10105#L363-8 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 9865#L920-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 9838#L920-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 9839#L370-24 assume 1 == ~t1_pc~0; 9937#L371-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 9938#L381-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 10161#L382-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 9426#L928-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 9427#L928-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9432#L389-24 assume !(1 == ~t2_pc~0); 9949#L389-26 is_transmit2_triggered_~__retres1~2 := 0; 9428#L400-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9429#L401-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 9566#L936-24 assume !(0 != activate_threads_~tmp___1~0); 10042#L936-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 10034#L408-24 assume 1 == ~t3_pc~0; 10035#L409-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 9621#L419-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9622#L420-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 9692#L944-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 9739#L944-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9741#L427-24 assume 1 == ~t4_pc~0; 10100#L428-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 9738#L438-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9721#L439-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 9524#L952-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 9525#L952-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 10174#L446-24 assume 1 == ~t5_pc~0; 10156#L447-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 9992#L457-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 9857#L458-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 9858#L960-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 10085#L960-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 9491#L465-24 assume 1 == ~t6_pc~0; 9460#L466-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 9461#L476-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 9977#L477-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 9792#L968-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 9764#L968-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 9754#L484-24 assume 1 == ~t7_pc~0; 9613#L485-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 9614#L495-8 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 10051#L496-8 activate_threads_#t~ret16 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 10052#L976-24 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 10178#L976-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10032#L827-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10033#L827-5 assume !(1 == ~T1_E~0); 9904#L832-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9752#L837-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9553#L842-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9554#L847-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9957#L852-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9732#L857-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9508#L862-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9509#L867-3 assume !(1 == ~E_2~0); 10096#L872-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9834#L877-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9598#L882-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9599#L887-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10133#L892-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10000#L897-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 10001#L559-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 9665#L601-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 10172#L602-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 10056#L1157 assume !(0 == start_simulation_~tmp~3); 9776#L1157-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 10043#L559-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 9668#L601-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 10173#L602-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 10140#L1112 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 9867#L1119 stop_simulation_#res := stop_simulation_~__retres2~0; 9868#L1120 start_simulation_#t~ret19 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 9659#L1170 assume !(0 != start_simulation_~tmp___0~1); 9660#L1138-3 [2018-11-18 10:50:52,420 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:52,420 INFO L82 PathProgramCache]: Analyzing trace with hash 1821437803, now seen corresponding path program 1 times [2018-11-18 10:50:52,420 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:52,420 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:52,421 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:52,421 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:50:52,421 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:52,424 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:50:52,444 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:50:52,444 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:50:52,445 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:50:52,445 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 10:50:52,445 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:52,445 INFO L82 PathProgramCache]: Analyzing trace with hash 2140214550, now seen corresponding path program 4 times [2018-11-18 10:50:52,445 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:52,445 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:52,446 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:52,446 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:50:52,446 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:52,451 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:50:52,486 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:50:52,486 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:50:52,486 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:50:52,487 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 10:50:52,487 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 10:50:52,487 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:50:52,487 INFO L87 Difference]: Start difference. First operand 779 states and 1154 transitions. cyclomatic complexity: 376 Second operand 3 states. [2018-11-18 10:50:52,497 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:50:52,497 INFO L93 Difference]: Finished difference Result 779 states and 1153 transitions. [2018-11-18 10:50:52,498 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 10:50:52,498 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 779 states and 1153 transitions. [2018-11-18 10:50:52,501 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 678 [2018-11-18 10:50:52,503 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 779 states to 779 states and 1153 transitions. [2018-11-18 10:50:52,504 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 779 [2018-11-18 10:50:52,504 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 779 [2018-11-18 10:50:52,504 INFO L73 IsDeterministic]: Start isDeterministic. Operand 779 states and 1153 transitions. [2018-11-18 10:50:52,505 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 10:50:52,506 INFO L705 BuchiCegarLoop]: Abstraction has 779 states and 1153 transitions. [2018-11-18 10:50:52,507 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 779 states and 1153 transitions. [2018-11-18 10:50:52,513 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 779 to 779. [2018-11-18 10:50:52,514 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 779 states. [2018-11-18 10:50:52,515 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 779 states to 779 states and 1153 transitions. [2018-11-18 10:50:52,515 INFO L728 BuchiCegarLoop]: Abstraction has 779 states and 1153 transitions. [2018-11-18 10:50:52,515 INFO L608 BuchiCegarLoop]: Abstraction has 779 states and 1153 transitions. [2018-11-18 10:50:52,515 INFO L442 BuchiCegarLoop]: ======== Iteration 8============ [2018-11-18 10:50:52,515 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 779 states and 1153 transitions. [2018-11-18 10:50:52,517 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 678 [2018-11-18 10:50:52,518 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:50:52,518 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:50:52,519 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:52,519 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:52,519 INFO L794 eck$LassoCheckResult]: Stem: 11348#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 11268#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 11269#L1101 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 11334#L504 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10973#L511 assume 1 == ~m_i~0;~m_st~0 := 0; 10974#L511-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11140#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11545#L521-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11481#L526-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11235#L531-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 11236#L536-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 11590#L541-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 11463#L546-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11464#L744 assume !(0 == ~M_E~0); 11468#L744-2 assume !(0 == ~T1_E~0); 11319#L749-1 assume !(0 == ~T2_E~0); 11120#L754-1 assume !(0 == ~T3_E~0); 11121#L759-1 assume !(0 == ~T4_E~0); 11523#L764-1 assume !(0 == ~T5_E~0); 11298#L769-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11075#L774-1 assume !(0 == ~T7_E~0); 11076#L779-1 assume !(0 == ~E_1~0); 11662#L784-1 assume !(0 == ~E_2~0); 11508#L789-1 assume !(0 == ~E_3~0); 11157#L794-1 assume !(0 == ~E_4~0); 11158#L799-1 assume !(0 == ~E_5~0); 11700#L804-1 assume !(0 == ~E_6~0); 11567#L809-1 assume 0 == ~E_7~0;~E_7~0 := 1; 11379#L814-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 11291#L351 assume 1 == ~m_pc~0; 11292#L352 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 11275#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 11695#L363 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 11475#L920 assume !(0 != activate_threads_~tmp~1); 11476#L920-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 11440#L370 assume !(1 == ~t1_pc~0); 11441#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 11450#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 11727#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 11221#L928 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 11065#L928-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 11066#L389 assume 1 == ~t2_pc~0; 11549#L390 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 11045#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 11046#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 11142#L936 assume !(0 != activate_threads_~tmp___1~0); 11703#L936-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 11629#L408 assume !(1 == ~t3_pc~0); 11574#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 11194#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 11145#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 11146#L944 assume !(0 != activate_threads_~tmp___2~0); 11493#L944-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 11494#L427 assume 1 == ~t4_pc~0; 11689#L428 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 11485#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 11288#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 11127#L952 assume !(0 != activate_threads_~tmp___3~0); 11128#L952-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 11096#L446 assume !(1 == ~t5_pc~0); 11097#L446-2 is_transmit5_triggered_~__retres1~5 := 0; 11102#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 11465#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 11466#L960 assume !(0 != activate_threads_~tmp___4~0); 11658#L960-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 11237#L465 assume 1 == ~t6_pc~0; 11033#L466 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 11034#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 11546#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 11385#L968 assume !(0 != activate_threads_~tmp___5~0); 11386#L968-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 11362#L484 assume 1 == ~t7_pc~0; 11217#L485 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 11218#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 11641#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 11642#L976 assume !(0 != activate_threads_~tmp___6~0); 11710#L976-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11606#L827 assume !(1 == ~M_E~0); 11593#L827-2 assume !(1 == ~T1_E~0); 11478#L832-1 assume !(1 == ~T2_E~0); 11316#L837-1 assume !(1 == ~T3_E~0); 11113#L842-1 assume !(1 == ~T4_E~0); 11114#L847-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11519#L852-1 assume !(1 == ~T6_E~0); 11296#L857-1 assume !(1 == ~T7_E~0); 11067#L862-1 assume !(1 == ~E_1~0); 11068#L867-1 assume !(1 == ~E_2~0); 11660#L872-1 assume !(1 == ~E_3~0); 11394#L877-1 assume !(1 == ~E_4~0); 11161#L882-1 assume !(1 == ~E_5~0); 11162#L887-1 assume 1 == ~E_6~0;~E_6~0 := 2; 11704#L892-1 assume !(1 == ~E_7~0); 11572#L897-1 assume { :end_inline_reset_delta_events } true; 11225#L1138-3 [2018-11-18 10:50:52,519 INFO L796 eck$LassoCheckResult]: Loop: 11225#L1138-3 assume true; 11531#L1138-1 assume !false; 11532#L1139 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 11321#L719 assume true; 11553#L611-1 assume !false; 11457#L612 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 11458#L559 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 11241#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 11735#L602 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 11369#L616 assume !(0 != eval_~tmp~0); 11371#L734 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 11483#L504-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 11473#L744-3 assume 0 == ~M_E~0;~M_E~0 := 1; 11459#L744-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11322#L749-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11124#L754-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11125#L759-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11512#L764-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11293#L769-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11057#L774-3 assume !(0 == ~T7_E~0); 11058#L779-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11655#L784-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11509#L789-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11159#L794-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11160#L799-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11702#L804-3 assume 0 == ~E_6~0;~E_6~0 := 1; 11568#L809-3 assume 0 == ~E_7~0;~E_7~0 := 1; 11382#L814-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 11374#L351-24 assume 1 == ~m_pc~0; 11330#L352-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 11331#L362-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 11670#L363-8 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 11430#L920-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 11403#L920-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 11404#L370-24 assume !(1 == ~t1_pc~0); 11504#L370-26 is_transmit1_triggered_~__retres1~1 := 0; 11503#L381-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 11726#L382-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 10991#L928-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 10992#L928-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 10997#L389-24 assume !(1 == ~t2_pc~0); 11514#L389-26 is_transmit2_triggered_~__retres1~2 := 0; 10993#L400-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 10994#L401-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 11131#L936-24 assume !(0 != activate_threads_~tmp___1~0); 11607#L936-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 11599#L408-24 assume 1 == ~t3_pc~0; 11600#L409-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 11186#L419-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 11187#L420-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 11257#L944-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 11304#L944-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 11306#L427-24 assume 1 == ~t4_pc~0; 11665#L428-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 11303#L438-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 11286#L439-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 11089#L952-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 11090#L952-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 11739#L446-24 assume 1 == ~t5_pc~0; 11721#L447-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 11557#L457-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 11422#L458-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 11423#L960-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 11650#L960-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 11056#L465-24 assume 1 == ~t6_pc~0; 11025#L466-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 11026#L476-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 11542#L477-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 11357#L968-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 11329#L968-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 11318#L484-24 assume 1 == ~t7_pc~0; 11178#L485-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 11179#L495-8 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 11616#L496-8 activate_threads_#t~ret16 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 11617#L976-24 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 11743#L976-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11597#L827-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11598#L827-5 assume !(1 == ~T1_E~0); 11469#L832-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11317#L837-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11118#L842-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11119#L847-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11522#L852-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11297#L857-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11073#L862-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11074#L867-3 assume !(1 == ~E_2~0); 11661#L872-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11399#L877-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11163#L882-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11164#L887-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11698#L892-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11565#L897-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 11566#L559-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 11230#L601-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 11737#L602-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 11621#L1157 assume !(0 == start_simulation_~tmp~3); 11341#L1157-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 11608#L559-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 11233#L601-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 11738#L602-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 11705#L1112 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 11432#L1119 stop_simulation_#res := stop_simulation_~__retres2~0; 11433#L1120 start_simulation_#t~ret19 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 11224#L1170 assume !(0 != start_simulation_~tmp___0~1); 11225#L1138-3 [2018-11-18 10:50:52,520 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:52,520 INFO L82 PathProgramCache]: Analyzing trace with hash 254679853, now seen corresponding path program 1 times [2018-11-18 10:50:52,520 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:52,520 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:52,520 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:52,521 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:50:52,521 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:52,525 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:50:52,561 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:50:52,561 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:50:52,561 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 10:50:52,561 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 10:50:52,561 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:52,562 INFO L82 PathProgramCache]: Analyzing trace with hash -1247996299, now seen corresponding path program 1 times [2018-11-18 10:50:52,562 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:52,562 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:52,562 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:52,562 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:50:52,562 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:52,568 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:50:52,611 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:50:52,611 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:50:52,611 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:50:52,613 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 10:50:52,613 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 10:50:52,613 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:50:52,613 INFO L87 Difference]: Start difference. First operand 779 states and 1153 transitions. cyclomatic complexity: 375 Second operand 3 states. [2018-11-18 10:50:52,628 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:50:52,628 INFO L93 Difference]: Finished difference Result 779 states and 1148 transitions. [2018-11-18 10:50:52,629 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 10:50:52,629 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 779 states and 1148 transitions. [2018-11-18 10:50:52,632 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 678 [2018-11-18 10:50:52,634 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 779 states to 779 states and 1148 transitions. [2018-11-18 10:50:52,634 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 779 [2018-11-18 10:50:52,635 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 779 [2018-11-18 10:50:52,635 INFO L73 IsDeterministic]: Start isDeterministic. Operand 779 states and 1148 transitions. [2018-11-18 10:50:52,636 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 10:50:52,636 INFO L705 BuchiCegarLoop]: Abstraction has 779 states and 1148 transitions. [2018-11-18 10:50:52,637 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 779 states and 1148 transitions. [2018-11-18 10:50:52,644 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 779 to 779. [2018-11-18 10:50:52,644 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 779 states. [2018-11-18 10:50:52,645 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 779 states to 779 states and 1148 transitions. [2018-11-18 10:50:52,645 INFO L728 BuchiCegarLoop]: Abstraction has 779 states and 1148 transitions. [2018-11-18 10:50:52,645 INFO L608 BuchiCegarLoop]: Abstraction has 779 states and 1148 transitions. [2018-11-18 10:50:52,645 INFO L442 BuchiCegarLoop]: ======== Iteration 9============ [2018-11-18 10:50:52,646 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 779 states and 1148 transitions. [2018-11-18 10:50:52,648 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 678 [2018-11-18 10:50:52,648 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:50:52,648 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:50:52,649 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:52,649 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:52,649 INFO L794 eck$LassoCheckResult]: Stem: 12913#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 12832#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 12833#L1101 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 12896#L504 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12538#L511 assume 1 == ~m_i~0;~m_st~0 := 0; 12539#L511-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12705#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13110#L521-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13046#L526-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12800#L531-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12801#L536-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 13155#L541-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 13028#L546-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13029#L744 assume !(0 == ~M_E~0); 13033#L744-2 assume !(0 == ~T1_E~0); 12884#L749-1 assume !(0 == ~T2_E~0); 12685#L754-1 assume !(0 == ~T3_E~0); 12686#L759-1 assume !(0 == ~T4_E~0); 13088#L764-1 assume !(0 == ~T5_E~0); 12863#L769-1 assume !(0 == ~T6_E~0); 12640#L774-1 assume !(0 == ~T7_E~0); 12641#L779-1 assume !(0 == ~E_1~0); 13227#L784-1 assume !(0 == ~E_2~0); 13073#L789-1 assume !(0 == ~E_3~0); 12722#L794-1 assume !(0 == ~E_4~0); 12723#L799-1 assume !(0 == ~E_5~0); 13264#L804-1 assume !(0 == ~E_6~0); 13132#L809-1 assume 0 == ~E_7~0;~E_7~0 := 1; 12943#L814-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12856#L351 assume 1 == ~m_pc~0; 12857#L352 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 12840#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 13258#L363 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 13040#L920 assume !(0 != activate_threads_~tmp~1); 13041#L920-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 13005#L370 assume !(1 == ~t1_pc~0); 13006#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 13015#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 13292#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 12786#L928 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 12630#L928-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12631#L389 assume 1 == ~t2_pc~0; 13114#L390 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 12607#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12608#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 12707#L936 assume !(0 != activate_threads_~tmp___1~0); 13268#L936-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 13194#L408 assume !(1 == ~t3_pc~0); 13139#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 12762#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 12710#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 12711#L944 assume !(0 != activate_threads_~tmp___2~0); 13058#L944-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 13059#L427 assume 1 == ~t4_pc~0; 13254#L428 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 13050#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 12853#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 12692#L952 assume !(0 != activate_threads_~tmp___3~0); 12693#L952-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 12661#L446 assume !(1 == ~t5_pc~0); 12662#L446-2 is_transmit5_triggered_~__retres1~5 := 0; 12667#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 13030#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 13031#L960 assume !(0 != activate_threads_~tmp___4~0); 13223#L960-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 12802#L465 assume 1 == ~t6_pc~0; 12598#L466 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 12599#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 13111#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 12950#L968 assume !(0 != activate_threads_~tmp___5~0); 12951#L968-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 12928#L484 assume 1 == ~t7_pc~0; 12782#L485 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 12783#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 13206#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 13207#L976 assume !(0 != activate_threads_~tmp___6~0); 13275#L976-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13171#L827 assume !(1 == ~M_E~0); 13158#L827-2 assume !(1 == ~T1_E~0); 13043#L832-1 assume !(1 == ~T2_E~0); 12881#L837-1 assume !(1 == ~T3_E~0); 12678#L842-1 assume !(1 == ~T4_E~0); 12679#L847-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13084#L852-1 assume !(1 == ~T6_E~0); 12861#L857-1 assume !(1 == ~T7_E~0); 12632#L862-1 assume !(1 == ~E_1~0); 12633#L867-1 assume !(1 == ~E_2~0); 13225#L872-1 assume !(1 == ~E_3~0); 12959#L877-1 assume !(1 == ~E_4~0); 12726#L882-1 assume !(1 == ~E_5~0); 12727#L887-1 assume 1 == ~E_6~0;~E_6~0 := 2; 13269#L892-1 assume !(1 == ~E_7~0); 13137#L897-1 assume { :end_inline_reset_delta_events } true; 12790#L1138-3 [2018-11-18 10:50:52,649 INFO L796 eck$LassoCheckResult]: Loop: 12790#L1138-3 assume true; 13096#L1138-1 assume !false; 13097#L1139 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 12886#L719 assume true; 13118#L611-1 assume !false; 13022#L612 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 13023#L559 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 12806#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 13300#L602 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 12934#L616 assume !(0 != eval_~tmp~0); 12936#L734 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 13048#L504-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 13038#L744-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13024#L744-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12887#L749-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 12689#L754-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 12690#L759-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13077#L764-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12858#L769-3 assume !(0 == ~T6_E~0); 12622#L774-3 assume !(0 == ~T7_E~0); 12623#L779-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13220#L784-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13074#L789-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12724#L794-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12725#L799-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13267#L804-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13133#L809-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12947#L814-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 12939#L351-24 assume 1 == ~m_pc~0; 12897#L352-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 12898#L362-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 13235#L363-8 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 12995#L920-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 12968#L920-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 12969#L370-24 assume 1 == ~t1_pc~0; 13067#L371-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 13068#L381-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 13291#L382-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 12556#L928-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 12557#L928-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 12562#L389-24 assume !(1 == ~t2_pc~0); 13079#L389-26 is_transmit2_triggered_~__retres1~2 := 0; 12558#L400-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 12559#L401-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 12696#L936-24 assume !(0 != activate_threads_~tmp___1~0); 13173#L936-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 13164#L408-24 assume 1 == ~t3_pc~0; 13165#L409-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 12751#L419-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 12752#L420-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 12822#L944-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 12869#L944-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 12871#L427-24 assume 1 == ~t4_pc~0; 13229#L428-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 12868#L438-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 12851#L439-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 12654#L952-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 12655#L952-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 13304#L446-24 assume 1 == ~t5_pc~0; 13285#L447-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 13122#L457-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 12987#L458-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 12988#L960-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 13215#L960-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 12621#L465-24 assume 1 == ~t6_pc~0; 12588#L466-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 12589#L476-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 13107#L477-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 12922#L968-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 12894#L968-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 12883#L484-24 assume 1 == ~t7_pc~0; 12741#L485-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 12742#L495-8 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 13181#L496-8 activate_threads_#t~ret16 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 13182#L976-24 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 13308#L976-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13162#L827-3 assume 1 == ~M_E~0;~M_E~0 := 2; 13163#L827-5 assume !(1 == ~T1_E~0); 13034#L832-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12882#L837-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12683#L842-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12684#L847-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13087#L852-3 assume !(1 == ~T6_E~0); 12862#L857-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12637#L862-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12638#L867-3 assume !(1 == ~E_2~0); 13226#L872-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12964#L877-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12728#L882-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12729#L887-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13263#L892-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13130#L897-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 13131#L559-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 12795#L601-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 13302#L602-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 13186#L1157 assume !(0 == start_simulation_~tmp~3); 12906#L1157-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 13172#L559-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 12798#L601-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 13303#L602-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 13270#L1112 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 12996#L1119 stop_simulation_#res := stop_simulation_~__retres2~0; 12997#L1120 start_simulation_#t~ret19 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 12789#L1170 assume !(0 != start_simulation_~tmp___0~1); 12790#L1138-3 [2018-11-18 10:50:52,650 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:52,650 INFO L82 PathProgramCache]: Analyzing trace with hash 1141902699, now seen corresponding path program 1 times [2018-11-18 10:50:52,650 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:52,650 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:52,651 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:52,651 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:50:52,651 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:52,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:50:52,684 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:50:52,684 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:50:52,684 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 10:50:52,685 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 10:50:52,685 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:52,685 INFO L82 PathProgramCache]: Analyzing trace with hash 400494482, now seen corresponding path program 1 times [2018-11-18 10:50:52,685 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:52,685 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:52,686 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:52,686 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:50:52,686 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:52,691 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:50:52,711 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:50:52,711 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:50:52,711 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:50:52,711 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 10:50:52,711 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 10:50:52,711 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:50:52,712 INFO L87 Difference]: Start difference. First operand 779 states and 1148 transitions. cyclomatic complexity: 370 Second operand 3 states. [2018-11-18 10:50:52,755 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:50:52,755 INFO L93 Difference]: Finished difference Result 779 states and 1134 transitions. [2018-11-18 10:50:52,756 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 10:50:52,756 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 779 states and 1134 transitions. [2018-11-18 10:50:52,759 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 678 [2018-11-18 10:50:52,761 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 779 states to 779 states and 1134 transitions. [2018-11-18 10:50:52,761 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 779 [2018-11-18 10:50:52,762 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 779 [2018-11-18 10:50:52,762 INFO L73 IsDeterministic]: Start isDeterministic. Operand 779 states and 1134 transitions. [2018-11-18 10:50:52,763 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 10:50:52,763 INFO L705 BuchiCegarLoop]: Abstraction has 779 states and 1134 transitions. [2018-11-18 10:50:52,764 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 779 states and 1134 transitions. [2018-11-18 10:50:52,772 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 779 to 779. [2018-11-18 10:50:52,772 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 779 states. [2018-11-18 10:50:52,774 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 779 states to 779 states and 1134 transitions. [2018-11-18 10:50:52,774 INFO L728 BuchiCegarLoop]: Abstraction has 779 states and 1134 transitions. [2018-11-18 10:50:52,774 INFO L608 BuchiCegarLoop]: Abstraction has 779 states and 1134 transitions. [2018-11-18 10:50:52,774 INFO L442 BuchiCegarLoop]: ======== Iteration 10============ [2018-11-18 10:50:52,774 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 779 states and 1134 transitions. [2018-11-18 10:50:52,776 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 678 [2018-11-18 10:50:52,776 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:50:52,776 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:50:52,777 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:52,777 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:52,778 INFO L794 eck$LassoCheckResult]: Stem: 14473#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 14389#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 14390#L1101 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 14456#L504 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14103#L511 assume 1 == ~m_i~0;~m_st~0 := 0; 14104#L511-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14270#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14675#L521-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14611#L526-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14357#L531-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14358#L536-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14720#L541-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 14593#L546-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14594#L744 assume !(0 == ~M_E~0); 14598#L744-2 assume !(0 == ~T1_E~0); 14440#L749-1 assume !(0 == ~T2_E~0); 14250#L754-1 assume !(0 == ~T3_E~0); 14251#L759-1 assume !(0 == ~T4_E~0); 14653#L764-1 assume !(0 == ~T5_E~0); 14420#L769-1 assume !(0 == ~T6_E~0); 14205#L774-1 assume !(0 == ~T7_E~0); 14206#L779-1 assume !(0 == ~E_1~0); 14792#L784-1 assume !(0 == ~E_2~0); 14638#L789-1 assume !(0 == ~E_3~0); 14287#L794-1 assume !(0 == ~E_4~0); 14288#L799-1 assume !(0 == ~E_5~0); 14829#L804-1 assume !(0 == ~E_6~0); 14697#L809-1 assume !(0 == ~E_7~0); 14508#L814-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 14413#L351 assume 1 == ~m_pc~0; 14414#L352 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 14397#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 14823#L363 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 14605#L920 assume !(0 != activate_threads_~tmp~1); 14606#L920-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 14570#L370 assume !(1 == ~t1_pc~0); 14571#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 14580#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14857#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 14343#L928 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 14195#L928-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 14196#L389 assume 1 == ~t2_pc~0; 14679#L390 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 14172#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 14173#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 14272#L936 assume !(0 != activate_threads_~tmp___1~0); 14833#L936-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 14759#L408 assume !(1 == ~t3_pc~0); 14704#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 14321#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 14275#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 14276#L944 assume !(0 != activate_threads_~tmp___2~0); 14623#L944-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 14624#L427 assume 1 == ~t4_pc~0; 14819#L428 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 14615#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 14410#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 14257#L952 assume !(0 != activate_threads_~tmp___3~0); 14258#L952-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 14226#L446 assume !(1 == ~t5_pc~0); 14227#L446-2 is_transmit5_triggered_~__retres1~5 := 0; 14232#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 14595#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 14596#L960 assume !(0 != activate_threads_~tmp___4~0); 14788#L960-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 14359#L465 assume 1 == ~t6_pc~0; 14163#L466 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 14164#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 14676#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 14515#L968 assume !(0 != activate_threads_~tmp___5~0); 14516#L968-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 14490#L484 assume !(1 == ~t7_pc~0); 14341#L484-2 is_transmit7_triggered_~__retres1~7 := 0; 14494#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 14771#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 14772#L976 assume !(0 != activate_threads_~tmp___6~0); 14840#L976-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14736#L827 assume !(1 == ~M_E~0); 14723#L827-2 assume !(1 == ~T1_E~0); 14608#L832-1 assume !(1 == ~T2_E~0); 14438#L837-1 assume !(1 == ~T3_E~0); 14243#L842-1 assume !(1 == ~T4_E~0); 14244#L847-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14649#L852-1 assume !(1 == ~T6_E~0); 14418#L857-1 assume !(1 == ~T7_E~0); 14197#L862-1 assume !(1 == ~E_1~0); 14198#L867-1 assume !(1 == ~E_2~0); 14790#L872-1 assume !(1 == ~E_3~0); 14524#L877-1 assume !(1 == ~E_4~0); 14291#L882-1 assume !(1 == ~E_5~0); 14292#L887-1 assume 1 == ~E_6~0;~E_6~0 := 2; 14834#L892-1 assume !(1 == ~E_7~0); 14702#L897-1 assume { :end_inline_reset_delta_events } true; 14347#L1138-3 [2018-11-18 10:50:52,778 INFO L796 eck$LassoCheckResult]: Loop: 14347#L1138-3 assume true; 14661#L1138-1 assume !false; 14662#L1139 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 14443#L719 assume true; 14683#L611-1 assume !false; 14587#L612 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 14588#L559 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 14363#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 14865#L602 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 14499#L616 assume !(0 != eval_~tmp~0); 14501#L734 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 14613#L504-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 14603#L744-3 assume 0 == ~M_E~0;~M_E~0 := 1; 14589#L744-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14444#L749-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14254#L754-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14255#L759-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14642#L764-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14415#L769-3 assume !(0 == ~T6_E~0); 14187#L774-3 assume !(0 == ~T7_E~0); 14188#L779-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14785#L784-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14639#L789-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14289#L794-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14290#L799-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14832#L804-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14698#L809-3 assume !(0 == ~E_7~0); 14512#L814-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 14504#L351-24 assume 1 == ~m_pc~0; 14457#L352-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 14458#L362-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 14800#L363-8 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 14560#L920-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 14533#L920-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 14534#L370-24 assume 1 == ~t1_pc~0; 14632#L371-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 14633#L381-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 14856#L382-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 14121#L928-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 14122#L928-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 14127#L389-24 assume !(1 == ~t2_pc~0); 14644#L389-26 is_transmit2_triggered_~__retres1~2 := 0; 14123#L400-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 14124#L401-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 14261#L936-24 assume !(0 != activate_threads_~tmp___1~0); 14737#L936-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 14729#L408-24 assume 1 == ~t3_pc~0; 14730#L409-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 14314#L419-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 14315#L420-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 14379#L944-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 14426#L944-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 14428#L427-24 assume 1 == ~t4_pc~0; 14795#L428-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 14425#L438-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 14408#L439-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 14219#L952-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 14220#L952-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 14869#L446-24 assume 1 == ~t5_pc~0; 14851#L447-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 14687#L457-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 14552#L458-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 14553#L960-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 14780#L960-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 14186#L465-24 assume 1 == ~t6_pc~0; 14155#L466-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 14156#L476-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 14672#L477-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 14485#L968-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 14455#L968-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 14441#L484-24 assume !(1 == ~t7_pc~0); 14309#L484-26 is_transmit7_triggered_~__retres1~7 := 0; 14445#L495-8 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 14746#L496-8 activate_threads_#t~ret16 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 14747#L976-24 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 14873#L976-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14727#L827-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14728#L827-5 assume !(1 == ~T1_E~0); 14599#L832-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14439#L837-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14248#L842-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14249#L847-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14652#L852-3 assume !(1 == ~T6_E~0); 14419#L857-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14203#L862-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14204#L867-3 assume !(1 == ~E_2~0); 14791#L872-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14529#L877-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14293#L882-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14294#L887-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14828#L892-3 assume !(1 == ~E_7~0); 14695#L897-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 14696#L559-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 14352#L601-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 14867#L602-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 14751#L1157 assume !(0 == start_simulation_~tmp~3); 14468#L1157-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 14738#L559-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 14355#L601-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 14868#L602-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 14835#L1112 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 14562#L1119 stop_simulation_#res := stop_simulation_~__retres2~0; 14563#L1120 start_simulation_#t~ret19 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 14346#L1170 assume !(0 != start_simulation_~tmp___0~1); 14347#L1138-3 [2018-11-18 10:50:52,778 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:52,778 INFO L82 PathProgramCache]: Analyzing trace with hash 296548616, now seen corresponding path program 1 times [2018-11-18 10:50:52,778 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:52,778 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:52,779 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:52,779 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:50:52,779 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:52,782 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:50:52,803 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:50:52,803 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:50:52,803 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 10:50:52,803 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 10:50:52,803 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:52,803 INFO L82 PathProgramCache]: Analyzing trace with hash -1400239379, now seen corresponding path program 1 times [2018-11-18 10:50:52,803 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:52,804 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:52,804 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:52,804 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:50:52,804 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:52,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:50:52,834 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:50:52,834 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:50:52,834 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:50:52,835 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 10:50:52,835 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 10:50:52,835 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:50:52,835 INFO L87 Difference]: Start difference. First operand 779 states and 1134 transitions. cyclomatic complexity: 356 Second operand 3 states. [2018-11-18 10:50:52,916 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:50:52,917 INFO L93 Difference]: Finished difference Result 1446 states and 2085 transitions. [2018-11-18 10:50:52,917 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 10:50:52,917 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1446 states and 2085 transitions. [2018-11-18 10:50:52,923 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1344 [2018-11-18 10:50:52,929 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1446 states to 1446 states and 2085 transitions. [2018-11-18 10:50:52,929 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1446 [2018-11-18 10:50:52,930 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1446 [2018-11-18 10:50:52,930 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1446 states and 2085 transitions. [2018-11-18 10:50:52,932 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 10:50:52,932 INFO L705 BuchiCegarLoop]: Abstraction has 1446 states and 2085 transitions. [2018-11-18 10:50:52,933 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1446 states and 2085 transitions. [2018-11-18 10:50:52,948 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1446 to 1388. [2018-11-18 10:50:52,948 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1388 states. [2018-11-18 10:50:52,951 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1388 states to 1388 states and 2006 transitions. [2018-11-18 10:50:52,951 INFO L728 BuchiCegarLoop]: Abstraction has 1388 states and 2006 transitions. [2018-11-18 10:50:52,952 INFO L608 BuchiCegarLoop]: Abstraction has 1388 states and 2006 transitions. [2018-11-18 10:50:52,952 INFO L442 BuchiCegarLoop]: ======== Iteration 11============ [2018-11-18 10:50:52,952 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1388 states and 2006 transitions. [2018-11-18 10:50:52,956 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1286 [2018-11-18 10:50:52,956 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:50:52,956 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:50:52,957 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:52,958 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:52,958 INFO L794 eck$LassoCheckResult]: Stem: 16706#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 16621#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 16622#L1101 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 16686#L504 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16335#L511 assume 1 == ~m_i~0;~m_st~0 := 0; 16336#L511-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16504#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16921#L521-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16857#L526-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16591#L531-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16592#L536-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 16966#L541-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 16839#L546-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16840#L744 assume !(0 == ~M_E~0); 16844#L744-2 assume !(0 == ~T1_E~0); 16670#L749-1 assume !(0 == ~T2_E~0); 16483#L754-1 assume !(0 == ~T3_E~0); 16484#L759-1 assume !(0 == ~T4_E~0); 16899#L764-1 assume !(0 == ~T5_E~0); 16650#L769-1 assume !(0 == ~T6_E~0); 16438#L774-1 assume !(0 == ~T7_E~0); 16439#L779-1 assume !(0 == ~E_1~0); 17040#L784-1 assume !(0 == ~E_2~0); 16884#L789-1 assume !(0 == ~E_3~0); 16521#L794-1 assume !(0 == ~E_4~0); 16522#L799-1 assume !(0 == ~E_5~0); 17080#L804-1 assume !(0 == ~E_6~0); 16943#L809-1 assume !(0 == ~E_7~0); 16748#L814-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 16644#L351 assume !(1 == ~m_pc~0); 16628#L351-2 is_master_triggered_~__retres1~0 := 0; 16629#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 17073#L363 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 16851#L920 assume !(0 != activate_threads_~tmp~1); 16852#L920-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 16816#L370 assume !(1 == ~t1_pc~0); 16817#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 16826#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 17113#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 16577#L928 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 16428#L928-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 16429#L389 assume 1 == ~t2_pc~0; 16925#L390 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 16403#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 16404#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 16506#L936 assume !(0 != activate_threads_~tmp___1~0); 17084#L936-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 17005#L408 assume !(1 == ~t3_pc~0); 16950#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 16555#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 16509#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 16510#L944 assume !(0 != activate_threads_~tmp___2~0); 16869#L944-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 16870#L427 assume 1 == ~t4_pc~0; 17069#L428 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 16861#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 16641#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 16490#L952 assume !(0 != activate_threads_~tmp___3~0); 16491#L952-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 16459#L446 assume !(1 == ~t5_pc~0); 16460#L446-2 is_transmit5_triggered_~__retres1~5 := 0; 16465#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 16841#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 16842#L960 assume !(0 != activate_threads_~tmp___4~0); 17036#L960-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 16593#L465 assume 1 == ~t6_pc~0; 16394#L466 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 16395#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 16922#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 16758#L968 assume !(0 != activate_threads_~tmp___5~0); 16759#L968-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 16725#L484 assume !(1 == ~t7_pc~0); 16575#L484-2 is_transmit7_triggered_~__retres1~7 := 0; 16730#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 17017#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 17018#L976 assume !(0 != activate_threads_~tmp___6~0); 17096#L976-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16982#L827 assume !(1 == ~M_E~0); 16969#L827-2 assume !(1 == ~T1_E~0); 16854#L832-1 assume !(1 == ~T2_E~0); 16668#L837-1 assume !(1 == ~T3_E~0); 16476#L842-1 assume !(1 == ~T4_E~0); 16477#L847-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16895#L852-1 assume !(1 == ~T6_E~0); 16648#L857-1 assume !(1 == ~T7_E~0); 16430#L862-1 assume !(1 == ~E_1~0); 16431#L867-1 assume !(1 == ~E_2~0); 17038#L872-1 assume !(1 == ~E_3~0); 16769#L877-1 assume !(1 == ~E_4~0); 16525#L882-1 assume !(1 == ~E_5~0); 16526#L887-1 assume 1 == ~E_6~0;~E_6~0 := 2; 17085#L892-1 assume !(1 == ~E_7~0); 16948#L897-1 assume { :end_inline_reset_delta_events } true; 16581#L1138-3 [2018-11-18 10:50:52,958 INFO L796 eck$LassoCheckResult]: Loop: 16581#L1138-3 assume true; 16907#L1138-1 assume !false; 16908#L1139 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 16673#L719 assume true; 16929#L611-1 assume !false; 16833#L612 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 16834#L559 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 16597#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 17121#L602 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 16737#L616 assume !(0 != eval_~tmp~0); 16739#L734 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 17719#L504-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 17718#L744-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17717#L744-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17716#L749-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17715#L754-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17714#L759-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17713#L764-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17712#L769-3 assume !(0 == ~T6_E~0); 17711#L774-3 assume !(0 == ~T7_E~0); 17710#L779-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17709#L784-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17708#L789-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17707#L794-3 assume 0 == ~E_4~0;~E_4~0 := 1; 17706#L799-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17668#L804-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17667#L809-3 assume !(0 == ~E_7~0); 17666#L814-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 17665#L351-24 assume !(1 == ~m_pc~0); 17664#L351-26 is_master_triggered_~__retres1~0 := 0; 17663#L362-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 17086#L363-8 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 16806#L920-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 16778#L920-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 16779#L370-24 assume !(1 == ~t1_pc~0); 16880#L370-26 is_transmit1_triggered_~__retres1~1 := 0; 16879#L381-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 17112#L382-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 16352#L928-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 16353#L928-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 16358#L389-24 assume !(1 == ~t2_pc~0); 16890#L389-26 is_transmit2_triggered_~__retres1~2 := 0; 16354#L400-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 16355#L401-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 16495#L936-24 assume !(0 != activate_threads_~tmp___1~0); 16983#L936-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 16975#L408-24 assume 1 == ~t3_pc~0; 16976#L409-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 16548#L419-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 16549#L420-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 16613#L944-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 16656#L944-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 16658#L427-24 assume 1 == ~t4_pc~0; 17044#L428-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 17046#L438-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 17636#L439-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 17635#L952-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 17634#L952-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 17633#L446-24 assume !(1 == ~t5_pc~0); 17632#L446-26 is_transmit5_triggered_~__retres1~5 := 0; 17630#L457-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 17629#L458-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 17628#L960-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 17627#L960-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 17626#L465-24 assume 1 == ~t6_pc~0; 16386#L466-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 16387#L476-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 17624#L477-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 17623#L968-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 17622#L968-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 17621#L484-24 assume !(1 == ~t7_pc~0); 17619#L484-26 is_transmit7_triggered_~__retres1~7 := 0; 17092#L495-8 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 16992#L496-8 activate_threads_#t~ret16 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 16993#L976-24 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 17129#L976-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16973#L827-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16974#L827-5 assume !(1 == ~T1_E~0); 16845#L832-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16669#L837-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16481#L842-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16482#L847-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16898#L852-3 assume !(1 == ~T6_E~0); 16649#L857-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16436#L862-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16437#L867-3 assume !(1 == ~E_2~0); 17039#L872-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16774#L877-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16527#L882-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16528#L887-3 assume 1 == ~E_6~0;~E_6~0 := 2; 17079#L892-3 assume !(1 == ~E_7~0); 16941#L897-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 16942#L559-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 16586#L601-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 17123#L602-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 16997#L1157 assume !(0 == start_simulation_~tmp~3); 16698#L1157-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 16984#L559-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 16589#L601-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 17124#L602-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 17087#L1112 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 16808#L1119 stop_simulation_#res := stop_simulation_~__retres2~0; 16809#L1120 start_simulation_#t~ret19 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 16580#L1170 assume !(0 != start_simulation_~tmp___0~1); 16581#L1138-3 [2018-11-18 10:50:52,958 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:52,959 INFO L82 PathProgramCache]: Analyzing trace with hash 1001467303, now seen corresponding path program 1 times [2018-11-18 10:50:52,959 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:52,959 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:52,959 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:52,960 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:50:52,960 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:52,964 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:50:52,988 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:50:52,988 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:50:52,989 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 10:50:52,989 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 10:50:52,989 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:52,989 INFO L82 PathProgramCache]: Analyzing trace with hash -1722369846, now seen corresponding path program 1 times [2018-11-18 10:50:52,989 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:52,989 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:52,990 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:52,990 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:50:52,990 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:52,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:50:53,033 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:50:53,034 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:50:53,034 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:50:53,034 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 10:50:53,034 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 10:50:53,034 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:50:53,034 INFO L87 Difference]: Start difference. First operand 1388 states and 2006 transitions. cyclomatic complexity: 620 Second operand 3 states. [2018-11-18 10:50:53,114 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:50:53,114 INFO L93 Difference]: Finished difference Result 2543 states and 3653 transitions. [2018-11-18 10:50:53,115 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 10:50:53,115 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2543 states and 3653 transitions. [2018-11-18 10:50:53,123 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2436 [2018-11-18 10:50:53,131 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2543 states to 2543 states and 3653 transitions. [2018-11-18 10:50:53,131 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2543 [2018-11-18 10:50:53,133 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2543 [2018-11-18 10:50:53,133 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2543 states and 3653 transitions. [2018-11-18 10:50:53,135 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 10:50:53,135 INFO L705 BuchiCegarLoop]: Abstraction has 2543 states and 3653 transitions. [2018-11-18 10:50:53,137 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2543 states and 3653 transitions. [2018-11-18 10:50:53,160 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2543 to 2537. [2018-11-18 10:50:53,160 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2537 states. [2018-11-18 10:50:53,165 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2537 states to 2537 states and 3647 transitions. [2018-11-18 10:50:53,165 INFO L728 BuchiCegarLoop]: Abstraction has 2537 states and 3647 transitions. [2018-11-18 10:50:53,165 INFO L608 BuchiCegarLoop]: Abstraction has 2537 states and 3647 transitions. [2018-11-18 10:50:53,165 INFO L442 BuchiCegarLoop]: ======== Iteration 12============ [2018-11-18 10:50:53,165 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2537 states and 3647 transitions. [2018-11-18 10:50:53,170 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2430 [2018-11-18 10:50:53,171 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:50:53,171 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:50:53,172 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:53,172 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:53,172 INFO L794 eck$LassoCheckResult]: Stem: 20650#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 20563#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 20564#L1101 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 20630#L504 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20273#L511 assume 1 == ~m_i~0;~m_st~0 := 0; 20274#L511-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 20442#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20869#L521-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20806#L526-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20530#L531-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 20531#L536-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 20942#L541-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 20788#L546-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20789#L744 assume !(0 == ~M_E~0); 20793#L744-2 assume !(0 == ~T1_E~0); 20614#L749-1 assume !(0 == ~T2_E~0); 20421#L754-1 assume !(0 == ~T3_E~0); 20422#L759-1 assume !(0 == ~T4_E~0); 20848#L764-1 assume !(0 == ~T5_E~0); 20594#L769-1 assume !(0 == ~T6_E~0); 20376#L774-1 assume !(0 == ~T7_E~0); 20377#L779-1 assume !(0 == ~E_1~0); 21029#L784-1 assume !(0 == ~E_2~0); 20836#L789-1 assume !(0 == ~E_3~0); 20459#L794-1 assume !(0 == ~E_4~0); 20460#L799-1 assume !(0 == ~E_5~0); 21080#L804-1 assume !(0 == ~E_6~0); 20895#L809-1 assume !(0 == ~E_7~0); 20696#L814-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 20588#L351 assume !(1 == ~m_pc~0); 20572#L351-2 is_master_triggered_~__retres1~0 := 0; 20573#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 21066#L363 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 20800#L920 assume !(0 != activate_threads_~tmp~1); 20801#L920-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 20765#L370 assume !(1 == ~t1_pc~0); 20766#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 20775#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 21114#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 20516#L928 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 20366#L928-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 20367#L389 assume !(1 == ~t2_pc~0); 20859#L389-2 is_transmit2_triggered_~__retres1~2 := 0; 20343#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 20344#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 20444#L936 assume !(0 != activate_threads_~tmp___1~0); 21084#L936-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 20985#L408 assume !(1 == ~t3_pc~0); 20925#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 20494#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 20447#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 20448#L944 assume !(0 != activate_threads_~tmp___2~0); 20818#L944-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 20819#L427 assume 1 == ~t4_pc~0; 21062#L428 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 20810#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 20585#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 20428#L952 assume !(0 != activate_threads_~tmp___3~0); 20429#L952-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 20397#L446 assume !(1 == ~t5_pc~0); 20398#L446-2 is_transmit5_triggered_~__retres1~5 := 0; 20403#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 20790#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 20791#L960 assume !(0 != activate_threads_~tmp___4~0); 21025#L960-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 20532#L465 assume 1 == ~t6_pc~0; 20333#L466 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 20334#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 20870#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 20707#L968 assume !(0 != activate_threads_~tmp___5~0); 20708#L968-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 20669#L484 assume !(1 == ~t7_pc~0); 20514#L484-2 is_transmit7_triggered_~__retres1~7 := 0; 20674#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 20999#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 21000#L976 assume !(0 != activate_threads_~tmp___6~0); 21096#L976-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20958#L827 assume !(1 == ~M_E~0); 20945#L827-2 assume !(1 == ~T1_E~0); 20803#L832-1 assume !(1 == ~T2_E~0); 20612#L837-1 assume !(1 == ~T3_E~0); 20414#L842-1 assume !(1 == ~T4_E~0); 20415#L847-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20845#L852-1 assume !(1 == ~T6_E~0); 20592#L857-1 assume !(1 == ~T7_E~0); 20368#L862-1 assume !(1 == ~E_1~0); 20369#L867-1 assume !(1 == ~E_2~0); 21027#L872-1 assume !(1 == ~E_3~0); 20718#L877-1 assume !(1 == ~E_4~0); 20463#L882-1 assume !(1 == ~E_5~0); 20464#L887-1 assume 1 == ~E_6~0;~E_6~0 := 2; 21085#L892-1 assume !(1 == ~E_7~0); 20900#L897-1 assume { :end_inline_reset_delta_events } true; 20901#L1138-3 [2018-11-18 10:50:53,172 INFO L796 eck$LassoCheckResult]: Loop: 20901#L1138-3 assume true; 22465#L1138-1 assume !false; 20902#L1139 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 20617#L719 assume true; 20889#L611-1 assume !false; 20782#L612 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 20783#L559 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 22443#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 21145#L602 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 21146#L616 assume !(0 != eval_~tmp~0); 22439#L734 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 22784#L504-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 22783#L744-3 assume 0 == ~M_E~0;~M_E~0 := 1; 22782#L744-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22781#L749-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22779#L754-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22777#L759-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 22775#L764-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22773#L769-3 assume !(0 == ~T6_E~0); 22771#L774-3 assume !(0 == ~T7_E~0); 22768#L779-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22766#L784-3 assume 0 == ~E_2~0;~E_2~0 := 1; 22764#L789-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22762#L794-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22760#L799-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22758#L804-3 assume 0 == ~E_6~0;~E_6~0 := 1; 22755#L809-3 assume !(0 == ~E_7~0); 22753#L814-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 22751#L351-24 assume !(1 == ~m_pc~0); 22743#L351-26 is_master_triggered_~__retres1~0 := 0; 22742#L362-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 22741#L363-8 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 22740#L920-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 22739#L920-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 22738#L370-24 assume !(1 == ~t1_pc~0); 22736#L370-26 is_transmit1_triggered_~__retres1~1 := 0; 22734#L381-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 22733#L382-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 22732#L928-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 22730#L928-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 22728#L389-24 assume !(1 == ~t2_pc~0); 22726#L389-26 is_transmit2_triggered_~__retres1~2 := 0; 22724#L400-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 22723#L401-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 22720#L936-24 assume !(0 != activate_threads_~tmp___1~0); 22718#L936-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 22716#L408-24 assume 1 == ~t3_pc~0; 22713#L409-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 22711#L419-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 22709#L420-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 22707#L944-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 22705#L944-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 22703#L427-24 assume !(1 == ~t4_pc~0); 22700#L427-26 is_transmit4_triggered_~__retres1~4 := 0; 22698#L438-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 22696#L439-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 22693#L952-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 22691#L952-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 22688#L446-24 assume 1 == ~t5_pc~0; 22684#L447-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 22681#L457-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 22677#L458-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 22674#L960-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 22671#L960-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 22668#L465-24 assume !(1 == ~t6_pc~0); 22664#L465-26 is_transmit6_triggered_~__retres1~6 := 0; 22660#L476-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 22657#L477-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 22653#L968-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 22650#L968-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 22647#L484-24 assume !(1 == ~t7_pc~0); 22643#L484-26 is_transmit7_triggered_~__retres1~7 := 0; 22640#L495-8 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 20969#L496-8 activate_threads_#t~ret16 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 20970#L976-24 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 21134#L976-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 20949#L827-3 assume 1 == ~M_E~0;~M_E~0 := 2; 20950#L827-5 assume !(1 == ~T1_E~0); 20794#L832-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20613#L837-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20419#L842-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20420#L847-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20847#L852-3 assume !(1 == ~T6_E~0); 20593#L857-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 20374#L862-3 assume 1 == ~E_1~0;~E_1~0 := 2; 20375#L867-3 assume !(1 == ~E_2~0); 21028#L872-3 assume 1 == ~E_3~0;~E_3~0 := 2; 20724#L877-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20465#L882-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20466#L887-3 assume 1 == ~E_6~0;~E_6~0 := 2; 21126#L892-3 assume !(1 == ~E_7~0); 22561#L897-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 21129#L559-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 20525#L601-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 21124#L602-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 21140#L1157 assume !(0 == start_simulation_~tmp~3); 22480#L1157-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 22479#L559-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 22471#L601-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 22470#L602-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 22469#L1112 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 22468#L1119 stop_simulation_#res := stop_simulation_~__retres2~0; 22467#L1120 start_simulation_#t~ret19 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 22466#L1170 assume !(0 != start_simulation_~tmp___0~1); 20901#L1138-3 [2018-11-18 10:50:53,172 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:53,172 INFO L82 PathProgramCache]: Analyzing trace with hash 299899078, now seen corresponding path program 1 times [2018-11-18 10:50:53,173 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:53,173 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:53,173 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:53,173 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:50:53,173 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:53,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:50:53,209 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:50:53,209 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:50:53,210 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 10:50:53,210 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 10:50:53,210 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:53,210 INFO L82 PathProgramCache]: Analyzing trace with hash -715942103, now seen corresponding path program 1 times [2018-11-18 10:50:53,210 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:53,210 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:53,211 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:53,211 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:50:53,211 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:53,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:50:53,235 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:50:53,235 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:50:53,235 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:50:53,235 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 10:50:53,235 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 10:50:53,235 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:50:53,236 INFO L87 Difference]: Start difference. First operand 2537 states and 3647 transitions. cyclomatic complexity: 1114 Second operand 3 states. [2018-11-18 10:50:53,304 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:50:53,304 INFO L93 Difference]: Finished difference Result 4714 states and 6742 transitions. [2018-11-18 10:50:53,306 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 10:50:53,306 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4714 states and 6742 transitions. [2018-11-18 10:50:53,322 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4592 [2018-11-18 10:50:53,338 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4714 states to 4714 states and 6742 transitions. [2018-11-18 10:50:53,338 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4714 [2018-11-18 10:50:53,342 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4714 [2018-11-18 10:50:53,343 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4714 states and 6742 transitions. [2018-11-18 10:50:53,348 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 10:50:53,348 INFO L705 BuchiCegarLoop]: Abstraction has 4714 states and 6742 transitions. [2018-11-18 10:50:53,351 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4714 states and 6742 transitions. [2018-11-18 10:50:53,390 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4714 to 4702. [2018-11-18 10:50:53,390 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 4702 states. [2018-11-18 10:50:53,399 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4702 states to 4702 states and 6730 transitions. [2018-11-18 10:50:53,399 INFO L728 BuchiCegarLoop]: Abstraction has 4702 states and 6730 transitions. [2018-11-18 10:50:53,399 INFO L608 BuchiCegarLoop]: Abstraction has 4702 states and 6730 transitions. [2018-11-18 10:50:53,399 INFO L442 BuchiCegarLoop]: ======== Iteration 13============ [2018-11-18 10:50:53,399 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4702 states and 6730 transitions. [2018-11-18 10:50:53,411 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4580 [2018-11-18 10:50:53,412 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:50:53,412 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:50:53,413 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:53,413 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:53,413 INFO L794 eck$LassoCheckResult]: Stem: 27917#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 27829#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 27830#L1101 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 27902#L504 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 27531#L511 assume 1 == ~m_i~0;~m_st~0 := 0; 27532#L511-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 27703#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 28132#L521-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 28064#L526-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 27793#L531-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 27794#L536-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 28190#L541-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 28045#L546-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 28046#L744 assume !(0 == ~M_E~0); 28051#L744-2 assume !(0 == ~T1_E~0); 27881#L749-1 assume !(0 == ~T2_E~0); 27678#L754-1 assume !(0 == ~T3_E~0); 27679#L759-1 assume !(0 == ~T4_E~0); 28110#L764-1 assume !(0 == ~T5_E~0); 27858#L769-1 assume !(0 == ~T6_E~0); 27632#L774-1 assume !(0 == ~T7_E~0); 27633#L779-1 assume !(0 == ~E_1~0); 28267#L784-1 assume !(0 == ~E_2~0); 28095#L789-1 assume !(0 == ~E_3~0); 27720#L794-1 assume !(0 == ~E_4~0); 27721#L799-1 assume !(0 == ~E_5~0); 28330#L804-1 assume !(0 == ~E_6~0); 28155#L809-1 assume !(0 == ~E_7~0); 27958#L814-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 27852#L351 assume !(1 == ~m_pc~0); 27835#L351-2 is_master_triggered_~__retres1~0 := 0; 27836#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 28315#L363 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 28058#L920 assume !(0 != activate_threads_~tmp~1); 28059#L920-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 28023#L370 assume !(1 == ~t1_pc~0); 28024#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 28032#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 28367#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 27777#L928 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 27622#L928-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 27623#L389 assume !(1 == ~t2_pc~0); 28122#L389-2 is_transmit2_triggered_~__retres1~2 := 0; 27602#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 27603#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 27705#L936 assume !(0 != activate_threads_~tmp___1~0); 28334#L936-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 28233#L408 assume !(1 == ~t3_pc~0); 28174#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 27757#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 27708#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 27709#L944 assume !(0 != activate_threads_~tmp___2~0); 28076#L944-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 28077#L427 assume !(1 == ~t4_pc~0); 28324#L427-2 is_transmit4_triggered_~__retres1~4 := 0; 28068#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 27849#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 27685#L952 assume !(0 != activate_threads_~tmp___3~0); 27686#L952-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 27653#L446 assume !(1 == ~t5_pc~0); 27654#L446-2 is_transmit5_triggered_~__retres1~5 := 0; 27659#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 28047#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 28048#L960 assume !(0 != activate_threads_~tmp___4~0); 28263#L960-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 27795#L465 assume 1 == ~t6_pc~0; 27591#L466 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 27592#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 28133#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 27965#L968 assume !(0 != activate_threads_~tmp___5~0); 27966#L968-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 27935#L484 assume !(1 == ~t7_pc~0); 27775#L484-2 is_transmit7_triggered_~__retres1~7 := 0; 27939#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 28246#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 28247#L976 assume !(0 != activate_threads_~tmp___6~0); 28347#L976-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28207#L827 assume !(1 == ~M_E~0); 28194#L827-2 assume !(1 == ~T1_E~0); 28061#L832-1 assume !(1 == ~T2_E~0); 27878#L837-1 assume !(1 == ~T3_E~0); 27671#L842-1 assume !(1 == ~T4_E~0); 27672#L847-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 28108#L852-1 assume !(1 == ~T6_E~0); 27856#L857-1 assume !(1 == ~T7_E~0); 27624#L862-1 assume !(1 == ~E_1~0); 27625#L867-1 assume !(1 == ~E_2~0); 28265#L872-1 assume !(1 == ~E_3~0); 27976#L877-1 assume !(1 == ~E_4~0); 27724#L882-1 assume !(1 == ~E_5~0); 27725#L887-1 assume 1 == ~E_6~0;~E_6~0 := 2; 28335#L892-1 assume !(1 == ~E_7~0); 28160#L897-1 assume { :end_inline_reset_delta_events } true; 28161#L1138-3 [2018-11-18 10:50:53,413 INFO L796 eck$LassoCheckResult]: Loop: 28161#L1138-3 assume true; 30794#L1138-1 assume !false; 30772#L1139 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 30765#L719 assume true; 30761#L611-1 assume !false; 30756#L612 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 30696#L559 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 30690#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 30688#L602 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 30686#L616 assume !(0 != eval_~tmp~0); 30687#L734 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 31642#L504-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 31640#L744-3 assume 0 == ~M_E~0;~M_E~0 := 1; 31638#L744-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 31636#L749-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 31633#L754-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 31631#L759-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 31629#L764-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 31627#L769-3 assume !(0 == ~T6_E~0); 31625#L774-3 assume !(0 == ~T7_E~0); 31623#L779-3 assume 0 == ~E_1~0;~E_1~0 := 1; 31622#L784-3 assume 0 == ~E_2~0;~E_2~0 := 1; 31619#L789-3 assume 0 == ~E_3~0;~E_3~0 := 1; 31617#L794-3 assume 0 == ~E_4~0;~E_4~0 := 1; 31615#L799-3 assume 0 == ~E_5~0;~E_5~0 := 1; 31613#L804-3 assume 0 == ~E_6~0;~E_6~0 := 1; 31611#L809-3 assume !(0 == ~E_7~0); 31609#L814-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 31607#L351-24 assume !(1 == ~m_pc~0); 31605#L351-26 is_master_triggered_~__retres1~0 := 0; 31603#L362-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 31601#L363-8 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 31599#L920-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 31597#L920-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 31594#L370-24 assume !(1 == ~t1_pc~0); 31591#L370-26 is_transmit1_triggered_~__retres1~1 := 0; 31589#L381-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 31587#L382-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 31585#L928-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 31583#L928-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 31581#L389-24 assume !(1 == ~t2_pc~0); 31579#L389-26 is_transmit2_triggered_~__retres1~2 := 0; 31577#L400-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 31575#L401-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 31573#L936-24 assume !(0 != activate_threads_~tmp___1~0); 31571#L936-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 31570#L408-24 assume 1 == ~t3_pc~0; 31568#L409-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 31567#L419-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 31565#L420-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 31556#L944-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 31555#L944-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 31554#L427-24 assume !(1 == ~t4_pc~0); 31553#L427-26 is_transmit4_triggered_~__retres1~4 := 0; 31552#L438-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 31551#L439-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 31550#L952-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 31549#L952-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 31548#L446-24 assume 1 == ~t5_pc~0; 31546#L447-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 31544#L457-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 31542#L458-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 31540#L960-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 31538#L960-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 31537#L465-24 assume 1 == ~t6_pc~0; 31536#L466-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 31534#L476-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 31533#L477-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 31532#L968-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 31531#L968-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 31530#L484-24 assume !(1 == ~t7_pc~0); 31528#L484-26 is_transmit7_triggered_~__retres1~7 := 0; 31527#L495-8 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 31526#L496-8 activate_threads_#t~ret16 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 31525#L976-24 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 31524#L976-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31523#L827-3 assume 1 == ~M_E~0;~M_E~0 := 2; 31522#L827-5 assume !(1 == ~T1_E~0); 31521#L832-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 31520#L837-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 31519#L842-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31342#L847-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 31341#L852-3 assume !(1 == ~T6_E~0); 31340#L857-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 31339#L862-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28384#L867-3 assume !(1 == ~E_2~0); 28385#L872-3 assume 1 == ~E_3~0;~E_3~0 := 2; 31316#L877-3 assume 1 == ~E_4~0;~E_4~0 := 2; 31304#L882-3 assume 1 == ~E_5~0;~E_5~0 := 2; 31303#L887-3 assume 1 == ~E_6~0;~E_6~0 := 2; 31302#L892-3 assume !(1 == ~E_7~0); 31294#L897-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 31288#L559-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 30825#L601-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 30824#L602-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 30821#L1157 assume !(0 == start_simulation_~tmp~3); 30818#L1157-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 30816#L559-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 30807#L601-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 30804#L602-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 30802#L1112 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 30800#L1119 stop_simulation_#res := stop_simulation_~__retres2~0; 30798#L1120 start_simulation_#t~ret19 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 30796#L1170 assume !(0 != start_simulation_~tmp___0~1); 28161#L1138-3 [2018-11-18 10:50:53,413 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:53,413 INFO L82 PathProgramCache]: Analyzing trace with hash 699890277, now seen corresponding path program 1 times [2018-11-18 10:50:53,413 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:53,414 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:53,414 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:53,414 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:50:53,414 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:53,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:50:53,446 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:50:53,447 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:50:53,447 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 10:50:53,447 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 10:50:53,447 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:53,447 INFO L82 PathProgramCache]: Analyzing trace with hash -1115933302, now seen corresponding path program 1 times [2018-11-18 10:50:53,447 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:53,447 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:53,448 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:53,448 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:50:53,448 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:53,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:50:53,482 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:50:53,482 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:50:53,482 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:50:53,483 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 10:50:53,483 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 10:50:53,483 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:50:53,483 INFO L87 Difference]: Start difference. First operand 4702 states and 6730 transitions. cyclomatic complexity: 2036 Second operand 3 states. [2018-11-18 10:50:53,560 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:50:53,560 INFO L93 Difference]: Finished difference Result 8793 states and 12523 transitions. [2018-11-18 10:50:53,561 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 10:50:53,561 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8793 states and 12523 transitions. [2018-11-18 10:50:53,587 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8632 [2018-11-18 10:50:53,619 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8793 states to 8793 states and 12523 transitions. [2018-11-18 10:50:53,619 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8793 [2018-11-18 10:50:53,624 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8793 [2018-11-18 10:50:53,624 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8793 states and 12523 transitions. [2018-11-18 10:50:53,632 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 10:50:53,632 INFO L705 BuchiCegarLoop]: Abstraction has 8793 states and 12523 transitions. [2018-11-18 10:50:53,639 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8793 states and 12523 transitions. [2018-11-18 10:50:53,708 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8793 to 8769. [2018-11-18 10:50:53,708 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8769 states. [2018-11-18 10:50:53,721 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8769 states to 8769 states and 12499 transitions. [2018-11-18 10:50:53,721 INFO L728 BuchiCegarLoop]: Abstraction has 8769 states and 12499 transitions. [2018-11-18 10:50:53,721 INFO L608 BuchiCegarLoop]: Abstraction has 8769 states and 12499 transitions. [2018-11-18 10:50:53,721 INFO L442 BuchiCegarLoop]: ======== Iteration 14============ [2018-11-18 10:50:53,722 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8769 states and 12499 transitions. [2018-11-18 10:50:53,742 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8608 [2018-11-18 10:50:53,742 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:50:53,742 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:50:53,743 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:53,743 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:53,743 INFO L794 eck$LassoCheckResult]: Stem: 41427#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 41334#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 41335#L1101 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 41409#L504 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 41033#L511 assume 1 == ~m_i~0;~m_st~0 := 0; 41034#L511-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41203#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41640#L521-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 41576#L526-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 41298#L531-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 41299#L536-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 41707#L541-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 41558#L546-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 41559#L744 assume !(0 == ~M_E~0); 41563#L744-2 assume !(0 == ~T1_E~0); 41389#L749-1 assume !(0 == ~T2_E~0); 41180#L754-1 assume !(0 == ~T3_E~0); 41181#L759-1 assume !(0 == ~T4_E~0); 41618#L764-1 assume !(0 == ~T5_E~0); 41365#L769-1 assume !(0 == ~T6_E~0); 41134#L774-1 assume !(0 == ~T7_E~0); 41135#L779-1 assume !(0 == ~E_1~0); 41785#L784-1 assume !(0 == ~E_2~0); 41605#L789-1 assume !(0 == ~E_3~0); 41220#L794-1 assume !(0 == ~E_4~0); 41221#L799-1 assume !(0 == ~E_5~0); 41837#L804-1 assume !(0 == ~E_6~0); 41662#L809-1 assume !(0 == ~E_7~0); 41471#L814-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 41359#L351 assume !(1 == ~m_pc~0); 41340#L351-2 is_master_triggered_~__retres1~0 := 0; 41341#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 41821#L363 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 41570#L920 assume !(0 != activate_threads_~tmp~1); 41571#L920-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 41536#L370 assume !(1 == ~t1_pc~0); 41537#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 41545#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 41871#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 41280#L928 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 41124#L928-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 41125#L389 assume !(1 == ~t2_pc~0); 41630#L389-2 is_transmit2_triggered_~__retres1~2 := 0; 41102#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 41103#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 41205#L936 assume !(0 != activate_threads_~tmp___1~0); 41842#L936-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 41748#L408 assume !(1 == ~t3_pc~0); 41691#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 41257#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 41208#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 41209#L944 assume !(0 != activate_threads_~tmp___2~0); 41588#L944-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 41589#L427 assume !(1 == ~t4_pc~0); 41831#L427-2 is_transmit4_triggered_~__retres1~4 := 0; 41580#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 41355#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 41187#L952 assume !(0 != activate_threads_~tmp___3~0); 41188#L952-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 41155#L446 assume !(1 == ~t5_pc~0); 41156#L446-2 is_transmit5_triggered_~__retres1~5 := 0; 41161#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 41560#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 41561#L960 assume !(0 != activate_threads_~tmp___4~0); 41781#L960-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 41300#L465 assume !(1 == ~t6_pc~0); 41301#L465-2 is_transmit6_triggered_~__retres1~6 := 0; 41302#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 41641#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 41480#L968 assume !(0 != activate_threads_~tmp___5~0); 41481#L968-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 41446#L484 assume !(1 == ~t7_pc~0); 41275#L484-2 is_transmit7_triggered_~__retres1~7 := 0; 41450#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 41761#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 41762#L976 assume !(0 != activate_threads_~tmp___6~0); 41851#L976-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 41724#L827 assume !(1 == ~M_E~0); 41710#L827-2 assume !(1 == ~T1_E~0); 41573#L832-1 assume !(1 == ~T2_E~0); 41386#L837-1 assume !(1 == ~T3_E~0); 41173#L842-1 assume !(1 == ~T4_E~0); 41174#L847-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 41616#L852-1 assume !(1 == ~T6_E~0); 41363#L857-1 assume !(1 == ~T7_E~0); 41128#L862-1 assume !(1 == ~E_1~0); 41129#L867-1 assume !(1 == ~E_2~0); 41783#L872-1 assume !(1 == ~E_3~0); 41490#L877-1 assume !(1 == ~E_4~0); 41224#L882-1 assume !(1 == ~E_5~0); 41225#L887-1 assume 1 == ~E_6~0;~E_6~0 := 2; 41843#L892-1 assume !(1 == ~E_7~0); 41667#L897-1 assume { :end_inline_reset_delta_events } true; 41668#L1138-3 [2018-11-18 10:50:53,743 INFO L796 eck$LassoCheckResult]: Loop: 41668#L1138-3 assume true; 47244#L1138-1 assume !false; 47236#L1139 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 47233#L719 assume true; 47231#L611-1 assume !false; 47230#L612 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 47154#L559 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 47148#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 47146#L602 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 47143#L616 assume !(0 != eval_~tmp~0); 47144#L734 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 47998#L504-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 47996#L744-3 assume 0 == ~M_E~0;~M_E~0 := 1; 47994#L744-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 47992#L749-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 47990#L754-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 47988#L759-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 47986#L764-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 47984#L769-3 assume !(0 == ~T6_E~0); 47982#L774-3 assume !(0 == ~T7_E~0); 47980#L779-3 assume 0 == ~E_1~0;~E_1~0 := 1; 47978#L784-3 assume 0 == ~E_2~0;~E_2~0 := 1; 47975#L789-3 assume 0 == ~E_3~0;~E_3~0 := 1; 47973#L794-3 assume 0 == ~E_4~0;~E_4~0 := 1; 47971#L799-3 assume 0 == ~E_5~0;~E_5~0 := 1; 47969#L804-3 assume 0 == ~E_6~0;~E_6~0 := 1; 47967#L809-3 assume !(0 == ~E_7~0); 47965#L814-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 47963#L351-24 assume !(1 == ~m_pc~0); 47961#L351-26 is_master_triggered_~__retres1~0 := 0; 47959#L362-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 47957#L363-8 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 47955#L920-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 47952#L920-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 47950#L370-24 assume !(1 == ~t1_pc~0); 47947#L370-26 is_transmit1_triggered_~__retres1~1 := 0; 47945#L381-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 47943#L382-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 47941#L928-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 47939#L928-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 47937#L389-24 assume !(1 == ~t2_pc~0); 47935#L389-26 is_transmit2_triggered_~__retres1~2 := 0; 47933#L400-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 47931#L401-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 47929#L936-24 assume !(0 != activate_threads_~tmp___1~0); 47927#L936-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 47925#L408-24 assume 1 == ~t3_pc~0; 47922#L409-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 47920#L419-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 47918#L420-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 47916#L944-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 47914#L944-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 47912#L427-24 assume !(1 == ~t4_pc~0); 47910#L427-26 is_transmit4_triggered_~__retres1~4 := 0; 47909#L438-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 47908#L439-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 47907#L952-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 47906#L952-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 47905#L446-24 assume !(1 == ~t5_pc~0); 47904#L446-26 is_transmit5_triggered_~__retres1~5 := 0; 47902#L457-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 47901#L458-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 47900#L960-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 47898#L960-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 47896#L465-24 assume !(1 == ~t6_pc~0); 47894#L465-26 is_transmit6_triggered_~__retres1~6 := 0; 47892#L476-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 47890#L477-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 47888#L968-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 47886#L968-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 47883#L484-24 assume !(1 == ~t7_pc~0); 47880#L484-26 is_transmit7_triggered_~__retres1~7 := 0; 47878#L495-8 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 47876#L496-8 activate_threads_#t~ret16 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 47874#L976-24 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 47872#L976-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 47870#L827-3 assume 1 == ~M_E~0;~M_E~0 := 2; 47868#L827-5 assume !(1 == ~T1_E~0); 47866#L832-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 47864#L837-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 47862#L842-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 47860#L847-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 47857#L852-3 assume !(1 == ~T6_E~0); 47855#L857-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 47853#L862-3 assume 1 == ~E_1~0;~E_1~0 := 2; 47851#L867-3 assume !(1 == ~E_2~0); 47849#L872-3 assume 1 == ~E_3~0;~E_3~0 := 2; 47847#L877-3 assume 1 == ~E_4~0;~E_4~0 := 2; 47844#L882-3 assume 1 == ~E_5~0;~E_5~0 := 2; 47842#L887-3 assume 1 == ~E_6~0;~E_6~0 := 2; 47840#L892-3 assume !(1 == ~E_7~0); 47838#L897-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 47826#L559-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 47820#L601-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 47818#L602-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 47815#L1157 assume !(0 == start_simulation_~tmp~3); 47812#L1157-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 47810#L559-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 47801#L601-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 47798#L602-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 47770#L1112 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 47761#L1119 stop_simulation_#res := stop_simulation_~__retres2~0; 47742#L1120 start_simulation_#t~ret19 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 47706#L1170 assume !(0 != start_simulation_~tmp___0~1); 41668#L1138-3 [2018-11-18 10:50:53,744 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:53,744 INFO L82 PathProgramCache]: Analyzing trace with hash 391451268, now seen corresponding path program 1 times [2018-11-18 10:50:53,744 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:53,744 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:53,744 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:53,745 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:50:53,745 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:53,749 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:50:53,770 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:50:53,770 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:50:53,770 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 10:50:53,771 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 10:50:53,771 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:53,771 INFO L82 PathProgramCache]: Analyzing trace with hash -2023946872, now seen corresponding path program 1 times [2018-11-18 10:50:53,771 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:53,771 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:53,772 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:53,772 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:50:53,772 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:53,777 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:50:53,806 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:50:53,806 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:50:53,806 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:50:53,806 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 10:50:53,807 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 10:50:53,807 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:50:53,807 INFO L87 Difference]: Start difference. First operand 8769 states and 12499 transitions. cyclomatic complexity: 3746 Second operand 3 states. [2018-11-18 10:50:53,867 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:50:53,868 INFO L93 Difference]: Finished difference Result 8769 states and 12449 transitions. [2018-11-18 10:50:53,869 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 10:50:53,870 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8769 states and 12449 transitions. [2018-11-18 10:50:53,895 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8608 [2018-11-18 10:50:53,920 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8769 states to 8769 states and 12449 transitions. [2018-11-18 10:50:53,921 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8769 [2018-11-18 10:50:53,926 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8769 [2018-11-18 10:50:53,926 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8769 states and 12449 transitions. [2018-11-18 10:50:53,933 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 10:50:53,933 INFO L705 BuchiCegarLoop]: Abstraction has 8769 states and 12449 transitions. [2018-11-18 10:50:53,939 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8769 states and 12449 transitions. [2018-11-18 10:50:53,999 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8769 to 8769. [2018-11-18 10:50:53,999 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8769 states. [2018-11-18 10:50:54,012 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8769 states to 8769 states and 12449 transitions. [2018-11-18 10:50:54,012 INFO L728 BuchiCegarLoop]: Abstraction has 8769 states and 12449 transitions. [2018-11-18 10:50:54,012 INFO L608 BuchiCegarLoop]: Abstraction has 8769 states and 12449 transitions. [2018-11-18 10:50:54,012 INFO L442 BuchiCegarLoop]: ======== Iteration 15============ [2018-11-18 10:50:54,012 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8769 states and 12449 transitions. [2018-11-18 10:50:54,032 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8608 [2018-11-18 10:50:54,032 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:50:54,032 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:50:54,033 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:54,033 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:54,033 INFO L794 eck$LassoCheckResult]: Stem: 58956#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 58868#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 58869#L1101 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 58936#L504 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 58578#L511 assume 1 == ~m_i~0;~m_st~0 := 0; 58579#L511-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 58746#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 59175#L521-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 59107#L526-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 58836#L531-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 58837#L536-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 59223#L541-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 59088#L546-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 59089#L744 assume !(0 == ~M_E~0); 59093#L744-2 assume !(0 == ~T1_E~0); 58920#L749-1 assume !(0 == ~T2_E~0); 58724#L754-1 assume !(0 == ~T3_E~0); 58725#L759-1 assume !(0 == ~T4_E~0); 59151#L764-1 assume !(0 == ~T5_E~0); 58899#L769-1 assume !(0 == ~T6_E~0); 58678#L774-1 assume !(0 == ~T7_E~0); 58679#L779-1 assume !(0 == ~E_1~0); 59296#L784-1 assume !(0 == ~E_2~0); 59136#L789-1 assume !(0 == ~E_3~0); 58763#L794-1 assume !(0 == ~E_4~0); 58764#L799-1 assume !(0 == ~E_5~0); 59351#L804-1 assume !(0 == ~E_6~0); 59198#L809-1 assume !(0 == ~E_7~0); 59000#L814-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 58892#L351 assume !(1 == ~m_pc~0); 58876#L351-2 is_master_triggered_~__retres1~0 := 0; 58877#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 59333#L363 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 59100#L920 assume !(0 != activate_threads_~tmp~1); 59101#L920-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 59066#L370 assume !(1 == ~t1_pc~0); 59067#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 59075#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 59384#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 58820#L928 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 58668#L928-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 58669#L389 assume !(1 == ~t2_pc~0); 59165#L389-2 is_transmit2_triggered_~__retres1~2 := 0; 58645#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 58646#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 58748#L936 assume !(0 != activate_threads_~tmp___1~0); 59355#L936-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 59262#L408 assume !(1 == ~t3_pc~0); 59207#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 58797#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 58751#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 58752#L944 assume !(0 != activate_threads_~tmp___2~0); 59119#L944-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 59120#L427 assume !(1 == ~t4_pc~0); 59346#L427-2 is_transmit4_triggered_~__retres1~4 := 0; 59111#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 58889#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 58731#L952 assume !(0 != activate_threads_~tmp___3~0); 58732#L952-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 58699#L446 assume !(1 == ~t5_pc~0); 58700#L446-2 is_transmit5_triggered_~__retres1~5 := 0; 58706#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 59090#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 59091#L960 assume !(0 != activate_threads_~tmp___4~0); 59292#L960-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 58838#L465 assume !(1 == ~t6_pc~0); 58839#L465-2 is_transmit6_triggered_~__retres1~6 := 0; 58840#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 59176#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 59010#L968 assume !(0 != activate_threads_~tmp___5~0); 59011#L968-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 58975#L484 assume !(1 == ~t7_pc~0); 58817#L484-2 is_transmit7_triggered_~__retres1~7 := 0; 58980#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 59274#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 59275#L976 assume !(0 != activate_threads_~tmp___6~0); 59365#L976-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 59239#L827 assume !(1 == ~M_E~0); 59226#L827-2 assume !(1 == ~T1_E~0); 59103#L832-1 assume !(1 == ~T2_E~0); 58918#L837-1 assume !(1 == ~T3_E~0); 58717#L842-1 assume !(1 == ~T4_E~0); 58718#L847-1 assume !(1 == ~T5_E~0); 59147#L852-1 assume !(1 == ~T6_E~0); 58897#L857-1 assume !(1 == ~T7_E~0); 58670#L862-1 assume !(1 == ~E_1~0); 58671#L867-1 assume !(1 == ~E_2~0); 59294#L872-1 assume !(1 == ~E_3~0); 59020#L877-1 assume !(1 == ~E_4~0); 58767#L882-1 assume !(1 == ~E_5~0); 58768#L887-1 assume 1 == ~E_6~0;~E_6~0 := 2; 59356#L892-1 assume !(1 == ~E_7~0); 59203#L897-1 assume { :end_inline_reset_delta_events } true; 59204#L1138-3 [2018-11-18 10:50:54,034 INFO L796 eck$LassoCheckResult]: Loop: 59204#L1138-3 assume true; 62000#L1138-1 assume !false; 61843#L1139 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 61840#L719 assume true; 61838#L611-1 assume !false; 61835#L612 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 61823#L559 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 61817#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 61815#L602 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 61812#L616 assume !(0 != eval_~tmp~0); 61813#L734 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 62213#L504-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 62211#L744-3 assume 0 == ~M_E~0;~M_E~0 := 1; 62209#L744-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 62207#L749-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 62205#L754-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 62203#L759-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 62201#L764-3 assume !(0 == ~T5_E~0); 62199#L769-3 assume !(0 == ~T6_E~0); 62197#L774-3 assume !(0 == ~T7_E~0); 62195#L779-3 assume 0 == ~E_1~0;~E_1~0 := 1; 62193#L784-3 assume 0 == ~E_2~0;~E_2~0 := 1; 62191#L789-3 assume 0 == ~E_3~0;~E_3~0 := 1; 62188#L794-3 assume 0 == ~E_4~0;~E_4~0 := 1; 62186#L799-3 assume 0 == ~E_5~0;~E_5~0 := 1; 62184#L804-3 assume 0 == ~E_6~0;~E_6~0 := 1; 62182#L809-3 assume !(0 == ~E_7~0); 62180#L814-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 62178#L351-24 assume !(1 == ~m_pc~0); 62176#L351-26 is_master_triggered_~__retres1~0 := 0; 62174#L362-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 62172#L363-8 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 62170#L920-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 62168#L920-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 62165#L370-24 assume !(1 == ~t1_pc~0); 62162#L370-26 is_transmit1_triggered_~__retres1~1 := 0; 62160#L381-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 62158#L382-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 62156#L928-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 62154#L928-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 62152#L389-24 assume !(1 == ~t2_pc~0); 62150#L389-26 is_transmit2_triggered_~__retres1~2 := 0; 62148#L400-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 62146#L401-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 62144#L936-24 assume !(0 != activate_threads_~tmp___1~0); 62142#L936-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 62140#L408-24 assume 1 == ~t3_pc~0; 62137#L409-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 62135#L419-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 62133#L420-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 62131#L944-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 62129#L944-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 62127#L427-24 assume !(1 == ~t4_pc~0); 62125#L427-26 is_transmit4_triggered_~__retres1~4 := 0; 62123#L438-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 62122#L439-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 62121#L952-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 62120#L952-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 62119#L446-24 assume 1 == ~t5_pc~0; 62117#L447-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 62116#L457-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 62115#L458-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 62114#L960-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 62112#L960-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 62110#L465-24 assume !(1 == ~t6_pc~0); 62108#L465-26 is_transmit6_triggered_~__retres1~6 := 0; 62106#L476-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 62104#L477-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 62102#L968-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 62100#L968-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 62097#L484-24 assume !(1 == ~t7_pc~0); 62094#L484-26 is_transmit7_triggered_~__retres1~7 := 0; 62092#L495-8 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 62090#L496-8 activate_threads_#t~ret16 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 62088#L976-24 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 62086#L976-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 62084#L827-3 assume 1 == ~M_E~0;~M_E~0 := 2; 62082#L827-5 assume !(1 == ~T1_E~0); 62080#L832-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 62078#L837-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 62076#L842-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 62074#L847-3 assume !(1 == ~T5_E~0); 62071#L852-3 assume !(1 == ~T6_E~0); 62069#L857-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 62067#L862-3 assume 1 == ~E_1~0;~E_1~0 := 2; 62065#L867-3 assume !(1 == ~E_2~0); 62063#L872-3 assume 1 == ~E_3~0;~E_3~0 := 2; 62061#L877-3 assume 1 == ~E_4~0;~E_4~0 := 2; 62059#L882-3 assume 1 == ~E_5~0;~E_5~0 := 2; 62057#L887-3 assume 1 == ~E_6~0;~E_6~0 := 2; 62055#L892-3 assume !(1 == ~E_7~0); 62053#L897-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 62041#L559-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 62035#L601-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 62033#L602-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 62030#L1157 assume !(0 == start_simulation_~tmp~3); 62027#L1157-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 62025#L559-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 62016#L601-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 62013#L602-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 62011#L1112 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 62009#L1119 stop_simulation_#res := stop_simulation_~__retres2~0; 62007#L1120 start_simulation_#t~ret19 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 62005#L1170 assume !(0 != start_simulation_~tmp___0~1); 59204#L1138-3 [2018-11-18 10:50:54,034 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:54,034 INFO L82 PathProgramCache]: Analyzing trace with hash 1092515846, now seen corresponding path program 1 times [2018-11-18 10:50:54,034 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:54,034 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:54,035 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:54,035 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:50:54,035 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:54,043 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:50:54,090 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:50:54,090 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:50:54,090 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 10:50:54,090 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 10:50:54,091 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:54,091 INFO L82 PathProgramCache]: Analyzing trace with hash 1187310637, now seen corresponding path program 1 times [2018-11-18 10:50:54,091 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:54,091 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:54,092 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:54,092 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:50:54,092 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:54,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:50:54,128 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:50:54,128 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:50:54,128 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:50:54,129 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 10:50:54,129 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 10:50:54,129 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:50:54,132 INFO L87 Difference]: Start difference. First operand 8769 states and 12449 transitions. cyclomatic complexity: 3696 Second operand 3 states. [2018-11-18 10:50:54,200 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:50:54,200 INFO L93 Difference]: Finished difference Result 8769 states and 12347 transitions. [2018-11-18 10:50:54,201 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 10:50:54,202 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8769 states and 12347 transitions. [2018-11-18 10:50:54,233 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8608 [2018-11-18 10:50:54,257 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8769 states to 8769 states and 12347 transitions. [2018-11-18 10:50:54,257 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8769 [2018-11-18 10:50:54,263 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8769 [2018-11-18 10:50:54,263 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8769 states and 12347 transitions. [2018-11-18 10:50:54,331 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 10:50:54,331 INFO L705 BuchiCegarLoop]: Abstraction has 8769 states and 12347 transitions. [2018-11-18 10:50:54,336 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8769 states and 12347 transitions. [2018-11-18 10:50:54,385 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8769 to 8769. [2018-11-18 10:50:54,386 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 8769 states. [2018-11-18 10:50:54,396 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8769 states to 8769 states and 12347 transitions. [2018-11-18 10:50:54,397 INFO L728 BuchiCegarLoop]: Abstraction has 8769 states and 12347 transitions. [2018-11-18 10:50:54,397 INFO L608 BuchiCegarLoop]: Abstraction has 8769 states and 12347 transitions. [2018-11-18 10:50:54,397 INFO L442 BuchiCegarLoop]: ======== Iteration 16============ [2018-11-18 10:50:54,397 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8769 states and 12347 transitions. [2018-11-18 10:50:54,416 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8608 [2018-11-18 10:50:54,416 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:50:54,416 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:50:54,417 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:54,417 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:54,417 INFO L794 eck$LassoCheckResult]: Stem: 76512#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 76426#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 76427#L1101 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 76495#L504 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 76123#L511 assume 1 == ~m_i~0;~m_st~0 := 0; 76124#L511-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 76290#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 76722#L521-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 76659#L526-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 76390#L531-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 76391#L536-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 76789#L541-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 76641#L546-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 76642#L744 assume !(0 == ~M_E~0); 76646#L744-2 assume !(0 == ~T1_E~0); 76479#L749-1 assume !(0 == ~T2_E~0); 76270#L754-1 assume !(0 == ~T3_E~0); 76271#L759-1 assume !(0 == ~T4_E~0); 76702#L764-1 assume !(0 == ~T5_E~0); 76457#L769-1 assume !(0 == ~T6_E~0); 76222#L774-1 assume !(0 == ~T7_E~0); 76223#L779-1 assume !(0 == ~E_1~0); 76868#L784-1 assume !(0 == ~E_2~0); 76688#L789-1 assume !(0 == ~E_3~0); 76307#L794-1 assume !(0 == ~E_4~0); 76308#L799-1 assume !(0 == ~E_5~0); 76921#L804-1 assume !(0 == ~E_6~0); 76744#L809-1 assume !(0 == ~E_7~0); 76552#L814-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 76451#L351 assume !(1 == ~m_pc~0); 76435#L351-2 is_master_triggered_~__retres1~0 := 0; 76436#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 76905#L363 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 76653#L920 assume !(0 != activate_threads_~tmp~1); 76654#L920-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 76619#L370 assume !(1 == ~t1_pc~0); 76620#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 76628#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 76958#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 76368#L928 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 76210#L928-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 76211#L389 assume !(1 == ~t2_pc~0); 76714#L389-2 is_transmit2_triggered_~__retres1~2 := 0; 76186#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 76187#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 76292#L936 assume !(0 != activate_threads_~tmp___1~0); 76926#L936-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 76829#L408 assume !(1 == ~t3_pc~0); 76772#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 76343#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 76295#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 76296#L944 assume !(0 != activate_threads_~tmp___2~0); 76671#L944-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 76672#L427 assume !(1 == ~t4_pc~0); 76915#L427-2 is_transmit4_triggered_~__retres1~4 := 0; 76663#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 76448#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 76277#L952 assume !(0 != activate_threads_~tmp___3~0); 76278#L952-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 76245#L446 assume !(1 == ~t5_pc~0); 76246#L446-2 is_transmit5_triggered_~__retres1~5 := 0; 76251#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 76643#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 76644#L960 assume !(0 != activate_threads_~tmp___4~0); 76864#L960-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 76392#L465 assume !(1 == ~t6_pc~0); 76393#L465-2 is_transmit6_triggered_~__retres1~6 := 0; 76394#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 76723#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 76563#L968 assume !(0 != activate_threads_~tmp___5~0); 76564#L968-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 76529#L484 assume !(1 == ~t7_pc~0); 76363#L484-2 is_transmit7_triggered_~__retres1~7 := 0; 76533#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 76842#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 76843#L976 assume !(0 != activate_threads_~tmp___6~0); 76939#L976-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 76805#L827 assume !(1 == ~M_E~0); 76792#L827-2 assume !(1 == ~T1_E~0); 76656#L832-1 assume !(1 == ~T2_E~0); 76477#L837-1 assume !(1 == ~T3_E~0); 76263#L842-1 assume !(1 == ~T4_E~0); 76264#L847-1 assume !(1 == ~T5_E~0); 76699#L852-1 assume !(1 == ~T6_E~0); 76455#L857-1 assume !(1 == ~T7_E~0); 76212#L862-1 assume !(1 == ~E_1~0); 76213#L867-1 assume !(1 == ~E_2~0); 76866#L872-1 assume !(1 == ~E_3~0); 76572#L877-1 assume !(1 == ~E_4~0); 76311#L882-1 assume !(1 == ~E_5~0); 76312#L887-1 assume !(1 == ~E_6~0); 76927#L892-1 assume !(1 == ~E_7~0); 76751#L897-1 assume { :end_inline_reset_delta_events } true; 76752#L1138-3 [2018-11-18 10:50:54,417 INFO L796 eck$LassoCheckResult]: Loop: 76752#L1138-3 assume true; 80932#L1138-1 assume !false; 80924#L1139 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 80918#L719 assume true; 80913#L611-1 assume !false; 80911#L612 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 80841#L559 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 80832#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 80827#L602 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 80819#L616 assume !(0 != eval_~tmp~0); 80820#L734 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 84774#L504-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 84773#L744-3 assume 0 == ~M_E~0;~M_E~0 := 1; 84772#L744-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 84771#L749-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 84770#L754-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 84769#L759-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 84768#L764-3 assume !(0 == ~T5_E~0); 84767#L769-3 assume !(0 == ~T6_E~0); 84766#L774-3 assume !(0 == ~T7_E~0); 84765#L779-3 assume 0 == ~E_1~0;~E_1~0 := 1; 84764#L784-3 assume 0 == ~E_2~0;~E_2~0 := 1; 84763#L789-3 assume 0 == ~E_3~0;~E_3~0 := 1; 84762#L794-3 assume 0 == ~E_4~0;~E_4~0 := 1; 84761#L799-3 assume 0 == ~E_5~0;~E_5~0 := 1; 84760#L804-3 assume !(0 == ~E_6~0); 84758#L809-3 assume !(0 == ~E_7~0); 84756#L814-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 84754#L351-24 assume !(1 == ~m_pc~0); 84752#L351-26 is_master_triggered_~__retres1~0 := 0; 84750#L362-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 84748#L363-8 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 84746#L920-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 84743#L920-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 84741#L370-24 assume 1 == ~t1_pc~0; 84739#L371-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 84737#L381-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 84736#L382-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 76140#L928-24 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 76141#L928-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 76146#L389-24 assume !(1 == ~t2_pc~0); 76696#L389-26 is_transmit2_triggered_~__retres1~2 := 0; 76142#L400-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 76143#L401-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 76281#L936-24 assume !(0 != activate_threads_~tmp___1~0); 76806#L936-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 76798#L408-24 assume 1 == ~t3_pc~0; 76799#L409-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 76334#L419-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 76335#L420-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 76416#L944-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 76464#L944-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 76467#L427-24 assume !(1 == ~t4_pc~0); 76908#L427-26 is_transmit4_triggered_~__retres1~4 := 0; 84775#L438-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 76446#L439-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 76238#L952-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 76239#L952-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 76972#L446-24 assume 1 == ~t5_pc~0; 76951#L447-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 76734#L457-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 76601#L458-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 76602#L960-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 76852#L960-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 76199#L465-24 assume !(1 == ~t6_pc~0); 76200#L465-26 is_transmit6_triggered_~__retres1~6 := 0; 76207#L476-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 76719#L477-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 76524#L968-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 76494#L968-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 76480#L484-24 assume !(1 == ~t7_pc~0); 76329#L484-26 is_transmit7_triggered_~__retres1~7 := 0; 76484#L495-8 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 76816#L496-8 activate_threads_#t~ret16 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 76817#L976-24 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 76979#L976-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 76796#L827-3 assume 1 == ~M_E~0;~M_E~0 := 2; 76797#L827-5 assume !(1 == ~T1_E~0); 76647#L832-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 76478#L837-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 76268#L842-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 76269#L847-3 assume !(1 == ~T5_E~0); 76701#L852-3 assume !(1 == ~T6_E~0); 76456#L857-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 76220#L862-3 assume 1 == ~E_1~0;~E_1~0 := 2; 76221#L867-3 assume !(1 == ~E_2~0); 76867#L872-3 assume 1 == ~E_3~0;~E_3~0 := 2; 76577#L877-3 assume 1 == ~E_4~0;~E_4~0 := 2; 76313#L882-3 assume 1 == ~E_5~0;~E_5~0 := 2; 76314#L887-3 assume !(1 == ~E_6~0); 76919#L892-3 assume !(1 == ~E_7~0); 76920#L897-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 81111#L559-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 81100#L601-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 81095#L602-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 81089#L1157 assume !(0 == start_simulation_~tmp~3); 81085#L1157-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 80977#L559-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 80964#L601-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 80959#L602-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 80954#L1112 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 80949#L1119 stop_simulation_#res := stop_simulation_~__retres2~0; 80945#L1120 start_simulation_#t~ret19 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 80941#L1170 assume !(0 != start_simulation_~tmp___0~1); 76752#L1138-3 [2018-11-18 10:50:54,418 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:54,418 INFO L82 PathProgramCache]: Analyzing trace with hash 1092517768, now seen corresponding path program 1 times [2018-11-18 10:50:54,418 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:54,418 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:54,418 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:54,418 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:50:54,419 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:54,425 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:50:54,485 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:50:54,486 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:50:54,486 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 10:50:54,487 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 10:50:54,489 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:54,489 INFO L82 PathProgramCache]: Analyzing trace with hash -759069742, now seen corresponding path program 1 times [2018-11-18 10:50:54,489 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:54,489 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:54,490 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:54,490 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:50:54,490 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:54,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:50:54,511 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:50:54,512 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:50:54,512 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:50:54,512 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 10:50:54,512 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 10:50:54,512 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 10:50:54,512 INFO L87 Difference]: Start difference. First operand 8769 states and 12347 transitions. cyclomatic complexity: 3594 Second operand 5 states. [2018-11-18 10:50:54,758 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:50:54,758 INFO L93 Difference]: Finished difference Result 24480 states and 34278 transitions. [2018-11-18 10:50:54,759 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 10:50:54,760 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 24480 states and 34278 transitions. [2018-11-18 10:50:54,829 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 24076 [2018-11-18 10:50:54,890 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 24480 states to 24480 states and 34278 transitions. [2018-11-18 10:50:54,891 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 24480 [2018-11-18 10:50:54,905 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 24480 [2018-11-18 10:50:54,905 INFO L73 IsDeterministic]: Start isDeterministic. Operand 24480 states and 34278 transitions. [2018-11-18 10:50:54,918 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 10:50:54,918 INFO L705 BuchiCegarLoop]: Abstraction has 24480 states and 34278 transitions. [2018-11-18 10:50:54,933 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24480 states and 34278 transitions. [2018-11-18 10:50:55,026 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24480 to 9108. [2018-11-18 10:50:55,026 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9108 states. [2018-11-18 10:50:55,037 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9108 states to 9108 states and 12686 transitions. [2018-11-18 10:50:55,037 INFO L728 BuchiCegarLoop]: Abstraction has 9108 states and 12686 transitions. [2018-11-18 10:50:55,037 INFO L608 BuchiCegarLoop]: Abstraction has 9108 states and 12686 transitions. [2018-11-18 10:50:55,037 INFO L442 BuchiCegarLoop]: ======== Iteration 17============ [2018-11-18 10:50:55,037 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9108 states and 12686 transitions. [2018-11-18 10:50:55,056 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8944 [2018-11-18 10:50:55,056 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:50:55,056 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:50:55,057 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:55,057 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:55,058 INFO L794 eck$LassoCheckResult]: Stem: 109766#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 109680#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 109681#L1101 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 109748#L504 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 109385#L511 assume 1 == ~m_i~0;~m_st~0 := 0; 109386#L511-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 109548#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 110012#L521-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 109927#L526-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 109644#L531-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 109645#L536-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 110073#L541-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 109907#L546-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 109908#L744 assume !(0 == ~M_E~0); 109914#L744-2 assume !(0 == ~T1_E~0); 109729#L749-1 assume !(0 == ~T2_E~0); 109526#L754-1 assume !(0 == ~T3_E~0); 109527#L759-1 assume !(0 == ~T4_E~0); 109992#L764-1 assume !(0 == ~T5_E~0); 109708#L769-1 assume !(0 == ~T6_E~0); 109480#L774-1 assume !(0 == ~T7_E~0); 109481#L779-1 assume !(0 == ~E_1~0); 110153#L784-1 assume !(0 == ~E_2~0); 109970#L789-1 assume !(0 == ~E_3~0); 109565#L794-1 assume !(0 == ~E_4~0); 109566#L799-1 assume !(0 == ~E_5~0); 110198#L804-1 assume !(0 == ~E_6~0); 110036#L809-1 assume !(0 == ~E_7~0); 109813#L814-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 109702#L351 assume !(1 == ~m_pc~0); 109686#L351-2 is_master_triggered_~__retres1~0 := 0; 109687#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 110187#L363 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 109921#L920 assume !(0 != activate_threads_~tmp~1); 109922#L920-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 109883#L370 assume !(1 == ~t1_pc~0); 109884#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 109893#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 110236#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 109625#L928 assume !(0 != activate_threads_~tmp___0~0); 109470#L928-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 109471#L389 assume !(1 == ~t2_pc~0); 110004#L389-2 is_transmit2_triggered_~__retres1~2 := 0; 109448#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 109449#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 109550#L936 assume !(0 != activate_threads_~tmp___1~0); 110204#L936-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 110115#L408 assume !(1 == ~t3_pc~0); 110057#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 109601#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 109553#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 109554#L944 assume !(0 != activate_threads_~tmp___2~0); 109939#L944-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 109940#L427 assume !(1 == ~t4_pc~0); 110193#L427-2 is_transmit4_triggered_~__retres1~4 := 0; 109931#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 109699#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 109533#L952 assume !(0 != activate_threads_~tmp___3~0); 109534#L952-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 109502#L446 assume !(1 == ~t5_pc~0); 109503#L446-2 is_transmit5_triggered_~__retres1~5 := 0; 109508#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 109910#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 109911#L960 assume !(0 != activate_threads_~tmp___4~0); 110149#L960-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 109646#L465 assume !(1 == ~t6_pc~0); 109647#L465-2 is_transmit6_triggered_~__retres1~6 := 0; 109648#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 110013#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 109822#L968 assume !(0 != activate_threads_~tmp___5~0); 109823#L968-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 109786#L484 assume !(1 == ~t7_pc~0); 109620#L484-2 is_transmit7_triggered_~__retres1~7 := 0; 109790#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 110127#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 110128#L976 assume !(0 != activate_threads_~tmp___6~0); 110218#L976-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 110090#L827 assume !(1 == ~M_E~0); 110076#L827-2 assume !(1 == ~T1_E~0); 109924#L832-1 assume !(1 == ~T2_E~0); 109726#L837-1 assume !(1 == ~T3_E~0); 109519#L842-1 assume !(1 == ~T4_E~0); 109520#L847-1 assume !(1 == ~T5_E~0); 109990#L852-1 assume !(1 == ~T6_E~0); 109706#L857-1 assume !(1 == ~T7_E~0); 109472#L862-1 assume !(1 == ~E_1~0); 109473#L867-1 assume !(1 == ~E_2~0); 110151#L872-1 assume !(1 == ~E_3~0); 109833#L877-1 assume !(1 == ~E_4~0); 109569#L882-1 assume !(1 == ~E_5~0); 109570#L887-1 assume !(1 == ~E_6~0); 110205#L892-1 assume !(1 == ~E_7~0); 110042#L897-1 assume { :end_inline_reset_delta_events } true; 110043#L1138-3 [2018-11-18 10:50:55,058 INFO L796 eck$LassoCheckResult]: Loop: 110043#L1138-3 assume true; 111793#L1138-1 assume !false; 111622#L1139 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 111620#L719 assume true; 111529#L611-1 assume !false; 111525#L612 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 111350#L559 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 111343#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 111341#L602 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 111338#L616 assume !(0 != eval_~tmp~0); 111339#L734 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 112540#L504-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 112537#L744-3 assume 0 == ~M_E~0;~M_E~0 := 1; 112535#L744-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 112533#L749-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 112531#L754-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 112529#L759-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 112527#L764-3 assume !(0 == ~T5_E~0); 112525#L769-3 assume !(0 == ~T6_E~0); 112523#L774-3 assume !(0 == ~T7_E~0); 112520#L779-3 assume 0 == ~E_1~0;~E_1~0 := 1; 112517#L784-3 assume 0 == ~E_2~0;~E_2~0 := 1; 112514#L789-3 assume 0 == ~E_3~0;~E_3~0 := 1; 112495#L794-3 assume 0 == ~E_4~0;~E_4~0 := 1; 112490#L799-3 assume 0 == ~E_5~0;~E_5~0 := 1; 112486#L804-3 assume !(0 == ~E_6~0); 112481#L809-3 assume !(0 == ~E_7~0); 112461#L814-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 112460#L351-24 assume !(1 == ~m_pc~0); 112459#L351-26 is_master_triggered_~__retres1~0 := 0; 112458#L362-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 112457#L363-8 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 112456#L920-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 112455#L920-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 112454#L370-24 assume !(1 == ~t1_pc~0); 112453#L370-26 is_transmit1_triggered_~__retres1~1 := 0; 112451#L381-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 112449#L382-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 112447#L928-24 assume !(0 != activate_threads_~tmp___0~0); 112441#L928-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 112435#L389-24 assume !(1 == ~t2_pc~0); 112429#L389-26 is_transmit2_triggered_~__retres1~2 := 0; 112424#L400-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 112418#L401-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 112413#L936-24 assume !(0 != activate_threads_~tmp___1~0); 112408#L936-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 112402#L408-24 assume 1 == ~t3_pc~0; 112379#L409-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 112375#L419-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 112371#L420-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 112368#L944-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 112364#L944-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 112327#L427-24 assume !(1 == ~t4_pc~0); 112307#L427-26 is_transmit4_triggered_~__retres1~4 := 0; 112301#L438-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 112295#L439-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 112289#L952-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 112284#L952-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 112279#L446-24 assume 1 == ~t5_pc~0; 112273#L447-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 112268#L457-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 112261#L458-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 112240#L960-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 112234#L960-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 112228#L465-24 assume !(1 == ~t6_pc~0); 112222#L465-26 is_transmit6_triggered_~__retres1~6 := 0; 112216#L476-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 112210#L477-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 112204#L968-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 112183#L968-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 112177#L484-24 assume !(1 == ~t7_pc~0); 112169#L484-26 is_transmit7_triggered_~__retres1~7 := 0; 112162#L495-8 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 112154#L496-8 activate_threads_#t~ret16 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 112147#L976-24 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 112141#L976-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 112135#L827-3 assume 1 == ~M_E~0;~M_E~0 := 2; 112129#L827-5 assume !(1 == ~T1_E~0); 112121#L832-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 112114#L837-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 112108#L842-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 112103#L847-3 assume !(1 == ~T5_E~0); 112098#L852-3 assume !(1 == ~T6_E~0); 112092#L857-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 112087#L862-3 assume 1 == ~E_1~0;~E_1~0 := 2; 112081#L867-3 assume !(1 == ~E_2~0); 112060#L872-3 assume 1 == ~E_3~0;~E_3~0 := 2; 112054#L877-3 assume 1 == ~E_4~0;~E_4~0 := 2; 112048#L882-3 assume 1 == ~E_5~0;~E_5~0 := 2; 112042#L887-3 assume !(1 == ~E_6~0); 112036#L892-3 assume !(1 == ~E_7~0); 112033#L897-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 111986#L559-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 111976#L601-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 111970#L602-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 111962#L1157 assume !(0 == start_simulation_~tmp~3); 111956#L1157-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 111813#L559-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 111803#L601-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 111802#L602-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 111801#L1112 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 111800#L1119 stop_simulation_#res := stop_simulation_~__retres2~0; 111798#L1120 start_simulation_#t~ret19 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 111796#L1170 assume !(0 != start_simulation_~tmp___0~1); 110043#L1138-3 [2018-11-18 10:50:55,058 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:55,058 INFO L82 PathProgramCache]: Analyzing trace with hash 1968536774, now seen corresponding path program 1 times [2018-11-18 10:50:55,058 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:55,058 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:55,059 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:55,059 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:50:55,059 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:55,063 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:50:55,068 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:50:55,107 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:55,107 INFO L82 PathProgramCache]: Analyzing trace with hash -584280721, now seen corresponding path program 1 times [2018-11-18 10:50:55,107 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:55,108 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:55,108 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:55,108 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:50:55,108 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:55,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:50:55,143 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:50:55,143 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:50:55,143 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:50:55,144 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 10:50:55,144 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 10:50:55,144 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:50:55,144 INFO L87 Difference]: Start difference. First operand 9108 states and 12686 transitions. cyclomatic complexity: 3594 Second operand 3 states. [2018-11-18 10:50:55,188 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:50:55,188 INFO L93 Difference]: Finished difference Result 10347 states and 14406 transitions. [2018-11-18 10:50:55,190 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 10:50:55,190 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10347 states and 14406 transitions. [2018-11-18 10:50:55,217 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 10112 [2018-11-18 10:50:55,241 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10347 states to 10347 states and 14406 transitions. [2018-11-18 10:50:55,241 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10347 [2018-11-18 10:50:55,247 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10347 [2018-11-18 10:50:55,247 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10347 states and 14406 transitions. [2018-11-18 10:50:55,253 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 10:50:55,253 INFO L705 BuchiCegarLoop]: Abstraction has 10347 states and 14406 transitions. [2018-11-18 10:50:55,259 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10347 states and 14406 transitions. [2018-11-18 10:50:55,318 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10347 to 10347. [2018-11-18 10:50:55,319 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10347 states. [2018-11-18 10:50:55,330 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10347 states to 10347 states and 14406 transitions. [2018-11-18 10:50:55,330 INFO L728 BuchiCegarLoop]: Abstraction has 10347 states and 14406 transitions. [2018-11-18 10:50:55,330 INFO L608 BuchiCegarLoop]: Abstraction has 10347 states and 14406 transitions. [2018-11-18 10:50:55,330 INFO L442 BuchiCegarLoop]: ======== Iteration 18============ [2018-11-18 10:50:55,330 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10347 states and 14406 transitions. [2018-11-18 10:50:55,353 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 10112 [2018-11-18 10:50:55,353 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:50:55,353 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:50:55,354 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:55,354 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:55,354 INFO L794 eck$LassoCheckResult]: Stem: 129231#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 129141#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 129142#L1101 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 129214#L504 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 128846#L511 assume 1 == ~m_i~0;~m_st~0 := 0; 128847#L511-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 129010#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 129475#L521-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 129391#L526-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 129107#L531-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 129108#L536-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 129529#L541-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 129369#L546-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 129370#L744 assume !(0 == ~M_E~0); 129375#L744-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 129196#L749-1 assume !(0 == ~T2_E~0); 129197#L754-1 assume !(0 == ~T3_E~0); 129697#L759-1 assume !(0 == ~T4_E~0); 129698#L764-1 assume !(0 == ~T5_E~0); 129173#L769-1 assume !(0 == ~T6_E~0); 129174#L774-1 assume !(0 == ~T7_E~0); 129742#L779-1 assume !(0 == ~E_1~0); 129743#L784-1 assume !(0 == ~E_2~0); 129431#L789-1 assume !(0 == ~E_3~0); 129432#L794-1 assume !(0 == ~E_4~0); 129731#L799-1 assume !(0 == ~E_5~0); 129732#L804-1 assume !(0 == ~E_6~0); 129500#L809-1 assume !(0 == ~E_7~0); 129501#L814-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 129166#L351 assume !(1 == ~m_pc~0); 129167#L351-2 is_master_triggered_~__retres1~0 := 0; 129655#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 129656#L363 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 129383#L920 assume !(0 != activate_threads_~tmp~1); 129384#L920-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 129345#L370 assume !(1 == ~t1_pc~0); 129346#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 129783#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 129781#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 129087#L928 assume !(0 != activate_threads_~tmp___0~0); 128930#L928-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 128931#L389 assume !(1 == ~t2_pc~0); 129464#L389-2 is_transmit2_triggered_~__retres1~2 := 0; 129465#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 129774#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 129679#L936 assume !(0 != activate_threads_~tmp___1~0); 129680#L936-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 129570#L408 assume !(1 == ~t3_pc~0); 129571#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 129773#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 129772#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 129771#L944 assume !(0 != activate_threads_~tmp___2~0); 129770#L944-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 129740#L427 assume !(1 == ~t4_pc~0); 129741#L427-2 is_transmit4_triggered_~__retres1~4 := 0; 129396#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 129162#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 129163#L952 assume !(0 != activate_threads_~tmp___3~0); 129768#L952-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 128962#L446 assume !(1 == ~t5_pc~0); 128963#L446-2 is_transmit5_triggered_~__retres1~5 := 0; 129767#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 129371#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 129372#L960 assume !(0 != activate_threads_~tmp___4~0); 129611#L960-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 129612#L465 assume !(1 == ~t6_pc~0); 129111#L465-2 is_transmit6_triggered_~__retres1~6 := 0; 129112#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 129766#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 129288#L968 assume !(0 != activate_threads_~tmp___5~0); 129289#L968-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 129765#L484 assume !(1 == ~t7_pc~0); 129256#L484-2 is_transmit7_triggered_~__retres1~7 := 0; 129257#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 129585#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 129586#L976 assume !(0 != activate_threads_~tmp___6~0); 129699#L976-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 129546#L827 assume !(1 == ~M_E~0); 129532#L827-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 129388#L832-1 assume !(1 == ~T2_E~0); 129194#L837-1 assume !(1 == ~T3_E~0); 128980#L842-1 assume !(1 == ~T4_E~0); 128981#L847-1 assume !(1 == ~T5_E~0); 129445#L852-1 assume !(1 == ~T6_E~0); 129171#L857-1 assume !(1 == ~T7_E~0); 128932#L862-1 assume !(1 == ~E_1~0); 128933#L867-1 assume !(1 == ~E_2~0); 129614#L872-1 assume !(1 == ~E_3~0); 129299#L877-1 assume !(1 == ~E_4~0); 129031#L882-1 assume !(1 == ~E_5~0); 129032#L887-1 assume !(1 == ~E_6~0); 129683#L892-1 assume !(1 == ~E_7~0); 129506#L897-1 assume { :end_inline_reset_delta_events } true; 129507#L1138-3 [2018-11-18 10:50:55,355 INFO L796 eck$LassoCheckResult]: Loop: 129507#L1138-3 assume true; 132562#L1138-1 assume !false; 132430#L1139 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 132427#L719 assume true; 132425#L611-1 assume !false; 132423#L612 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 132408#L559 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 132402#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 132400#L602 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 132398#L616 assume !(0 != eval_~tmp~0); 132399#L734 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 132785#L504-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 132783#L744-3 assume 0 == ~M_E~0;~M_E~0 := 1; 132780#L744-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 132778#L749-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 132776#L754-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 132774#L759-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 132770#L764-3 assume !(0 == ~T5_E~0); 132768#L769-3 assume !(0 == ~T6_E~0); 132766#L774-3 assume !(0 == ~T7_E~0); 132764#L779-3 assume 0 == ~E_1~0;~E_1~0 := 1; 132761#L784-3 assume 0 == ~E_2~0;~E_2~0 := 1; 132759#L789-3 assume 0 == ~E_3~0;~E_3~0 := 1; 132757#L794-3 assume 0 == ~E_4~0;~E_4~0 := 1; 132755#L799-3 assume 0 == ~E_5~0;~E_5~0 := 1; 132753#L804-3 assume !(0 == ~E_6~0); 132751#L809-3 assume !(0 == ~E_7~0); 132749#L814-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 132747#L351-24 assume !(1 == ~m_pc~0); 132745#L351-26 is_master_triggered_~__retres1~0 := 0; 132742#L362-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 132740#L363-8 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 132738#L920-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 132736#L920-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 132734#L370-24 assume !(1 == ~t1_pc~0); 132730#L370-26 is_transmit1_triggered_~__retres1~1 := 0; 132728#L381-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 132726#L382-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 132724#L928-24 assume !(0 != activate_threads_~tmp___0~0); 132721#L928-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 132719#L389-24 assume !(1 == ~t2_pc~0); 132717#L389-26 is_transmit2_triggered_~__retres1~2 := 0; 132714#L400-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 132712#L401-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 132710#L936-24 assume !(0 != activate_threads_~tmp___1~0); 132708#L936-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 132706#L408-24 assume !(1 == ~t3_pc~0); 132704#L408-26 is_transmit3_triggered_~__retres1~3 := 0; 132701#L419-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 132699#L420-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 132697#L944-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 132695#L944-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 132693#L427-24 assume !(1 == ~t4_pc~0); 132690#L427-26 is_transmit4_triggered_~__retres1~4 := 0; 132688#L438-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 132686#L439-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 132684#L952-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 132682#L952-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 132680#L446-24 assume !(1 == ~t5_pc~0); 132678#L446-26 is_transmit5_triggered_~__retres1~5 := 0; 132676#L457-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 132675#L458-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 132673#L960-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 132672#L960-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 132671#L465-24 assume !(1 == ~t6_pc~0); 132670#L465-26 is_transmit6_triggered_~__retres1~6 := 0; 132669#L476-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 132667#L477-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 132665#L968-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 132663#L968-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 132661#L484-24 assume !(1 == ~t7_pc~0); 132658#L484-26 is_transmit7_triggered_~__retres1~7 := 0; 132656#L495-8 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 132652#L496-8 activate_threads_#t~ret16 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 132650#L976-24 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 132648#L976-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 132646#L827-3 assume 1 == ~M_E~0;~M_E~0 := 2; 132643#L827-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 132640#L832-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 132638#L837-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 132636#L842-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 132634#L847-3 assume !(1 == ~T5_E~0); 132632#L852-3 assume !(1 == ~T6_E~0); 132630#L857-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 132628#L862-3 assume 1 == ~E_1~0;~E_1~0 := 2; 132626#L867-3 assume !(1 == ~E_2~0); 132623#L872-3 assume 1 == ~E_3~0;~E_3~0 := 2; 132621#L877-3 assume 1 == ~E_4~0;~E_4~0 := 2; 132619#L882-3 assume 1 == ~E_5~0;~E_5~0 := 2; 132617#L887-3 assume !(1 == ~E_6~0); 132615#L892-3 assume !(1 == ~E_7~0); 132613#L897-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 132601#L559-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 132595#L601-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 132593#L602-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 132590#L1157 assume !(0 == start_simulation_~tmp~3); 132587#L1157-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 132585#L559-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 132576#L601-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 132574#L602-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 132572#L1112 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 132570#L1119 stop_simulation_#res := stop_simulation_~__retres2~0; 132568#L1120 start_simulation_#t~ret19 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 132565#L1170 assume !(0 != start_simulation_~tmp___0~1); 129507#L1138-3 [2018-11-18 10:50:55,355 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:55,355 INFO L82 PathProgramCache]: Analyzing trace with hash -1286806590, now seen corresponding path program 1 times [2018-11-18 10:50:55,355 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:55,355 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:55,356 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:55,356 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:50:55,356 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:55,359 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:50:55,381 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:50:55,382 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:50:55,382 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 10:50:55,382 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 10:50:55,382 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:55,382 INFO L82 PathProgramCache]: Analyzing trace with hash -662193621, now seen corresponding path program 1 times [2018-11-18 10:50:55,382 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:55,382 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:55,383 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:55,383 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:50:55,383 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:55,387 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:50:55,404 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:50:55,404 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:50:55,404 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:50:55,405 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 10:50:55,405 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 10:50:55,405 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:50:55,405 INFO L87 Difference]: Start difference. First operand 10347 states and 14406 transitions. cyclomatic complexity: 4075 Second operand 3 states. [2018-11-18 10:50:55,437 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:50:55,437 INFO L93 Difference]: Finished difference Result 9108 states and 12636 transitions. [2018-11-18 10:50:55,439 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 10:50:55,439 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9108 states and 12636 transitions. [2018-11-18 10:50:55,502 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8944 [2018-11-18 10:50:55,518 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9108 states to 9108 states and 12636 transitions. [2018-11-18 10:50:55,518 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9108 [2018-11-18 10:50:55,522 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9108 [2018-11-18 10:50:55,523 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9108 states and 12636 transitions. [2018-11-18 10:50:55,528 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 10:50:55,528 INFO L705 BuchiCegarLoop]: Abstraction has 9108 states and 12636 transitions. [2018-11-18 10:50:55,532 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9108 states and 12636 transitions. [2018-11-18 10:50:55,582 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9108 to 9108. [2018-11-18 10:50:55,582 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9108 states. [2018-11-18 10:50:55,592 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9108 states to 9108 states and 12636 transitions. [2018-11-18 10:50:55,592 INFO L728 BuchiCegarLoop]: Abstraction has 9108 states and 12636 transitions. [2018-11-18 10:50:55,592 INFO L608 BuchiCegarLoop]: Abstraction has 9108 states and 12636 transitions. [2018-11-18 10:50:55,592 INFO L442 BuchiCegarLoop]: ======== Iteration 19============ [2018-11-18 10:50:55,592 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9108 states and 12636 transitions. [2018-11-18 10:50:55,611 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8944 [2018-11-18 10:50:55,611 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:50:55,611 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:50:55,612 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:55,612 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:55,613 INFO L794 eck$LassoCheckResult]: Stem: 148694#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 148605#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 148606#L1101 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 148674#L504 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 148308#L511 assume 1 == ~m_i~0;~m_st~0 := 0; 148309#L511-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 148472#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 148921#L521-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 148845#L526-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 148571#L531-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 148572#L536-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 148990#L541-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 148827#L546-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 148828#L744 assume !(0 == ~M_E~0); 148832#L744-2 assume !(0 == ~T1_E~0); 148657#L749-1 assume !(0 == ~T2_E~0); 148449#L754-1 assume !(0 == ~T3_E~0); 148450#L759-1 assume !(0 == ~T4_E~0); 148900#L764-1 assume !(0 == ~T5_E~0); 148635#L769-1 assume !(0 == ~T6_E~0); 148403#L774-1 assume !(0 == ~T7_E~0); 148404#L779-1 assume !(0 == ~E_1~0); 149068#L784-1 assume !(0 == ~E_2~0); 148884#L789-1 assume !(0 == ~E_3~0); 148489#L794-1 assume !(0 == ~E_4~0); 148490#L799-1 assume !(0 == ~E_5~0); 149117#L804-1 assume !(0 == ~E_6~0); 148943#L809-1 assume !(0 == ~E_7~0); 148737#L814-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 148629#L351 assume !(1 == ~m_pc~0); 148613#L351-2 is_master_triggered_~__retres1~0 := 0; 148614#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 149104#L363 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 148839#L920 assume !(0 != activate_threads_~tmp~1); 148840#L920-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 148805#L370 assume !(1 == ~t1_pc~0); 148806#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 148814#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 149153#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 148549#L928 assume !(0 != activate_threads_~tmp___0~0); 148393#L928-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 148394#L389 assume !(1 == ~t2_pc~0); 148912#L389-2 is_transmit2_triggered_~__retres1~2 := 0; 148370#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 148371#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 148474#L936 assume !(0 != activate_threads_~tmp___1~0); 149121#L936-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 149031#L408 assume !(1 == ~t3_pc~0); 148974#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 148524#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 148477#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 148478#L944 assume !(0 != activate_threads_~tmp___2~0); 148859#L944-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 148860#L427 assume !(1 == ~t4_pc~0); 149112#L427-2 is_transmit4_triggered_~__retres1~4 := 0; 148850#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 148626#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 148456#L952 assume !(0 != activate_threads_~tmp___3~0); 148457#L952-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 148425#L446 assume !(1 == ~t5_pc~0); 148426#L446-2 is_transmit5_triggered_~__retres1~5 := 0; 148431#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 148829#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 148830#L960 assume !(0 != activate_threads_~tmp___4~0); 149064#L960-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 148573#L465 assume !(1 == ~t6_pc~0); 148574#L465-2 is_transmit6_triggered_~__retres1~6 := 0; 148575#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 148922#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 148748#L968 assume !(0 != activate_threads_~tmp___5~0); 148749#L968-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 148715#L484 assume !(1 == ~t7_pc~0); 148544#L484-2 is_transmit7_triggered_~__retres1~7 := 0; 148719#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 149043#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 149044#L976 assume !(0 != activate_threads_~tmp___6~0); 149135#L976-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 149007#L827 assume !(1 == ~M_E~0); 148993#L827-2 assume !(1 == ~T1_E~0); 148842#L832-1 assume !(1 == ~T2_E~0); 148655#L837-1 assume !(1 == ~T3_E~0); 148442#L842-1 assume !(1 == ~T4_E~0); 148443#L847-1 assume !(1 == ~T5_E~0); 148897#L852-1 assume !(1 == ~T6_E~0); 148633#L857-1 assume !(1 == ~T7_E~0); 148395#L862-1 assume !(1 == ~E_1~0); 148396#L867-1 assume !(1 == ~E_2~0); 149066#L872-1 assume !(1 == ~E_3~0); 148759#L877-1 assume !(1 == ~E_4~0); 148493#L882-1 assume !(1 == ~E_5~0); 148494#L887-1 assume !(1 == ~E_6~0); 149122#L892-1 assume !(1 == ~E_7~0); 148948#L897-1 assume { :end_inline_reset_delta_events } true; 148949#L1138-3 [2018-11-18 10:50:55,613 INFO L796 eck$LassoCheckResult]: Loop: 148949#L1138-3 assume true; 153357#L1138-1 assume !false; 153351#L1139 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 153348#L719 assume true; 153346#L611-1 assume !false; 153344#L612 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 153332#L559 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 153326#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 153324#L602 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 153322#L616 assume !(0 != eval_~tmp~0); 153323#L734 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 153576#L504-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 153574#L744-3 assume 0 == ~M_E~0;~M_E~0 := 1; 153572#L744-5 assume !(0 == ~T1_E~0); 153568#L749-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 153566#L754-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 153564#L759-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 153562#L764-3 assume !(0 == ~T5_E~0); 153559#L769-3 assume !(0 == ~T6_E~0); 153557#L774-3 assume !(0 == ~T7_E~0); 153555#L779-3 assume 0 == ~E_1~0;~E_1~0 := 1; 153553#L784-3 assume 0 == ~E_2~0;~E_2~0 := 1; 153551#L789-3 assume 0 == ~E_3~0;~E_3~0 := 1; 153549#L794-3 assume 0 == ~E_4~0;~E_4~0 := 1; 153547#L799-3 assume 0 == ~E_5~0;~E_5~0 := 1; 153545#L804-3 assume !(0 == ~E_6~0); 153543#L809-3 assume !(0 == ~E_7~0); 153540#L814-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 153538#L351-24 assume !(1 == ~m_pc~0); 153536#L351-26 is_master_triggered_~__retres1~0 := 0; 153534#L362-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 153532#L363-8 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 153530#L920-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 153528#L920-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 153526#L370-24 assume !(1 == ~t1_pc~0); 153522#L370-26 is_transmit1_triggered_~__retres1~1 := 0; 153520#L381-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 153518#L382-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 153516#L928-24 assume !(0 != activate_threads_~tmp___0~0); 153512#L928-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 153510#L389-24 assume !(1 == ~t2_pc~0); 153508#L389-26 is_transmit2_triggered_~__retres1~2 := 0; 153506#L400-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 153504#L401-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 153502#L936-24 assume !(0 != activate_threads_~tmp___1~0); 153500#L936-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 153498#L408-24 assume 1 == ~t3_pc~0; 153495#L409-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 153493#L419-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 153491#L420-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 153488#L944-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 153486#L944-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 153484#L427-24 assume !(1 == ~t4_pc~0); 153482#L427-26 is_transmit4_triggered_~__retres1~4 := 0; 153480#L438-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 153478#L439-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 153476#L952-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 153474#L952-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 153472#L446-24 assume !(1 == ~t5_pc~0); 153470#L446-26 is_transmit5_triggered_~__retres1~5 := 0; 153467#L457-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 153465#L458-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 153463#L960-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 153461#L960-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 153459#L465-24 assume !(1 == ~t6_pc~0); 153457#L465-26 is_transmit6_triggered_~__retres1~6 := 0; 153455#L476-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 153453#L477-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 153451#L968-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 153449#L968-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 153447#L484-24 assume !(1 == ~t7_pc~0); 153445#L484-26 is_transmit7_triggered_~__retres1~7 := 0; 153444#L495-8 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 153443#L496-8 activate_threads_#t~ret16 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 153442#L976-24 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 153440#L976-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 153439#L827-3 assume 1 == ~M_E~0;~M_E~0 := 2; 153438#L827-5 assume !(1 == ~T1_E~0); 153437#L832-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 153435#L837-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 153433#L842-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 153431#L847-3 assume !(1 == ~T5_E~0); 153429#L852-3 assume !(1 == ~T6_E~0); 153427#L857-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 153425#L862-3 assume 1 == ~E_1~0;~E_1~0 := 2; 153421#L867-3 assume !(1 == ~E_2~0); 153419#L872-3 assume 1 == ~E_3~0;~E_3~0 := 2; 153417#L877-3 assume 1 == ~E_4~0;~E_4~0 := 2; 153415#L882-3 assume 1 == ~E_5~0;~E_5~0 := 2; 153412#L887-3 assume !(1 == ~E_6~0); 153410#L892-3 assume !(1 == ~E_7~0); 153408#L897-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 153396#L559-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 153390#L601-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 153388#L602-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 153385#L1157 assume !(0 == start_simulation_~tmp~3); 153382#L1157-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 153380#L559-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 153371#L601-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 153369#L602-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 153367#L1112 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 153365#L1119 stop_simulation_#res := stop_simulation_~__retres2~0; 153363#L1120 start_simulation_#t~ret19 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 153361#L1170 assume !(0 != start_simulation_~tmp___0~1); 148949#L1138-3 [2018-11-18 10:50:55,613 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:55,613 INFO L82 PathProgramCache]: Analyzing trace with hash 1968536774, now seen corresponding path program 2 times [2018-11-18 10:50:55,613 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:55,613 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:55,614 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:55,614 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:50:55,614 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:55,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:50:55,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:50:55,643 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:55,643 INFO L82 PathProgramCache]: Analyzing trace with hash 462099792, now seen corresponding path program 1 times [2018-11-18 10:50:55,643 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:55,643 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:55,644 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:55,644 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:50:55,644 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:55,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:50:55,675 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:50:55,675 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:50:55,675 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:50:55,676 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 10:50:55,676 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 10:50:55,676 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:50:55,676 INFO L87 Difference]: Start difference. First operand 9108 states and 12636 transitions. cyclomatic complexity: 3544 Second operand 3 states. [2018-11-18 10:50:55,758 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:50:55,758 INFO L93 Difference]: Finished difference Result 13583 states and 18747 transitions. [2018-11-18 10:50:55,760 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 10:50:55,760 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13583 states and 18747 transitions. [2018-11-18 10:50:55,799 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 13324 [2018-11-18 10:50:55,825 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13583 states to 13583 states and 18747 transitions. [2018-11-18 10:50:55,825 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13583 [2018-11-18 10:50:55,832 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13583 [2018-11-18 10:50:55,832 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13583 states and 18747 transitions. [2018-11-18 10:50:55,840 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 10:50:55,841 INFO L705 BuchiCegarLoop]: Abstraction has 13583 states and 18747 transitions. [2018-11-18 10:50:55,848 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13583 states and 18747 transitions. [2018-11-18 10:50:55,924 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13583 to 13575. [2018-11-18 10:50:55,924 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13575 states. [2018-11-18 10:50:55,939 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13575 states to 13575 states and 18739 transitions. [2018-11-18 10:50:55,939 INFO L728 BuchiCegarLoop]: Abstraction has 13575 states and 18739 transitions. [2018-11-18 10:50:55,939 INFO L608 BuchiCegarLoop]: Abstraction has 13575 states and 18739 transitions. [2018-11-18 10:50:55,940 INFO L442 BuchiCegarLoop]: ======== Iteration 20============ [2018-11-18 10:50:55,940 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13575 states and 18739 transitions. [2018-11-18 10:50:55,968 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 13316 [2018-11-18 10:50:55,968 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:50:55,968 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:50:55,969 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:55,969 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:55,970 INFO L794 eck$LassoCheckResult]: Stem: 171396#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 171304#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 171305#L1101 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 171378#L504 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 171005#L511 assume 1 == ~m_i~0;~m_st~0 := 0; 171006#L511-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 171169#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 171633#L521-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 171554#L526-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 171267#L531-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 171268#L536-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 171697#L541-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 171534#L546-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 171535#L744 assume !(0 == ~M_E~0); 171539#L744-2 assume !(0 == ~T1_E~0); 171359#L749-1 assume !(0 == ~T2_E~0); 171145#L754-1 assume !(0 == ~T3_E~0); 171146#L759-1 assume !(0 == ~T4_E~0); 171609#L764-1 assume !(0 == ~T5_E~0); 171335#L769-1 assume !(0 == ~T6_E~0); 171097#L774-1 assume !(0 == ~T7_E~0); 171098#L779-1 assume !(0 == ~E_1~0); 171781#L784-1 assume 0 == ~E_2~0;~E_2~0 := 1; 171594#L789-1 assume !(0 == ~E_3~0); 171186#L794-1 assume !(0 == ~E_4~0); 171187#L799-1 assume !(0 == ~E_5~0); 171833#L804-1 assume !(0 == ~E_6~0); 171658#L809-1 assume !(0 == ~E_7~0); 171659#L814-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 171941#L351 assume !(1 == ~m_pc~0); 171310#L351-2 is_master_triggered_~__retres1~0 := 0; 171311#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 171852#L363 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 171853#L920 assume !(0 != activate_threads_~tmp~1); 171548#L920-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 171549#L370 assume !(1 == ~t1_pc~0); 171520#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 171521#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 171939#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 171247#L928 assume !(0 != activate_threads_~tmp___0~0); 171087#L928-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 171088#L389 assume !(1 == ~t2_pc~0); 171621#L389-2 is_transmit2_triggered_~__retres1~2 := 0; 171622#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 171932#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 171838#L936 assume !(0 != activate_threads_~tmp___1~0); 171839#L936-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 171740#L408 assume !(1 == ~t3_pc~0); 171741#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 171931#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 171930#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 171571#L944 assume !(0 != activate_threads_~tmp___2~0); 171572#L944-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 171900#L427 assume !(1 == ~t4_pc~0); 171901#L427-2 is_transmit4_triggered_~__retres1~4 := 0; 171558#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 171323#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 171324#L952 assume !(0 != activate_threads_~tmp___3~0); 171156#L952-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 171157#L446 assume !(1 == ~t5_pc~0); 171126#L446-2 is_transmit5_triggered_~__retres1~5 := 0; 171127#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 171647#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 171786#L960 assume !(0 != activate_threads_~tmp___4~0); 171787#L960-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 171269#L465 assume !(1 == ~t6_pc~0); 171270#L465-2 is_transmit6_triggered_~__retres1~6 := 0; 171769#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 171634#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 171635#L968 assume !(0 != activate_threads_~tmp___5~0); 171453#L968-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 171454#L484 assume !(1 == ~t7_pc~0); 171419#L484-2 is_transmit7_triggered_~__retres1~7 := 0; 171420#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 171754#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 171755#L976 assume !(0 != activate_threads_~tmp___6~0); 171859#L976-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 171715#L827 assume !(1 == ~M_E~0); 171700#L827-2 assume !(1 == ~T1_E~0); 171701#L832-1 assume !(1 == ~T2_E~0); 171923#L837-1 assume !(1 == ~T3_E~0); 171138#L842-1 assume !(1 == ~T4_E~0); 171139#L847-1 assume !(1 == ~T5_E~0); 171607#L852-1 assume !(1 == ~T6_E~0); 171332#L857-1 assume !(1 == ~T7_E~0); 171091#L862-1 assume !(1 == ~E_1~0); 171092#L867-1 assume 1 == ~E_2~0;~E_2~0 := 2; 171779#L872-1 assume !(1 == ~E_3~0); 171463#L877-1 assume !(1 == ~E_4~0); 171190#L882-1 assume !(1 == ~E_5~0); 171191#L887-1 assume !(1 == ~E_6~0); 171842#L892-1 assume !(1 == ~E_7~0); 171664#L897-1 assume { :end_inline_reset_delta_events } true; 171665#L1138-3 [2018-11-18 10:50:55,970 INFO L796 eck$LassoCheckResult]: Loop: 171665#L1138-3 assume true; 173478#L1138-1 assume !false; 173469#L1139 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 173461#L719 assume true; 173454#L611-1 assume !false; 173449#L612 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 173438#L559 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 173428#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 173423#L602 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 173417#L616 assume !(0 != eval_~tmp~0); 173418#L734 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 173872#L504-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 173870#L744-3 assume 0 == ~M_E~0;~M_E~0 := 1; 173868#L744-5 assume !(0 == ~T1_E~0); 173866#L749-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 173864#L754-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 173862#L759-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 173860#L764-3 assume !(0 == ~T5_E~0); 173858#L769-3 assume !(0 == ~T6_E~0); 173856#L774-3 assume !(0 == ~T7_E~0); 173854#L779-3 assume 0 == ~E_1~0;~E_1~0 := 1; 173852#L784-3 assume 0 == ~E_2~0;~E_2~0 := 1; 173851#L789-3 assume 0 == ~E_3~0;~E_3~0 := 1; 173850#L794-3 assume 0 == ~E_4~0;~E_4~0 := 1; 173849#L799-3 assume 0 == ~E_5~0;~E_5~0 := 1; 173848#L804-3 assume !(0 == ~E_6~0); 173847#L809-3 assume !(0 == ~E_7~0); 173846#L814-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 173845#L351-24 assume !(1 == ~m_pc~0); 173843#L351-26 is_master_triggered_~__retres1~0 := 0; 173842#L362-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 173841#L363-8 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 173840#L920-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 173839#L920-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 173837#L370-24 assume !(1 == ~t1_pc~0); 173834#L370-26 is_transmit1_triggered_~__retres1~1 := 0; 173833#L381-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 173831#L382-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 173829#L928-24 assume !(0 != activate_threads_~tmp___0~0); 173826#L928-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 173824#L389-24 assume !(1 == ~t2_pc~0); 173822#L389-26 is_transmit2_triggered_~__retres1~2 := 0; 173820#L400-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 173816#L401-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 173814#L936-24 assume !(0 != activate_threads_~tmp___1~0); 173812#L936-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 173810#L408-24 assume 1 == ~t3_pc~0; 173806#L409-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 173804#L419-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 173802#L420-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 173800#L944-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 173798#L944-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 173796#L427-24 assume !(1 == ~t4_pc~0); 173794#L427-26 is_transmit4_triggered_~__retres1~4 := 0; 173792#L438-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 173790#L439-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 173787#L952-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 173785#L952-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 173783#L446-24 assume 1 == ~t5_pc~0; 173780#L447-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 173778#L457-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 173776#L458-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 173774#L960-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 173772#L960-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 173770#L465-24 assume !(1 == ~t6_pc~0); 173768#L465-26 is_transmit6_triggered_~__retres1~6 := 0; 173766#L476-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 173764#L477-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 173761#L968-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 173759#L968-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 173757#L484-24 assume !(1 == ~t7_pc~0); 173754#L484-26 is_transmit7_triggered_~__retres1~7 := 0; 173752#L495-8 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 173750#L496-8 activate_threads_#t~ret16 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 173748#L976-24 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 173746#L976-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 173744#L827-3 assume 1 == ~M_E~0;~M_E~0 := 2; 173742#L827-5 assume !(1 == ~T1_E~0); 173740#L832-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 173737#L837-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 173735#L842-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 173733#L847-3 assume !(1 == ~T5_E~0); 173731#L852-3 assume !(1 == ~T6_E~0); 173729#L857-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 173727#L862-3 assume 1 == ~E_1~0;~E_1~0 := 2; 173725#L867-3 assume 1 == ~E_2~0;~E_2~0 := 2; 173722#L872-3 assume 1 == ~E_3~0;~E_3~0 := 2; 173720#L877-3 assume 1 == ~E_4~0;~E_4~0 := 2; 173718#L882-3 assume 1 == ~E_5~0;~E_5~0 := 2; 173716#L887-3 assume !(1 == ~E_6~0); 173714#L892-3 assume !(1 == ~E_7~0); 173712#L897-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 173702#L559-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 173696#L601-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 173694#L602-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 173692#L1157 assume !(0 == start_simulation_~tmp~3); 173690#L1157-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 173689#L559-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 173681#L601-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 173680#L602-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 173678#L1112 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 173677#L1119 stop_simulation_#res := stop_simulation_~__retres2~0; 173676#L1120 start_simulation_#t~ret19 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 173675#L1170 assume !(0 != start_simulation_~tmp___0~1); 171665#L1138-3 [2018-11-18 10:50:55,970 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:55,970 INFO L82 PathProgramCache]: Analyzing trace with hash 1160880066, now seen corresponding path program 1 times [2018-11-18 10:50:55,970 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:55,970 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:55,971 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:55,971 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:50:55,971 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:55,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:50:56,008 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:50:56,008 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:50:56,008 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 10:50:56,008 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 10:50:56,009 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:56,009 INFO L82 PathProgramCache]: Analyzing trace with hash -835918993, now seen corresponding path program 1 times [2018-11-18 10:50:56,009 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:56,009 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:56,009 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:56,009 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:50:56,010 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:56,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:50:56,034 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:50:56,034 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:50:56,034 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 10:50:56,034 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 10:50:56,034 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 10:50:56,035 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:50:56,035 INFO L87 Difference]: Start difference. First operand 13575 states and 18739 transitions. cyclomatic complexity: 5180 Second operand 3 states. [2018-11-18 10:50:56,086 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:50:56,086 INFO L93 Difference]: Finished difference Result 9108 states and 12526 transitions. [2018-11-18 10:50:56,088 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 10:50:56,088 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9108 states and 12526 transitions. [2018-11-18 10:50:56,113 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8944 [2018-11-18 10:50:56,129 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9108 states to 9108 states and 12526 transitions. [2018-11-18 10:50:56,129 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9108 [2018-11-18 10:50:56,134 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9108 [2018-11-18 10:50:56,134 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9108 states and 12526 transitions. [2018-11-18 10:50:56,141 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 10:50:56,141 INFO L705 BuchiCegarLoop]: Abstraction has 9108 states and 12526 transitions. [2018-11-18 10:50:56,148 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9108 states and 12526 transitions. [2018-11-18 10:50:56,194 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9108 to 9108. [2018-11-18 10:50:56,194 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9108 states. [2018-11-18 10:50:56,206 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9108 states to 9108 states and 12526 transitions. [2018-11-18 10:50:56,206 INFO L728 BuchiCegarLoop]: Abstraction has 9108 states and 12526 transitions. [2018-11-18 10:50:56,206 INFO L608 BuchiCegarLoop]: Abstraction has 9108 states and 12526 transitions. [2018-11-18 10:50:56,207 INFO L442 BuchiCegarLoop]: ======== Iteration 21============ [2018-11-18 10:50:56,207 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9108 states and 12526 transitions. [2018-11-18 10:50:56,230 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8944 [2018-11-18 10:50:56,230 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:50:56,230 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:50:56,231 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:56,231 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:56,231 INFO L794 eck$LassoCheckResult]: Stem: 194073#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 193987#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 193988#L1101 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 194053#L504 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 193697#L511 assume 1 == ~m_i~0;~m_st~0 := 0; 193698#L511-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 193859#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 194308#L521-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 194230#L526-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 193954#L531-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 193955#L536-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 194358#L541-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 194211#L546-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 194212#L744 assume !(0 == ~M_E~0); 194217#L744-2 assume !(0 == ~T1_E~0); 194037#L749-1 assume !(0 == ~T2_E~0); 193837#L754-1 assume !(0 == ~T3_E~0); 193838#L759-1 assume !(0 == ~T4_E~0); 194284#L764-1 assume !(0 == ~T5_E~0); 194017#L769-1 assume !(0 == ~T6_E~0); 193790#L774-1 assume !(0 == ~T7_E~0); 193791#L779-1 assume !(0 == ~E_1~0); 194432#L784-1 assume !(0 == ~E_2~0); 194267#L789-1 assume !(0 == ~E_3~0); 193876#L794-1 assume !(0 == ~E_4~0); 193877#L799-1 assume !(0 == ~E_5~0); 194483#L804-1 assume !(0 == ~E_6~0); 194331#L809-1 assume !(0 == ~E_7~0); 194119#L814-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 194010#L351 assume !(1 == ~m_pc~0); 193994#L351-2 is_master_triggered_~__retres1~0 := 0; 193995#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 194468#L363 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 194224#L920 assume !(0 != activate_threads_~tmp~1); 194225#L920-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 194188#L370 assume !(1 == ~t1_pc~0); 194189#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 194198#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 194515#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 193934#L928 assume !(0 != activate_threads_~tmp___0~0); 193780#L928-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 193781#L389 assume !(1 == ~t2_pc~0); 194298#L389-2 is_transmit2_triggered_~__retres1~2 := 0; 193757#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 193758#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 193861#L936 assume !(0 != activate_threads_~tmp___1~0); 194487#L936-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 194397#L408 assume !(1 == ~t3_pc~0); 194341#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 193910#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 193864#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 193865#L944 assume !(0 != activate_threads_~tmp___2~0); 194242#L944-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 194243#L427 assume !(1 == ~t4_pc~0); 194478#L427-2 is_transmit4_triggered_~__retres1~4 := 0; 194234#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 194007#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 193844#L952 assume !(0 != activate_threads_~tmp___3~0); 193845#L952-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 193813#L446 assume !(1 == ~t5_pc~0); 193814#L446-2 is_transmit5_triggered_~__retres1~5 := 0; 193819#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 194213#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 194214#L960 assume !(0 != activate_threads_~tmp___4~0); 194428#L960-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 193956#L465 assume !(1 == ~t6_pc~0); 193957#L465-2 is_transmit6_triggered_~__retres1~6 := 0; 193958#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 194309#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 194131#L968 assume !(0 != activate_threads_~tmp___5~0); 194132#L968-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 194092#L484 assume !(1 == ~t7_pc~0); 193930#L484-2 is_transmit7_triggered_~__retres1~7 := 0; 194097#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 194409#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 194410#L976 assume !(0 != activate_threads_~tmp___6~0); 194498#L976-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 194374#L827 assume !(1 == ~M_E~0); 194361#L827-2 assume !(1 == ~T1_E~0); 194227#L832-1 assume !(1 == ~T2_E~0); 194035#L837-1 assume !(1 == ~T3_E~0); 193830#L842-1 assume !(1 == ~T4_E~0); 193831#L847-1 assume !(1 == ~T5_E~0); 194280#L852-1 assume !(1 == ~T6_E~0); 194015#L857-1 assume !(1 == ~T7_E~0); 193782#L862-1 assume !(1 == ~E_1~0); 193783#L867-1 assume !(1 == ~E_2~0); 194430#L872-1 assume !(1 == ~E_3~0); 194141#L877-1 assume !(1 == ~E_4~0); 193880#L882-1 assume !(1 == ~E_5~0); 193881#L887-1 assume !(1 == ~E_6~0); 194488#L892-1 assume !(1 == ~E_7~0); 194336#L897-1 assume { :end_inline_reset_delta_events } true; 194337#L1138-3 [2018-11-18 10:50:56,231 INFO L796 eck$LassoCheckResult]: Loop: 194337#L1138-3 assume true; 199682#L1138-1 assume !false; 197586#L1139 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 197214#L719 assume true; 196531#L611-1 assume !false; 196530#L612 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 196397#L559 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 196391#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 196380#L602 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 196369#L616 assume !(0 != eval_~tmp~0); 196370#L734 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 199894#L504-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 199892#L744-3 assume 0 == ~M_E~0;~M_E~0 := 1; 199890#L744-5 assume !(0 == ~T1_E~0); 199888#L749-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 199886#L754-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 199884#L759-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 199881#L764-3 assume !(0 == ~T5_E~0); 199879#L769-3 assume !(0 == ~T6_E~0); 199877#L774-3 assume !(0 == ~T7_E~0); 199875#L779-3 assume 0 == ~E_1~0;~E_1~0 := 1; 199873#L784-3 assume !(0 == ~E_2~0); 199871#L789-3 assume 0 == ~E_3~0;~E_3~0 := 1; 199869#L794-3 assume 0 == ~E_4~0;~E_4~0 := 1; 199867#L799-3 assume 0 == ~E_5~0;~E_5~0 := 1; 199865#L804-3 assume !(0 == ~E_6~0); 199863#L809-3 assume !(0 == ~E_7~0); 199861#L814-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 199858#L351-24 assume !(1 == ~m_pc~0); 199856#L351-26 is_master_triggered_~__retres1~0 := 0; 199854#L362-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 199852#L363-8 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 199850#L920-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 199848#L920-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 199846#L370-24 assume !(1 == ~t1_pc~0); 199842#L370-26 is_transmit1_triggered_~__retres1~1 := 0; 199840#L381-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 199838#L382-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 199836#L928-24 assume !(0 != activate_threads_~tmp___0~0); 199833#L928-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 199831#L389-24 assume !(1 == ~t2_pc~0); 199829#L389-26 is_transmit2_triggered_~__retres1~2 := 0; 199827#L400-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 199825#L401-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 199823#L936-24 assume !(0 != activate_threads_~tmp___1~0); 199821#L936-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 199819#L408-24 assume !(1 == ~t3_pc~0); 199817#L408-26 is_transmit3_triggered_~__retres1~3 := 0; 199814#L419-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 199813#L420-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 199812#L944-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 199811#L944-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 199810#L427-24 assume !(1 == ~t4_pc~0); 199809#L427-26 is_transmit4_triggered_~__retres1~4 := 0; 199808#L438-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 199807#L439-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 199806#L952-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 199805#L952-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 199804#L446-24 assume !(1 == ~t5_pc~0); 199802#L446-26 is_transmit5_triggered_~__retres1~5 := 0; 199800#L457-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 199799#L458-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 199798#L960-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 199797#L960-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 199796#L465-24 assume !(1 == ~t6_pc~0); 199794#L465-26 is_transmit6_triggered_~__retres1~6 := 0; 199792#L476-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 199790#L477-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 199787#L968-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 199785#L968-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 199783#L484-24 assume !(1 == ~t7_pc~0); 199780#L484-26 is_transmit7_triggered_~__retres1~7 := 0; 199778#L495-8 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 199774#L496-8 activate_threads_#t~ret16 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 199772#L976-24 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 199770#L976-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 199768#L827-3 assume 1 == ~M_E~0;~M_E~0 := 2; 199765#L827-5 assume !(1 == ~T1_E~0); 199763#L832-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 199760#L837-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 199758#L842-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 199756#L847-3 assume !(1 == ~T5_E~0); 199754#L852-3 assume !(1 == ~T6_E~0); 199752#L857-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 199750#L862-3 assume 1 == ~E_1~0;~E_1~0 := 2; 199748#L867-3 assume !(1 == ~E_2~0); 199745#L872-3 assume 1 == ~E_3~0;~E_3~0 := 2; 199743#L877-3 assume 1 == ~E_4~0;~E_4~0 := 2; 199741#L882-3 assume 1 == ~E_5~0;~E_5~0 := 2; 199739#L887-3 assume !(1 == ~E_6~0); 199737#L892-3 assume !(1 == ~E_7~0); 199735#L897-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 199722#L559-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 199716#L601-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 199714#L602-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 199711#L1157 assume !(0 == start_simulation_~tmp~3); 199707#L1157-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 199705#L559-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 199696#L601-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 199694#L602-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 199692#L1112 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 199690#L1119 stop_simulation_#res := stop_simulation_~__retres2~0; 199687#L1120 start_simulation_#t~ret19 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 199685#L1170 assume !(0 != start_simulation_~tmp___0~1); 194337#L1138-3 [2018-11-18 10:50:56,231 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:56,231 INFO L82 PathProgramCache]: Analyzing trace with hash 1968536774, now seen corresponding path program 3 times [2018-11-18 10:50:56,231 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:56,232 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:56,240 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:56,240 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:50:56,240 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:56,244 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:50:56,249 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:50:56,266 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:56,267 INFO L82 PathProgramCache]: Analyzing trace with hash 645308593, now seen corresponding path program 1 times [2018-11-18 10:50:56,267 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:56,267 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:56,267 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:56,267 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:50:56,267 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:56,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:50:56,299 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:50:56,300 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:50:56,300 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 10:50:56,300 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 10:50:56,300 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 10:50:56,300 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 10:50:56,300 INFO L87 Difference]: Start difference. First operand 9108 states and 12526 transitions. cyclomatic complexity: 3434 Second operand 5 states. [2018-11-18 10:50:56,466 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:50:56,466 INFO L93 Difference]: Finished difference Result 16516 states and 22470 transitions. [2018-11-18 10:50:56,467 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-18 10:50:56,467 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16516 states and 22470 transitions. [2018-11-18 10:50:56,513 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 16288 [2018-11-18 10:50:56,543 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16516 states to 16516 states and 22470 transitions. [2018-11-18 10:50:56,543 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16516 [2018-11-18 10:50:56,552 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16516 [2018-11-18 10:50:56,552 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16516 states and 22470 transitions. [2018-11-18 10:50:56,562 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 10:50:56,562 INFO L705 BuchiCegarLoop]: Abstraction has 16516 states and 22470 transitions. [2018-11-18 10:50:56,570 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16516 states and 22470 transitions. [2018-11-18 10:50:56,641 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16516 to 9156. [2018-11-18 10:50:56,641 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9156 states. [2018-11-18 10:50:56,653 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9156 states to 9156 states and 12574 transitions. [2018-11-18 10:50:56,653 INFO L728 BuchiCegarLoop]: Abstraction has 9156 states and 12574 transitions. [2018-11-18 10:50:56,653 INFO L608 BuchiCegarLoop]: Abstraction has 9156 states and 12574 transitions. [2018-11-18 10:50:56,653 INFO L442 BuchiCegarLoop]: ======== Iteration 22============ [2018-11-18 10:50:56,653 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9156 states and 12574 transitions. [2018-11-18 10:50:56,673 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8992 [2018-11-18 10:50:56,673 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:50:56,673 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:50:56,674 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:56,674 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:56,674 INFO L794 eck$LassoCheckResult]: Stem: 219724#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 219636#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 219637#L1101 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 219706#L504 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 219337#L511 assume 1 == ~m_i~0;~m_st~0 := 0; 219338#L511-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 219503#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 219952#L521-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 219873#L526-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 219601#L531-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 219602#L536-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 220012#L541-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 219854#L546-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 219855#L744 assume !(0 == ~M_E~0); 219860#L744-2 assume !(0 == ~T1_E~0); 219690#L749-1 assume !(0 == ~T2_E~0); 219480#L754-1 assume !(0 == ~T3_E~0); 219481#L759-1 assume !(0 == ~T4_E~0); 219931#L764-1 assume !(0 == ~T5_E~0); 219667#L769-1 assume !(0 == ~T6_E~0); 219434#L774-1 assume !(0 == ~T7_E~0); 219435#L779-1 assume !(0 == ~E_1~0); 220093#L784-1 assume !(0 == ~E_2~0); 219910#L789-1 assume !(0 == ~E_3~0); 219520#L794-1 assume !(0 == ~E_4~0); 219521#L799-1 assume !(0 == ~E_5~0); 220141#L804-1 assume !(0 == ~E_6~0); 219978#L809-1 assume !(0 == ~E_7~0); 219761#L814-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 219661#L351 assume !(1 == ~m_pc~0); 219644#L351-2 is_master_triggered_~__retres1~0 := 0; 219645#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 220128#L363 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 219867#L920 assume !(0 != activate_threads_~tmp~1); 219868#L920-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 219832#L370 assume !(1 == ~t1_pc~0); 219833#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 219841#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 220174#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 219580#L928 assume !(0 != activate_threads_~tmp___0~0); 219422#L928-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 219423#L389 assume !(1 == ~t2_pc~0); 219944#L389-2 is_transmit2_triggered_~__retres1~2 := 0; 219399#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 219400#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 219505#L936 assume !(0 != activate_threads_~tmp___1~0); 220145#L936-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 220055#L408 assume !(1 == ~t3_pc~0); 219995#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 219554#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 219508#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 219509#L944 assume !(0 != activate_threads_~tmp___2~0); 219885#L944-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 219886#L427 assume !(1 == ~t4_pc~0); 220137#L427-2 is_transmit4_triggered_~__retres1~4 := 0; 219877#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 219658#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 219487#L952 assume !(0 != activate_threads_~tmp___3~0); 219488#L952-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 219456#L446 assume !(1 == ~t5_pc~0); 219457#L446-2 is_transmit5_triggered_~__retres1~5 := 0; 219462#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 219856#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 219857#L960 assume !(0 != activate_threads_~tmp___4~0); 220089#L960-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 219603#L465 assume !(1 == ~t6_pc~0); 219604#L465-2 is_transmit6_triggered_~__retres1~6 := 0; 219605#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 219953#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 219772#L968 assume !(0 != activate_threads_~tmp___5~0); 219773#L968-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 219741#L484 assume !(1 == ~t7_pc~0); 219575#L484-2 is_transmit7_triggered_~__retres1~7 := 0; 219745#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 220067#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 220068#L976 assume !(0 != activate_threads_~tmp___6~0); 220155#L976-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 220029#L827 assume !(1 == ~M_E~0); 220015#L827-2 assume !(1 == ~T1_E~0); 219870#L832-1 assume !(1 == ~T2_E~0); 219688#L837-1 assume !(1 == ~T3_E~0); 219473#L842-1 assume !(1 == ~T4_E~0); 219474#L847-1 assume !(1 == ~T5_E~0); 219927#L852-1 assume !(1 == ~T6_E~0); 219665#L857-1 assume !(1 == ~T7_E~0); 219424#L862-1 assume !(1 == ~E_1~0); 219425#L867-1 assume !(1 == ~E_2~0); 220091#L872-1 assume !(1 == ~E_3~0); 219784#L877-1 assume !(1 == ~E_4~0); 219524#L882-1 assume !(1 == ~E_5~0); 219525#L887-1 assume !(1 == ~E_6~0); 220146#L892-1 assume !(1 == ~E_7~0); 219984#L897-1 assume { :end_inline_reset_delta_events } true; 219985#L1138-3 [2018-11-18 10:50:56,675 INFO L796 eck$LassoCheckResult]: Loop: 219985#L1138-3 assume true; 228020#L1138-1 assume !false; 228016#L1139 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 227707#L719 assume true; 227696#L611-1 assume !false; 227676#L612 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 227670#L559 assume !(0 == ~m_st~0); 227671#L563 assume !(0 == ~t1_st~0); 227674#L567 assume !(0 == ~t2_st~0); 227668#L571 assume !(0 == ~t3_st~0); 227669#L575 assume !(0 == ~t4_st~0); 227673#L579 assume !(0 == ~t5_st~0); 227666#L583 assume !(0 == ~t6_st~0); 227667#L587 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8 := 0; 227672#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 224203#L602 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 224204#L616 assume !(0 != eval_~tmp~0); 227660#L734 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 227659#L504-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 227658#L744-3 assume 0 == ~M_E~0;~M_E~0 := 1; 227657#L744-5 assume !(0 == ~T1_E~0); 227656#L749-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 227655#L754-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 227654#L759-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 227653#L764-3 assume !(0 == ~T5_E~0); 227652#L769-3 assume !(0 == ~T6_E~0); 227651#L774-3 assume !(0 == ~T7_E~0); 227650#L779-3 assume 0 == ~E_1~0;~E_1~0 := 1; 220086#L784-3 assume !(0 == ~E_2~0); 219913#L789-3 assume 0 == ~E_3~0;~E_3~0 := 1; 219522#L794-3 assume 0 == ~E_4~0;~E_4~0 := 1; 219523#L799-3 assume 0 == ~E_5~0;~E_5~0 := 1; 220188#L804-3 assume !(0 == ~E_6~0); 227646#L809-3 assume !(0 == ~E_7~0); 219767#L814-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 219768#L351-24 assume !(1 == ~m_pc~0); 227645#L351-26 is_master_triggered_~__retres1~0 := 0; 220105#L362-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 220106#L363-8 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 219821#L920-24 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 219822#L920-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 219917#L370-24 assume !(1 == ~t1_pc~0); 219919#L370-26 is_transmit1_triggered_~__retres1~1 := 0; 227585#L381-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 227582#L382-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 227579#L928-24 assume !(0 != activate_threads_~tmp___0~0); 219359#L928-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 219360#L389-24 assume !(1 == ~t2_pc~0); 219922#L389-26 is_transmit2_triggered_~__retres1~2 := 0; 219923#L400-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 219492#L401-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 219493#L936-24 assume !(0 != activate_threads_~tmp___1~0); 220030#L936-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 220021#L408-24 assume !(1 == ~t3_pc~0); 220023#L408-26 is_transmit3_triggered_~__retres1~3 := 0; 219547#L419-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 219548#L420-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 219674#L944-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 219675#L944-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 220131#L427-24 assume !(1 == ~t4_pc~0); 220132#L427-26 is_transmit4_triggered_~__retres1~4 := 0; 228094#L438-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 228093#L439-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 228092#L952-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 228091#L952-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 228090#L446-24 assume !(1 == ~t5_pc~0); 228089#L446-26 is_transmit5_triggered_~__retres1~5 := 0; 228087#L457-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 228086#L458-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 228085#L960-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 228084#L960-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 228083#L465-24 assume !(1 == ~t6_pc~0); 228082#L465-26 is_transmit6_triggered_~__retres1~6 := 0; 228081#L476-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 228080#L477-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 228079#L968-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 228078#L968-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 228077#L484-24 assume !(1 == ~t7_pc~0); 228075#L484-26 is_transmit7_triggered_~__retres1~7 := 0; 228074#L495-8 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 228073#L496-8 activate_threads_#t~ret16 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 228072#L976-24 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 228071#L976-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 228070#L827-3 assume 1 == ~M_E~0;~M_E~0 := 2; 228069#L827-5 assume !(1 == ~T1_E~0); 228068#L832-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 228067#L837-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 228066#L842-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 228065#L847-3 assume !(1 == ~T5_E~0); 228064#L852-3 assume !(1 == ~T6_E~0); 228063#L857-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 228062#L862-3 assume 1 == ~E_1~0;~E_1~0 := 2; 228061#L867-3 assume !(1 == ~E_2~0); 228060#L872-3 assume 1 == ~E_3~0;~E_3~0 := 2; 228059#L877-3 assume 1 == ~E_4~0;~E_4~0 := 2; 228058#L882-3 assume 1 == ~E_5~0;~E_5~0 := 2; 228057#L887-3 assume !(1 == ~E_6~0); 228056#L892-3 assume !(1 == ~E_7~0); 228055#L897-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 228051#L559-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 228045#L601-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 228043#L602-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 228040#L1157 assume !(0 == start_simulation_~tmp~3); 228038#L1157-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 228037#L559-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 228029#L601-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 228028#L602-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 228027#L1112 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 228026#L1119 stop_simulation_#res := stop_simulation_~__retres2~0; 228025#L1120 start_simulation_#t~ret19 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 228023#L1170 assume !(0 != start_simulation_~tmp___0~1); 219985#L1138-3 [2018-11-18 10:50:56,675 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:56,675 INFO L82 PathProgramCache]: Analyzing trace with hash 1968536774, now seen corresponding path program 4 times [2018-11-18 10:50:56,675 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:56,675 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:56,676 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:56,676 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:50:56,676 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:56,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:50:56,688 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:50:56,716 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:56,717 INFO L82 PathProgramCache]: Analyzing trace with hash -1540279193, now seen corresponding path program 1 times [2018-11-18 10:50:56,717 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:56,717 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:56,717 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:56,718 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:50:56,718 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:56,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:50:56,813 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:50:56,813 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:50:56,813 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 10:50:56,813 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 10:50:56,813 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 10:50:56,814 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 10:50:56,814 INFO L87 Difference]: Start difference. First operand 9156 states and 12574 transitions. cyclomatic complexity: 3434 Second operand 5 states. [2018-11-18 10:50:56,975 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:50:56,975 INFO L93 Difference]: Finished difference Result 18264 states and 24917 transitions. [2018-11-18 10:50:56,975 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 10:50:56,975 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18264 states and 24917 transitions. [2018-11-18 10:50:57,056 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 18052 [2018-11-18 10:50:57,071 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18264 states to 18264 states and 24917 transitions. [2018-11-18 10:50:57,071 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18264 [2018-11-18 10:50:57,079 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18264 [2018-11-18 10:50:57,079 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18264 states and 24917 transitions. [2018-11-18 10:50:57,088 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 10:50:57,088 INFO L705 BuchiCegarLoop]: Abstraction has 18264 states and 24917 transitions. [2018-11-18 10:50:57,095 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18264 states and 24917 transitions. [2018-11-18 10:50:57,161 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18264 to 9336. [2018-11-18 10:50:57,161 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 9336 states. [2018-11-18 10:50:57,171 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9336 states to 9336 states and 12701 transitions. [2018-11-18 10:50:57,171 INFO L728 BuchiCegarLoop]: Abstraction has 9336 states and 12701 transitions. [2018-11-18 10:50:57,172 INFO L608 BuchiCegarLoop]: Abstraction has 9336 states and 12701 transitions. [2018-11-18 10:50:57,172 INFO L442 BuchiCegarLoop]: ======== Iteration 23============ [2018-11-18 10:50:57,172 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9336 states and 12701 transitions. [2018-11-18 10:50:57,190 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 9172 [2018-11-18 10:50:57,190 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:50:57,190 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:50:57,191 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:57,191 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:57,191 INFO L794 eck$LassoCheckResult]: Stem: 247162#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 247074#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 247075#L1101 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 247146#L504 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 246770#L511 assume 1 == ~m_i~0;~m_st~0 := 0; 246771#L511-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 246939#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 247402#L521-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 247325#L526-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 247038#L531-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 247039#L536-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 247462#L541-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 247306#L546-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 247307#L744 assume !(0 == ~M_E~0); 247311#L744-2 assume !(0 == ~T1_E~0); 247126#L749-1 assume !(0 == ~T2_E~0); 246917#L754-1 assume !(0 == ~T3_E~0); 246918#L759-1 assume !(0 == ~T4_E~0); 247380#L764-1 assume !(0 == ~T5_E~0); 247105#L769-1 assume !(0 == ~T6_E~0); 246868#L774-1 assume !(0 == ~T7_E~0); 246869#L779-1 assume !(0 == ~E_1~0); 247544#L784-1 assume !(0 == ~E_2~0); 247362#L789-1 assume !(0 == ~E_3~0); 246956#L794-1 assume !(0 == ~E_4~0); 246957#L799-1 assume !(0 == ~E_5~0); 247604#L804-1 assume !(0 == ~E_6~0); 247430#L809-1 assume !(0 == ~E_7~0); 247212#L814-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 247099#L351 assume !(1 == ~m_pc~0); 247082#L351-2 is_master_triggered_~__retres1~0 := 0; 247083#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 247583#L363 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 247319#L920 assume !(0 != activate_threads_~tmp~1); 247320#L920-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 247284#L370 assume !(1 == ~t1_pc~0); 247285#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 247293#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 247656#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 247016#L928 assume !(0 != activate_threads_~tmp___0~0); 246856#L928-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 246857#L389 assume !(1 == ~t2_pc~0); 247393#L389-2 is_transmit2_triggered_~__retres1~2 := 0; 246834#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 246835#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 246941#L936 assume !(0 != activate_threads_~tmp___1~0); 247609#L936-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 247501#L408 assume !(1 == ~t3_pc~0); 247444#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 246992#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 246944#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 246945#L944 assume !(0 != activate_threads_~tmp___2~0); 247337#L944-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 247338#L427 assume !(1 == ~t4_pc~0); 247595#L427-2 is_transmit4_triggered_~__retres1~4 := 0; 247329#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 247096#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 246924#L952 assume !(0 != activate_threads_~tmp___3~0); 246925#L952-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 246890#L446 assume !(1 == ~t5_pc~0); 246891#L446-2 is_transmit5_triggered_~__retres1~5 := 0; 246896#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 247308#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 247309#L960 assume !(0 != activate_threads_~tmp___4~0); 247539#L960-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 247040#L465 assume !(1 == ~t6_pc~0); 247041#L465-2 is_transmit6_triggered_~__retres1~6 := 0; 247042#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 247403#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 247226#L968 assume !(0 != activate_threads_~tmp___5~0); 247227#L968-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 247182#L484 assume !(1 == ~t7_pc~0); 247010#L484-2 is_transmit7_triggered_~__retres1~7 := 0; 247186#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 247517#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 247518#L976 assume !(0 != activate_threads_~tmp___6~0); 247639#L976-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 247478#L827 assume !(1 == ~M_E~0); 247465#L827-2 assume !(1 == ~T1_E~0); 247322#L832-1 assume !(1 == ~T2_E~0); 247123#L837-1 assume !(1 == ~T3_E~0); 246909#L842-1 assume !(1 == ~T4_E~0); 246910#L847-1 assume !(1 == ~T5_E~0); 247378#L852-1 assume !(1 == ~T6_E~0); 247103#L857-1 assume !(1 == ~T7_E~0); 246862#L862-1 assume !(1 == ~E_1~0); 246863#L867-1 assume !(1 == ~E_2~0); 247541#L872-1 assume !(1 == ~E_3~0); 247237#L877-1 assume !(1 == ~E_4~0); 246960#L882-1 assume !(1 == ~E_5~0); 246961#L887-1 assume !(1 == ~E_6~0); 247610#L892-1 assume !(1 == ~E_7~0); 247435#L897-1 assume { :end_inline_reset_delta_events } true; 247436#L1138-3 [2018-11-18 10:50:57,192 INFO L796 eck$LassoCheckResult]: Loop: 247436#L1138-3 assume true; 251729#L1138-1 assume !false; 251725#L1139 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 251723#L719 assume true; 251722#L611-1 assume !false; 251721#L612 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 251716#L559 assume !(0 == ~m_st~0); 251717#L563 assume !(0 == ~t1_st~0); 251720#L567 assume !(0 == ~t2_st~0); 251714#L571 assume !(0 == ~t3_st~0); 251715#L575 assume !(0 == ~t4_st~0); 251719#L579 assume !(0 == ~t5_st~0); 251712#L583 assume !(0 == ~t6_st~0); 251713#L587 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8 := 0; 251718#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 250813#L602 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 250814#L616 assume !(0 != eval_~tmp~0); 251919#L734 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 251918#L504-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 251917#L744-3 assume 0 == ~M_E~0;~M_E~0 := 1; 251916#L744-5 assume !(0 == ~T1_E~0); 251915#L749-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 251914#L754-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 251913#L759-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 251912#L764-3 assume !(0 == ~T5_E~0); 251911#L769-3 assume !(0 == ~T6_E~0); 251910#L774-3 assume !(0 == ~T7_E~0); 251909#L779-3 assume 0 == ~E_1~0;~E_1~0 := 1; 251908#L784-3 assume !(0 == ~E_2~0); 251907#L789-3 assume 0 == ~E_3~0;~E_3~0 := 1; 251906#L794-3 assume 0 == ~E_4~0;~E_4~0 := 1; 251905#L799-3 assume 0 == ~E_5~0;~E_5~0 := 1; 251904#L804-3 assume !(0 == ~E_6~0); 251903#L809-3 assume !(0 == ~E_7~0); 251902#L814-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 251901#L351-24 assume !(1 == ~m_pc~0); 251900#L351-26 is_master_triggered_~__retres1~0 := 0; 251899#L362-8 is_master_triggered_#res := is_master_triggered_~__retres1~0; 251898#L363-8 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 251897#L920-24 assume !(0 != activate_threads_~tmp~1); 251895#L920-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 251893#L370-24 assume !(1 == ~t1_pc~0); 251891#L370-26 is_transmit1_triggered_~__retres1~1 := 0; 251888#L381-8 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 251885#L382-8 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 251882#L928-24 assume !(0 != activate_threads_~tmp___0~0); 251879#L928-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 251876#L389-24 assume !(1 == ~t2_pc~0); 251873#L389-26 is_transmit2_triggered_~__retres1~2 := 0; 251870#L400-8 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 251867#L401-8 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 251865#L936-24 assume !(0 != activate_threads_~tmp___1~0); 251863#L936-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 251861#L408-24 assume !(1 == ~t3_pc~0); 251859#L408-26 is_transmit3_triggered_~__retres1~3 := 0; 251856#L419-8 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 251854#L420-8 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 251852#L944-24 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 251850#L944-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 251847#L427-24 assume !(1 == ~t4_pc~0); 251845#L427-26 is_transmit4_triggered_~__retres1~4 := 0; 251843#L438-8 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 251841#L439-8 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 251839#L952-24 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 251837#L952-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 251835#L446-24 assume !(1 == ~t5_pc~0); 251833#L446-26 is_transmit5_triggered_~__retres1~5 := 0; 251830#L457-8 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 251828#L458-8 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 251826#L960-24 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 251824#L960-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 251821#L465-24 assume !(1 == ~t6_pc~0); 251819#L465-26 is_transmit6_triggered_~__retres1~6 := 0; 251817#L476-8 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 251815#L477-8 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 251813#L968-24 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 251811#L968-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 251809#L484-24 assume !(1 == ~t7_pc~0); 251806#L484-26 is_transmit7_triggered_~__retres1~7 := 0; 251804#L495-8 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 251802#L496-8 activate_threads_#t~ret16 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 251800#L976-24 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 251797#L976-26 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 251795#L827-3 assume 1 == ~M_E~0;~M_E~0 := 2; 251793#L827-5 assume !(1 == ~T1_E~0); 251791#L832-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 251789#L837-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 251787#L842-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 251785#L847-3 assume !(1 == ~T5_E~0); 251783#L852-3 assume !(1 == ~T6_E~0); 251781#L857-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 251779#L862-3 assume 1 == ~E_1~0;~E_1~0 := 2; 251777#L867-3 assume !(1 == ~E_2~0); 251775#L872-3 assume 1 == ~E_3~0;~E_3~0 := 2; 251773#L877-3 assume 1 == ~E_4~0;~E_4~0 := 2; 251771#L882-3 assume 1 == ~E_5~0;~E_5~0 := 2; 251769#L887-3 assume !(1 == ~E_6~0); 251767#L892-3 assume !(1 == ~E_7~0); 251765#L897-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 251760#L559-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 251754#L601-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 251752#L602-1 start_simulation_#t~ret18 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret18;havoc start_simulation_#t~ret18; 251749#L1157 assume !(0 == start_simulation_~tmp~3); 251747#L1157-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret17, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 251746#L559-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 251738#L601-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 251737#L602-2 stop_simulation_#t~ret17 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret17;havoc stop_simulation_#t~ret17; 251736#L1112 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 251735#L1119 stop_simulation_#res := stop_simulation_~__retres2~0; 251734#L1120 start_simulation_#t~ret19 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret19;havoc start_simulation_#t~ret19; 251732#L1170 assume !(0 != start_simulation_~tmp___0~1); 247436#L1138-3 [2018-11-18 10:50:57,192 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:57,192 INFO L82 PathProgramCache]: Analyzing trace with hash 1968536774, now seen corresponding path program 5 times [2018-11-18 10:50:57,192 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:57,192 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:57,193 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:57,193 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:50:57,193 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:57,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:50:57,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:50:57,220 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:57,220 INFO L82 PathProgramCache]: Analyzing trace with hash -1463378395, now seen corresponding path program 1 times [2018-11-18 10:50:57,220 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:57,221 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:57,221 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:57,221 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:50:57,221 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:57,226 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:50:57,279 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:50:57,279 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:50:57,279 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:50:57,279 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 10:50:57,280 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 10:50:57,280 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:50:57,280 INFO L87 Difference]: Start difference. First operand 9336 states and 12701 transitions. cyclomatic complexity: 3381 Second operand 3 states. [2018-11-18 10:50:57,391 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:50:57,391 INFO L93 Difference]: Finished difference Result 16359 states and 21976 transitions. [2018-11-18 10:50:57,393 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 10:50:57,393 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16359 states and 21976 transitions. [2018-11-18 10:50:57,439 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 16144 [2018-11-18 10:50:57,471 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16359 states to 16359 states and 21976 transitions. [2018-11-18 10:50:57,471 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16359 [2018-11-18 10:50:57,481 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16359 [2018-11-18 10:50:57,481 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16359 states and 21976 transitions. [2018-11-18 10:50:57,491 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 10:50:57,491 INFO L705 BuchiCegarLoop]: Abstraction has 16359 states and 21976 transitions. [2018-11-18 10:50:57,498 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16359 states and 21976 transitions. [2018-11-18 10:50:57,576 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16359 to 15915. [2018-11-18 10:50:57,576 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15915 states. [2018-11-18 10:50:57,593 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15915 states to 15915 states and 21404 transitions. [2018-11-18 10:50:57,593 INFO L728 BuchiCegarLoop]: Abstraction has 15915 states and 21404 transitions. [2018-11-18 10:50:57,593 INFO L608 BuchiCegarLoop]: Abstraction has 15915 states and 21404 transitions. [2018-11-18 10:50:57,593 INFO L442 BuchiCegarLoop]: ======== Iteration 24============ [2018-11-18 10:50:57,593 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15915 states and 21404 transitions. [2018-11-18 10:50:57,621 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 15700 [2018-11-18 10:50:57,621 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:50:57,621 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:50:57,622 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:57,622 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:57,622 INFO L794 eck$LassoCheckResult]: Stem: 272857#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 272766#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 272767#L1101 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 272839#L504 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 272471#L511 assume 1 == ~m_i~0;~m_st~0 := 0; 272472#L511-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 272634#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 273086#L521-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 273009#L526-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 272731#L531-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 272732#L536-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 273145#L541-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 272990#L546-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 272991#L744 assume !(0 == ~M_E~0); 272995#L744-2 assume !(0 == ~T1_E~0); 272819#L749-1 assume !(0 == ~T2_E~0); 272612#L754-1 assume !(0 == ~T3_E~0); 272613#L759-1 assume !(0 == ~T4_E~0); 273065#L764-1 assume !(0 == ~T5_E~0); 272795#L769-1 assume !(0 == ~T6_E~0); 272566#L774-1 assume !(0 == ~T7_E~0); 272567#L779-1 assume !(0 == ~E_1~0); 273220#L784-1 assume !(0 == ~E_2~0); 273049#L789-1 assume !(0 == ~E_3~0); 272651#L794-1 assume !(0 == ~E_4~0); 272652#L799-1 assume !(0 == ~E_5~0); 273273#L804-1 assume !(0 == ~E_6~0); 273110#L809-1 assume !(0 == ~E_7~0); 272903#L814-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 272789#L351 assume !(1 == ~m_pc~0); 272773#L351-2 is_master_triggered_~__retres1~0 := 0; 272774#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 273260#L363 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 273002#L920 assume !(0 != activate_threads_~tmp~1); 273003#L920-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 272968#L370 assume !(1 == ~t1_pc~0); 272969#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 272977#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 273303#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 272711#L928 assume !(0 != activate_threads_~tmp___0~0); 272554#L928-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 272555#L389 assume !(1 == ~t2_pc~0); 273077#L389-2 is_transmit2_triggered_~__retres1~2 := 0; 272534#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 272535#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 272636#L936 assume !(0 != activate_threads_~tmp___1~0); 273276#L936-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 273186#L408 assume !(1 == ~t3_pc~0); 273129#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 272687#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 272639#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 272640#L944 assume !(0 != activate_threads_~tmp___2~0); 273024#L944-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 273025#L427 assume !(1 == ~t4_pc~0); 273267#L427-2 is_transmit4_triggered_~__retres1~4 := 0; 273014#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 272786#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 272619#L952 assume !(0 != activate_threads_~tmp___3~0); 272620#L952-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 272588#L446 assume !(1 == ~t5_pc~0); 272589#L446-2 is_transmit5_triggered_~__retres1~5 := 0; 272594#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 272992#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 272993#L960 assume !(0 != activate_threads_~tmp___4~0); 273216#L960-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 272733#L465 assume !(1 == ~t6_pc~0); 272734#L465-2 is_transmit6_triggered_~__retres1~6 := 0; 272735#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 273087#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 272912#L968 assume !(0 != activate_threads_~tmp___5~0); 272913#L968-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 272876#L484 assume !(1 == ~t7_pc~0); 272705#L484-2 is_transmit7_triggered_~__retres1~7 := 0; 272880#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 273198#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 273199#L976 assume !(0 != activate_threads_~tmp___6~0); 273285#L976-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 273163#L827 assume !(1 == ~M_E~0); 273150#L827-2 assume !(1 == ~T1_E~0); 273005#L832-1 assume !(1 == ~T2_E~0); 272816#L837-1 assume !(1 == ~T3_E~0); 272605#L842-1 assume !(1 == ~T4_E~0); 272606#L847-1 assume !(1 == ~T5_E~0); 273062#L852-1 assume !(1 == ~T6_E~0); 272793#L857-1 assume !(1 == ~T7_E~0); 272560#L862-1 assume !(1 == ~E_1~0); 272561#L867-1 assume !(1 == ~E_2~0); 273218#L872-1 assume !(1 == ~E_3~0); 272922#L877-1 assume !(1 == ~E_4~0); 272655#L882-1 assume !(1 == ~E_5~0); 272656#L887-1 assume !(1 == ~E_6~0); 273277#L892-1 assume !(1 == ~E_7~0); 273115#L897-1 assume { :end_inline_reset_delta_events } true; 273116#L1138-3 assume true; 274227#L1138-1 assume !false; 274197#L1139 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 274189#L719 [2018-11-18 10:50:57,622 INFO L796 eck$LassoCheckResult]: Loop: 274189#L719 assume true; 274182#L611-1 assume !false; 274177#L612 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 274172#L559 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 274167#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 274162#L602 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 274154#L616 assume 0 != eval_~tmp~0; 274146#L616-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 274140#L624 assume !(0 != eval_~tmp_ndt_1~0); 274135#L621 assume !(0 == ~t1_st~0); 274128#L635 assume !(0 == ~t2_st~0); 274120#L649 assume !(0 == ~t3_st~0); 274116#L663 assume !(0 == ~t4_st~0); 274112#L677 assume !(0 == ~t5_st~0); 274230#L691 assume !(0 == ~t6_st~0); 274200#L705 assume !(0 == ~t7_st~0); 274189#L719 [2018-11-18 10:50:57,623 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:57,623 INFO L82 PathProgramCache]: Analyzing trace with hash 1196000841, now seen corresponding path program 1 times [2018-11-18 10:50:57,623 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:57,623 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:57,623 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:57,623 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:50:57,624 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:57,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:50:57,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:50:57,651 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:57,651 INFO L82 PathProgramCache]: Analyzing trace with hash -81033362, now seen corresponding path program 1 times [2018-11-18 10:50:57,651 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:57,651 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:57,652 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:57,652 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:50:57,652 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:57,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:50:57,655 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:50:57,656 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:57,656 INFO L82 PathProgramCache]: Analyzing trace with hash 711949750, now seen corresponding path program 1 times [2018-11-18 10:50:57,656 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:57,657 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:57,657 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:57,657 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:50:57,657 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:57,662 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:50:57,696 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:50:57,697 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:50:57,697 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:50:57,760 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 10:50:57,760 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:50:57,761 INFO L87 Difference]: Start difference. First operand 15915 states and 21404 transitions. cyclomatic complexity: 5513 Second operand 3 states. [2018-11-18 10:50:57,878 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:50:57,878 INFO L93 Difference]: Finished difference Result 30144 states and 40257 transitions. [2018-11-18 10:50:57,879 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 10:50:57,879 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30144 states and 40257 transitions. [2018-11-18 10:50:57,941 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 29720 [2018-11-18 10:50:57,982 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30144 states to 30144 states and 40257 transitions. [2018-11-18 10:50:57,982 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30144 [2018-11-18 10:50:57,994 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30144 [2018-11-18 10:50:57,995 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30144 states and 40257 transitions. [2018-11-18 10:50:58,005 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 10:50:58,005 INFO L705 BuchiCegarLoop]: Abstraction has 30144 states and 40257 transitions. [2018-11-18 10:50:58,016 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30144 states and 40257 transitions. [2018-11-18 10:50:58,138 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30144 to 28688. [2018-11-18 10:50:58,138 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 28688 states. [2018-11-18 10:50:58,162 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28688 states to 28688 states and 38385 transitions. [2018-11-18 10:50:58,163 INFO L728 BuchiCegarLoop]: Abstraction has 28688 states and 38385 transitions. [2018-11-18 10:50:58,163 INFO L608 BuchiCegarLoop]: Abstraction has 28688 states and 38385 transitions. [2018-11-18 10:50:58,163 INFO L442 BuchiCegarLoop]: ======== Iteration 25============ [2018-11-18 10:50:58,163 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28688 states and 38385 transitions. [2018-11-18 10:50:58,210 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 28264 [2018-11-18 10:50:58,210 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:50:58,210 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:50:58,211 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:58,211 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:58,211 INFO L794 eck$LassoCheckResult]: Stem: 318925#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 318834#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 318835#L1101 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 318905#L504 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 318537#L511 assume 1 == ~m_i~0;~m_st~0 := 0; 318538#L511-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 318700#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 324108#L521-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 324107#L526-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 324106#L531-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 324105#L536-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 324104#L541-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 324103#L546-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 324102#L744 assume !(0 == ~M_E~0); 324101#L744-2 assume !(0 == ~T1_E~0); 324100#L749-1 assume !(0 == ~T2_E~0); 324099#L754-1 assume !(0 == ~T3_E~0); 324098#L759-1 assume !(0 == ~T4_E~0); 324097#L764-1 assume !(0 == ~T5_E~0); 324096#L769-1 assume !(0 == ~T6_E~0); 324095#L774-1 assume !(0 == ~T7_E~0); 324094#L779-1 assume !(0 == ~E_1~0); 324093#L784-1 assume !(0 == ~E_2~0); 324092#L789-1 assume !(0 == ~E_3~0); 324091#L794-1 assume !(0 == ~E_4~0); 324090#L799-1 assume !(0 == ~E_5~0); 324089#L804-1 assume !(0 == ~E_6~0); 324088#L809-1 assume !(0 == ~E_7~0); 324087#L814-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 324086#L351 assume !(1 == ~m_pc~0); 324085#L351-2 is_master_triggered_~__retres1~0 := 0; 324084#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 324083#L363 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 324082#L920 assume !(0 != activate_threads_~tmp~1); 324081#L920-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 324080#L370 assume !(1 == ~t1_pc~0); 324079#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 324110#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 324109#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 324074#L928 assume !(0 != activate_threads_~tmp___0~0); 324073#L928-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 324072#L389 assume !(1 == ~t2_pc~0); 324071#L389-2 is_transmit2_triggered_~__retres1~2 := 0; 324070#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 318703#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 318704#L936 assume !(0 != activate_threads_~tmp___1~0); 319392#L936-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 319283#L408 assume !(1 == ~t3_pc~0); 319284#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 323941#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 323940#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 319112#L944 assume !(0 != activate_threads_~tmp___2~0); 319113#L944-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 319454#L427 assume !(1 == ~t4_pc~0); 319455#L427-2 is_transmit4_triggered_~__retres1~4 := 0; 319096#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 319097#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 318685#L952 assume !(0 != activate_threads_~tmp___3~0); 318686#L952-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 318689#L446 assume !(1 == ~t5_pc~0); 318659#L446-2 is_transmit5_triggered_~__retres1~5 := 0; 318660#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 319191#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 319329#L960 assume !(0 != activate_threads_~tmp___4~0); 319330#L960-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 318799#L465 assume !(1 == ~t6_pc~0); 318800#L465-2 is_transmit6_triggered_~__retres1~6 := 0; 319311#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 319312#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 318988#L968 assume !(0 != activate_threads_~tmp___5~0); 318989#L968-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 318945#L484 assume !(1 == ~t7_pc~0); 318773#L484-2 is_transmit7_triggered_~__retres1~7 := 0; 318950#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 319408#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 319415#L976 assume !(0 != activate_threads_~tmp___6~0); 319416#L976-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 323637#L827 assume !(1 == ~M_E~0); 323636#L827-2 assume !(1 == ~T1_E~0); 319088#L832-1 assume !(1 == ~T2_E~0); 319089#L837-1 assume !(1 == ~T3_E~0); 318671#L842-1 assume !(1 == ~T4_E~0); 318672#L847-1 assume !(1 == ~T5_E~0); 319150#L852-1 assume !(1 == ~T6_E~0); 319151#L857-1 assume !(1 == ~T7_E~0); 318623#L862-1 assume !(1 == ~E_1~0); 318624#L867-1 assume !(1 == ~E_2~0); 319322#L872-1 assume !(1 == ~E_3~0); 319323#L877-1 assume !(1 == ~E_4~0); 318723#L882-1 assume !(1 == ~E_5~0); 318724#L887-1 assume !(1 == ~E_6~0); 319393#L892-1 assume !(1 == ~E_7~0); 319394#L897-1 assume { :end_inline_reset_delta_events } true; 323570#L1138-3 assume true; 323565#L1138-1 assume !false; 323444#L1139 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 323441#L719 [2018-11-18 10:50:58,211 INFO L796 eck$LassoCheckResult]: Loop: 323441#L719 assume true; 323439#L611-1 assume !false; 323437#L612 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 323435#L559 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 323431#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 323429#L602 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 323427#L616 assume 0 != eval_~tmp~0; 323424#L616-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 323421#L624 assume !(0 != eval_~tmp_ndt_1~0); 323419#L621 assume !(0 == ~t1_st~0); 323417#L635 assume !(0 == ~t2_st~0); 323399#L649 assume !(0 == ~t3_st~0); 323391#L663 assume !(0 == ~t4_st~0); 323382#L677 assume !(0 == ~t5_st~0); 323451#L691 assume !(0 == ~t6_st~0); 323447#L705 assume !(0 == ~t7_st~0); 323441#L719 [2018-11-18 10:50:58,211 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:58,211 INFO L82 PathProgramCache]: Analyzing trace with hash -744581173, now seen corresponding path program 1 times [2018-11-18 10:50:58,211 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:58,212 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:58,212 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:58,212 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:50:58,212 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:58,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:50:58,239 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:50:58,239 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:50:58,239 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:50:58,240 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 10:50:58,240 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:58,240 INFO L82 PathProgramCache]: Analyzing trace with hash -81033362, now seen corresponding path program 2 times [2018-11-18 10:50:58,240 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:58,240 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:58,241 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:58,241 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:50:58,241 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:58,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:50:58,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:50:58,355 WARN L180 SmtUtils]: Spent 108.00 ms on a formula simplification. DAG size of input: 38 DAG size of output: 36 [2018-11-18 10:50:58,383 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 10:50:58,383 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:50:58,384 INFO L87 Difference]: Start difference. First operand 28688 states and 38385 transitions. cyclomatic complexity: 9721 Second operand 3 states. [2018-11-18 10:50:58,523 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:50:58,523 INFO L93 Difference]: Finished difference Result 28591 states and 38255 transitions. [2018-11-18 10:50:58,524 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 10:50:58,524 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 28591 states and 38255 transitions. [2018-11-18 10:50:58,581 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 28264 [2018-11-18 10:50:58,618 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 28591 states to 28591 states and 38255 transitions. [2018-11-18 10:50:58,618 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28591 [2018-11-18 10:50:58,629 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28591 [2018-11-18 10:50:58,630 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28591 states and 38255 transitions. [2018-11-18 10:50:58,639 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 10:50:58,640 INFO L705 BuchiCegarLoop]: Abstraction has 28591 states and 38255 transitions. [2018-11-18 10:50:58,649 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28591 states and 38255 transitions. [2018-11-18 10:50:58,760 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28591 to 28591. [2018-11-18 10:50:58,761 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 28591 states. [2018-11-18 10:50:58,785 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28591 states to 28591 states and 38255 transitions. [2018-11-18 10:50:58,785 INFO L728 BuchiCegarLoop]: Abstraction has 28591 states and 38255 transitions. [2018-11-18 10:50:58,785 INFO L608 BuchiCegarLoop]: Abstraction has 28591 states and 38255 transitions. [2018-11-18 10:50:58,786 INFO L442 BuchiCegarLoop]: ======== Iteration 26============ [2018-11-18 10:50:58,786 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28591 states and 38255 transitions. [2018-11-18 10:50:58,833 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 28264 [2018-11-18 10:50:58,834 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:50:58,834 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:50:58,834 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:58,834 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:58,834 INFO L794 eck$LassoCheckResult]: Stem: 376200#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 376114#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 376115#L1101 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 376180#L504 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 375822#L511 assume 1 == ~m_i~0;~m_st~0 := 0; 375823#L511-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 375984#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 376444#L521-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 376365#L526-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 376080#L531-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 376081#L536-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 376507#L541-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 376347#L546-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 376348#L744 assume !(0 == ~M_E~0); 376352#L744-2 assume !(0 == ~T1_E~0); 376163#L749-1 assume !(0 == ~T2_E~0); 375962#L754-1 assume !(0 == ~T3_E~0); 375963#L759-1 assume !(0 == ~T4_E~0); 376422#L764-1 assume !(0 == ~T5_E~0); 376143#L769-1 assume !(0 == ~T6_E~0); 375916#L774-1 assume !(0 == ~T7_E~0); 375917#L779-1 assume !(0 == ~E_1~0); 376583#L784-1 assume !(0 == ~E_2~0); 376405#L789-1 assume !(0 == ~E_3~0); 376001#L794-1 assume !(0 == ~E_4~0); 376002#L799-1 assume !(0 == ~E_5~0); 376642#L804-1 assume !(0 == ~E_6~0); 376468#L809-1 assume !(0 == ~E_7~0); 376252#L814-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 376137#L351 assume !(1 == ~m_pc~0); 376121#L351-2 is_master_triggered_~__retres1~0 := 0; 376122#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 376624#L363 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 376359#L920 assume !(0 != activate_threads_~tmp~1); 376360#L920-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 376324#L370 assume !(1 == ~t1_pc~0); 376325#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 376333#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 376675#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 376059#L928 assume !(0 != activate_threads_~tmp___0~0); 375906#L928-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 375907#L389 assume !(1 == ~t2_pc~0); 376434#L389-2 is_transmit2_triggered_~__retres1~2 := 0; 375883#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 375884#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 375986#L936 assume !(0 != activate_threads_~tmp___1~0); 376646#L936-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 376547#L408 assume !(1 == ~t3_pc~0); 376488#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 376035#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 375989#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 375990#L944 assume !(0 != activate_threads_~tmp___2~0); 376378#L944-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 376379#L427 assume !(1 == ~t4_pc~0); 376635#L427-2 is_transmit4_triggered_~__retres1~4 := 0; 376370#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 376134#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 375969#L952 assume !(0 != activate_threads_~tmp___3~0); 375970#L952-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 375938#L446 assume !(1 == ~t5_pc~0); 375939#L446-2 is_transmit5_triggered_~__retres1~5 := 0; 375944#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 376349#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 376350#L960 assume !(0 != activate_threads_~tmp___4~0); 376579#L960-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 376082#L465 assume !(1 == ~t6_pc~0); 376083#L465-2 is_transmit6_triggered_~__retres1~6 := 0; 376084#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 376445#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 376264#L968 assume !(0 != activate_threads_~tmp___5~0); 376265#L968-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 376220#L484 assume !(1 == ~t7_pc~0); 376055#L484-2 is_transmit7_triggered_~__retres1~7 := 0; 376225#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 376561#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 376562#L976 assume !(0 != activate_threads_~tmp___6~0); 376657#L976-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 376524#L827 assume !(1 == ~M_E~0); 376511#L827-2 assume !(1 == ~T1_E~0); 376362#L832-1 assume !(1 == ~T2_E~0); 376161#L837-1 assume !(1 == ~T3_E~0); 375955#L842-1 assume !(1 == ~T4_E~0); 375956#L847-1 assume !(1 == ~T5_E~0); 376419#L852-1 assume !(1 == ~T6_E~0); 376141#L857-1 assume !(1 == ~T7_E~0); 375908#L862-1 assume !(1 == ~E_1~0); 375909#L867-1 assume !(1 == ~E_2~0); 376581#L872-1 assume !(1 == ~E_3~0); 376274#L877-1 assume !(1 == ~E_4~0); 376005#L882-1 assume !(1 == ~E_5~0); 376006#L887-1 assume !(1 == ~E_6~0); 376647#L892-1 assume !(1 == ~E_7~0); 376473#L897-1 assume { :end_inline_reset_delta_events } true; 376474#L1138-3 assume true; 378886#L1138-1 assume !false; 378875#L1139 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 378866#L719 [2018-11-18 10:50:58,834 INFO L796 eck$LassoCheckResult]: Loop: 378866#L719 assume true; 378859#L611-1 assume !false; 378850#L612 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 378842#L559 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 378835#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 378828#L602 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 378821#L616 assume 0 != eval_~tmp~0; 378816#L616-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 378810#L624 assume !(0 != eval_~tmp_ndt_1~0); 378043#L621 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 378012#L638 assume !(0 != eval_~tmp_ndt_2~0); 377875#L635 assume !(0 == ~t2_st~0); 377831#L649 assume !(0 == ~t3_st~0); 377824#L663 assume !(0 == ~t4_st~0); 377817#L677 assume !(0 == ~t5_st~0); 378716#L691 assume !(0 == ~t6_st~0); 378710#L705 assume !(0 == ~t7_st~0); 378866#L719 [2018-11-18 10:50:58,835 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:58,835 INFO L82 PathProgramCache]: Analyzing trace with hash 1196000841, now seen corresponding path program 2 times [2018-11-18 10:50:58,835 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:58,835 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:58,835 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:58,836 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:50:58,836 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:58,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:50:58,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:50:58,862 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:58,862 INFO L82 PathProgramCache]: Analyzing trace with hash 930469249, now seen corresponding path program 1 times [2018-11-18 10:50:58,863 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:58,863 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:58,863 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:58,863 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:50:58,863 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:58,864 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:50:58,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:50:58,867 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:58,867 INFO L82 PathProgramCache]: Analyzing trace with hash -256858055, now seen corresponding path program 1 times [2018-11-18 10:50:58,867 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:58,867 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:58,868 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:58,868 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:50:58,868 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:58,872 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:50:58,906 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:50:58,906 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:50:58,906 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:50:58,998 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 10:50:58,998 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:50:58,998 INFO L87 Difference]: Start difference. First operand 28591 states and 38255 transitions. cyclomatic complexity: 9688 Second operand 3 states. [2018-11-18 10:50:59,097 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:50:59,097 INFO L93 Difference]: Finished difference Result 38343 states and 51019 transitions. [2018-11-18 10:50:59,097 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 10:50:59,097 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 38343 states and 51019 transitions. [2018-11-18 10:50:59,175 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 37936 [2018-11-18 10:50:59,229 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 38343 states to 38343 states and 51019 transitions. [2018-11-18 10:50:59,229 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 38343 [2018-11-18 10:50:59,245 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 38343 [2018-11-18 10:50:59,245 INFO L73 IsDeterministic]: Start isDeterministic. Operand 38343 states and 51019 transitions. [2018-11-18 10:50:59,259 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 10:50:59,259 INFO L705 BuchiCegarLoop]: Abstraction has 38343 states and 51019 transitions. [2018-11-18 10:50:59,273 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38343 states and 51019 transitions. [2018-11-18 10:50:59,412 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38343 to 37095. [2018-11-18 10:50:59,412 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37095 states. [2018-11-18 10:50:59,443 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37095 states to 37095 states and 49403 transitions. [2018-11-18 10:50:59,444 INFO L728 BuchiCegarLoop]: Abstraction has 37095 states and 49403 transitions. [2018-11-18 10:50:59,444 INFO L608 BuchiCegarLoop]: Abstraction has 37095 states and 49403 transitions. [2018-11-18 10:50:59,444 INFO L442 BuchiCegarLoop]: ======== Iteration 27============ [2018-11-18 10:50:59,444 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 37095 states and 49403 transitions. [2018-11-18 10:50:59,506 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 36688 [2018-11-18 10:50:59,506 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:50:59,506 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:50:59,507 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:59,507 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:50:59,507 INFO L794 eck$LassoCheckResult]: Stem: 443157#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 443063#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 443064#L1101 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 443137#L504 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 442764#L511 assume 1 == ~m_i~0;~m_st~0 := 0; 442765#L511-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 442929#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 443413#L521-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 443322#L526-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 443025#L531-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 443026#L536-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 443486#L541-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 443303#L546-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 443304#L744 assume !(0 == ~M_E~0); 443308#L744-2 assume !(0 == ~T1_E~0); 443120#L749-1 assume !(0 == ~T2_E~0); 442907#L754-1 assume !(0 == ~T3_E~0); 442908#L759-1 assume !(0 == ~T4_E~0); 443391#L764-1 assume !(0 == ~T5_E~0); 443097#L769-1 assume !(0 == ~T6_E~0); 442860#L774-1 assume !(0 == ~T7_E~0); 442861#L779-1 assume !(0 == ~E_1~0); 443585#L784-1 assume !(0 == ~E_2~0); 443367#L789-1 assume !(0 == ~E_3~0); 442947#L794-1 assume !(0 == ~E_4~0); 442948#L799-1 assume !(0 == ~E_5~0); 443636#L804-1 assume !(0 == ~E_6~0); 443443#L809-1 assume !(0 == ~E_7~0); 443207#L814-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 443087#L351 assume !(1 == ~m_pc~0); 443071#L351-2 is_master_triggered_~__retres1~0 := 0; 443072#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 443621#L363 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 443316#L920 assume !(0 != activate_threads_~tmp~1); 443317#L920-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 443279#L370 assume !(1 == ~t1_pc~0); 443280#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 443289#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 443688#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 443004#L928 assume !(0 != activate_threads_~tmp___0~0); 442850#L928-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 442851#L389 assume !(1 == ~t2_pc~0); 443405#L389-2 is_transmit2_triggered_~__retres1~2 := 0; 442827#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 442828#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 442932#L936 assume !(0 != activate_threads_~tmp___1~0); 443640#L936-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 443539#L408 assume !(1 == ~t3_pc~0); 443466#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 442981#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 442935#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 442936#L944 assume !(0 != activate_threads_~tmp___2~0); 443336#L944-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 443337#L427 assume !(1 == ~t4_pc~0); 443633#L427-2 is_transmit4_triggered_~__retres1~4 := 0; 443327#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 443084#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 442915#L952 assume !(0 != activate_threads_~tmp___3~0); 442916#L952-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 442882#L446 assume !(1 == ~t5_pc~0); 442883#L446-2 is_transmit5_triggered_~__retres1~5 := 0; 442888#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 443305#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 443306#L960 assume !(0 != activate_threads_~tmp___4~0); 443581#L960-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 443027#L465 assume !(1 == ~t6_pc~0); 443028#L465-2 is_transmit6_triggered_~__retres1~6 := 0; 443029#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 443414#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 443219#L968 assume !(0 != activate_threads_~tmp___5~0); 443220#L968-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 443176#L484 assume !(1 == ~t7_pc~0); 443001#L484-2 is_transmit7_triggered_~__retres1~7 := 0; 443180#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 443551#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 443552#L976 assume !(0 != activate_threads_~tmp___6~0); 443668#L976-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 443506#L827 assume !(1 == ~M_E~0); 443492#L827-2 assume !(1 == ~T1_E~0); 443319#L832-1 assume !(1 == ~T2_E~0); 443118#L837-1 assume !(1 == ~T3_E~0); 442900#L842-1 assume !(1 == ~T4_E~0); 442901#L847-1 assume !(1 == ~T5_E~0); 443388#L852-1 assume !(1 == ~T6_E~0); 443094#L857-1 assume !(1 == ~T7_E~0); 442852#L862-1 assume !(1 == ~E_1~0); 442853#L867-1 assume !(1 == ~E_2~0); 443583#L872-1 assume !(1 == ~E_3~0); 443230#L877-1 assume !(1 == ~E_4~0); 442951#L882-1 assume !(1 == ~E_5~0); 442952#L887-1 assume !(1 == ~E_6~0); 443641#L892-1 assume !(1 == ~E_7~0); 443450#L897-1 assume { :end_inline_reset_delta_events } true; 443451#L1138-3 assume true; 456147#L1138-1 assume !false; 455985#L1139 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 455982#L719 [2018-11-18 10:50:59,507 INFO L796 eck$LassoCheckResult]: Loop: 455982#L719 assume true; 455980#L611-1 assume !false; 455978#L612 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 455975#L559 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 455973#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 455971#L602 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 455969#L616 assume 0 != eval_~tmp~0; 455966#L616-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 455963#L624 assume !(0 != eval_~tmp_ndt_1~0); 455961#L621 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 455905#L638 assume !(0 != eval_~tmp_ndt_2~0); 455959#L635 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 456062#L652 assume !(0 != eval_~tmp_ndt_3~0); 456003#L649 assume !(0 == ~t3_st~0); 456001#L663 assume !(0 == ~t4_st~0); 455997#L677 assume !(0 == ~t5_st~0); 455992#L691 assume !(0 == ~t6_st~0); 455988#L705 assume !(0 == ~t7_st~0); 455982#L719 [2018-11-18 10:50:59,507 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:59,507 INFO L82 PathProgramCache]: Analyzing trace with hash 1196000841, now seen corresponding path program 3 times [2018-11-18 10:50:59,507 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:59,507 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:59,508 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:59,508 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:50:59,508 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:59,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:50:59,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:50:59,534 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:59,534 INFO L82 PathProgramCache]: Analyzing trace with hash -693526056, now seen corresponding path program 1 times [2018-11-18 10:50:59,534 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:59,535 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:59,535 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:59,535 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:50:59,535 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:59,536 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:50:59,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:50:59,539 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:50:59,539 INFO L82 PathProgramCache]: Analyzing trace with hash 1154033184, now seen corresponding path program 1 times [2018-11-18 10:50:59,539 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:50:59,539 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:50:59,540 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:59,540 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:50:59,540 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:50:59,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:50:59,574 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:50:59,574 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:50:59,574 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:50:59,694 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 10:50:59,694 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:50:59,695 INFO L87 Difference]: Start difference. First operand 37095 states and 49403 transitions. cyclomatic complexity: 12332 Second operand 3 states. [2018-11-18 10:50:59,906 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:50:59,906 INFO L93 Difference]: Finished difference Result 69719 states and 92599 transitions. [2018-11-18 10:50:59,906 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 10:50:59,906 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 69719 states and 92599 transitions. [2018-11-18 10:51:00,214 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 69008 [2018-11-18 10:51:00,290 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 69719 states to 69719 states and 92599 transitions. [2018-11-18 10:51:00,291 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 69719 [2018-11-18 10:51:00,312 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 69719 [2018-11-18 10:51:00,312 INFO L73 IsDeterministic]: Start isDeterministic. Operand 69719 states and 92599 transitions. [2018-11-18 10:51:00,332 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 10:51:00,332 INFO L705 BuchiCegarLoop]: Abstraction has 69719 states and 92599 transitions. [2018-11-18 10:51:00,351 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69719 states and 92599 transitions. [2018-11-18 10:51:00,605 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69719 to 66647. [2018-11-18 10:51:00,605 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 66647 states. [2018-11-18 10:51:00,665 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66647 states to 66647 states and 88711 transitions. [2018-11-18 10:51:00,665 INFO L728 BuchiCegarLoop]: Abstraction has 66647 states and 88711 transitions. [2018-11-18 10:51:00,665 INFO L608 BuchiCegarLoop]: Abstraction has 66647 states and 88711 transitions. [2018-11-18 10:51:00,665 INFO L442 BuchiCegarLoop]: ======== Iteration 28============ [2018-11-18 10:51:00,665 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 66647 states and 88711 transitions. [2018-11-18 10:51:00,782 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 65936 [2018-11-18 10:51:00,782 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:51:00,782 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:51:00,783 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:51:00,783 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:51:00,783 INFO L794 eck$LassoCheckResult]: Stem: 549997#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 549900#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 549901#L1101 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 549981#L504 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 549586#L511 assume 1 == ~m_i~0;~m_st~0 := 0; 549587#L511-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 549758#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 550259#L521-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 550168#L526-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 549856#L531-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 549857#L536-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 550321#L541-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 550148#L546-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 550149#L744 assume !(0 == ~M_E~0); 550153#L744-2 assume !(0 == ~T1_E~0); 549959#L749-1 assume !(0 == ~T2_E~0); 549733#L754-1 assume !(0 == ~T3_E~0); 549734#L759-1 assume !(0 == ~T4_E~0); 550232#L764-1 assume !(0 == ~T5_E~0); 549934#L769-1 assume !(0 == ~T6_E~0); 549685#L774-1 assume !(0 == ~T7_E~0); 549686#L779-1 assume !(0 == ~E_1~0); 550416#L784-1 assume !(0 == ~E_2~0); 550213#L789-1 assume !(0 == ~E_3~0); 549776#L794-1 assume !(0 == ~E_4~0); 549777#L799-1 assume !(0 == ~E_5~0); 550476#L804-1 assume !(0 == ~E_6~0); 550286#L809-1 assume !(0 == ~E_7~0); 550047#L814-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 549925#L351 assume !(1 == ~m_pc~0); 549907#L351-2 is_master_triggered_~__retres1~0 := 0; 549908#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 550460#L363 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 550161#L920 assume !(0 != activate_threads_~tmp~1); 550162#L920-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 550121#L370 assume !(1 == ~t1_pc~0); 550122#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 550132#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 550532#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 549836#L928 assume !(0 != activate_threads_~tmp___0~0); 549675#L928-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 549676#L389 assume !(1 == ~t2_pc~0); 550248#L389-2 is_transmit2_triggered_~__retres1~2 := 0; 549652#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 549653#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 549761#L936 assume !(0 != activate_threads_~tmp___1~0); 550483#L936-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 550364#L408 assume !(1 == ~t3_pc~0); 550303#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 549812#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 549764#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 549765#L944 assume !(0 != activate_threads_~tmp___2~0); 550181#L944-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 550182#L427 assume !(1 == ~t4_pc~0); 550469#L427-2 is_transmit4_triggered_~__retres1~4 := 0; 550173#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 549921#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 549742#L952 assume !(0 != activate_threads_~tmp___3~0); 549743#L952-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 549707#L446 assume !(1 == ~t5_pc~0); 549708#L446-2 is_transmit5_triggered_~__retres1~5 := 0; 549713#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 550150#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 550151#L960 assume !(0 != activate_threads_~tmp___4~0); 550409#L960-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 549858#L465 assume !(1 == ~t6_pc~0); 549859#L465-2 is_transmit6_triggered_~__retres1~6 := 0; 549860#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 550260#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 550059#L968 assume !(0 != activate_threads_~tmp___5~0); 550060#L968-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 550017#L484 assume !(1 == ~t7_pc~0); 549831#L484-2 is_transmit7_triggered_~__retres1~7 := 0; 550022#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 550381#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 550382#L976 assume !(0 != activate_threads_~tmp___6~0); 550512#L976-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 550338#L827 assume !(1 == ~M_E~0); 550325#L827-2 assume !(1 == ~T1_E~0); 550164#L832-1 assume !(1 == ~T2_E~0); 549956#L837-1 assume !(1 == ~T3_E~0); 549725#L842-1 assume !(1 == ~T4_E~0); 549726#L847-1 assume !(1 == ~T5_E~0); 550230#L852-1 assume !(1 == ~T6_E~0); 549932#L857-1 assume !(1 == ~T7_E~0); 549677#L862-1 assume !(1 == ~E_1~0); 549678#L867-1 assume !(1 == ~E_2~0); 550412#L872-1 assume !(1 == ~E_3~0); 550071#L877-1 assume !(1 == ~E_4~0); 549780#L882-1 assume !(1 == ~E_5~0); 549781#L887-1 assume !(1 == ~E_6~0); 550484#L892-1 assume !(1 == ~E_7~0); 550293#L897-1 assume { :end_inline_reset_delta_events } true; 550294#L1138-3 assume true; 571093#L1138-1 assume !false; 571072#L1139 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 571069#L719 [2018-11-18 10:51:00,784 INFO L796 eck$LassoCheckResult]: Loop: 571069#L719 assume true; 571067#L611-1 assume !false; 571065#L612 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 570959#L559 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 570960#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 571268#L602 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 571267#L616 assume 0 != eval_~tmp~0; 571266#L616-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 571264#L624 assume !(0 != eval_~tmp_ndt_1~0); 563783#L621 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 563780#L638 assume !(0 != eval_~tmp_ndt_2~0); 563778#L635 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 563776#L652 assume !(0 != eval_~tmp_ndt_3~0); 560539#L649 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 560536#L666 assume !(0 != eval_~tmp_ndt_4~0); 560534#L663 assume !(0 == ~t4_st~0); 560532#L677 assume !(0 == ~t5_st~0); 567846#L691 assume !(0 == ~t6_st~0); 567844#L705 assume !(0 == ~t7_st~0); 571069#L719 [2018-11-18 10:51:00,784 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:51:00,784 INFO L82 PathProgramCache]: Analyzing trace with hash 1196000841, now seen corresponding path program 4 times [2018-11-18 10:51:00,784 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:51:00,784 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:51:00,785 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:51:00,785 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:51:00,785 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:51:00,790 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:51:00,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:51:00,813 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:51:00,813 INFO L82 PathProgramCache]: Analyzing trace with hash 1932189463, now seen corresponding path program 1 times [2018-11-18 10:51:00,813 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:51:00,814 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:51:00,814 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:51:00,814 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:51:00,814 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:51:00,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:51:00,816 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:51:00,818 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:51:00,818 INFO L82 PathProgramCache]: Analyzing trace with hash -923016241, now seen corresponding path program 1 times [2018-11-18 10:51:00,818 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:51:00,818 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:51:00,819 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:51:00,819 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:51:00,819 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:51:00,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:51:00,861 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:51:00,861 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:51:00,861 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:51:00,953 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 10:51:00,953 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:51:00,954 INFO L87 Difference]: Start difference. First operand 66647 states and 88711 transitions. cyclomatic complexity: 22088 Second operand 3 states. [2018-11-18 10:51:01,128 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:51:01,129 INFO L93 Difference]: Finished difference Result 91307 states and 121267 transitions. [2018-11-18 10:51:01,129 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 10:51:01,129 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 91307 states and 121267 transitions. [2018-11-18 10:51:01,326 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 90388 [2018-11-18 10:51:01,455 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 91307 states to 91307 states and 121267 transitions. [2018-11-18 10:51:01,455 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 91307 [2018-11-18 10:51:01,494 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 91307 [2018-11-18 10:51:01,494 INFO L73 IsDeterministic]: Start isDeterministic. Operand 91307 states and 121267 transitions. [2018-11-18 10:51:01,527 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 10:51:01,527 INFO L705 BuchiCegarLoop]: Abstraction has 91307 states and 121267 transitions. [2018-11-18 10:51:01,857 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 91307 states and 121267 transitions. [2018-11-18 10:51:02,168 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 91307 to 88859. [2018-11-18 10:51:02,168 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 88859 states. [2018-11-18 10:51:02,245 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 88859 states to 88859 states and 118195 transitions. [2018-11-18 10:51:02,245 INFO L728 BuchiCegarLoop]: Abstraction has 88859 states and 118195 transitions. [2018-11-18 10:51:02,245 INFO L608 BuchiCegarLoop]: Abstraction has 88859 states and 118195 transitions. [2018-11-18 10:51:02,245 INFO L442 BuchiCegarLoop]: ======== Iteration 29============ [2018-11-18 10:51:02,245 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 88859 states and 118195 transitions. [2018-11-18 10:51:02,404 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 87940 [2018-11-18 10:51:02,404 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:51:02,404 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:51:02,405 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:51:02,405 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:51:02,405 INFO L794 eck$LassoCheckResult]: Stem: 707947#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 707850#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 707851#L1101 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 707931#L504 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 707548#L511 assume 1 == ~m_i~0;~m_st~0 := 0; 707549#L511-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 707716#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 708198#L521-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 708110#L526-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 707811#L531-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 707812#L536-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 708265#L541-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 708090#L546-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 708091#L744 assume !(0 == ~M_E~0); 708095#L744-2 assume !(0 == ~T1_E~0); 707909#L749-1 assume !(0 == ~T2_E~0); 707691#L754-1 assume !(0 == ~T3_E~0); 707692#L759-1 assume !(0 == ~T4_E~0); 708173#L764-1 assume !(0 == ~T5_E~0); 707883#L769-1 assume !(0 == ~T6_E~0); 707643#L774-1 assume !(0 == ~T7_E~0); 707644#L779-1 assume !(0 == ~E_1~0); 708359#L784-1 assume !(0 == ~E_2~0); 708150#L789-1 assume !(0 == ~E_3~0); 707734#L794-1 assume !(0 == ~E_4~0); 707735#L799-1 assume !(0 == ~E_5~0); 708413#L804-1 assume !(0 == ~E_6~0); 708229#L809-1 assume !(0 == ~E_7~0); 707993#L814-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 707874#L351 assume !(1 == ~m_pc~0); 707857#L351-2 is_master_triggered_~__retres1~0 := 0; 707858#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 708400#L363 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 708104#L920 assume !(0 != activate_threads_~tmp~1); 708105#L920-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 708066#L370 assume !(1 == ~t1_pc~0); 708067#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 708075#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 708462#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 707793#L928 assume !(0 != activate_threads_~tmp___0~0); 707631#L928-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 707632#L389 assume !(1 == ~t2_pc~0); 708187#L389-2 is_transmit2_triggered_~__retres1~2 := 0; 707611#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 707612#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 707719#L936 assume !(0 != activate_threads_~tmp___1~0); 708419#L936-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 708315#L408 assume !(1 == ~t3_pc~0); 708244#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 707770#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 707722#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 707723#L944 assume !(0 != activate_threads_~tmp___2~0); 708124#L944-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 708125#L427 assume !(1 == ~t4_pc~0); 708408#L427-2 is_transmit4_triggered_~__retres1~4 := 0; 708115#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 707871#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 707699#L952 assume !(0 != activate_threads_~tmp___3~0); 707700#L952-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 707667#L446 assume !(1 == ~t5_pc~0); 707668#L446-2 is_transmit5_triggered_~__retres1~5 := 0; 707673#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 708092#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 708093#L960 assume !(0 != activate_threads_~tmp___4~0); 708354#L960-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 707813#L465 assume !(1 == ~t6_pc~0); 707814#L465-2 is_transmit6_triggered_~__retres1~6 := 0; 707815#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 708199#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 708004#L968 assume !(0 != activate_threads_~tmp___5~0); 708005#L968-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 707964#L484 assume !(1 == ~t7_pc~0); 707789#L484-2 is_transmit7_triggered_~__retres1~7 := 0; 707969#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 708330#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 708331#L976 assume !(0 != activate_threads_~tmp___6~0); 708441#L976-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 708284#L827 assume !(1 == ~M_E~0); 708270#L827-2 assume !(1 == ~T1_E~0); 708107#L832-1 assume !(1 == ~T2_E~0); 707906#L837-1 assume !(1 == ~T3_E~0); 707684#L842-1 assume !(1 == ~T4_E~0); 707685#L847-1 assume !(1 == ~T5_E~0); 708171#L852-1 assume !(1 == ~T6_E~0); 707881#L857-1 assume !(1 == ~T7_E~0); 707635#L862-1 assume !(1 == ~E_1~0); 707636#L867-1 assume !(1 == ~E_2~0); 708356#L872-1 assume !(1 == ~E_3~0); 708015#L877-1 assume !(1 == ~E_4~0); 707738#L882-1 assume !(1 == ~E_5~0); 707739#L887-1 assume !(1 == ~E_6~0); 708420#L892-1 assume !(1 == ~E_7~0); 708237#L897-1 assume { :end_inline_reset_delta_events } true; 708238#L1138-3 assume true; 734507#L1138-1 assume !false; 734054#L1139 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 734052#L719 [2018-11-18 10:51:02,405 INFO L796 eck$LassoCheckResult]: Loop: 734052#L719 assume true; 734050#L611-1 assume !false; 734048#L612 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 734045#L559 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 734043#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 734041#L602 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 734039#L616 assume 0 != eval_~tmp~0; 734037#L616-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 734034#L624 assume !(0 != eval_~tmp_ndt_1~0); 734032#L621 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 731728#L638 assume !(0 != eval_~tmp_ndt_2~0); 734030#L635 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 735337#L652 assume !(0 != eval_~tmp_ndt_3~0); 734077#L649 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 734071#L666 assume !(0 != eval_~tmp_ndt_4~0); 734069#L663 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 734067#L680 assume !(0 != eval_~tmp_ndt_5~0); 734065#L677 assume !(0 == ~t5_st~0); 734060#L691 assume !(0 == ~t6_st~0); 734057#L705 assume !(0 == ~t7_st~0); 734052#L719 [2018-11-18 10:51:02,405 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:51:02,406 INFO L82 PathProgramCache]: Analyzing trace with hash 1196000841, now seen corresponding path program 5 times [2018-11-18 10:51:02,406 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:51:02,406 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:51:02,406 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:51:02,406 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:51:02,406 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:51:02,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:51:02,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:51:02,429 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:51:02,429 INFO L82 PathProgramCache]: Analyzing trace with hash -445637566, now seen corresponding path program 1 times [2018-11-18 10:51:02,429 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:51:02,429 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:51:02,430 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:51:02,430 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:51:02,430 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:51:02,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:51:02,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:51:02,434 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:51:02,434 INFO L82 PathProgramCache]: Analyzing trace with hash 1237298826, now seen corresponding path program 1 times [2018-11-18 10:51:02,434 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:51:02,434 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:51:02,435 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:51:02,435 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:51:02,435 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:51:02,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:51:02,477 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:51:02,477 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:51:02,477 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:51:02,566 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 10:51:02,566 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:51:02,566 INFO L87 Difference]: Start difference. First operand 88859 states and 118195 transitions. cyclomatic complexity: 29360 Second operand 3 states. [2018-11-18 10:51:02,826 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:51:02,826 INFO L93 Difference]: Finished difference Result 161951 states and 214635 transitions. [2018-11-18 10:51:02,827 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 10:51:02,827 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 161951 states and 214635 transitions. [2018-11-18 10:51:03,201 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 160216 [2018-11-18 10:51:05,579 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 161951 states to 161951 states and 214635 transitions. [2018-11-18 10:51:05,579 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 161951 [2018-11-18 10:51:05,606 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 161951 [2018-11-18 10:51:05,607 INFO L73 IsDeterministic]: Start isDeterministic. Operand 161951 states and 214635 transitions. [2018-11-18 10:51:05,640 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 10:51:05,640 INFO L705 BuchiCegarLoop]: Abstraction has 161951 states and 214635 transitions. [2018-11-18 10:51:05,676 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 161951 states and 214635 transitions. [2018-11-18 10:51:06,298 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 161951 to 156623. [2018-11-18 10:51:06,299 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 156623 states. [2018-11-18 10:51:06,446 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 156623 states to 156623 states and 208155 transitions. [2018-11-18 10:51:06,446 INFO L728 BuchiCegarLoop]: Abstraction has 156623 states and 208155 transitions. [2018-11-18 10:51:06,447 INFO L608 BuchiCegarLoop]: Abstraction has 156623 states and 208155 transitions. [2018-11-18 10:51:06,447 INFO L442 BuchiCegarLoop]: ======== Iteration 30============ [2018-11-18 10:51:06,447 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 156623 states and 208155 transitions. [2018-11-18 10:51:06,743 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 154888 [2018-11-18 10:51:06,743 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:51:06,743 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:51:06,744 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:51:06,744 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:51:06,744 INFO L794 eck$LassoCheckResult]: Stem: 958768#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 958672#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 958673#L1101 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 958750#L504 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 958366#L511 assume 1 == ~m_i~0;~m_st~0 := 0; 958367#L511-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 958538#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 959022#L521-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 958934#L526-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 958632#L531-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 958633#L536-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 959086#L541-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 958913#L546-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 958914#L744 assume !(0 == ~M_E~0); 958920#L744-2 assume !(0 == ~T1_E~0); 958731#L749-1 assume !(0 == ~T2_E~0); 958511#L754-1 assume !(0 == ~T3_E~0); 958512#L759-1 assume !(0 == ~T4_E~0); 958997#L764-1 assume !(0 == ~T5_E~0); 958707#L769-1 assume !(0 == ~T6_E~0); 958463#L774-1 assume !(0 == ~T7_E~0); 958464#L779-1 assume !(0 == ~E_1~0); 959185#L784-1 assume !(0 == ~E_2~0); 958977#L789-1 assume !(0 == ~E_3~0); 958555#L794-1 assume !(0 == ~E_4~0); 958556#L799-1 assume !(0 == ~E_5~0); 959236#L804-1 assume !(0 == ~E_6~0); 959054#L809-1 assume !(0 == ~E_7~0); 958819#L814-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 958698#L351 assume !(1 == ~m_pc~0); 958680#L351-2 is_master_triggered_~__retres1~0 := 0; 958681#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 959222#L363 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 958928#L920 assume !(0 != activate_threads_~tmp~1); 958929#L920-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 958890#L370 assume !(1 == ~t1_pc~0); 958891#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 958899#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 959290#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 958614#L928 assume !(0 != activate_threads_~tmp___0~0); 958451#L928-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 958452#L389 assume !(1 == ~t2_pc~0); 959013#L389-2 is_transmit2_triggered_~__retres1~2 := 0; 958427#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 958428#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 958540#L936 assume !(0 != activate_threads_~tmp___1~0); 959244#L936-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 959137#L408 assume !(1 == ~t3_pc~0); 959068#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 958589#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 958543#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 958544#L944 assume !(0 != activate_threads_~tmp___2~0); 958949#L944-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 958950#L427 assume !(1 == ~t4_pc~0); 959232#L427-2 is_transmit4_triggered_~__retres1~4 := 0; 958939#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 958695#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 958521#L952 assume !(0 != activate_threads_~tmp___3~0); 958522#L952-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 958486#L446 assume !(1 == ~t5_pc~0); 958487#L446-2 is_transmit5_triggered_~__retres1~5 := 0; 958492#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 958915#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 958916#L960 assume !(0 != activate_threads_~tmp___4~0); 959180#L960-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 958634#L465 assume !(1 == ~t6_pc~0); 958635#L465-2 is_transmit6_triggered_~__retres1~6 := 0; 958636#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 959023#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 958830#L968 assume !(0 != activate_threads_~tmp___5~0); 958831#L968-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 958786#L484 assume !(1 == ~t7_pc~0); 958610#L484-2 is_transmit7_triggered_~__retres1~7 := 0; 958790#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 959152#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 959153#L976 assume !(0 != activate_threads_~tmp___6~0); 959268#L976-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 959105#L827 assume !(1 == ~M_E~0); 959091#L827-2 assume !(1 == ~T1_E~0); 958931#L832-1 assume !(1 == ~T2_E~0); 958729#L837-1 assume !(1 == ~T3_E~0); 958504#L842-1 assume !(1 == ~T4_E~0); 958505#L847-1 assume !(1 == ~T5_E~0); 958992#L852-1 assume !(1 == ~T6_E~0); 958705#L857-1 assume !(1 == ~T7_E~0); 958453#L862-1 assume !(1 == ~E_1~0); 958454#L867-1 assume !(1 == ~E_2~0); 959182#L872-1 assume !(1 == ~E_3~0); 958842#L877-1 assume !(1 == ~E_4~0); 958559#L882-1 assume !(1 == ~E_5~0); 958560#L887-1 assume !(1 == ~E_6~0); 959245#L892-1 assume !(1 == ~E_7~0); 959060#L897-1 assume { :end_inline_reset_delta_events } true; 959061#L1138-3 assume true; 971309#L1138-1 assume !false; 971289#L1139 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 971286#L719 [2018-11-18 10:51:06,744 INFO L796 eck$LassoCheckResult]: Loop: 971286#L719 assume true; 971284#L611-1 assume !false; 971282#L612 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 971279#L559 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 971277#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 971275#L602 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 971272#L616 assume 0 != eval_~tmp~0; 971269#L616-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 971266#L624 assume !(0 != eval_~tmp_ndt_1~0); 971264#L621 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 971253#L638 assume !(0 != eval_~tmp_ndt_2~0); 971262#L635 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 971569#L652 assume !(0 != eval_~tmp_ndt_3~0); 971567#L649 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 971542#L666 assume !(0 != eval_~tmp_ndt_4~0); 971564#L663 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 1003975#L680 assume !(0 != eval_~tmp_ndt_5~0); 971300#L677 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 971297#L694 assume !(0 != eval_~tmp_ndt_6~0); 971295#L691 assume !(0 == ~t6_st~0); 971292#L705 assume !(0 == ~t7_st~0); 971286#L719 [2018-11-18 10:51:06,745 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:51:06,745 INFO L82 PathProgramCache]: Analyzing trace with hash 1196000841, now seen corresponding path program 6 times [2018-11-18 10:51:06,745 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:51:06,745 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:51:06,745 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:51:06,746 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:51:06,746 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:51:06,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:51:06,755 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:51:06,780 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:51:06,780 INFO L82 PathProgramCache]: Analyzing trace with hash -936757075, now seen corresponding path program 1 times [2018-11-18 10:51:06,780 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:51:06,781 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:51:06,784 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:51:06,784 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:51:06,785 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:51:06,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:51:06,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:51:06,789 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:51:06,789 INFO L82 PathProgramCache]: Analyzing trace with hash -305336475, now seen corresponding path program 1 times [2018-11-18 10:51:06,789 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:51:06,789 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:51:06,789 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:51:06,790 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:51:06,790 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:51:06,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:51:06,815 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:51:06,815 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:51:06,815 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 10:51:06,945 WARN L180 SmtUtils]: Spent 129.00 ms on a formula simplification. DAG size of input: 53 DAG size of output: 51 [2018-11-18 10:51:06,973 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 10:51:06,974 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:51:06,974 INFO L87 Difference]: Start difference. First operand 156623 states and 208155 transitions. cyclomatic complexity: 51556 Second operand 3 states. [2018-11-18 10:51:07,591 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:51:07,591 INFO L93 Difference]: Finished difference Result 214463 states and 283993 transitions. [2018-11-18 10:51:07,591 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 10:51:07,591 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 214463 states and 283993 transitions. [2018-11-18 10:51:08,107 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 212200 [2018-11-18 10:51:08,412 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 214463 states to 214463 states and 283993 transitions. [2018-11-18 10:51:08,412 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 214463 [2018-11-18 10:51:08,496 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 214463 [2018-11-18 10:51:08,496 INFO L73 IsDeterministic]: Start isDeterministic. Operand 214463 states and 283993 transitions. [2018-11-18 10:51:08,559 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 10:51:08,559 INFO L705 BuchiCegarLoop]: Abstraction has 214463 states and 283993 transitions. [2018-11-18 10:51:08,629 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 214463 states and 283993 transitions. [2018-11-18 10:51:09,609 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 214463 to 211007. [2018-11-18 10:51:09,610 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 211007 states. [2018-11-18 10:51:10,509 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 211007 states to 211007 states and 279673 transitions. [2018-11-18 10:51:10,510 INFO L728 BuchiCegarLoop]: Abstraction has 211007 states and 279673 transitions. [2018-11-18 10:51:10,510 INFO L608 BuchiCegarLoop]: Abstraction has 211007 states and 279673 transitions. [2018-11-18 10:51:10,510 INFO L442 BuchiCegarLoop]: ======== Iteration 31============ [2018-11-18 10:51:10,510 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 211007 states and 279673 transitions. [2018-11-18 10:51:10,873 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 208744 [2018-11-18 10:51:10,873 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:51:10,873 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:51:10,874 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:51:10,874 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:51:10,874 INFO L794 eck$LassoCheckResult]: Stem: 1329858#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 1329764#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1329765#L1101 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 1329838#L504 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1329460#L511 assume 1 == ~m_i~0;~m_st~0 := 0; 1329461#L511-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1329630#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1330133#L521-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1330038#L526-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1329725#L531-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1329726#L536-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1330202#L541-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1330014#L546-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1330015#L744 assume !(0 == ~M_E~0); 1330022#L744-2 assume !(0 == ~T1_E~0); 1329820#L749-1 assume !(0 == ~T2_E~0); 1329604#L754-1 assume !(0 == ~T3_E~0); 1329605#L759-1 assume !(0 == ~T4_E~0); 1330108#L764-1 assume !(0 == ~T5_E~0); 1329798#L769-1 assume !(0 == ~T6_E~0); 1329554#L774-1 assume !(0 == ~T7_E~0); 1329555#L779-1 assume !(0 == ~E_1~0); 1330299#L784-1 assume !(0 == ~E_2~0); 1330088#L789-1 assume !(0 == ~E_3~0); 1329647#L794-1 assume !(0 == ~E_4~0); 1329648#L799-1 assume !(0 == ~E_5~0); 1330356#L804-1 assume !(0 == ~E_6~0); 1330166#L809-1 assume !(0 == ~E_7~0); 1329915#L814-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1329789#L351 assume !(1 == ~m_pc~0); 1329772#L351-2 is_master_triggered_~__retres1~0 := 0; 1329773#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1330337#L363 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1330030#L920 assume !(0 != activate_threads_~tmp~1); 1330031#L920-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1329990#L370 assume !(1 == ~t1_pc~0); 1329991#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 1329999#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1330401#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1329705#L928 assume !(0 != activate_threads_~tmp___0~0); 1329544#L928-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1329545#L389 assume !(1 == ~t2_pc~0); 1330121#L389-2 is_transmit2_triggered_~__retres1~2 := 0; 1329522#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1329523#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1329632#L936 assume !(0 != activate_threads_~tmp___1~0); 1330363#L936-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1330249#L408 assume !(1 == ~t3_pc~0); 1330182#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 1329681#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1329635#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1329636#L944 assume !(0 != activate_threads_~tmp___2~0); 1330054#L944-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1330055#L427 assume !(1 == ~t4_pc~0); 1330349#L427-2 is_transmit4_triggered_~__retres1~4 := 0; 1330043#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1329786#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1329614#L952 assume !(0 != activate_threads_~tmp___3~0); 1329615#L952-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1329578#L446 assume !(1 == ~t5_pc~0); 1329579#L446-2 is_transmit5_triggered_~__retres1~5 := 0; 1329584#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1330016#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1330017#L960 assume !(0 != activate_threads_~tmp___4~0); 1330294#L960-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1329727#L465 assume !(1 == ~t6_pc~0); 1329728#L465-2 is_transmit6_triggered_~__retres1~6 := 0; 1329729#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1330134#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1329928#L968 assume !(0 != activate_threads_~tmp___5~0); 1329929#L968-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1329883#L484 assume !(1 == ~t7_pc~0); 1329701#L484-2 is_transmit7_triggered_~__retres1~7 := 0; 1329888#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1330262#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1330263#L976 assume !(0 != activate_threads_~tmp___6~0); 1330383#L976-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1330220#L827 assume !(1 == ~M_E~0); 1330206#L827-2 assume !(1 == ~T1_E~0); 1330034#L832-1 assume !(1 == ~T2_E~0); 1329818#L837-1 assume !(1 == ~T3_E~0); 1329596#L842-1 assume !(1 == ~T4_E~0); 1329597#L847-1 assume !(1 == ~T5_E~0); 1330101#L852-1 assume !(1 == ~T6_E~0); 1329796#L857-1 assume !(1 == ~T7_E~0); 1329546#L862-1 assume !(1 == ~E_1~0); 1329547#L867-1 assume !(1 == ~E_2~0); 1330296#L872-1 assume !(1 == ~E_3~0); 1329940#L877-1 assume !(1 == ~E_4~0); 1329651#L882-1 assume !(1 == ~E_5~0); 1329652#L887-1 assume !(1 == ~E_6~0); 1330364#L892-1 assume !(1 == ~E_7~0); 1330172#L897-1 assume { :end_inline_reset_delta_events } true; 1330173#L1138-3 assume true; 1389951#L1138-1 assume !false; 1389930#L1139 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 1389927#L719 [2018-11-18 10:51:10,874 INFO L796 eck$LassoCheckResult]: Loop: 1389927#L719 assume true; 1389925#L611-1 assume !false; 1389923#L612 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 1389920#L559 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 1389918#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 1389916#L602 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 1389914#L616 assume 0 != eval_~tmp~0; 1389912#L616-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 1389910#L624 assume !(0 != eval_~tmp_ndt_1~0); 1389907#L621 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 1389500#L638 assume !(0 != eval_~tmp_ndt_2~0); 1389904#L635 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 1389899#L652 assume !(0 != eval_~tmp_ndt_3~0); 1389897#L649 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 1389858#L666 assume !(0 != eval_~tmp_ndt_4~0); 1389895#L663 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 1389944#L680 assume !(0 != eval_~tmp_ndt_5~0); 1389942#L677 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 1389693#L694 assume !(0 != eval_~tmp_ndt_6~0); 1389938#L691 assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0;eval_~tmp_ndt_7~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 1389935#L708 assume !(0 != eval_~tmp_ndt_7~0); 1389933#L705 assume !(0 == ~t7_st~0); 1389927#L719 [2018-11-18 10:51:10,874 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:51:10,874 INFO L82 PathProgramCache]: Analyzing trace with hash 1196000841, now seen corresponding path program 7 times [2018-11-18 10:51:10,875 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:51:10,875 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:51:10,875 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:51:10,875 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:51:10,875 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:51:10,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:51:10,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:51:10,896 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:51:10,897 INFO L82 PathProgramCache]: Analyzing trace with hash 1025087148, now seen corresponding path program 1 times [2018-11-18 10:51:10,897 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:51:10,897 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:51:10,897 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:51:10,897 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:51:10,898 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:51:10,899 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:51:10,900 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:51:10,902 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:51:10,902 INFO L82 PathProgramCache]: Analyzing trace with hash -875710732, now seen corresponding path program 1 times [2018-11-18 10:51:10,902 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:51:10,902 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:51:10,902 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:51:10,902 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:51:10,903 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:51:10,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 10:51:10,936 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 10:51:10,936 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 10:51:10,936 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 10:51:11,030 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 10:51:11,030 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 10:51:11,030 INFO L87 Difference]: Start difference. First operand 211007 states and 279673 transitions. cyclomatic complexity: 68690 Second operand 3 states. [2018-11-18 10:51:11,814 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 10:51:11,814 INFO L93 Difference]: Finished difference Result 413125 states and 546955 transitions. [2018-11-18 10:51:11,815 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 10:51:11,815 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 413125 states and 546955 transitions. [2018-11-18 10:51:12,961 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 408702 [2018-11-18 10:51:17,301 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 413125 states to 413125 states and 546955 transitions. [2018-11-18 10:51:17,301 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 413125 [2018-11-18 10:51:17,470 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 413125 [2018-11-18 10:51:17,471 INFO L73 IsDeterministic]: Start isDeterministic. Operand 413125 states and 546955 transitions. [2018-11-18 10:51:17,603 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 10:51:17,603 INFO L705 BuchiCegarLoop]: Abstraction has 413125 states and 546955 transitions. [2018-11-18 10:51:17,757 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 413125 states and 546955 transitions. [2018-11-18 10:51:19,759 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 413125 to 413125. [2018-11-18 10:51:19,759 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 413125 states. [2018-11-18 10:51:20,745 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 413125 states to 413125 states and 546955 transitions. [2018-11-18 10:51:20,745 INFO L728 BuchiCegarLoop]: Abstraction has 413125 states and 546955 transitions. [2018-11-18 10:51:20,745 INFO L608 BuchiCegarLoop]: Abstraction has 413125 states and 546955 transitions. [2018-11-18 10:51:20,745 INFO L442 BuchiCegarLoop]: ======== Iteration 32============ [2018-11-18 10:51:20,745 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 413125 states and 546955 transitions. [2018-11-18 10:51:21,558 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 408702 [2018-11-18 10:51:21,558 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 10:51:21,558 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 10:51:21,559 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:51:21,559 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 10:51:21,559 INFO L794 eck$LassoCheckResult]: Stem: 1953999#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 1953902#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~9;havoc main_~__retres1~9;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1953903#L1101 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18, start_simulation_#t~ret19, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 1953978#L504 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1953600#L511 assume 1 == ~m_i~0;~m_st~0 := 0; 1953601#L511-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1953766#L516-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1954268#L521-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1954173#L526-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1953864#L531-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1953865#L536-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1954330#L541-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1954151#L546-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1954152#L744 assume !(0 == ~M_E~0); 1954156#L744-2 assume !(0 == ~T1_E~0); 1953959#L749-1 assume !(0 == ~T2_E~0); 1953741#L754-1 assume !(0 == ~T3_E~0); 1953742#L759-1 assume !(0 == ~T4_E~0); 1954242#L764-1 assume !(0 == ~T5_E~0); 1953936#L769-1 assume !(0 == ~T6_E~0); 1953694#L774-1 assume !(0 == ~T7_E~0); 1953695#L779-1 assume !(0 == ~E_1~0); 1954424#L784-1 assume !(0 == ~E_2~0); 1954221#L789-1 assume !(0 == ~E_3~0); 1953784#L794-1 assume !(0 == ~E_4~0); 1953785#L799-1 assume !(0 == ~E_5~0); 1954473#L804-1 assume !(0 == ~E_6~0); 1954298#L809-1 assume !(0 == ~E_7~0); 1954055#L814-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9, activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1953927#L351 assume !(1 == ~m_pc~0); 1953910#L351-2 is_master_triggered_~__retres1~0 := 0; 1953911#L362 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1954460#L363 activate_threads_#t~ret9 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret9;havoc activate_threads_#t~ret9; 1954167#L920 assume !(0 != activate_threads_~tmp~1); 1954168#L920-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1954128#L370 assume !(1 == ~t1_pc~0); 1954129#L370-2 is_transmit1_triggered_~__retres1~1 := 0; 1954137#L381 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1954527#L382 activate_threads_#t~ret10 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1953845#L928 assume !(0 != activate_threads_~tmp___0~0); 1953684#L928-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1953685#L389 assume !(1 == ~t2_pc~0); 1954257#L389-2 is_transmit2_triggered_~__retres1~2 := 0; 1953662#L400 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1953663#L401 activate_threads_#t~ret11 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1953769#L936 assume !(0 != activate_threads_~tmp___1~0); 1954480#L936-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1954378#L408 assume !(1 == ~t3_pc~0); 1954311#L408-2 is_transmit3_triggered_~__retres1~3 := 0; 1953819#L419 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1953772#L420 activate_threads_#t~ret12 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1953773#L944 assume !(0 != activate_threads_~tmp___2~0); 1954191#L944-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1954192#L427 assume !(1 == ~t4_pc~0); 1954469#L427-2 is_transmit4_triggered_~__retres1~4 := 0; 1954179#L438 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1953924#L439 activate_threads_#t~ret13 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1953751#L952 assume !(0 != activate_threads_~tmp___3~0); 1953752#L952-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1953717#L446 assume !(1 == ~t5_pc~0); 1953718#L446-2 is_transmit5_triggered_~__retres1~5 := 0; 1953723#L457 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1954153#L458 activate_threads_#t~ret14 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1954154#L960 assume !(0 != activate_threads_~tmp___4~0); 1954420#L960-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1953866#L465 assume !(1 == ~t6_pc~0); 1953867#L465-2 is_transmit6_triggered_~__retres1~6 := 0; 1953868#L476 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1954269#L477 activate_threads_#t~ret15 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1954068#L968 assume !(0 != activate_threads_~tmp___5~0); 1954069#L968-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1954022#L484 assume !(1 == ~t7_pc~0); 1953841#L484-2 is_transmit7_triggered_~__retres1~7 := 0; 1954026#L495 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1954391#L496 activate_threads_#t~ret16 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1954392#L976 assume !(0 != activate_threads_~tmp___6~0); 1954508#L976-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1954349#L827 assume !(1 == ~M_E~0); 1954335#L827-2 assume !(1 == ~T1_E~0); 1954170#L832-1 assume !(1 == ~T2_E~0); 1953957#L837-1 assume !(1 == ~T3_E~0); 1953734#L842-1 assume !(1 == ~T4_E~0); 1953735#L847-1 assume !(1 == ~T5_E~0); 1954238#L852-1 assume !(1 == ~T6_E~0); 1953934#L857-1 assume !(1 == ~T7_E~0); 1953686#L862-1 assume !(1 == ~E_1~0); 1953687#L867-1 assume !(1 == ~E_2~0); 1954422#L872-1 assume !(1 == ~E_3~0); 1954079#L877-1 assume !(1 == ~E_4~0); 1953788#L882-1 assume !(1 == ~E_5~0); 1953789#L887-1 assume !(1 == ~E_6~0); 1954481#L892-1 assume !(1 == ~E_7~0); 1954304#L897-1 assume { :end_inline_reset_delta_events } true; 1954305#L1138-3 assume true; 2126496#L1138-1 assume !false; 2126494#L1139 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_~tmp~0;havoc eval_~tmp~0; 2124667#L719 [2018-11-18 10:51:21,559 INFO L796 eck$LassoCheckResult]: Loop: 2124667#L719 assume true; 2126492#L611-1 assume !false; 2126490#L612 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~8;havoc exists_runnable_thread_~__retres1~8; 2126487#L559 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8 := 1; 2126485#L601 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~8; 2126483#L602 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 2126481#L616 assume 0 != eval_~tmp~0; 2126477#L616-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 2126474#L624 assume !(0 != eval_~tmp_ndt_1~0); 2126472#L621 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 2126439#L638 assume !(0 != eval_~tmp_ndt_2~0); 2126470#L635 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 2194854#L652 assume !(0 != eval_~tmp_ndt_3~0); 2025181#L649 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 2025178#L666 assume !(0 != eval_~tmp_ndt_4~0); 2025174#L663 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 2025170#L680 assume !(0 != eval_~tmp_ndt_5~0); 2025171#L677 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 2086846#L694 assume !(0 != eval_~tmp_ndt_6~0); 2087447#L691 assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0;eval_~tmp_ndt_7~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 2124671#L708 assume !(0 != eval_~tmp_ndt_7~0); 2124669#L705 assume 0 == ~t7_st~0;havoc eval_~tmp_ndt_8~0;eval_~tmp_ndt_8~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 2124620#L722 assume !(0 != eval_~tmp_ndt_8~0); 2124667#L719 [2018-11-18 10:51:21,560 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:51:21,560 INFO L82 PathProgramCache]: Analyzing trace with hash 1196000841, now seen corresponding path program 8 times [2018-11-18 10:51:21,560 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:51:21,560 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:51:21,561 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:51:21,561 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:51:21,561 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:51:21,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:51:21,568 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:51:21,582 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:51:21,582 INFO L82 PathProgramCache]: Analyzing trace with hash 1712931395, now seen corresponding path program 1 times [2018-11-18 10:51:21,582 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:51:21,582 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:51:21,583 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:51:21,583 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 10:51:21,583 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:51:21,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:51:21,586 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:51:21,587 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 10:51:21,587 INFO L82 PathProgramCache]: Analyzing trace with hash -1377228037, now seen corresponding path program 1 times [2018-11-18 10:51:21,587 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 10:51:21,587 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 10:51:21,588 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:51:21,588 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 10:51:21,588 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 10:51:21,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:51:21,596 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 10:51:22,197 WARN L180 SmtUtils]: Spent 480.00 ms on a formula simplification. DAG size of input: 250 DAG size of output: 166 [2018-11-18 10:51:22,312 WARN L180 SmtUtils]: Spent 107.00 ms on a formula simplification that was a NOOP. DAG size: 132 [2018-11-18 10:51:22,343 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 18.11 10:51:22 BoogieIcfgContainer [2018-11-18 10:51:22,343 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2018-11-18 10:51:22,343 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-18 10:51:22,343 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-18 10:51:22,343 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-18 10:51:22,344 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 10:50:51" (3/4) ... [2018-11-18 10:51:22,346 INFO L141 WitnessPrinter]: Generating witness for non-termination counterexample [2018-11-18 10:51:22,396 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_eeb28a43-bad7-4f07-a222-3d03d3a88e9c/bin-2019/uautomizer/witness.graphml [2018-11-18 10:51:22,396 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-18 10:51:22,396 INFO L168 Benchmark]: Toolchain (without parser) took 32466.00 ms. Allocated memory was 1.0 GB in the beginning and 5.5 GB in the end (delta: 4.5 GB). Free memory was 958.1 MB in the beginning and 2.6 GB in the end (delta: -1.6 GB). Peak memory consumption was 2.8 GB. Max. memory is 11.5 GB. [2018-11-18 10:51:22,397 INFO L168 Benchmark]: CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 985.4 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-18 10:51:22,397 INFO L168 Benchmark]: CACSL2BoogieTranslator took 236.31 ms. Allocated memory is still 1.0 GB. Free memory was 958.1 MB in the beginning and 936.6 MB in the end (delta: 21.5 MB). Peak memory consumption was 21.5 MB. Max. memory is 11.5 GB. [2018-11-18 10:51:22,397 INFO L168 Benchmark]: Boogie Procedure Inliner took 91.85 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 137.4 MB). Free memory was 936.6 MB in the beginning and 1.1 GB in the end (delta: -192.0 MB). Peak memory consumption was 17.7 MB. Max. memory is 11.5 GB. [2018-11-18 10:51:22,398 INFO L168 Benchmark]: Boogie Preprocessor took 52.71 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.7 MB). Peak memory consumption was 6.7 MB. Max. memory is 11.5 GB. [2018-11-18 10:51:22,398 INFO L168 Benchmark]: RCFGBuilder took 1026.86 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 951.3 MB in the end (delta: 170.6 MB). Peak memory consumption was 170.6 MB. Max. memory is 11.5 GB. [2018-11-18 10:51:22,398 INFO L168 Benchmark]: BuchiAutomizer took 31002.79 ms. Allocated memory was 1.2 GB in the beginning and 5.5 GB in the end (delta: 4.3 GB). Free memory was 951.3 MB in the beginning and 2.6 GB in the end (delta: -1.6 GB). Peak memory consumption was 2.7 GB. Max. memory is 11.5 GB. [2018-11-18 10:51:22,398 INFO L168 Benchmark]: Witness Printer took 52.76 ms. Allocated memory is still 5.5 GB. Free memory is still 2.6 GB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-18 10:51:22,400 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 985.4 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 236.31 ms. Allocated memory is still 1.0 GB. Free memory was 958.1 MB in the beginning and 936.6 MB in the end (delta: 21.5 MB). Peak memory consumption was 21.5 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 91.85 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 137.4 MB). Free memory was 936.6 MB in the beginning and 1.1 GB in the end (delta: -192.0 MB). Peak memory consumption was 17.7 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 52.71 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.7 MB). Peak memory consumption was 6.7 MB. Max. memory is 11.5 GB. * RCFGBuilder took 1026.86 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 951.3 MB in the end (delta: 170.6 MB). Peak memory consumption was 170.6 MB. Max. memory is 11.5 GB. * BuchiAutomizer took 31002.79 ms. Allocated memory was 1.2 GB in the beginning and 5.5 GB in the end (delta: 4.3 GB). Free memory was 951.3 MB in the beginning and 2.6 GB in the end (delta: -1.6 GB). Peak memory consumption was 2.7 GB. Max. memory is 11.5 GB. * Witness Printer took 52.76 ms. Allocated memory is still 5.5 GB. Free memory is still 2.6 GB. There was no memory consumed. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 31 terminating modules (31 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.31 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 413125 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 30.9s and 32 iterations. TraceHistogramMax:1. Analysis of lassos took 4.0s. Construction of modules took 0.9s. Büchi inclusion checks took 2.9s. Highest rank in rank-based complementation 0. Minimization of det autom 31. Minimization of nondet autom 0. Automata minimization 8.5s AutomataMinimizationTime, 31 MinimizatonAttempts, 49220 StatesRemovedByMinimization, 15 NontrivialMinimizations. Non-live state removal took 11.0s Buchi closure took 0.4s. Biggest automaton had 413125 states and ocurred in iteration 31. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 36397 SDtfs, 36318 SDslu, 25967 SDs, 0 SdLazy, 657 SolverSat, 410 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.9s Time LassoAnalysisResults: nont1 unkn0 SFLI5 SFLT0 conc7 concLT0 SILN1 SILU0 SILI18 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 611]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {E_7=2, t3_st=0, __retres1=0, t5_i=1, __retres1=0, kernel_st=1, \result=0, E_3=2, T6_E=2, t7_i=1, tmp_ndt_8=0, \result=0, tmp_ndt_4=0, m_st=0, t6_pc=0, tmp___2=0, __retres1=0, t3_pc=0, \result=0, m_pc=0, tmp___6=0, t6_st=0, E_6=2, __retres1=0, \result=0, T2_E=2, t5_st=0, __retres1=1, E_2=2, t7_pc=0, M_E=2, tmp=0, tmp_ndt_3=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@16aaef86=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@d5b9e6b=0, T4_E=2, t3_i=1, t4_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4c4c8ebb=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3bd365fa=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@34f97414=0, t7_st=0, t5_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7ab020a9=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@52215500=0, \result=0, tmp_ndt_7=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@727d1200=0, tmp___3=0, t1_i=1, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@10cc421f=0, T7_E=2, tmp=1, t2_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@561e6ece=0, t4_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@52d291eb=0, t4_pc=0, E_5=2, \result=0, E_1=2, tmp_ndt_2=0, \result=0, __retres1=0, tmp_ndt_6=0, tmp___0=0, tmp=0, t6_i=1, tmp___4=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@630ac487=0, \result=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@22cdbe16=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3f1621d7=0, tmp___0=0, t1_pc=0, E_4=2, T1_E=2, tmp_ndt_1=0, T5_E=2, t2_i=1, m_i=1, t1_st=0, tmp_ndt_5=0, __retres1=0, t2_pc=0, tmp___1=0, T3_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@615fa09b=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@358546aa=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@f2e1b46=0, \result=1, tmp___5=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7502aba=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@1f272765=0} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 611]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int t4_pc = 0; [L20] int t5_pc = 0; [L21] int t6_pc = 0; [L22] int t7_pc = 0; [L23] int m_st ; [L24] int t1_st ; [L25] int t2_st ; [L26] int t3_st ; [L27] int t4_st ; [L28] int t5_st ; [L29] int t6_st ; [L30] int t7_st ; [L31] int m_i ; [L32] int t1_i ; [L33] int t2_i ; [L34] int t3_i ; [L35] int t4_i ; [L36] int t5_i ; [L37] int t6_i ; [L38] int t7_i ; [L39] int M_E = 2; [L40] int T1_E = 2; [L41] int T2_E = 2; [L42] int T3_E = 2; [L43] int T4_E = 2; [L44] int T5_E = 2; [L45] int T6_E = 2; [L46] int T7_E = 2; [L47] int E_1 = 2; [L48] int E_2 = 2; [L49] int E_3 = 2; [L50] int E_4 = 2; [L51] int E_5 = 2; [L52] int E_6 = 2; [L53] int E_7 = 2; [L1183] int __retres1 ; [L1187] CALL init_model() [L1092] m_i = 1 [L1093] t1_i = 1 [L1094] t2_i = 1 [L1095] t3_i = 1 [L1096] t4_i = 1 [L1097] t5_i = 1 [L1098] t6_i = 1 [L1099] RET t7_i = 1 [L1187] init_model() [L1188] CALL start_simulation() [L1124] int kernel_st ; [L1125] int tmp ; [L1126] int tmp___0 ; [L1130] kernel_st = 0 [L1131] FCALL update_channels() [L1132] CALL init_threads() [L511] COND TRUE m_i == 1 [L512] m_st = 0 [L516] COND TRUE t1_i == 1 [L517] t1_st = 0 [L521] COND TRUE t2_i == 1 [L522] t2_st = 0 [L526] COND TRUE t3_i == 1 [L527] t3_st = 0 [L531] COND TRUE t4_i == 1 [L532] t4_st = 0 [L536] COND TRUE t5_i == 1 [L537] t5_st = 0 [L541] COND TRUE t6_i == 1 [L542] t6_st = 0 [L546] COND TRUE t7_i == 1 [L547] RET t7_st = 0 [L1132] init_threads() [L1133] CALL fire_delta_events() [L744] COND FALSE !(M_E == 0) [L749] COND FALSE !(T1_E == 0) [L754] COND FALSE !(T2_E == 0) [L759] COND FALSE !(T3_E == 0) [L764] COND FALSE !(T4_E == 0) [L769] COND FALSE !(T5_E == 0) [L774] COND FALSE !(T6_E == 0) [L779] COND FALSE !(T7_E == 0) [L784] COND FALSE !(E_1 == 0) [L789] COND FALSE !(E_2 == 0) [L794] COND FALSE !(E_3 == 0) [L799] COND FALSE !(E_4 == 0) [L804] COND FALSE !(E_5 == 0) [L809] COND FALSE !(E_6 == 0) [L814] COND FALSE, RET !(E_7 == 0) [L1133] fire_delta_events() [L1134] CALL activate_threads() [L907] int tmp ; [L908] int tmp___0 ; [L909] int tmp___1 ; [L910] int tmp___2 ; [L911] int tmp___3 ; [L912] int tmp___4 ; [L913] int tmp___5 ; [L914] int tmp___6 ; [L918] CALL, EXPR is_master_triggered() [L348] int __retres1 ; [L351] COND FALSE !(m_pc == 1) [L361] __retres1 = 0 [L363] RET return (__retres1); [L918] EXPR is_master_triggered() [L918] tmp = is_master_triggered() [L920] COND FALSE !(\read(tmp)) [L926] CALL, EXPR is_transmit1_triggered() [L367] int __retres1 ; [L370] COND FALSE !(t1_pc == 1) [L380] __retres1 = 0 [L382] RET return (__retres1); [L926] EXPR is_transmit1_triggered() [L926] tmp___0 = is_transmit1_triggered() [L928] COND FALSE !(\read(tmp___0)) [L934] CALL, EXPR is_transmit2_triggered() [L386] int __retres1 ; [L389] COND FALSE !(t2_pc == 1) [L399] __retres1 = 0 [L401] RET return (__retres1); [L934] EXPR is_transmit2_triggered() [L934] tmp___1 = is_transmit2_triggered() [L936] COND FALSE !(\read(tmp___1)) [L942] CALL, EXPR is_transmit3_triggered() [L405] int __retres1 ; [L408] COND FALSE !(t3_pc == 1) [L418] __retres1 = 0 [L420] RET return (__retres1); [L942] EXPR is_transmit3_triggered() [L942] tmp___2 = is_transmit3_triggered() [L944] COND FALSE !(\read(tmp___2)) [L950] CALL, EXPR is_transmit4_triggered() [L424] int __retres1 ; [L427] COND FALSE !(t4_pc == 1) [L437] __retres1 = 0 [L439] RET return (__retres1); [L950] EXPR is_transmit4_triggered() [L950] tmp___3 = is_transmit4_triggered() [L952] COND FALSE !(\read(tmp___3)) [L958] CALL, EXPR is_transmit5_triggered() [L443] int __retres1 ; [L446] COND FALSE !(t5_pc == 1) [L456] __retres1 = 0 [L458] RET return (__retres1); [L958] EXPR is_transmit5_triggered() [L958] tmp___4 = is_transmit5_triggered() [L960] COND FALSE !(\read(tmp___4)) [L966] CALL, EXPR is_transmit6_triggered() [L462] int __retres1 ; [L465] COND FALSE !(t6_pc == 1) [L475] __retres1 = 0 [L477] RET return (__retres1); [L966] EXPR is_transmit6_triggered() [L966] tmp___5 = is_transmit6_triggered() [L968] COND FALSE !(\read(tmp___5)) [L974] CALL, EXPR is_transmit7_triggered() [L481] int __retres1 ; [L484] COND FALSE !(t7_pc == 1) [L494] __retres1 = 0 [L496] RET return (__retres1); [L974] EXPR is_transmit7_triggered() [L974] tmp___6 = is_transmit7_triggered() [L976] COND FALSE, RET !(\read(tmp___6)) [L1134] activate_threads() [L1135] CALL reset_delta_events() [L827] COND FALSE !(M_E == 1) [L832] COND FALSE !(T1_E == 1) [L837] COND FALSE !(T2_E == 1) [L842] COND FALSE !(T3_E == 1) [L847] COND FALSE !(T4_E == 1) [L852] COND FALSE !(T5_E == 1) [L857] COND FALSE !(T6_E == 1) [L862] COND FALSE !(T7_E == 1) [L867] COND FALSE !(E_1 == 1) [L872] COND FALSE !(E_2 == 1) [L877] COND FALSE !(E_3 == 1) [L882] COND FALSE !(E_4 == 1) [L887] COND FALSE !(E_5 == 1) [L892] COND FALSE !(E_6 == 1) [L897] COND FALSE, RET !(E_7 == 1) [L1135] reset_delta_events() [L1138] COND TRUE 1 [L1141] kernel_st = 1 [L1142] CALL eval() [L607] int tmp ; Loop: [L611] COND TRUE 1 [L614] CALL, EXPR exists_runnable_thread() [L556] int __retres1 ; [L559] COND TRUE m_st == 0 [L560] __retres1 = 1 [L602] RET return (__retres1); [L614] EXPR exists_runnable_thread() [L614] tmp = exists_runnable_thread() [L616] COND TRUE \read(tmp) [L621] COND TRUE m_st == 0 [L622] int tmp_ndt_1; [L623] tmp_ndt_1 = __VERIFIER_nondet_int() [L624] COND FALSE !(\read(tmp_ndt_1)) [L635] COND TRUE t1_st == 0 [L636] int tmp_ndt_2; [L637] tmp_ndt_2 = __VERIFIER_nondet_int() [L638] COND FALSE !(\read(tmp_ndt_2)) [L649] COND TRUE t2_st == 0 [L650] int tmp_ndt_3; [L651] tmp_ndt_3 = __VERIFIER_nondet_int() [L652] COND FALSE !(\read(tmp_ndt_3)) [L663] COND TRUE t3_st == 0 [L664] int tmp_ndt_4; [L665] tmp_ndt_4 = __VERIFIER_nondet_int() [L666] COND FALSE !(\read(tmp_ndt_4)) [L677] COND TRUE t4_st == 0 [L678] int tmp_ndt_5; [L679] tmp_ndt_5 = __VERIFIER_nondet_int() [L680] COND FALSE !(\read(tmp_ndt_5)) [L691] COND TRUE t5_st == 0 [L692] int tmp_ndt_6; [L693] tmp_ndt_6 = __VERIFIER_nondet_int() [L694] COND FALSE !(\read(tmp_ndt_6)) [L705] COND TRUE t6_st == 0 [L706] int tmp_ndt_7; [L707] tmp_ndt_7 = __VERIFIER_nondet_int() [L708] COND FALSE !(\read(tmp_ndt_7)) [L719] COND TRUE t7_st == 0 [L720] int tmp_ndt_8; [L721] tmp_ndt_8 = __VERIFIER_nondet_int() [L722] COND FALSE !(\read(tmp_ndt_8)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...