./Ultimate.py --spec ../../sv-benchmarks/c/Termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.08_false-unreach-call_false-termination.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 5842f4b8 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_a1d43ee8-d7c4-46fe-b4be-e0cabd484ca0/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_a1d43ee8-d7c4-46fe-b4be-e0cabd484ca0/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_a1d43ee8-d7c4-46fe-b4be-e0cabd484ca0/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_a1d43ee8-d7c4-46fe-b4be-e0cabd484ca0/bin-2019/uautomizer/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.08_false-unreach-call_false-termination.cil.c -s /tmp/vcloud-vcloud-master/worker/working_dir_a1d43ee8-d7c4-46fe-b4be-e0cabd484ca0/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_a1d43ee8-d7c4-46fe-b4be-e0cabd484ca0/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 0273045f436e57bbaf687c13388f6f87c9f85e85 ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM) --- Real Ultimate output --- This is Ultimate 0.1.23-5842f4b [2018-11-18 14:32:27,295 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-18 14:32:27,296 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-18 14:32:27,304 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-18 14:32:27,304 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-18 14:32:27,305 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-18 14:32:27,305 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-18 14:32:27,307 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-18 14:32:27,308 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-18 14:32:27,309 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-18 14:32:27,309 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-18 14:32:27,309 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-18 14:32:27,310 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-18 14:32:27,311 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-18 14:32:27,311 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-18 14:32:27,312 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-18 14:32:27,313 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-18 14:32:27,314 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-18 14:32:27,316 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-18 14:32:27,317 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-18 14:32:27,318 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-18 14:32:27,319 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-18 14:32:27,320 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-18 14:32:27,321 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-18 14:32:27,321 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-18 14:32:27,321 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-18 14:32:27,322 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-18 14:32:27,323 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-18 14:32:27,323 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-18 14:32:27,324 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-18 14:32:27,324 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-18 14:32:27,324 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-18 14:32:27,324 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-18 14:32:27,325 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-18 14:32:27,325 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-18 14:32:27,325 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-18 14:32:27,326 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_a1d43ee8-d7c4-46fe-b4be-e0cabd484ca0/bin-2019/uautomizer/config/svcomp-Termination-32bit-Automizer_Default.epf [2018-11-18 14:32:27,336 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-18 14:32:27,336 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-18 14:32:27,337 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-18 14:32:27,337 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-18 14:32:27,337 INFO L133 SettingsManager]: * Use SBE=true [2018-11-18 14:32:27,337 INFO L131 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2018-11-18 14:32:27,338 INFO L133 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2018-11-18 14:32:27,338 INFO L133 SettingsManager]: * Use old map elimination=false [2018-11-18 14:32:27,338 INFO L133 SettingsManager]: * Use external solver (rank synthesis)=false [2018-11-18 14:32:27,338 INFO L133 SettingsManager]: * Use only trivial implications for array writes=true [2018-11-18 14:32:27,338 INFO L133 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2018-11-18 14:32:27,338 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-18 14:32:27,338 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-18 14:32:27,338 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-11-18 14:32:27,339 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-18 14:32:27,339 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-18 14:32:27,339 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-18 14:32:27,339 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2018-11-18 14:32:27,339 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2018-11-18 14:32:27,339 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2018-11-18 14:32:27,341 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-18 14:32:27,341 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-18 14:32:27,341 INFO L133 SettingsManager]: * Assume nondeterminstic values are in range=false [2018-11-18 14:32:27,341 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-18 14:32:27,341 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2018-11-18 14:32:27,342 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-18 14:32:27,342 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-18 14:32:27,342 INFO L133 SettingsManager]: * To the following directory=/home/matthias/ultimate/dump [2018-11-18 14:32:27,342 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-18 14:32:27,342 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-18 14:32:27,342 INFO L133 SettingsManager]: * Dump automata to the following directory=/home/matthias/ultimate/dump/auto [2018-11-18 14:32:27,343 INFO L131 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2018-11-18 14:32:27,343 INFO L133 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_a1d43ee8-d7c4-46fe-b4be-e0cabd484ca0/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 0273045f436e57bbaf687c13388f6f87c9f85e85 [2018-11-18 14:32:27,367 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-18 14:32:27,376 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-18 14:32:27,378 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-18 14:32:27,380 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-18 14:32:27,380 INFO L276 PluginConnector]: CDTParser initialized [2018-11-18 14:32:27,380 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_a1d43ee8-d7c4-46fe-b4be-e0cabd484ca0/bin-2019/uautomizer/../../sv-benchmarks/c/systemc/transmitter.08_false-unreach-call_false-termination.cil.c [2018-11-18 14:32:27,422 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_a1d43ee8-d7c4-46fe-b4be-e0cabd484ca0/bin-2019/uautomizer/data/4f6bd23f7/e438470a0ccf45ddb9578596c361fe24/FLAG142fa0d71 [2018-11-18 14:32:27,751 INFO L307 CDTParser]: Found 1 translation units. [2018-11-18 14:32:27,752 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_a1d43ee8-d7c4-46fe-b4be-e0cabd484ca0/sv-benchmarks/c/systemc/transmitter.08_false-unreach-call_false-termination.cil.c [2018-11-18 14:32:27,760 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_a1d43ee8-d7c4-46fe-b4be-e0cabd484ca0/bin-2019/uautomizer/data/4f6bd23f7/e438470a0ccf45ddb9578596c361fe24/FLAG142fa0d71 [2018-11-18 14:32:27,770 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_a1d43ee8-d7c4-46fe-b4be-e0cabd484ca0/bin-2019/uautomizer/data/4f6bd23f7/e438470a0ccf45ddb9578596c361fe24 [2018-11-18 14:32:27,773 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-18 14:32:27,774 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-18 14:32:27,775 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-18 14:32:27,775 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-18 14:32:27,777 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-18 14:32:27,778 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 02:32:27" (1/1) ... [2018-11-18 14:32:27,779 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@44c74022 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 02:32:27, skipping insertion in model container [2018-11-18 14:32:27,779 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 18.11 02:32:27" (1/1) ... [2018-11-18 14:32:27,786 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-18 14:32:27,815 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-18 14:32:27,988 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 14:32:27,994 INFO L191 MainTranslator]: Completed pre-run [2018-11-18 14:32:28,042 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-18 14:32:28,060 INFO L195 MainTranslator]: Completed translation [2018-11-18 14:32:28,061 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 02:32:28 WrapperNode [2018-11-18 14:32:28,061 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-18 14:32:28,062 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-18 14:32:28,062 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-18 14:32:28,062 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-18 14:32:28,104 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 02:32:28" (1/1) ... [2018-11-18 14:32:28,112 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 02:32:28" (1/1) ... [2018-11-18 14:32:28,158 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-18 14:32:28,159 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-18 14:32:28,159 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-18 14:32:28,159 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-18 14:32:28,167 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 02:32:28" (1/1) ... [2018-11-18 14:32:28,167 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 02:32:28" (1/1) ... [2018-11-18 14:32:28,172 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 02:32:28" (1/1) ... [2018-11-18 14:32:28,172 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 02:32:28" (1/1) ... [2018-11-18 14:32:28,187 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 02:32:28" (1/1) ... [2018-11-18 14:32:28,205 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 02:32:28" (1/1) ... [2018-11-18 14:32:28,209 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 02:32:28" (1/1) ... [2018-11-18 14:32:28,216 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-18 14:32:28,216 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-18 14:32:28,216 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-18 14:32:28,216 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-18 14:32:28,218 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 02:32:28" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a1d43ee8-d7c4-46fe-b4be-e0cabd484ca0/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 14:32:28,265 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-18 14:32:28,266 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-18 14:32:29,439 INFO L278 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-18 14:32:29,440 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 02:32:29 BoogieIcfgContainer [2018-11-18 14:32:29,440 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-18 14:32:29,440 INFO L113 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2018-11-18 14:32:29,441 INFO L271 PluginConnector]: Initializing BuchiAutomizer... [2018-11-18 14:32:29,443 INFO L276 PluginConnector]: BuchiAutomizer initialized [2018-11-18 14:32:29,444 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-18 14:32:29,444 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 18.11 02:32:27" (1/3) ... [2018-11-18 14:32:29,445 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@72d369d7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 18.11 02:32:29, skipping insertion in model container [2018-11-18 14:32:29,446 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-18 14:32:29,446 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 18.11 02:32:28" (2/3) ... [2018-11-18 14:32:29,446 INFO L205 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@72d369d7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 18.11 02:32:29, skipping insertion in model container [2018-11-18 14:32:29,446 INFO L102 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2018-11-18 14:32:29,446 INFO L185 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 02:32:29" (3/3) ... [2018-11-18 14:32:29,448 INFO L375 chiAutomizerObserver]: Analyzing ICFG transmitter.08_false-unreach-call_false-termination.cil.c [2018-11-18 14:32:29,491 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-18 14:32:29,491 INFO L374 BuchiCegarLoop]: Interprodecural is true [2018-11-18 14:32:29,491 INFO L375 BuchiCegarLoop]: Hoare is false [2018-11-18 14:32:29,492 INFO L376 BuchiCegarLoop]: Compute interpolants for ForwardPredicates [2018-11-18 14:32:29,492 INFO L377 BuchiCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-18 14:32:29,492 INFO L378 BuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-18 14:32:29,492 INFO L379 BuchiCegarLoop]: Difference is false [2018-11-18 14:32:29,492 INFO L380 BuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-18 14:32:29,492 INFO L383 BuchiCegarLoop]: ======== Iteration 0==of CEGAR loop == BuchiCegarLoop======== [2018-11-18 14:32:29,519 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 943 states. [2018-11-18 14:32:29,559 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 826 [2018-11-18 14:32:29,559 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:32:29,559 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:32:29,567 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:29,567 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:29,567 INFO L442 BuchiCegarLoop]: ======== Iteration 1============ [2018-11-18 14:32:29,568 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 943 states. [2018-11-18 14:32:29,577 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 826 [2018-11-18 14:32:29,577 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:32:29,577 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:32:29,580 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:29,581 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:29,589 INFO L794 eck$LassoCheckResult]: Stem: 307#ULTIMATE.startENTRYtrue assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 229#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 660#L1225true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 670#L564true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 252#L571true assume !(1 == ~m_i~0);~m_st~0 := 2; 240#L571-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 45#L576-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 893#L581-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 671#L586-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 421#L591-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 120#L596-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 860#L601-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 652#L606-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 527#L611-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 685#L828true assume !(0 == ~M_E~0); 687#L828-2true assume !(0 == ~T1_E~0); 328#L833-1true assume !(0 == ~T2_E~0); 128#L838-1true assume !(0 == ~T3_E~0); 885#L843-1true assume !(0 == ~T4_E~0); 769#L848-1true assume 0 == ~T5_E~0;~T5_E~0 := 1; 537#L853-1true assume !(0 == ~T6_E~0); 315#L858-1true assume !(0 == ~T7_E~0); 6#L863-1true assume !(0 == ~T8_E~0); 730#L868-1true assume !(0 == ~E_1~0); 494#L873-1true assume !(0 == ~E_2~0); 387#L878-1true assume !(0 == ~E_3~0); 206#L883-1true assume !(0 == ~E_4~0); 814#L888-1true assume 0 == ~E_5~0;~E_5~0 := 1; 616#L893-1true assume !(0 == ~E_6~0); 361#L898-1true assume !(0 == ~E_7~0); 296#L903-1true assume !(0 == ~E_8~0); 84#L908-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 343#L392true assume !(1 == ~m_pc~0); 348#L392-2true is_master_triggered_~__retres1~0 := 0; 842#L403true is_master_triggered_#res := is_master_triggered_~__retres1~0; 924#L404true activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 626#L1025true assume !(0 != activate_threads_~tmp~1); 629#L1025-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 483#L411true assume 1 == ~t1_pc~0; 579#L412true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 35#L422true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 106#L423true activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 259#L1033true assume !(0 != activate_threads_~tmp___0~0); 260#L1033-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 641#L430true assume 1 == ~t2_pc~0; 603#L431true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 149#L441true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 121#L442true activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 889#L1041true assume !(0 != activate_threads_~tmp___1~0); 892#L1041-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 899#L449true assume !(1 == ~t3_pc~0); 903#L449-2true is_transmit3_triggered_~__retres1~3 := 0; 370#L460true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 241#L461true activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 656#L1049true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 657#L1049-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 57#L468true assume 1 == ~t4_pc~0; 864#L469true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 535#L479true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 354#L480true activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 302#L1057true assume !(0 != activate_threads_~tmp___3~0); 305#L1057-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 196#L487true assume !(1 == ~t5_pc~0); 198#L487-2true is_transmit5_triggered_~__retres1~5 := 0; 675#L498true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 476#L499true activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 914#L1065true assume !(0 != activate_threads_~tmp___4~0); 915#L1065-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 314#L506true assume 1 == ~t6_pc~0; 166#L507true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 799#L517true is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 654#L518true activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 561#L1073true assume !(0 != activate_threads_~tmp___5~0); 563#L1073-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 423#L525true assume !(1 == ~t7_pc~0); 425#L525-2true is_transmit7_triggered_~__retres1~7 := 0; 940#L536true is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 894#L537true activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 210#L1081true assume !(0 != activate_threads_~tmp___6~0); 211#L1081-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 441#L544true assume 1 == ~t8_pc~0; 530#L545true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 3#L555true is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 73#L556true activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 705#L1089true assume !(0 != activate_threads_~tmp___7~0); 706#L1089-2true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 322#L921true assume !(1 == ~M_E~0); 324#L921-2true assume 1 == ~T1_E~0;~T1_E~0 := 2; 126#L926-1true assume !(1 == ~T2_E~0); 878#L931-1true assume !(1 == ~T3_E~0); 767#L936-1true assume !(1 == ~T4_E~0); 549#L941-1true assume !(1 == ~T5_E~0); 320#L946-1true assume !(1 == ~T6_E~0); 11#L951-1true assume !(1 == ~T7_E~0); 739#L956-1true assume !(1 == ~T8_E~0); 659#L961-1true assume 1 == ~E_1~0;~E_1~0 := 2; 394#L966-1true assume !(1 == ~E_2~0); 214#L971-1true assume !(1 == ~E_3~0); 822#L976-1true assume !(1 == ~E_4~0); 612#L981-1true assume !(1 == ~E_5~0); 359#L986-1true assume !(1 == ~E_6~0); 291#L991-1true assume !(1 == ~E_7~0); 77#L996-1true assume !(1 == ~E_8~0); 809#L1001-1true assume { :end_inline_reset_delta_events } true; 833#L1262-3true [2018-11-18 14:32:29,591 INFO L796 eck$LassoCheckResult]: Loop: 833#L1262-3true assume true; 827#L1262-1true assume !false; 936#L1263true start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 803#L803true assume !true; 47#L818true assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 673#L564-1true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 680#L828-3true assume 0 == ~M_E~0;~M_E~0 := 1; 681#L828-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 431#L833-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 123#L838-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 868#L843-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 763#L848-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 542#L853-3true assume !(0 == ~T6_E~0); 317#L858-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 8#L863-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 733#L868-3true assume 0 == ~E_1~0;~E_1~0 := 1; 496#L873-3true assume 0 == ~E_2~0;~E_2~0 := 1; 389#L878-3true assume 0 == ~E_3~0;~E_3~0 := 1; 208#L883-3true assume 0 == ~E_4~0;~E_4~0 := 1; 815#L888-3true assume 0 == ~E_5~0;~E_5~0 := 1; 620#L893-3true assume !(0 == ~E_6~0); 362#L898-3true assume 0 == ~E_7~0;~E_7~0 := 1; 280#L903-3true assume 0 == ~E_8~0;~E_8~0 := 1; 76#L908-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 424#L392-27true assume 1 == ~m_pc~0; 402#L393-9true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 837#L403-9true is_master_triggered_#res := is_master_triggered_~__retres1~0; 922#L404-9true activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 698#L1025-27true assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 688#L1025-29true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 442#L411-27true assume !(1 == ~t1_pc~0); 576#L411-29true is_transmit1_triggered_~__retres1~1 := 0; 14#L422-9true is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 85#L423-9true activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 222#L1033-27true assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 226#L1033-29true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 597#L430-27true assume !(1 == ~t2_pc~0); 599#L430-29true is_transmit2_triggered_~__retres1~2 := 0; 147#L441-9true is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 218#L442-9true activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 835#L1041-27true assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 818#L1041-29true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 727#L449-27true assume !(1 == ~t3_pc~0); 715#L449-29true is_transmit3_triggered_~__retres1~3 := 0; 264#L460-9true is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 221#L461-9true activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 456#L1049-27true assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 459#L1049-29true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 858#L468-27true assume 1 == ~t4_pc~0; 832#L469-9true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 508#L479-9true is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 338#L480-9true activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 146#L1057-27true assume !(0 != activate_threads_~tmp___3~0); 129#L1057-29true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 43#L487-27true assume !(1 == ~t5_pc~0); 44#L487-29true is_transmit5_triggered_~__retres1~5 := 0; 661#L498-9true is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 475#L499-9true activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 743#L1065-27true assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 745#L1065-29true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 289#L506-27true assume !(1 == ~t6_pc~0); 163#L506-29true is_transmit6_triggered_~__retres1~6 := 0; 780#L517-9true is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 634#L518-9true activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 509#L1073-27true assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 364#L1073-29true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 377#L525-27true assume 1 == ~t7_pc~0; 278#L526-9true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 938#L536-9true is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 760#L537-9true activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 178#L1081-27true assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 181#L1081-29true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 546#L544-27true assume 1 == ~t8_pc~0; 504#L545-9true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 99#L555-9true is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 53#L556-9true activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 783#L1089-27true assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 770#L1089-29true assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 327#L921-3true assume 1 == ~M_E~0;~M_E~0 := 2; 430#L921-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 127#L926-3true assume !(1 == ~T2_E~0); 883#L931-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 768#L936-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 555#L941-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 321#L946-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 5#L951-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 729#L956-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 493#L961-3true assume 1 == ~E_1~0;~E_1~0 := 2; 385#L966-3true assume !(1 == ~E_2~0); 205#L971-3true assume 1 == ~E_3~0;~E_3~0 := 2; 813#L976-3true assume 1 == ~E_4~0;~E_4~0 := 2; 615#L981-3true assume 1 == ~E_5~0;~E_5~0 := 2; 360#L986-3true assume 1 == ~E_6~0;~E_6~0 := 2; 294#L991-3true assume 1 == ~E_7~0;~E_7~0 := 2; 81#L996-3true assume 1 == ~E_8~0;~E_8~0 := 2; 812#L1001-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 945#L624-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 796#L671-1true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 766#L672-1true start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 23#L1281true assume !(0 == start_simulation_~tmp~3); 28#L1281-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 939#L624-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 797#L671-2true exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 650#L672-2true stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 176#L1236true assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 711#L1243true stop_simulation_#res := stop_simulation_~__retres2~0; 781#L1244true start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 502#L1294true assume !(0 != start_simulation_~tmp___0~1); 833#L1262-3true [2018-11-18 14:32:29,597 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:29,597 INFO L82 PathProgramCache]: Analyzing trace with hash -1897256038, now seen corresponding path program 1 times [2018-11-18 14:32:29,599 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:29,600 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:29,635 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:29,635 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:29,636 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:29,667 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:29,744 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:29,747 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:29,747 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:32:29,751 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 14:32:29,752 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:29,752 INFO L82 PathProgramCache]: Analyzing trace with hash 304939143, now seen corresponding path program 1 times [2018-11-18 14:32:29,752 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:29,752 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:29,753 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:29,753 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:29,754 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:29,760 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:29,781 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:29,781 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:29,781 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 14:32:29,783 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 14:32:29,797 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 14:32:29,797 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 14:32:29,799 INFO L87 Difference]: Start difference. First operand 943 states. Second operand 3 states. [2018-11-18 14:32:29,850 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:32:29,850 INFO L93 Difference]: Finished difference Result 942 states and 1397 transitions. [2018-11-18 14:32:29,851 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 14:32:29,852 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 942 states and 1397 transitions. [2018-11-18 14:32:29,858 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 823 [2018-11-18 14:32:29,866 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 942 states to 936 states and 1391 transitions. [2018-11-18 14:32:29,867 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 936 [2018-11-18 14:32:29,869 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 936 [2018-11-18 14:32:29,869 INFO L73 IsDeterministic]: Start isDeterministic. Operand 936 states and 1391 transitions. [2018-11-18 14:32:29,873 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:32:29,873 INFO L705 BuchiCegarLoop]: Abstraction has 936 states and 1391 transitions. [2018-11-18 14:32:29,891 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 936 states and 1391 transitions. [2018-11-18 14:32:29,924 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 936 to 936. [2018-11-18 14:32:29,925 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 936 states. [2018-11-18 14:32:29,928 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 936 states to 936 states and 1391 transitions. [2018-11-18 14:32:29,929 INFO L728 BuchiCegarLoop]: Abstraction has 936 states and 1391 transitions. [2018-11-18 14:32:29,929 INFO L608 BuchiCegarLoop]: Abstraction has 936 states and 1391 transitions. [2018-11-18 14:32:29,929 INFO L442 BuchiCegarLoop]: ======== Iteration 2============ [2018-11-18 14:32:29,929 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 936 states and 1391 transitions. [2018-11-18 14:32:29,932 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 823 [2018-11-18 14:32:29,932 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:32:29,932 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:32:29,934 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:29,935 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:29,935 INFO L794 eck$LassoCheckResult]: Stem: 2356#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 2255#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 2256#L1225 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 2692#L564 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2292#L571 assume 1 == ~m_i~0;~m_st~0 := 0; 2273#L571-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1984#L576-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1985#L581-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2694#L586-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2478#L591-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2101#L596-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2102#L601-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 2686#L606-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 2603#L611-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2604#L828 assume !(0 == ~M_E~0); 2701#L828-2 assume !(0 == ~T1_E~0); 2377#L833-1 assume !(0 == ~T2_E~0); 2116#L838-1 assume !(0 == ~T3_E~0); 2117#L843-1 assume !(0 == ~T4_E~0); 2765#L848-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2612#L853-1 assume !(0 == ~T6_E~0); 2360#L858-1 assume !(0 == ~T7_E~0); 1900#L863-1 assume !(0 == ~T8_E~0); 1901#L868-1 assume !(0 == ~E_1~0); 2566#L873-1 assume !(0 == ~E_2~0); 2451#L878-1 assume !(0 == ~E_3~0); 2226#L883-1 assume !(0 == ~E_4~0); 2227#L888-1 assume 0 == ~E_5~0;~E_5~0 := 1; 2664#L893-1 assume !(0 == ~E_6~0); 2420#L898-1 assume !(0 == ~E_7~0); 2347#L903-1 assume !(0 == ~E_8~0); 2055#L908-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2056#L392 assume !(1 == ~m_pc~0); 2400#L392-2 is_master_triggered_~__retres1~0 := 0; 2406#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2798#L404 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2671#L1025 assume !(0 != activate_threads_~tmp~1); 2672#L1025-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2553#L411 assume 1 == ~t1_pc~0; 2554#L412 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 1966#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1967#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2082#L1033 assume !(0 != activate_threads_~tmp___0~0); 2299#L1033-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2300#L430 assume 1 == ~t2_pc~0; 2650#L431 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2149#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2103#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2104#L1041 assume !(0 != activate_threads_~tmp___1~0); 2816#L1041-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2817#L449 assume !(1 == ~t3_pc~0); 2731#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 2434#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2274#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2275#L1049 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2690#L1049-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2002#L468 assume 1 == ~t4_pc~0; 2003#L469 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2012#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2413#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2352#L1057 assume !(0 != activate_threads_~tmp___3~0); 2353#L1057-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2212#L487 assume !(1 == ~t5_pc~0); 1961#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 1962#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2541#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2542#L1065 assume !(0 != activate_threads_~tmp___4~0); 2829#L1065-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2359#L506 assume 1 == ~t6_pc~0; 2178#L507 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 2179#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2688#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2625#L1073 assume !(0 != activate_threads_~tmp___5~0); 2626#L1073-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 2479#L525 assume !(1 == ~t7_pc~0); 2430#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 2429#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 2818#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2232#L1081 assume !(0 != activate_threads_~tmp___6~0); 2233#L1081-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 2234#L544 assume 1 == ~t8_pc~0; 2491#L545 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 1894#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1895#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2037#L1089 assume !(0 != activate_threads_~tmp___7~0); 2716#L1089-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2367#L921 assume !(1 == ~M_E~0); 2368#L921-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2112#L926-1 assume !(1 == ~T2_E~0); 2113#L931-1 assume !(1 == ~T3_E~0); 2763#L936-1 assume !(1 == ~T4_E~0); 2620#L941-1 assume !(1 == ~T5_E~0); 2365#L946-1 assume !(1 == ~T6_E~0); 1912#L951-1 assume !(1 == ~T7_E~0); 1913#L956-1 assume !(1 == ~T8_E~0); 2691#L961-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2456#L966-1 assume !(1 == ~E_2~0); 2237#L971-1 assume !(1 == ~E_3~0); 2238#L976-1 assume !(1 == ~E_4~0); 2660#L981-1 assume !(1 == ~E_5~0); 2418#L986-1 assume !(1 == ~E_6~0); 2342#L991-1 assume !(1 == ~E_7~0); 2043#L996-1 assume !(1 == ~E_8~0); 2044#L1001-1 assume { :end_inline_reset_delta_events } true; 2576#L1262-3 [2018-11-18 14:32:29,936 INFO L796 eck$LassoCheckResult]: Loop: 2576#L1262-3 assume true; 2785#L1262-1 assume !false; 2786#L1263 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 2379#L803 assume true; 2288#L681-1 assume !false; 2289#L682 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 2363#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 2029#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 2761#L672 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 1978#L686 assume !(0 != eval_~tmp~0); 1980#L818 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 1986#L564-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 2696#L828-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2697#L828-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2482#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2108#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2109#L843-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2759#L848-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2616#L853-3 assume !(0 == ~T6_E~0); 2362#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1905#L863-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1906#L868-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2567#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2452#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2229#L883-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2230#L888-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2668#L893-3 assume !(0 == ~E_6~0); 2421#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2333#L903-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2041#L908-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2042#L392-27 assume 1 == ~m_pc~0; 2466#L393-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 2467#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2796#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2709#L1025-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2703#L1025-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2493#L411-27 assume !(1 == ~t1_pc~0); 2494#L411-29 is_transmit1_triggered_~__retres1~1 := 0; 1919#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1920#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2057#L1033-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 2248#L1033-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2253#L430-27 assume 1 == ~t2_pc~0; 2644#L431-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 2145#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2146#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2242#L1041-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 2778#L1041-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2740#L449-27 assume 1 == ~t3_pc~0; 2710#L450-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2305#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2246#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2247#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2513#L1049-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2518#L468-27 assume 1 == ~t4_pc~0; 2791#L469-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 2583#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2395#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2144#L1057-27 assume !(0 != activate_threads_~tmp___3~0); 2118#L1057-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1983#L487-27 assume 1 == ~t5_pc~0; 1956#L488-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 1957#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2539#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2540#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 2746#L1065-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2341#L506-27 assume 1 == ~t6_pc~0; 2136#L507-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 2138#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2674#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2584#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 2423#L1073-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 2424#L525-27 assume 1 == ~t7_pc~0; 2328#L526-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 2329#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 2757#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2191#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 2192#L1081-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 2195#L544-27 assume 1 == ~t8_pc~0; 2578#L545-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 2075#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1994#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1995#L1089-27 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 2766#L1089-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2375#L921-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2376#L921-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2114#L926-3 assume !(1 == ~T2_E~0); 2115#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2764#L936-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2622#L941-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2366#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1898#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1899#L956-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2565#L961-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2449#L966-3 assume !(1 == ~E_2~0); 2224#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2225#L976-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2663#L981-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2419#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2346#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2050#L996-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2051#L1001-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 2777#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 2032#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 2762#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 1940#L1281 assume !(0 == start_simulation_~tmp~3); 1941#L1281-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1953#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 2035#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 2684#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 2188#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2189#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 2724#L1244 start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 2575#L1294 assume !(0 != start_simulation_~tmp___0~1); 2576#L1262-3 [2018-11-18 14:32:29,936 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:29,937 INFO L82 PathProgramCache]: Analyzing trace with hash 500214492, now seen corresponding path program 1 times [2018-11-18 14:32:29,937 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:29,937 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:29,938 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:29,938 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:29,946 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:29,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:29,986 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:29,987 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:29,987 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:32:29,987 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 14:32:29,988 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:29,988 INFO L82 PathProgramCache]: Analyzing trace with hash 1409879850, now seen corresponding path program 1 times [2018-11-18 14:32:29,988 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:29,988 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:29,989 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:29,989 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:29,989 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:30,010 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:30,088 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:30,088 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:30,088 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:32:30,089 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 14:32:30,089 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 14:32:30,089 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 14:32:30,089 INFO L87 Difference]: Start difference. First operand 936 states and 1391 transitions. cyclomatic complexity: 456 Second operand 3 states. [2018-11-18 14:32:30,108 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:32:30,108 INFO L93 Difference]: Finished difference Result 936 states and 1390 transitions. [2018-11-18 14:32:30,110 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 14:32:30,110 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 936 states and 1390 transitions. [2018-11-18 14:32:30,134 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 823 [2018-11-18 14:32:30,136 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 936 states to 936 states and 1390 transitions. [2018-11-18 14:32:30,137 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 936 [2018-11-18 14:32:30,137 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 936 [2018-11-18 14:32:30,138 INFO L73 IsDeterministic]: Start isDeterministic. Operand 936 states and 1390 transitions. [2018-11-18 14:32:30,139 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:32:30,139 INFO L705 BuchiCegarLoop]: Abstraction has 936 states and 1390 transitions. [2018-11-18 14:32:30,140 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 936 states and 1390 transitions. [2018-11-18 14:32:30,150 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 936 to 936. [2018-11-18 14:32:30,150 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 936 states. [2018-11-18 14:32:30,152 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 936 states to 936 states and 1390 transitions. [2018-11-18 14:32:30,152 INFO L728 BuchiCegarLoop]: Abstraction has 936 states and 1390 transitions. [2018-11-18 14:32:30,152 INFO L608 BuchiCegarLoop]: Abstraction has 936 states and 1390 transitions. [2018-11-18 14:32:30,152 INFO L442 BuchiCegarLoop]: ======== Iteration 3============ [2018-11-18 14:32:30,153 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 936 states and 1390 transitions. [2018-11-18 14:32:30,155 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 823 [2018-11-18 14:32:30,155 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:32:30,155 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:32:30,157 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:30,157 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:30,158 INFO L794 eck$LassoCheckResult]: Stem: 4235#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 4134#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 4135#L1225 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 4571#L564 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4171#L571 assume 1 == ~m_i~0;~m_st~0 := 0; 4152#L571-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3863#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3864#L581-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4573#L586-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4357#L591-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3980#L596-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3981#L601-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4565#L606-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4482#L611-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4483#L828 assume !(0 == ~M_E~0); 4580#L828-2 assume !(0 == ~T1_E~0); 4256#L833-1 assume !(0 == ~T2_E~0); 3995#L838-1 assume !(0 == ~T3_E~0); 3996#L843-1 assume !(0 == ~T4_E~0); 4644#L848-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4491#L853-1 assume !(0 == ~T6_E~0); 4239#L858-1 assume !(0 == ~T7_E~0); 3779#L863-1 assume !(0 == ~T8_E~0); 3780#L868-1 assume !(0 == ~E_1~0); 4445#L873-1 assume !(0 == ~E_2~0); 4330#L878-1 assume !(0 == ~E_3~0); 4105#L883-1 assume !(0 == ~E_4~0); 4106#L888-1 assume 0 == ~E_5~0;~E_5~0 := 1; 4543#L893-1 assume !(0 == ~E_6~0); 4299#L898-1 assume !(0 == ~E_7~0); 4226#L903-1 assume !(0 == ~E_8~0); 3934#L908-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3935#L392 assume !(1 == ~m_pc~0); 4279#L392-2 is_master_triggered_~__retres1~0 := 0; 4285#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4677#L404 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 4550#L1025 assume !(0 != activate_threads_~tmp~1); 4551#L1025-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4432#L411 assume 1 == ~t1_pc~0; 4433#L412 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 3845#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3846#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3961#L1033 assume !(0 != activate_threads_~tmp___0~0); 4178#L1033-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4179#L430 assume 1 == ~t2_pc~0; 4529#L431 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4028#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3982#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3983#L1041 assume !(0 != activate_threads_~tmp___1~0); 4695#L1041-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4696#L449 assume !(1 == ~t3_pc~0); 4610#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 4313#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4153#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4154#L1049 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 4569#L1049-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3881#L468 assume 1 == ~t4_pc~0; 3882#L469 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 3891#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4292#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4231#L1057 assume !(0 != activate_threads_~tmp___3~0); 4232#L1057-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4091#L487 assume !(1 == ~t5_pc~0); 3840#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 3841#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4420#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4421#L1065 assume !(0 != activate_threads_~tmp___4~0); 4708#L1065-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 4238#L506 assume 1 == ~t6_pc~0; 4057#L507 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 4058#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 4567#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4504#L1073 assume !(0 != activate_threads_~tmp___5~0); 4505#L1073-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 4358#L525 assume !(1 == ~t7_pc~0); 4309#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 4308#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 4697#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4111#L1081 assume !(0 != activate_threads_~tmp___6~0); 4112#L1081-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 4113#L544 assume 1 == ~t8_pc~0; 4370#L545 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 3773#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 3774#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 3916#L1089 assume !(0 != activate_threads_~tmp___7~0); 4595#L1089-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4246#L921 assume !(1 == ~M_E~0); 4247#L921-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3991#L926-1 assume !(1 == ~T2_E~0); 3992#L931-1 assume !(1 == ~T3_E~0); 4642#L936-1 assume !(1 == ~T4_E~0); 4499#L941-1 assume !(1 == ~T5_E~0); 4244#L946-1 assume !(1 == ~T6_E~0); 3791#L951-1 assume !(1 == ~T7_E~0); 3792#L956-1 assume !(1 == ~T8_E~0); 4570#L961-1 assume 1 == ~E_1~0;~E_1~0 := 2; 4335#L966-1 assume !(1 == ~E_2~0); 4116#L971-1 assume !(1 == ~E_3~0); 4117#L976-1 assume !(1 == ~E_4~0); 4539#L981-1 assume !(1 == ~E_5~0); 4297#L986-1 assume !(1 == ~E_6~0); 4221#L991-1 assume !(1 == ~E_7~0); 3922#L996-1 assume !(1 == ~E_8~0); 3923#L1001-1 assume { :end_inline_reset_delta_events } true; 4455#L1262-3 [2018-11-18 14:32:30,158 INFO L796 eck$LassoCheckResult]: Loop: 4455#L1262-3 assume true; 4664#L1262-1 assume !false; 4665#L1263 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 4258#L803 assume true; 4167#L681-1 assume !false; 4168#L682 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 4242#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 3908#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 4640#L672 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 3857#L686 assume !(0 != eval_~tmp~0); 3859#L818 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 3865#L564-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 4575#L828-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4576#L828-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4361#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3987#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3988#L843-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4638#L848-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4495#L853-3 assume !(0 == ~T6_E~0); 4241#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3784#L863-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 3785#L868-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4446#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4331#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4108#L883-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4109#L888-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4547#L893-3 assume !(0 == ~E_6~0); 4300#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4212#L903-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3920#L908-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3921#L392-27 assume 1 == ~m_pc~0; 4345#L393-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 4346#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4675#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 4588#L1025-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 4582#L1025-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4372#L411-27 assume !(1 == ~t1_pc~0); 4373#L411-29 is_transmit1_triggered_~__retres1~1 := 0; 3798#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3799#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3936#L1033-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 4127#L1033-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4132#L430-27 assume 1 == ~t2_pc~0; 4523#L431-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 4024#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4025#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4121#L1041-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 4657#L1041-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4619#L449-27 assume 1 == ~t3_pc~0; 4589#L450-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 4184#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4125#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4126#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 4392#L1049-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4397#L468-27 assume 1 == ~t4_pc~0; 4670#L469-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 4462#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4274#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4023#L1057-27 assume !(0 != activate_threads_~tmp___3~0); 3997#L1057-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3862#L487-27 assume 1 == ~t5_pc~0; 3835#L488-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 3836#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4418#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4419#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 4625#L1065-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 4220#L506-27 assume !(1 == ~t6_pc~0); 4016#L506-29 is_transmit6_triggered_~__retres1~6 := 0; 4017#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 4553#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4463#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 4302#L1073-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 4303#L525-27 assume !(1 == ~t7_pc~0); 4209#L525-29 is_transmit7_triggered_~__retres1~7 := 0; 4208#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 4636#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4070#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 4071#L1081-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 4074#L544-27 assume 1 == ~t8_pc~0; 4457#L545-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 3954#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 3873#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 3874#L1089-27 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 4645#L1089-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4254#L921-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4255#L921-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3993#L926-3 assume !(1 == ~T2_E~0); 3994#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4643#L936-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4501#L941-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4245#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3777#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3778#L956-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4444#L961-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4328#L966-3 assume !(1 == ~E_2~0); 4103#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4104#L976-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4542#L981-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4298#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4225#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3929#L996-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3930#L1001-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 4656#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 3911#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 4641#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 3819#L1281 assume !(0 == start_simulation_~tmp~3); 3820#L1281-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 3832#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 3914#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 4563#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 4067#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 4068#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 4603#L1244 start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 4454#L1294 assume !(0 != start_simulation_~tmp___0~1); 4455#L1262-3 [2018-11-18 14:32:30,159 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:30,159 INFO L82 PathProgramCache]: Analyzing trace with hash -1888349538, now seen corresponding path program 1 times [2018-11-18 14:32:30,159 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:30,159 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:30,160 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:30,160 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:30,161 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:30,167 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:30,200 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:30,201 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:30,201 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:32:30,201 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 14:32:30,201 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:30,201 INFO L82 PathProgramCache]: Analyzing trace with hash 687200168, now seen corresponding path program 1 times [2018-11-18 14:32:30,202 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:30,202 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:30,202 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:30,202 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:30,203 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:30,214 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:30,251 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:30,251 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:30,251 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:32:30,251 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 14:32:30,251 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 14:32:30,251 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 14:32:30,252 INFO L87 Difference]: Start difference. First operand 936 states and 1390 transitions. cyclomatic complexity: 455 Second operand 3 states. [2018-11-18 14:32:30,266 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:32:30,266 INFO L93 Difference]: Finished difference Result 936 states and 1389 transitions. [2018-11-18 14:32:30,267 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 14:32:30,267 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 936 states and 1389 transitions. [2018-11-18 14:32:30,270 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 823 [2018-11-18 14:32:30,273 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 936 states to 936 states and 1389 transitions. [2018-11-18 14:32:30,273 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 936 [2018-11-18 14:32:30,273 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 936 [2018-11-18 14:32:30,274 INFO L73 IsDeterministic]: Start isDeterministic. Operand 936 states and 1389 transitions. [2018-11-18 14:32:30,275 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:32:30,275 INFO L705 BuchiCegarLoop]: Abstraction has 936 states and 1389 transitions. [2018-11-18 14:32:30,276 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 936 states and 1389 transitions. [2018-11-18 14:32:30,282 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 936 to 936. [2018-11-18 14:32:30,283 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 936 states. [2018-11-18 14:32:30,284 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 936 states to 936 states and 1389 transitions. [2018-11-18 14:32:30,284 INFO L728 BuchiCegarLoop]: Abstraction has 936 states and 1389 transitions. [2018-11-18 14:32:30,284 INFO L608 BuchiCegarLoop]: Abstraction has 936 states and 1389 transitions. [2018-11-18 14:32:30,284 INFO L442 BuchiCegarLoop]: ======== Iteration 4============ [2018-11-18 14:32:30,284 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 936 states and 1389 transitions. [2018-11-18 14:32:30,287 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 823 [2018-11-18 14:32:30,287 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:32:30,287 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:32:30,288 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:30,289 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:30,289 INFO L794 eck$LassoCheckResult]: Stem: 6114#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 6013#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 6014#L1225 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 6450#L564 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6050#L571 assume 1 == ~m_i~0;~m_st~0 := 0; 6031#L571-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5742#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5743#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6452#L586-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 6236#L591-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5859#L596-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5860#L601-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6444#L606-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6361#L611-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6362#L828 assume !(0 == ~M_E~0); 6459#L828-2 assume !(0 == ~T1_E~0); 6135#L833-1 assume !(0 == ~T2_E~0); 5874#L838-1 assume !(0 == ~T3_E~0); 5875#L843-1 assume !(0 == ~T4_E~0); 6523#L848-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6370#L853-1 assume !(0 == ~T6_E~0); 6118#L858-1 assume !(0 == ~T7_E~0); 5658#L863-1 assume !(0 == ~T8_E~0); 5659#L868-1 assume !(0 == ~E_1~0); 6324#L873-1 assume !(0 == ~E_2~0); 6209#L878-1 assume !(0 == ~E_3~0); 5984#L883-1 assume !(0 == ~E_4~0); 5985#L888-1 assume 0 == ~E_5~0;~E_5~0 := 1; 6422#L893-1 assume !(0 == ~E_6~0); 6178#L898-1 assume !(0 == ~E_7~0); 6105#L903-1 assume !(0 == ~E_8~0); 5813#L908-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5814#L392 assume !(1 == ~m_pc~0); 6158#L392-2 is_master_triggered_~__retres1~0 := 0; 6164#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6556#L404 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 6429#L1025 assume !(0 != activate_threads_~tmp~1); 6430#L1025-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6311#L411 assume 1 == ~t1_pc~0; 6312#L412 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 5724#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5725#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 5840#L1033 assume !(0 != activate_threads_~tmp___0~0); 6057#L1033-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6058#L430 assume 1 == ~t2_pc~0; 6408#L431 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5907#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5861#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 5862#L1041 assume !(0 != activate_threads_~tmp___1~0); 6574#L1041-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6575#L449 assume !(1 == ~t3_pc~0); 6489#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 6192#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6032#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 6033#L1049 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 6448#L1049-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 5760#L468 assume 1 == ~t4_pc~0; 5761#L469 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 5770#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6171#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 6110#L1057 assume !(0 != activate_threads_~tmp___3~0); 6111#L1057-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5970#L487 assume !(1 == ~t5_pc~0); 5719#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 5720#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 6299#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 6300#L1065 assume !(0 != activate_threads_~tmp___4~0); 6587#L1065-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 6117#L506 assume 1 == ~t6_pc~0; 5936#L507 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 5937#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 6446#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 6383#L1073 assume !(0 != activate_threads_~tmp___5~0); 6384#L1073-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 6237#L525 assume !(1 == ~t7_pc~0); 6188#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 6187#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 6576#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5990#L1081 assume !(0 != activate_threads_~tmp___6~0); 5991#L1081-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 5992#L544 assume 1 == ~t8_pc~0; 6249#L545 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 5652#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 5653#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 5795#L1089 assume !(0 != activate_threads_~tmp___7~0); 6474#L1089-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6125#L921 assume !(1 == ~M_E~0); 6126#L921-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5870#L926-1 assume !(1 == ~T2_E~0); 5871#L931-1 assume !(1 == ~T3_E~0); 6521#L936-1 assume !(1 == ~T4_E~0); 6378#L941-1 assume !(1 == ~T5_E~0); 6123#L946-1 assume !(1 == ~T6_E~0); 5670#L951-1 assume !(1 == ~T7_E~0); 5671#L956-1 assume !(1 == ~T8_E~0); 6449#L961-1 assume 1 == ~E_1~0;~E_1~0 := 2; 6214#L966-1 assume !(1 == ~E_2~0); 5995#L971-1 assume !(1 == ~E_3~0); 5996#L976-1 assume !(1 == ~E_4~0); 6418#L981-1 assume !(1 == ~E_5~0); 6176#L986-1 assume !(1 == ~E_6~0); 6100#L991-1 assume !(1 == ~E_7~0); 5801#L996-1 assume !(1 == ~E_8~0); 5802#L1001-1 assume { :end_inline_reset_delta_events } true; 6334#L1262-3 [2018-11-18 14:32:30,289 INFO L796 eck$LassoCheckResult]: Loop: 6334#L1262-3 assume true; 6543#L1262-1 assume !false; 6544#L1263 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 6137#L803 assume true; 6046#L681-1 assume !false; 6047#L682 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 6121#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 5787#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 6519#L672 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 5736#L686 assume !(0 != eval_~tmp~0); 5738#L818 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 5744#L564-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 6454#L828-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6455#L828-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6240#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5866#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5867#L843-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6517#L848-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6374#L853-3 assume !(0 == ~T6_E~0); 6120#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5663#L863-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5664#L868-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6325#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6210#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5987#L883-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5988#L888-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6426#L893-3 assume !(0 == ~E_6~0); 6179#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6091#L903-3 assume 0 == ~E_8~0;~E_8~0 := 1; 5799#L908-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 5800#L392-27 assume 1 == ~m_pc~0; 6224#L393-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 6225#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6554#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 6467#L1025-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 6461#L1025-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6251#L411-27 assume !(1 == ~t1_pc~0); 6252#L411-29 is_transmit1_triggered_~__retres1~1 := 0; 5677#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 5678#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 5815#L1033-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 6006#L1033-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6011#L430-27 assume 1 == ~t2_pc~0; 6402#L431-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 5903#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 5904#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 6000#L1041-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 6536#L1041-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6498#L449-27 assume 1 == ~t3_pc~0; 6468#L450-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 6063#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6004#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 6005#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 6271#L1049-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6276#L468-27 assume 1 == ~t4_pc~0; 6549#L469-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 6341#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6153#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 5902#L1057-27 assume !(0 != activate_threads_~tmp___3~0); 5876#L1057-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 5741#L487-27 assume 1 == ~t5_pc~0; 5714#L488-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 5715#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 6297#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 6298#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 6504#L1065-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 6099#L506-27 assume 1 == ~t6_pc~0; 5894#L507-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 5896#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 6432#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 6342#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 6181#L1073-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 6182#L525-27 assume 1 == ~t7_pc~0; 6086#L526-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 6087#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 6515#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 5949#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 5950#L1081-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 5953#L544-27 assume 1 == ~t8_pc~0; 6336#L545-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 5833#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 5752#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 5753#L1089-27 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 6524#L1089-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6133#L921-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6134#L921-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5872#L926-3 assume !(1 == ~T2_E~0); 5873#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6522#L936-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6380#L941-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6124#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5656#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5657#L956-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6323#L961-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6207#L966-3 assume !(1 == ~E_2~0); 5982#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5983#L976-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6421#L981-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6177#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6104#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5808#L996-3 assume 1 == ~E_8~0;~E_8~0 := 2; 5809#L1001-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 6535#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 5790#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 6520#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 5698#L1281 assume !(0 == start_simulation_~tmp~3); 5699#L1281-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 5711#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 5793#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 6442#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 5946#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 5947#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 6482#L1244 start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 6333#L1294 assume !(0 != start_simulation_~tmp___0~1); 6334#L1262-3 [2018-11-18 14:32:30,290 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:30,290 INFO L82 PathProgramCache]: Analyzing trace with hash 805546652, now seen corresponding path program 1 times [2018-11-18 14:32:30,290 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:30,290 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:30,290 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:30,291 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:30,291 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:30,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:30,321 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:30,321 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:30,321 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:32:30,322 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 14:32:30,322 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:30,322 INFO L82 PathProgramCache]: Analyzing trace with hash 1409879850, now seen corresponding path program 2 times [2018-11-18 14:32:30,322 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:30,322 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:30,323 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:30,323 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:30,323 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:30,330 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:30,375 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:30,375 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:30,375 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:32:30,375 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 14:32:30,375 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 14:32:30,375 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 14:32:30,376 INFO L87 Difference]: Start difference. First operand 936 states and 1389 transitions. cyclomatic complexity: 454 Second operand 3 states. [2018-11-18 14:32:30,387 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:32:30,387 INFO L93 Difference]: Finished difference Result 936 states and 1388 transitions. [2018-11-18 14:32:30,388 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 14:32:30,389 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 936 states and 1388 transitions. [2018-11-18 14:32:30,393 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 823 [2018-11-18 14:32:30,396 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 936 states to 936 states and 1388 transitions. [2018-11-18 14:32:30,396 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 936 [2018-11-18 14:32:30,397 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 936 [2018-11-18 14:32:30,397 INFO L73 IsDeterministic]: Start isDeterministic. Operand 936 states and 1388 transitions. [2018-11-18 14:32:30,399 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:32:30,399 INFO L705 BuchiCegarLoop]: Abstraction has 936 states and 1388 transitions. [2018-11-18 14:32:30,400 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 936 states and 1388 transitions. [2018-11-18 14:32:30,410 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 936 to 936. [2018-11-18 14:32:30,410 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 936 states. [2018-11-18 14:32:30,412 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 936 states to 936 states and 1388 transitions. [2018-11-18 14:32:30,412 INFO L728 BuchiCegarLoop]: Abstraction has 936 states and 1388 transitions. [2018-11-18 14:32:30,412 INFO L608 BuchiCegarLoop]: Abstraction has 936 states and 1388 transitions. [2018-11-18 14:32:30,412 INFO L442 BuchiCegarLoop]: ======== Iteration 5============ [2018-11-18 14:32:30,412 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 936 states and 1388 transitions. [2018-11-18 14:32:30,415 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 823 [2018-11-18 14:32:30,416 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:32:30,416 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:32:30,417 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:30,417 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:30,418 INFO L794 eck$LassoCheckResult]: Stem: 7993#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 7892#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 7893#L1225 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 8329#L564 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7929#L571 assume 1 == ~m_i~0;~m_st~0 := 0; 7910#L571-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7621#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7622#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8331#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8115#L591-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 7738#L596-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7739#L601-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8323#L606-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8240#L611-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8241#L828 assume !(0 == ~M_E~0); 8338#L828-2 assume !(0 == ~T1_E~0); 8014#L833-1 assume !(0 == ~T2_E~0); 7753#L838-1 assume !(0 == ~T3_E~0); 7754#L843-1 assume !(0 == ~T4_E~0); 8402#L848-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8249#L853-1 assume !(0 == ~T6_E~0); 7997#L858-1 assume !(0 == ~T7_E~0); 7537#L863-1 assume !(0 == ~T8_E~0); 7538#L868-1 assume !(0 == ~E_1~0); 8203#L873-1 assume !(0 == ~E_2~0); 8088#L878-1 assume !(0 == ~E_3~0); 7863#L883-1 assume !(0 == ~E_4~0); 7864#L888-1 assume 0 == ~E_5~0;~E_5~0 := 1; 8301#L893-1 assume !(0 == ~E_6~0); 8057#L898-1 assume !(0 == ~E_7~0); 7984#L903-1 assume !(0 == ~E_8~0); 7692#L908-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7693#L392 assume !(1 == ~m_pc~0); 8037#L392-2 is_master_triggered_~__retres1~0 := 0; 8043#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8435#L404 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 8308#L1025 assume !(0 != activate_threads_~tmp~1); 8309#L1025-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8190#L411 assume 1 == ~t1_pc~0; 8191#L412 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 7603#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7604#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 7719#L1033 assume !(0 != activate_threads_~tmp___0~0); 7936#L1033-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7937#L430 assume 1 == ~t2_pc~0; 8287#L431 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 7786#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7740#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 7741#L1041 assume !(0 != activate_threads_~tmp___1~0); 8453#L1041-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8454#L449 assume !(1 == ~t3_pc~0); 8368#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 8071#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7911#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 7912#L1049 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 8327#L1049-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 7639#L468 assume 1 == ~t4_pc~0; 7640#L469 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 7649#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 8050#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 7989#L1057 assume !(0 != activate_threads_~tmp___3~0); 7990#L1057-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7849#L487 assume !(1 == ~t5_pc~0); 7598#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 7599#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 8178#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 8179#L1065 assume !(0 != activate_threads_~tmp___4~0); 8466#L1065-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 7996#L506 assume 1 == ~t6_pc~0; 7815#L507 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 7816#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 8325#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 8262#L1073 assume !(0 != activate_threads_~tmp___5~0); 8263#L1073-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 8116#L525 assume !(1 == ~t7_pc~0); 8067#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 8066#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 8455#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 7869#L1081 assume !(0 != activate_threads_~tmp___6~0); 7870#L1081-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 7871#L544 assume 1 == ~t8_pc~0; 8128#L545 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 7531#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 7532#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 7674#L1089 assume !(0 != activate_threads_~tmp___7~0); 8353#L1089-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8004#L921 assume !(1 == ~M_E~0); 8005#L921-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7749#L926-1 assume !(1 == ~T2_E~0); 7750#L931-1 assume !(1 == ~T3_E~0); 8400#L936-1 assume !(1 == ~T4_E~0); 8257#L941-1 assume !(1 == ~T5_E~0); 8002#L946-1 assume !(1 == ~T6_E~0); 7549#L951-1 assume !(1 == ~T7_E~0); 7550#L956-1 assume !(1 == ~T8_E~0); 8328#L961-1 assume 1 == ~E_1~0;~E_1~0 := 2; 8093#L966-1 assume !(1 == ~E_2~0); 7874#L971-1 assume !(1 == ~E_3~0); 7875#L976-1 assume !(1 == ~E_4~0); 8297#L981-1 assume !(1 == ~E_5~0); 8055#L986-1 assume !(1 == ~E_6~0); 7979#L991-1 assume !(1 == ~E_7~0); 7680#L996-1 assume !(1 == ~E_8~0); 7681#L1001-1 assume { :end_inline_reset_delta_events } true; 8213#L1262-3 [2018-11-18 14:32:30,418 INFO L796 eck$LassoCheckResult]: Loop: 8213#L1262-3 assume true; 8422#L1262-1 assume !false; 8423#L1263 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 8016#L803 assume true; 7925#L681-1 assume !false; 7926#L682 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 8000#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 7666#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 8398#L672 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 7615#L686 assume !(0 != eval_~tmp~0); 7617#L818 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 7623#L564-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 8333#L828-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8334#L828-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8119#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7745#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 7746#L843-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8396#L848-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8253#L853-3 assume !(0 == ~T6_E~0); 7999#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7542#L863-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 7543#L868-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8204#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8089#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7866#L883-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7867#L888-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8305#L893-3 assume !(0 == ~E_6~0); 8058#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 7970#L903-3 assume 0 == ~E_8~0;~E_8~0 := 1; 7678#L908-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 7679#L392-27 assume 1 == ~m_pc~0; 8103#L393-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 8104#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8433#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 8346#L1025-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 8340#L1025-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8130#L411-27 assume !(1 == ~t1_pc~0); 8131#L411-29 is_transmit1_triggered_~__retres1~1 := 0; 7556#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 7557#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 7694#L1033-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 7885#L1033-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 7890#L430-27 assume 1 == ~t2_pc~0; 8281#L431-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 7782#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 7783#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 7879#L1041-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 8415#L1041-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8377#L449-27 assume 1 == ~t3_pc~0; 8347#L450-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 7942#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 7883#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 7884#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 8150#L1049-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 8155#L468-27 assume 1 == ~t4_pc~0; 8428#L469-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 8220#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 8032#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 7781#L1057-27 assume !(0 != activate_threads_~tmp___3~0); 7755#L1057-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 7620#L487-27 assume 1 == ~t5_pc~0; 7593#L488-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 7594#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 8176#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 8177#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 8383#L1065-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 7978#L506-27 assume 1 == ~t6_pc~0; 7773#L507-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 7775#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 8311#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 8221#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 8060#L1073-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 8061#L525-27 assume 1 == ~t7_pc~0; 7965#L526-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 7966#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 8394#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 7828#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 7829#L1081-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 7832#L544-27 assume 1 == ~t8_pc~0; 8215#L545-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 7712#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 7631#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 7632#L1089-27 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 8403#L1089-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8012#L921-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8013#L921-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7751#L926-3 assume !(1 == ~T2_E~0); 7752#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8401#L936-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8259#L941-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8003#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7535#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7536#L956-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8202#L961-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8086#L966-3 assume !(1 == ~E_2~0); 7861#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7862#L976-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8300#L981-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8056#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7983#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 7687#L996-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7688#L1001-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 8414#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 7669#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 8399#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 7577#L1281 assume !(0 == start_simulation_~tmp~3); 7578#L1281-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 7590#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 7672#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 8321#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 7825#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 7826#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 8361#L1244 start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 8212#L1294 assume !(0 != start_simulation_~tmp___0~1); 8213#L1262-3 [2018-11-18 14:32:30,418 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:30,418 INFO L82 PathProgramCache]: Analyzing trace with hash 1862277854, now seen corresponding path program 1 times [2018-11-18 14:32:30,418 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:30,419 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:30,419 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:30,419 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 14:32:30,419 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:30,424 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:30,460 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:30,460 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:30,461 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:32:30,461 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 14:32:30,461 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:30,461 INFO L82 PathProgramCache]: Analyzing trace with hash 1409879850, now seen corresponding path program 3 times [2018-11-18 14:32:30,461 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:30,461 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:30,462 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:30,462 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:30,462 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:30,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:30,506 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:30,507 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:30,507 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:32:30,507 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 14:32:30,507 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 14:32:30,507 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 14:32:30,508 INFO L87 Difference]: Start difference. First operand 936 states and 1388 transitions. cyclomatic complexity: 453 Second operand 3 states. [2018-11-18 14:32:30,520 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:32:30,520 INFO L93 Difference]: Finished difference Result 936 states and 1387 transitions. [2018-11-18 14:32:30,522 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 14:32:30,522 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 936 states and 1387 transitions. [2018-11-18 14:32:30,526 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 823 [2018-11-18 14:32:30,529 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 936 states to 936 states and 1387 transitions. [2018-11-18 14:32:30,529 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 936 [2018-11-18 14:32:30,530 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 936 [2018-11-18 14:32:30,530 INFO L73 IsDeterministic]: Start isDeterministic. Operand 936 states and 1387 transitions. [2018-11-18 14:32:30,532 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:32:30,532 INFO L705 BuchiCegarLoop]: Abstraction has 936 states and 1387 transitions. [2018-11-18 14:32:30,533 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 936 states and 1387 transitions. [2018-11-18 14:32:30,542 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 936 to 936. [2018-11-18 14:32:30,543 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 936 states. [2018-11-18 14:32:30,544 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 936 states to 936 states and 1387 transitions. [2018-11-18 14:32:30,545 INFO L728 BuchiCegarLoop]: Abstraction has 936 states and 1387 transitions. [2018-11-18 14:32:30,545 INFO L608 BuchiCegarLoop]: Abstraction has 936 states and 1387 transitions. [2018-11-18 14:32:30,545 INFO L442 BuchiCegarLoop]: ======== Iteration 6============ [2018-11-18 14:32:30,545 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 936 states and 1387 transitions. [2018-11-18 14:32:30,548 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 823 [2018-11-18 14:32:30,548 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:32:30,548 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:32:30,549 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:30,549 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:30,550 INFO L794 eck$LassoCheckResult]: Stem: 9872#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 9771#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 9772#L1225 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 10208#L564 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9808#L571 assume 1 == ~m_i~0;~m_st~0 := 0; 9789#L571-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9500#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9501#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10210#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9994#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9617#L596-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 9618#L601-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10202#L606-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 10119#L611-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10120#L828 assume !(0 == ~M_E~0); 10217#L828-2 assume !(0 == ~T1_E~0); 9893#L833-1 assume !(0 == ~T2_E~0); 9632#L838-1 assume !(0 == ~T3_E~0); 9633#L843-1 assume !(0 == ~T4_E~0); 10281#L848-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10128#L853-1 assume !(0 == ~T6_E~0); 9876#L858-1 assume !(0 == ~T7_E~0); 9416#L863-1 assume !(0 == ~T8_E~0); 9417#L868-1 assume !(0 == ~E_1~0); 10082#L873-1 assume !(0 == ~E_2~0); 9967#L878-1 assume !(0 == ~E_3~0); 9742#L883-1 assume !(0 == ~E_4~0); 9743#L888-1 assume 0 == ~E_5~0;~E_5~0 := 1; 10180#L893-1 assume !(0 == ~E_6~0); 9936#L898-1 assume !(0 == ~E_7~0); 9863#L903-1 assume !(0 == ~E_8~0); 9571#L908-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9572#L392 assume !(1 == ~m_pc~0); 9916#L392-2 is_master_triggered_~__retres1~0 := 0; 9922#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10314#L404 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 10187#L1025 assume !(0 != activate_threads_~tmp~1); 10188#L1025-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10069#L411 assume 1 == ~t1_pc~0; 10070#L412 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 9482#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9483#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 9598#L1033 assume !(0 != activate_threads_~tmp___0~0); 9815#L1033-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9816#L430 assume 1 == ~t2_pc~0; 10166#L431 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 9665#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9619#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 9620#L1041 assume !(0 != activate_threads_~tmp___1~0); 10332#L1041-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 10333#L449 assume !(1 == ~t3_pc~0); 10247#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 9950#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9790#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 9791#L1049 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 10206#L1049-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 9518#L468 assume 1 == ~t4_pc~0; 9519#L469 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 9528#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9929#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 9868#L1057 assume !(0 != activate_threads_~tmp___3~0); 9869#L1057-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 9728#L487 assume !(1 == ~t5_pc~0); 9477#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 9478#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 10057#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 10058#L1065 assume !(0 != activate_threads_~tmp___4~0); 10345#L1065-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 9875#L506 assume 1 == ~t6_pc~0; 9694#L507 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 9695#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 10204#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 10141#L1073 assume !(0 != activate_threads_~tmp___5~0); 10142#L1073-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 9995#L525 assume !(1 == ~t7_pc~0); 9946#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 9945#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 10334#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 9748#L1081 assume !(0 != activate_threads_~tmp___6~0); 9749#L1081-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 9750#L544 assume 1 == ~t8_pc~0; 10007#L545 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 9410#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 9411#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 9553#L1089 assume !(0 != activate_threads_~tmp___7~0); 10232#L1089-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9883#L921 assume !(1 == ~M_E~0); 9884#L921-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9628#L926-1 assume !(1 == ~T2_E~0); 9629#L931-1 assume !(1 == ~T3_E~0); 10279#L936-1 assume !(1 == ~T4_E~0); 10136#L941-1 assume !(1 == ~T5_E~0); 9881#L946-1 assume !(1 == ~T6_E~0); 9428#L951-1 assume !(1 == ~T7_E~0); 9429#L956-1 assume !(1 == ~T8_E~0); 10207#L961-1 assume 1 == ~E_1~0;~E_1~0 := 2; 9972#L966-1 assume !(1 == ~E_2~0); 9753#L971-1 assume !(1 == ~E_3~0); 9754#L976-1 assume !(1 == ~E_4~0); 10176#L981-1 assume !(1 == ~E_5~0); 9934#L986-1 assume !(1 == ~E_6~0); 9858#L991-1 assume !(1 == ~E_7~0); 9559#L996-1 assume !(1 == ~E_8~0); 9560#L1001-1 assume { :end_inline_reset_delta_events } true; 10092#L1262-3 [2018-11-18 14:32:30,550 INFO L796 eck$LassoCheckResult]: Loop: 10092#L1262-3 assume true; 10301#L1262-1 assume !false; 10302#L1263 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 9895#L803 assume true; 9804#L681-1 assume !false; 9805#L682 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 9879#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 9545#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 10277#L672 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 9494#L686 assume !(0 != eval_~tmp~0); 9496#L818 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 9502#L564-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 10212#L828-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10213#L828-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9998#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9624#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9625#L843-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10275#L848-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10132#L853-3 assume !(0 == ~T6_E~0); 9878#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9421#L863-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9422#L868-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10083#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9968#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9745#L883-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9746#L888-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10184#L893-3 assume !(0 == ~E_6~0); 9937#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9849#L903-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9557#L908-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 9558#L392-27 assume !(1 == ~m_pc~0); 9984#L392-29 is_master_triggered_~__retres1~0 := 0; 9983#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 10312#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 10225#L1025-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 10219#L1025-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 10009#L411-27 assume !(1 == ~t1_pc~0); 10010#L411-29 is_transmit1_triggered_~__retres1~1 := 0; 9435#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 9436#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 9573#L1033-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 9764#L1033-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 9769#L430-27 assume 1 == ~t2_pc~0; 10160#L431-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 9661#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 9662#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 9758#L1041-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 10294#L1041-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 10256#L449-27 assume 1 == ~t3_pc~0; 10226#L450-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 9821#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 9762#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 9763#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 10029#L1049-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 10034#L468-27 assume 1 == ~t4_pc~0; 10307#L469-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 10099#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 9911#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 9660#L1057-27 assume !(0 != activate_threads_~tmp___3~0); 9634#L1057-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 9499#L487-27 assume 1 == ~t5_pc~0; 9472#L488-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 9473#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 10055#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 10056#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 10262#L1065-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 9857#L506-27 assume 1 == ~t6_pc~0; 9652#L507-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 9654#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 10190#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 10100#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 9939#L1073-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 9940#L525-27 assume 1 == ~t7_pc~0; 9844#L526-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 9845#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 10273#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 9707#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 9708#L1081-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 9711#L544-27 assume 1 == ~t8_pc~0; 10094#L545-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 9591#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 9510#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 9511#L1089-27 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 10282#L1089-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9891#L921-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9892#L921-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9630#L926-3 assume !(1 == ~T2_E~0); 9631#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 10280#L936-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10138#L941-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9882#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9414#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9415#L956-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10081#L961-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9965#L966-3 assume !(1 == ~E_2~0); 9740#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9741#L976-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10179#L981-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9935#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9862#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9566#L996-3 assume 1 == ~E_8~0;~E_8~0 := 2; 9567#L1001-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 10293#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 9548#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 10278#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 9456#L1281 assume !(0 == start_simulation_~tmp~3); 9457#L1281-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 9469#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 9551#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 10200#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 9704#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 9705#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 10240#L1244 start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 10091#L1294 assume !(0 != start_simulation_~tmp___0~1); 10092#L1262-3 [2018-11-18 14:32:30,550 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:30,550 INFO L82 PathProgramCache]: Analyzing trace with hash 510892636, now seen corresponding path program 1 times [2018-11-18 14:32:30,550 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:30,551 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:30,551 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:30,551 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 14:32:30,552 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:30,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:30,594 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:30,595 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:30,595 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:32:30,595 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 14:32:30,595 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:30,595 INFO L82 PathProgramCache]: Analyzing trace with hash 954973769, now seen corresponding path program 1 times [2018-11-18 14:32:30,595 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:30,595 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:30,596 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:30,596 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:30,596 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:30,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:30,626 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:30,626 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:30,626 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:32:30,626 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 14:32:30,627 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 14:32:30,629 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 14:32:30,629 INFO L87 Difference]: Start difference. First operand 936 states and 1387 transitions. cyclomatic complexity: 452 Second operand 3 states. [2018-11-18 14:32:30,643 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:32:30,644 INFO L93 Difference]: Finished difference Result 936 states and 1386 transitions. [2018-11-18 14:32:30,645 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 14:32:30,645 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 936 states and 1386 transitions. [2018-11-18 14:32:30,649 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 823 [2018-11-18 14:32:30,652 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 936 states to 936 states and 1386 transitions. [2018-11-18 14:32:30,652 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 936 [2018-11-18 14:32:30,653 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 936 [2018-11-18 14:32:30,653 INFO L73 IsDeterministic]: Start isDeterministic. Operand 936 states and 1386 transitions. [2018-11-18 14:32:30,654 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:32:30,655 INFO L705 BuchiCegarLoop]: Abstraction has 936 states and 1386 transitions. [2018-11-18 14:32:30,656 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 936 states and 1386 transitions. [2018-11-18 14:32:30,664 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 936 to 936. [2018-11-18 14:32:30,664 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 936 states. [2018-11-18 14:32:30,666 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 936 states to 936 states and 1386 transitions. [2018-11-18 14:32:30,666 INFO L728 BuchiCegarLoop]: Abstraction has 936 states and 1386 transitions. [2018-11-18 14:32:30,667 INFO L608 BuchiCegarLoop]: Abstraction has 936 states and 1386 transitions. [2018-11-18 14:32:30,667 INFO L442 BuchiCegarLoop]: ======== Iteration 7============ [2018-11-18 14:32:30,667 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 936 states and 1386 transitions. [2018-11-18 14:32:30,670 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 823 [2018-11-18 14:32:30,670 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:32:30,670 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:32:30,671 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:30,671 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:30,672 INFO L794 eck$LassoCheckResult]: Stem: 11751#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 11650#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 11651#L1225 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 12087#L564 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11687#L571 assume 1 == ~m_i~0;~m_st~0 := 0; 11668#L571-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11379#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11380#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12089#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11873#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 11496#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 11497#L601-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12081#L606-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11998#L611-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11999#L828 assume !(0 == ~M_E~0); 12096#L828-2 assume !(0 == ~T1_E~0); 11772#L833-1 assume !(0 == ~T2_E~0); 11511#L838-1 assume !(0 == ~T3_E~0); 11512#L843-1 assume !(0 == ~T4_E~0); 12160#L848-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12007#L853-1 assume !(0 == ~T6_E~0); 11755#L858-1 assume !(0 == ~T7_E~0); 11295#L863-1 assume !(0 == ~T8_E~0); 11296#L868-1 assume !(0 == ~E_1~0); 11961#L873-1 assume !(0 == ~E_2~0); 11846#L878-1 assume !(0 == ~E_3~0); 11621#L883-1 assume !(0 == ~E_4~0); 11622#L888-1 assume 0 == ~E_5~0;~E_5~0 := 1; 12059#L893-1 assume !(0 == ~E_6~0); 11815#L898-1 assume !(0 == ~E_7~0); 11742#L903-1 assume !(0 == ~E_8~0); 11450#L908-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 11451#L392 assume !(1 == ~m_pc~0); 11795#L392-2 is_master_triggered_~__retres1~0 := 0; 11801#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12193#L404 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 12066#L1025 assume !(0 != activate_threads_~tmp~1); 12067#L1025-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 11948#L411 assume 1 == ~t1_pc~0; 11949#L412 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 11361#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 11362#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 11477#L1033 assume !(0 != activate_threads_~tmp___0~0); 11694#L1033-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 11695#L430 assume 1 == ~t2_pc~0; 12045#L431 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 11544#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 11498#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 11499#L1041 assume !(0 != activate_threads_~tmp___1~0); 12211#L1041-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 12212#L449 assume !(1 == ~t3_pc~0); 12126#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 11829#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 11669#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 11670#L1049 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 12085#L1049-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 11397#L468 assume 1 == ~t4_pc~0; 11398#L469 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 11407#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 11808#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 11747#L1057 assume !(0 != activate_threads_~tmp___3~0); 11748#L1057-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 11607#L487 assume !(1 == ~t5_pc~0); 11356#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 11357#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 11936#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 11937#L1065 assume !(0 != activate_threads_~tmp___4~0); 12224#L1065-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 11754#L506 assume 1 == ~t6_pc~0; 11573#L507 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 11574#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 12083#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 12020#L1073 assume !(0 != activate_threads_~tmp___5~0); 12021#L1073-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 11874#L525 assume !(1 == ~t7_pc~0); 11825#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 11824#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 12213#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 11627#L1081 assume !(0 != activate_threads_~tmp___6~0); 11628#L1081-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 11629#L544 assume 1 == ~t8_pc~0; 11886#L545 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 11289#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 11290#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 11432#L1089 assume !(0 != activate_threads_~tmp___7~0); 12111#L1089-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11762#L921 assume !(1 == ~M_E~0); 11763#L921-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11507#L926-1 assume !(1 == ~T2_E~0); 11508#L931-1 assume !(1 == ~T3_E~0); 12158#L936-1 assume !(1 == ~T4_E~0); 12015#L941-1 assume !(1 == ~T5_E~0); 11760#L946-1 assume !(1 == ~T6_E~0); 11307#L951-1 assume !(1 == ~T7_E~0); 11308#L956-1 assume !(1 == ~T8_E~0); 12086#L961-1 assume 1 == ~E_1~0;~E_1~0 := 2; 11851#L966-1 assume !(1 == ~E_2~0); 11632#L971-1 assume !(1 == ~E_3~0); 11633#L976-1 assume !(1 == ~E_4~0); 12055#L981-1 assume !(1 == ~E_5~0); 11813#L986-1 assume !(1 == ~E_6~0); 11737#L991-1 assume !(1 == ~E_7~0); 11438#L996-1 assume !(1 == ~E_8~0); 11439#L1001-1 assume { :end_inline_reset_delta_events } true; 11971#L1262-3 [2018-11-18 14:32:30,672 INFO L796 eck$LassoCheckResult]: Loop: 11971#L1262-3 assume true; 12180#L1262-1 assume !false; 12181#L1263 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 11774#L803 assume true; 11683#L681-1 assume !false; 11684#L682 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 11758#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 11424#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 12156#L672 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 11373#L686 assume !(0 != eval_~tmp~0); 11375#L818 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 11381#L564-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 12091#L828-3 assume 0 == ~M_E~0;~M_E~0 := 1; 12092#L828-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11877#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11503#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11504#L843-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12154#L848-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12011#L853-3 assume !(0 == ~T6_E~0); 11757#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11300#L863-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 11301#L868-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11962#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11847#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11624#L883-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11625#L888-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12063#L893-3 assume !(0 == ~E_6~0); 11816#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 11728#L903-3 assume 0 == ~E_8~0;~E_8~0 := 1; 11436#L908-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 11437#L392-27 assume 1 == ~m_pc~0; 11861#L393-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 11862#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 12191#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 12104#L1025-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 12098#L1025-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 11888#L411-27 assume !(1 == ~t1_pc~0); 11889#L411-29 is_transmit1_triggered_~__retres1~1 := 0; 11314#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 11315#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 11452#L1033-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 11643#L1033-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 11648#L430-27 assume 1 == ~t2_pc~0; 12039#L431-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 11540#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 11541#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 11637#L1041-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 12173#L1041-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 12135#L449-27 assume 1 == ~t3_pc~0; 12105#L450-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 11700#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 11641#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 11642#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 11908#L1049-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 11913#L468-27 assume 1 == ~t4_pc~0; 12186#L469-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 11978#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 11790#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 11539#L1057-27 assume !(0 != activate_threads_~tmp___3~0); 11513#L1057-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 11378#L487-27 assume 1 == ~t5_pc~0; 11351#L488-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 11352#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 11934#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 11935#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 12141#L1065-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 11736#L506-27 assume 1 == ~t6_pc~0; 11531#L507-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 11533#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 12069#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 11979#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 11818#L1073-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 11819#L525-27 assume 1 == ~t7_pc~0; 11723#L526-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 11724#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 12152#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 11586#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 11587#L1081-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 11590#L544-27 assume 1 == ~t8_pc~0; 11973#L545-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 11470#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 11389#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 11390#L1089-27 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 12161#L1089-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11770#L921-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11771#L921-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11509#L926-3 assume !(1 == ~T2_E~0); 11510#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12159#L936-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12017#L941-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11761#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11293#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11294#L956-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11960#L961-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11844#L966-3 assume !(1 == ~E_2~0); 11619#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11620#L976-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12058#L981-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11814#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11741#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11445#L996-3 assume 1 == ~E_8~0;~E_8~0 := 2; 11446#L1001-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 12172#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 11427#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 12157#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 11335#L1281 assume !(0 == start_simulation_~tmp~3); 11336#L1281-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 11348#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 11430#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 12079#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 11583#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 11584#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 12119#L1244 start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 11970#L1294 assume !(0 != start_simulation_~tmp___0~1); 11971#L1262-3 [2018-11-18 14:32:30,672 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:30,672 INFO L82 PathProgramCache]: Analyzing trace with hash 2129867550, now seen corresponding path program 1 times [2018-11-18 14:32:30,672 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:30,673 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:30,673 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:30,673 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:30,673 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:30,677 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:30,702 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:30,703 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:30,703 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:32:30,703 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 14:32:30,703 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:30,703 INFO L82 PathProgramCache]: Analyzing trace with hash 1409879850, now seen corresponding path program 4 times [2018-11-18 14:32:30,703 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:30,704 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:30,704 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:30,704 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:30,704 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:30,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:30,742 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:30,743 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:30,743 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:32:30,743 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 14:32:30,745 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 14:32:30,745 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 14:32:30,745 INFO L87 Difference]: Start difference. First operand 936 states and 1386 transitions. cyclomatic complexity: 451 Second operand 3 states. [2018-11-18 14:32:30,757 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:32:30,757 INFO L93 Difference]: Finished difference Result 936 states and 1385 transitions. [2018-11-18 14:32:30,758 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 14:32:30,758 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 936 states and 1385 transitions. [2018-11-18 14:32:30,761 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 823 [2018-11-18 14:32:30,764 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 936 states to 936 states and 1385 transitions. [2018-11-18 14:32:30,765 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 936 [2018-11-18 14:32:30,765 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 936 [2018-11-18 14:32:30,766 INFO L73 IsDeterministic]: Start isDeterministic. Operand 936 states and 1385 transitions. [2018-11-18 14:32:30,767 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:32:30,767 INFO L705 BuchiCegarLoop]: Abstraction has 936 states and 1385 transitions. [2018-11-18 14:32:30,768 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 936 states and 1385 transitions. [2018-11-18 14:32:30,776 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 936 to 936. [2018-11-18 14:32:30,777 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 936 states. [2018-11-18 14:32:30,778 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 936 states to 936 states and 1385 transitions. [2018-11-18 14:32:30,779 INFO L728 BuchiCegarLoop]: Abstraction has 936 states and 1385 transitions. [2018-11-18 14:32:30,779 INFO L608 BuchiCegarLoop]: Abstraction has 936 states and 1385 transitions. [2018-11-18 14:32:30,779 INFO L442 BuchiCegarLoop]: ======== Iteration 8============ [2018-11-18 14:32:30,779 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 936 states and 1385 transitions. [2018-11-18 14:32:30,782 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 823 [2018-11-18 14:32:30,782 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:32:30,782 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:32:30,783 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:30,783 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:30,784 INFO L794 eck$LassoCheckResult]: Stem: 13630#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 13529#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 13530#L1225 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 13966#L564 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13566#L571 assume 1 == ~m_i~0;~m_st~0 := 0; 13547#L571-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13258#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13259#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13969#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13752#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 13375#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 13376#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 13960#L606-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 13877#L611-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13878#L828 assume !(0 == ~M_E~0); 13975#L828-2 assume !(0 == ~T1_E~0); 13651#L833-1 assume !(0 == ~T2_E~0); 13390#L838-1 assume !(0 == ~T3_E~0); 13391#L843-1 assume !(0 == ~T4_E~0); 14039#L848-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13887#L853-1 assume !(0 == ~T6_E~0); 13634#L858-1 assume !(0 == ~T7_E~0); 13174#L863-1 assume !(0 == ~T8_E~0); 13175#L868-1 assume !(0 == ~E_1~0); 13840#L873-1 assume !(0 == ~E_2~0); 13725#L878-1 assume !(0 == ~E_3~0); 13500#L883-1 assume !(0 == ~E_4~0); 13501#L888-1 assume 0 == ~E_5~0;~E_5~0 := 1; 13940#L893-1 assume !(0 == ~E_6~0); 13694#L898-1 assume !(0 == ~E_7~0); 13622#L903-1 assume !(0 == ~E_8~0); 13329#L908-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 13330#L392 assume !(1 == ~m_pc~0); 13674#L392-2 is_master_triggered_~__retres1~0 := 0; 13680#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 14072#L404 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 13945#L1025 assume !(0 != activate_threads_~tmp~1); 13946#L1025-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 13827#L411 assume 1 == ~t1_pc~0; 13828#L412 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 13243#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 13244#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 13357#L1033 assume !(0 != activate_threads_~tmp___0~0); 13573#L1033-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 13574#L430 assume 1 == ~t2_pc~0; 13924#L431 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 13426#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 13377#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 13378#L1041 assume !(0 != activate_threads_~tmp___1~0); 14090#L1041-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 14091#L449 assume !(1 == ~t3_pc~0); 14005#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 13708#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 13548#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 13549#L1049 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 13964#L1049-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 13276#L468 assume 1 == ~t4_pc~0; 13277#L469 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 13286#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 13687#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 13626#L1057 assume !(0 != activate_threads_~tmp___3~0); 13627#L1057-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 13486#L487 assume !(1 == ~t5_pc~0); 13235#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 13236#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 13815#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 13816#L1065 assume !(0 != activate_threads_~tmp___4~0); 14103#L1065-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 13633#L506 assume 1 == ~t6_pc~0; 13452#L507 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 13453#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 13962#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 13899#L1073 assume !(0 != activate_threads_~tmp___5~0); 13900#L1073-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 13753#L525 assume !(1 == ~t7_pc~0); 13704#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 13703#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 14092#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 13506#L1081 assume !(0 != activate_threads_~tmp___6~0); 13507#L1081-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 13508#L544 assume 1 == ~t8_pc~0; 13765#L545 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 13168#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 13169#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 13311#L1089 assume !(0 != activate_threads_~tmp___7~0); 13990#L1089-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13641#L921 assume !(1 == ~M_E~0); 13642#L921-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13386#L926-1 assume !(1 == ~T2_E~0); 13387#L931-1 assume !(1 == ~T3_E~0); 14037#L936-1 assume !(1 == ~T4_E~0); 13894#L941-1 assume !(1 == ~T5_E~0); 13639#L946-1 assume !(1 == ~T6_E~0); 13186#L951-1 assume !(1 == ~T7_E~0); 13187#L956-1 assume !(1 == ~T8_E~0); 13965#L961-1 assume 1 == ~E_1~0;~E_1~0 := 2; 13730#L966-1 assume !(1 == ~E_2~0); 13511#L971-1 assume !(1 == ~E_3~0); 13512#L976-1 assume !(1 == ~E_4~0); 13934#L981-1 assume !(1 == ~E_5~0); 13692#L986-1 assume !(1 == ~E_6~0); 13616#L991-1 assume !(1 == ~E_7~0); 13317#L996-1 assume !(1 == ~E_8~0); 13318#L1001-1 assume { :end_inline_reset_delta_events } true; 13850#L1262-3 [2018-11-18 14:32:30,784 INFO L796 eck$LassoCheckResult]: Loop: 13850#L1262-3 assume true; 14059#L1262-1 assume !false; 14060#L1263 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 13653#L803 assume true; 13562#L681-1 assume !false; 13563#L682 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 13637#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 13303#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 14035#L672 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 13252#L686 assume !(0 != eval_~tmp~0); 13254#L818 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 13260#L564-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 13970#L828-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13971#L828-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13756#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13382#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13383#L843-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14033#L848-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13890#L853-3 assume !(0 == ~T6_E~0); 13636#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 13179#L863-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13180#L868-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13841#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13726#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13503#L883-3 assume 0 == ~E_4~0;~E_4~0 := 1; 13504#L888-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13942#L893-3 assume !(0 == ~E_6~0); 13695#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13607#L903-3 assume 0 == ~E_8~0;~E_8~0 := 1; 13315#L908-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 13316#L392-27 assume 1 == ~m_pc~0; 13740#L393-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 13741#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 14070#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 13983#L1025-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 13977#L1025-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 13767#L411-27 assume !(1 == ~t1_pc~0); 13768#L411-29 is_transmit1_triggered_~__retres1~1 := 0; 13193#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 13194#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 13331#L1033-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 13522#L1033-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 13527#L430-27 assume 1 == ~t2_pc~0; 13918#L431-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 13419#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 13420#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 13516#L1041-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 14052#L1041-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 14014#L449-27 assume 1 == ~t3_pc~0; 13984#L450-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 13579#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 13520#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 13521#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 13787#L1049-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 13792#L468-27 assume 1 == ~t4_pc~0; 14065#L469-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 13857#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 13669#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 13418#L1057-27 assume !(0 != activate_threads_~tmp___3~0); 13392#L1057-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 13257#L487-27 assume !(1 == ~t5_pc~0); 13232#L487-29 is_transmit5_triggered_~__retres1~5 := 0; 13231#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 13813#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 13814#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 14020#L1065-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 13615#L506-27 assume 1 == ~t6_pc~0; 13410#L507-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 13412#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 13948#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 13858#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 13697#L1073-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 13698#L525-27 assume 1 == ~t7_pc~0; 13602#L526-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 13603#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 14031#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 13465#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 13466#L1081-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 13469#L544-27 assume 1 == ~t8_pc~0; 13852#L545-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 13349#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 13268#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 13269#L1089-27 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 14040#L1089-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13649#L921-3 assume 1 == ~M_E~0;~M_E~0 := 2; 13650#L921-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13388#L926-3 assume !(1 == ~T2_E~0); 13389#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14038#L936-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13896#L941-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13640#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13172#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13173#L956-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13839#L961-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13723#L966-3 assume !(1 == ~E_2~0); 13498#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13499#L976-3 assume 1 == ~E_4~0;~E_4~0 := 2; 13937#L981-3 assume 1 == ~E_5~0;~E_5~0 := 2; 13693#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13620#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13324#L996-3 assume 1 == ~E_8~0;~E_8~0 := 2; 13325#L1001-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 14051#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 13306#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 14036#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 13214#L1281 assume !(0 == start_simulation_~tmp~3); 13215#L1281-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 13227#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 13309#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 13958#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 13462#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 13463#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 13998#L1244 start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 13849#L1294 assume !(0 != start_simulation_~tmp___0~1); 13850#L1262-3 [2018-11-18 14:32:30,784 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:30,784 INFO L82 PathProgramCache]: Analyzing trace with hash -1281590756, now seen corresponding path program 1 times [2018-11-18 14:32:30,784 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:30,785 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:30,785 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:30,785 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 14:32:30,785 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:30,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:30,811 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:30,811 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:30,811 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:32:30,811 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 14:32:30,812 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:30,812 INFO L82 PathProgramCache]: Analyzing trace with hash 1512681097, now seen corresponding path program 1 times [2018-11-18 14:32:30,812 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:30,812 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:30,813 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:30,813 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:30,813 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:30,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:30,843 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:30,843 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:30,843 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:32:30,843 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 14:32:30,844 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 14:32:30,844 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 14:32:30,844 INFO L87 Difference]: Start difference. First operand 936 states and 1385 transitions. cyclomatic complexity: 450 Second operand 3 states. [2018-11-18 14:32:30,864 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:32:30,865 INFO L93 Difference]: Finished difference Result 936 states and 1384 transitions. [2018-11-18 14:32:30,868 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 14:32:30,869 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 936 states and 1384 transitions. [2018-11-18 14:32:30,873 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 823 [2018-11-18 14:32:30,877 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 936 states to 936 states and 1384 transitions. [2018-11-18 14:32:30,877 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 936 [2018-11-18 14:32:30,878 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 936 [2018-11-18 14:32:30,878 INFO L73 IsDeterministic]: Start isDeterministic. Operand 936 states and 1384 transitions. [2018-11-18 14:32:30,880 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:32:30,880 INFO L705 BuchiCegarLoop]: Abstraction has 936 states and 1384 transitions. [2018-11-18 14:32:30,882 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 936 states and 1384 transitions. [2018-11-18 14:32:30,892 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 936 to 936. [2018-11-18 14:32:30,893 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 936 states. [2018-11-18 14:32:30,895 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 936 states to 936 states and 1384 transitions. [2018-11-18 14:32:30,895 INFO L728 BuchiCegarLoop]: Abstraction has 936 states and 1384 transitions. [2018-11-18 14:32:30,895 INFO L608 BuchiCegarLoop]: Abstraction has 936 states and 1384 transitions. [2018-11-18 14:32:30,895 INFO L442 BuchiCegarLoop]: ======== Iteration 9============ [2018-11-18 14:32:30,895 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 936 states and 1384 transitions. [2018-11-18 14:32:30,899 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 823 [2018-11-18 14:32:30,899 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:32:30,899 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:32:30,901 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:30,901 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:30,901 INFO L794 eck$LassoCheckResult]: Stem: 15509#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 15408#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 15409#L1225 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 15845#L564 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15445#L571 assume 1 == ~m_i~0;~m_st~0 := 0; 15426#L571-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15137#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15138#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15847#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15631#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 15254#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 15255#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 15839#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 15756#L611-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15757#L828 assume !(0 == ~M_E~0); 15854#L828-2 assume !(0 == ~T1_E~0); 15530#L833-1 assume !(0 == ~T2_E~0); 15269#L838-1 assume !(0 == ~T3_E~0); 15270#L843-1 assume !(0 == ~T4_E~0); 15918#L848-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15766#L853-1 assume !(0 == ~T6_E~0); 15513#L858-1 assume !(0 == ~T7_E~0); 15053#L863-1 assume !(0 == ~T8_E~0); 15054#L868-1 assume !(0 == ~E_1~0); 15719#L873-1 assume !(0 == ~E_2~0); 15604#L878-1 assume !(0 == ~E_3~0); 15379#L883-1 assume !(0 == ~E_4~0); 15380#L888-1 assume 0 == ~E_5~0;~E_5~0 := 1; 15819#L893-1 assume !(0 == ~E_6~0); 15573#L898-1 assume !(0 == ~E_7~0); 15501#L903-1 assume !(0 == ~E_8~0); 15208#L908-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15209#L392 assume !(1 == ~m_pc~0); 15553#L392-2 is_master_triggered_~__retres1~0 := 0; 15559#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15951#L404 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 15824#L1025 assume !(0 != activate_threads_~tmp~1); 15825#L1025-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15706#L411 assume 1 == ~t1_pc~0; 15707#L412 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 15122#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 15123#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 15236#L1033 assume !(0 != activate_threads_~tmp___0~0); 15452#L1033-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15453#L430 assume 1 == ~t2_pc~0; 15803#L431 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 15305#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 15256#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 15257#L1041 assume !(0 != activate_threads_~tmp___1~0); 15969#L1041-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 15970#L449 assume !(1 == ~t3_pc~0); 15884#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 15590#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 15429#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 15430#L1049 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 15843#L1049-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 15155#L468 assume 1 == ~t4_pc~0; 15156#L469 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 15165#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 15566#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 15505#L1057 assume !(0 != activate_threads_~tmp___3~0); 15506#L1057-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 15365#L487 assume !(1 == ~t5_pc~0); 15114#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 15115#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 15694#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 15695#L1065 assume !(0 != activate_threads_~tmp___4~0); 15982#L1065-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 15512#L506 assume 1 == ~t6_pc~0; 15331#L507 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 15332#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 15841#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 15778#L1073 assume !(0 != activate_threads_~tmp___5~0); 15779#L1073-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 15632#L525 assume !(1 == ~t7_pc~0); 15583#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 15582#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 15971#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 15385#L1081 assume !(0 != activate_threads_~tmp___6~0); 15386#L1081-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 15387#L544 assume 1 == ~t8_pc~0; 15647#L545 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 15047#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 15048#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 15190#L1089 assume !(0 != activate_threads_~tmp___7~0); 15869#L1089-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15520#L921 assume !(1 == ~M_E~0); 15521#L921-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15265#L926-1 assume !(1 == ~T2_E~0); 15266#L931-1 assume !(1 == ~T3_E~0); 15916#L936-1 assume !(1 == ~T4_E~0); 15773#L941-1 assume !(1 == ~T5_E~0); 15518#L946-1 assume !(1 == ~T6_E~0); 15065#L951-1 assume !(1 == ~T7_E~0); 15066#L956-1 assume !(1 == ~T8_E~0); 15844#L961-1 assume 1 == ~E_1~0;~E_1~0 := 2; 15609#L966-1 assume !(1 == ~E_2~0); 15390#L971-1 assume !(1 == ~E_3~0); 15391#L976-1 assume !(1 == ~E_4~0); 15813#L981-1 assume !(1 == ~E_5~0); 15571#L986-1 assume !(1 == ~E_6~0); 15495#L991-1 assume !(1 == ~E_7~0); 15198#L996-1 assume !(1 == ~E_8~0); 15199#L1001-1 assume { :end_inline_reset_delta_events } true; 15729#L1262-3 [2018-11-18 14:32:30,901 INFO L796 eck$LassoCheckResult]: Loop: 15729#L1262-3 assume true; 15938#L1262-1 assume !false; 15939#L1263 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 15532#L803 assume true; 15442#L681-1 assume !false; 15443#L682 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 15516#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 15182#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 15914#L672 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 15131#L686 assume !(0 != eval_~tmp~0); 15133#L818 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 15140#L564-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 15849#L828-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15850#L828-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15635#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15261#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15262#L843-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15912#L848-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15769#L853-3 assume !(0 == ~T6_E~0); 15515#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15058#L863-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 15059#L868-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15720#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15605#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15382#L883-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15383#L888-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15821#L893-3 assume !(0 == ~E_6~0); 15574#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15486#L903-3 assume 0 == ~E_8~0;~E_8~0 := 1; 15194#L908-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 15195#L392-27 assume 1 == ~m_pc~0; 15619#L393-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 15620#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 15949#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 15862#L1025-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 15856#L1025-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 15644#L411-27 assume !(1 == ~t1_pc~0); 15645#L411-29 is_transmit1_triggered_~__retres1~1 := 0; 15072#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 15073#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 15210#L1033-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 15401#L1033-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 15406#L430-27 assume 1 == ~t2_pc~0; 15797#L431-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 15298#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 15299#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 15395#L1041-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 15931#L1041-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 15893#L449-27 assume 1 == ~t3_pc~0; 15863#L450-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 15458#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 15399#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 15400#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 15666#L1049-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 15671#L468-27 assume 1 == ~t4_pc~0; 15944#L469-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 15736#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 15548#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 15297#L1057-27 assume !(0 != activate_threads_~tmp___3~0); 15271#L1057-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 15136#L487-27 assume 1 == ~t5_pc~0; 15109#L488-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 15110#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 15692#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 15693#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 15899#L1065-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 15494#L506-27 assume 1 == ~t6_pc~0; 15289#L507-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 15291#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 15827#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 15737#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 15576#L1073-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 15577#L525-27 assume 1 == ~t7_pc~0; 15481#L526-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 15482#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 15910#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 15344#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 15345#L1081-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 15348#L544-27 assume 1 == ~t8_pc~0; 15731#L545-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 15228#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 15147#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 15148#L1089-27 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 15919#L1089-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15528#L921-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15529#L921-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15267#L926-3 assume !(1 == ~T2_E~0); 15268#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15917#L936-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15775#L941-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 15519#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 15051#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15052#L956-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 15718#L961-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15602#L966-3 assume !(1 == ~E_2~0); 15377#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15378#L976-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15816#L981-3 assume 1 == ~E_5~0;~E_5~0 := 2; 15572#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15499#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 15203#L996-3 assume 1 == ~E_8~0;~E_8~0 := 2; 15204#L1001-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 15930#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 15185#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 15915#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 15093#L1281 assume !(0 == start_simulation_~tmp~3); 15094#L1281-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 15106#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 15188#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 15837#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 15341#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 15342#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 15877#L1244 start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 15728#L1294 assume !(0 != start_simulation_~tmp___0~1); 15729#L1262-3 [2018-11-18 14:32:30,902 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:30,902 INFO L82 PathProgramCache]: Analyzing trace with hash -1253090466, now seen corresponding path program 1 times [2018-11-18 14:32:30,902 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:30,902 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:30,903 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:30,903 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:30,903 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:30,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:30,950 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:30,951 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:30,951 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 14:32:30,951 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 14:32:30,951 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:30,951 INFO L82 PathProgramCache]: Analyzing trace with hash 1409879850, now seen corresponding path program 5 times [2018-11-18 14:32:30,951 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:30,952 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:30,952 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:30,952 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:30,952 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:30,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:31,000 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:31,001 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:31,001 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:32:31,001 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 14:32:31,001 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 14:32:31,002 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 14:32:31,002 INFO L87 Difference]: Start difference. First operand 936 states and 1384 transitions. cyclomatic complexity: 449 Second operand 3 states. [2018-11-18 14:32:31,029 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:32:31,029 INFO L93 Difference]: Finished difference Result 936 states and 1379 transitions. [2018-11-18 14:32:31,030 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 14:32:31,030 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 936 states and 1379 transitions. [2018-11-18 14:32:31,036 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 823 [2018-11-18 14:32:31,039 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 936 states to 936 states and 1379 transitions. [2018-11-18 14:32:31,039 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 936 [2018-11-18 14:32:31,041 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 936 [2018-11-18 14:32:31,041 INFO L73 IsDeterministic]: Start isDeterministic. Operand 936 states and 1379 transitions. [2018-11-18 14:32:31,042 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:32:31,043 INFO L705 BuchiCegarLoop]: Abstraction has 936 states and 1379 transitions. [2018-11-18 14:32:31,044 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 936 states and 1379 transitions. [2018-11-18 14:32:31,056 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 936 to 936. [2018-11-18 14:32:31,056 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 936 states. [2018-11-18 14:32:31,059 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 936 states to 936 states and 1379 transitions. [2018-11-18 14:32:31,060 INFO L728 BuchiCegarLoop]: Abstraction has 936 states and 1379 transitions. [2018-11-18 14:32:31,060 INFO L608 BuchiCegarLoop]: Abstraction has 936 states and 1379 transitions. [2018-11-18 14:32:31,060 INFO L442 BuchiCegarLoop]: ======== Iteration 10============ [2018-11-18 14:32:31,060 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 936 states and 1379 transitions. [2018-11-18 14:32:31,066 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 823 [2018-11-18 14:32:31,066 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:32:31,066 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:32:31,068 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:31,068 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:31,068 INFO L794 eck$LassoCheckResult]: Stem: 17388#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 17287#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 17288#L1225 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 17724#L564 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17324#L571 assume 1 == ~m_i~0;~m_st~0 := 0; 17305#L571-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17016#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17017#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17726#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17510#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 17133#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 17134#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 17718#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 17635#L611-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17636#L828 assume !(0 == ~M_E~0); 17733#L828-2 assume !(0 == ~T1_E~0); 17409#L833-1 assume !(0 == ~T2_E~0); 17148#L838-1 assume !(0 == ~T3_E~0); 17149#L843-1 assume !(0 == ~T4_E~0); 17797#L848-1 assume !(0 == ~T5_E~0); 17645#L853-1 assume !(0 == ~T6_E~0); 17392#L858-1 assume !(0 == ~T7_E~0); 16932#L863-1 assume !(0 == ~T8_E~0); 16933#L868-1 assume !(0 == ~E_1~0); 17598#L873-1 assume !(0 == ~E_2~0); 17483#L878-1 assume !(0 == ~E_3~0); 17258#L883-1 assume !(0 == ~E_4~0); 17259#L888-1 assume 0 == ~E_5~0;~E_5~0 := 1; 17696#L893-1 assume !(0 == ~E_6~0); 17452#L898-1 assume !(0 == ~E_7~0); 17380#L903-1 assume !(0 == ~E_8~0); 17087#L908-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 17088#L392 assume !(1 == ~m_pc~0); 17432#L392-2 is_master_triggered_~__retres1~0 := 0; 17438#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 17830#L404 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 17703#L1025 assume !(0 != activate_threads_~tmp~1); 17704#L1025-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 17585#L411 assume 1 == ~t1_pc~0; 17586#L412 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 17001#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 17002#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 17115#L1033 assume !(0 != activate_threads_~tmp___0~0); 17331#L1033-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 17332#L430 assume 1 == ~t2_pc~0; 17682#L431 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 17184#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 17135#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 17136#L1041 assume !(0 != activate_threads_~tmp___1~0); 17848#L1041-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 17849#L449 assume !(1 == ~t3_pc~0); 17763#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 17469#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 17306#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 17307#L1049 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 17722#L1049-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 17034#L468 assume 1 == ~t4_pc~0; 17035#L469 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 17044#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 17445#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 17384#L1057 assume !(0 != activate_threads_~tmp___3~0); 17385#L1057-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 17244#L487 assume !(1 == ~t5_pc~0); 16993#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 16994#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 17573#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 17574#L1065 assume !(0 != activate_threads_~tmp___4~0); 17861#L1065-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 17391#L506 assume 1 == ~t6_pc~0; 17210#L507 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 17211#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 17720#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 17657#L1073 assume !(0 != activate_threads_~tmp___5~0); 17658#L1073-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 17511#L525 assume !(1 == ~t7_pc~0); 17462#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 17461#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 17850#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 17264#L1081 assume !(0 != activate_threads_~tmp___6~0); 17265#L1081-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 17266#L544 assume 1 == ~t8_pc~0; 17526#L545 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 16926#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 16927#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 17069#L1089 assume !(0 != activate_threads_~tmp___7~0); 17748#L1089-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17399#L921 assume !(1 == ~M_E~0); 17400#L921-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17144#L926-1 assume !(1 == ~T2_E~0); 17145#L931-1 assume !(1 == ~T3_E~0); 17795#L936-1 assume !(1 == ~T4_E~0); 17652#L941-1 assume !(1 == ~T5_E~0); 17397#L946-1 assume !(1 == ~T6_E~0); 16944#L951-1 assume !(1 == ~T7_E~0); 16945#L956-1 assume !(1 == ~T8_E~0); 17723#L961-1 assume 1 == ~E_1~0;~E_1~0 := 2; 17488#L966-1 assume !(1 == ~E_2~0); 17269#L971-1 assume !(1 == ~E_3~0); 17270#L976-1 assume !(1 == ~E_4~0); 17692#L981-1 assume !(1 == ~E_5~0); 17450#L986-1 assume !(1 == ~E_6~0); 17374#L991-1 assume !(1 == ~E_7~0); 17077#L996-1 assume !(1 == ~E_8~0); 17078#L1001-1 assume { :end_inline_reset_delta_events } true; 17608#L1262-3 [2018-11-18 14:32:31,068 INFO L796 eck$LassoCheckResult]: Loop: 17608#L1262-3 assume true; 17817#L1262-1 assume !false; 17818#L1263 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 17411#L803 assume true; 17320#L681-1 assume !false; 17321#L682 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 17395#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 17061#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 17793#L672 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 17010#L686 assume !(0 != eval_~tmp~0); 17012#L818 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 17019#L564-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 17728#L828-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17729#L828-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17514#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17140#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17141#L843-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17791#L848-3 assume !(0 == ~T5_E~0); 17648#L853-3 assume !(0 == ~T6_E~0); 17394#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16937#L863-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16938#L868-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17599#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17484#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17261#L883-3 assume 0 == ~E_4~0;~E_4~0 := 1; 17262#L888-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17700#L893-3 assume !(0 == ~E_6~0); 17453#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17366#L903-3 assume 0 == ~E_8~0;~E_8~0 := 1; 17073#L908-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 17074#L392-27 assume 1 == ~m_pc~0; 17499#L393-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 17500#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 17828#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 17741#L1025-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 17735#L1025-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 17523#L411-27 assume !(1 == ~t1_pc~0); 17524#L411-29 is_transmit1_triggered_~__retres1~1 := 0; 16951#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 16952#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 17089#L1033-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 17280#L1033-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 17285#L430-27 assume 1 == ~t2_pc~0; 17676#L431-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 17177#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 17178#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 17274#L1041-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 17810#L1041-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 17772#L449-27 assume 1 == ~t3_pc~0; 17742#L450-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 17337#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 17278#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 17279#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 17544#L1049-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 17550#L468-27 assume 1 == ~t4_pc~0; 17822#L469-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 17615#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 17427#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 17176#L1057-27 assume !(0 != activate_threads_~tmp___3~0); 17150#L1057-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 17015#L487-27 assume 1 == ~t5_pc~0; 16986#L488-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5 := 1; 16987#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 17571#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 17572#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 17778#L1065-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 17373#L506-27 assume 1 == ~t6_pc~0; 17168#L507-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 17170#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 17706#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 17616#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 17455#L1073-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 17456#L525-27 assume 1 == ~t7_pc~0; 17360#L526-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 17361#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 17789#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 17223#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 17224#L1081-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 17227#L544-27 assume 1 == ~t8_pc~0; 17610#L545-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 17106#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 17026#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 17027#L1089-27 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 17798#L1089-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17404#L921-3 assume 1 == ~M_E~0;~M_E~0 := 2; 17405#L921-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17146#L926-3 assume !(1 == ~T2_E~0); 17147#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17796#L936-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17654#L941-3 assume !(1 == ~T5_E~0); 17398#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16930#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16931#L956-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 17597#L961-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17481#L966-3 assume !(1 == ~E_2~0); 17256#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 17257#L976-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17695#L981-3 assume 1 == ~E_5~0;~E_5~0 := 2; 17451#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 17378#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 17082#L996-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17083#L1001-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 17809#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 17064#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 17794#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 16972#L1281 assume !(0 == start_simulation_~tmp~3); 16973#L1281-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 16985#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 17067#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 17716#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 17220#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 17221#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 17756#L1244 start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 17607#L1294 assume !(0 != start_simulation_~tmp___0~1); 17608#L1262-3 [2018-11-18 14:32:31,069 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:31,069 INFO L82 PathProgramCache]: Analyzing trace with hash 623392352, now seen corresponding path program 1 times [2018-11-18 14:32:31,069 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:31,069 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:31,074 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:31,074 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 14:32:31,074 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:31,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:31,124 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:31,125 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:31,125 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 14:32:31,125 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 14:32:31,125 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:31,125 INFO L82 PathProgramCache]: Analyzing trace with hash -1143467730, now seen corresponding path program 1 times [2018-11-18 14:32:31,128 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:31,128 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:31,129 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:31,129 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:31,129 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:31,135 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:31,169 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:31,170 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:31,170 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:32:31,170 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 14:32:31,170 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 14:32:31,170 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 14:32:31,171 INFO L87 Difference]: Start difference. First operand 936 states and 1379 transitions. cyclomatic complexity: 444 Second operand 3 states. [2018-11-18 14:32:31,224 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:32:31,224 INFO L93 Difference]: Finished difference Result 936 states and 1364 transitions. [2018-11-18 14:32:31,224 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 14:32:31,224 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 936 states and 1364 transitions. [2018-11-18 14:32:31,227 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 823 [2018-11-18 14:32:31,229 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 936 states to 936 states and 1364 transitions. [2018-11-18 14:32:31,229 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 936 [2018-11-18 14:32:31,230 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 936 [2018-11-18 14:32:31,230 INFO L73 IsDeterministic]: Start isDeterministic. Operand 936 states and 1364 transitions. [2018-11-18 14:32:31,231 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:32:31,231 INFO L705 BuchiCegarLoop]: Abstraction has 936 states and 1364 transitions. [2018-11-18 14:32:31,232 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 936 states and 1364 transitions. [2018-11-18 14:32:31,239 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 936 to 936. [2018-11-18 14:32:31,239 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 936 states. [2018-11-18 14:32:31,240 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 936 states to 936 states and 1364 transitions. [2018-11-18 14:32:31,241 INFO L728 BuchiCegarLoop]: Abstraction has 936 states and 1364 transitions. [2018-11-18 14:32:31,241 INFO L608 BuchiCegarLoop]: Abstraction has 936 states and 1364 transitions. [2018-11-18 14:32:31,241 INFO L442 BuchiCegarLoop]: ======== Iteration 11============ [2018-11-18 14:32:31,241 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 936 states and 1364 transitions. [2018-11-18 14:32:31,243 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 823 [2018-11-18 14:32:31,243 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:32:31,243 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:32:31,245 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:31,245 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:31,245 INFO L794 eck$LassoCheckResult]: Stem: 19267#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 19166#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 19167#L1225 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 19603#L564 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19203#L571 assume 1 == ~m_i~0;~m_st~0 := 0; 19184#L571-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18888#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18889#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 19605#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19389#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19007#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19008#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 19597#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 19514#L611-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 19515#L828 assume !(0 == ~M_E~0); 19612#L828-2 assume !(0 == ~T1_E~0); 19288#L833-1 assume !(0 == ~T2_E~0); 19022#L838-1 assume !(0 == ~T3_E~0); 19023#L843-1 assume !(0 == ~T4_E~0); 19676#L848-1 assume !(0 == ~T5_E~0); 19524#L853-1 assume !(0 == ~T6_E~0); 19271#L858-1 assume !(0 == ~T7_E~0); 18811#L863-1 assume !(0 == ~T8_E~0); 18812#L868-1 assume !(0 == ~E_1~0); 19477#L873-1 assume !(0 == ~E_2~0); 19362#L878-1 assume !(0 == ~E_3~0); 19137#L883-1 assume !(0 == ~E_4~0); 19138#L888-1 assume !(0 == ~E_5~0); 19575#L893-1 assume !(0 == ~E_6~0); 19331#L898-1 assume !(0 == ~E_7~0); 19258#L903-1 assume !(0 == ~E_8~0); 18961#L908-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 18962#L392 assume !(1 == ~m_pc~0); 19311#L392-2 is_master_triggered_~__retres1~0 := 0; 19317#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 19709#L404 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 19582#L1025 assume !(0 != activate_threads_~tmp~1); 19583#L1025-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 19464#L411 assume 1 == ~t1_pc~0; 19465#L412 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1 := 1; 18870#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 18871#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 18989#L1033 assume !(0 != activate_threads_~tmp___0~0); 19210#L1033-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 19211#L430 assume 1 == ~t2_pc~0; 19561#L431 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 19058#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 19009#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 19010#L1041 assume !(0 != activate_threads_~tmp___1~0); 19727#L1041-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 19728#L449 assume !(1 == ~t3_pc~0); 19642#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 19348#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 19185#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 19186#L1049 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 19601#L1049-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 18908#L468 assume 1 == ~t4_pc~0; 18909#L469 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 18918#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 19324#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 19263#L1057 assume !(0 != activate_threads_~tmp___3~0); 19264#L1057-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 19122#L487 assume !(1 == ~t5_pc~0); 18866#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 19124#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 19452#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 19453#L1065 assume !(0 != activate_threads_~tmp___4~0); 19740#L1065-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 19270#L506 assume 1 == ~t6_pc~0; 19084#L507 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 19085#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 19599#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 19536#L1073 assume !(0 != activate_threads_~tmp___5~0); 19537#L1073-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 19390#L525 assume !(1 == ~t7_pc~0); 19341#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 19340#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 19729#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 19143#L1081 assume !(0 != activate_threads_~tmp___6~0); 19144#L1081-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 19145#L544 assume 1 == ~t8_pc~0; 19402#L545 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 18805#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 18806#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 18943#L1089 assume !(0 != activate_threads_~tmp___7~0); 19627#L1089-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19278#L921 assume !(1 == ~M_E~0); 19279#L921-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19018#L926-1 assume !(1 == ~T2_E~0); 19019#L931-1 assume !(1 == ~T3_E~0); 19674#L936-1 assume !(1 == ~T4_E~0); 19531#L941-1 assume !(1 == ~T5_E~0); 19276#L946-1 assume !(1 == ~T6_E~0); 18823#L951-1 assume !(1 == ~T7_E~0); 18824#L956-1 assume !(1 == ~T8_E~0); 19602#L961-1 assume 1 == ~E_1~0;~E_1~0 := 2; 19367#L966-1 assume !(1 == ~E_2~0); 19148#L971-1 assume !(1 == ~E_3~0); 19149#L976-1 assume !(1 == ~E_4~0); 19571#L981-1 assume !(1 == ~E_5~0); 19329#L986-1 assume !(1 == ~E_6~0); 19253#L991-1 assume !(1 == ~E_7~0); 18951#L996-1 assume !(1 == ~E_8~0); 18952#L1001-1 assume { :end_inline_reset_delta_events } true; 19487#L1262-3 [2018-11-18 14:32:31,246 INFO L796 eck$LassoCheckResult]: Loop: 19487#L1262-3 assume true; 19696#L1262-1 assume !false; 19697#L1263 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 19290#L803 assume true; 19199#L681-1 assume !false; 19200#L682 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 19274#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 18935#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 19672#L672 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 18880#L686 assume !(0 != eval_~tmp~0); 18882#L818 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 18892#L564-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 19607#L828-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19608#L828-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19393#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19014#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19015#L843-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 19670#L848-3 assume !(0 == ~T5_E~0); 19527#L853-3 assume !(0 == ~T6_E~0); 19273#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 18816#L863-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 18817#L868-3 assume 0 == ~E_1~0;~E_1~0 := 1; 19478#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 19363#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19140#L883-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19141#L888-3 assume !(0 == ~E_5~0); 19579#L893-3 assume !(0 == ~E_6~0); 19332#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 19244#L903-3 assume 0 == ~E_8~0;~E_8~0 := 1; 18947#L908-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 18948#L392-27 assume 1 == ~m_pc~0; 19378#L393-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 19379#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 19707#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 19620#L1025-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 19614#L1025-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 19404#L411-27 assume !(1 == ~t1_pc~0); 19405#L411-29 is_transmit1_triggered_~__retres1~1 := 0; 18829#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 18830#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 18965#L1033-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 19161#L1033-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 19164#L430-27 assume 1 == ~t2_pc~0; 19555#L431-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 19051#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 19052#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 19153#L1041-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 19690#L1041-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 19651#L449-27 assume 1 == ~t3_pc~0; 19621#L450-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 19216#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 19157#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 19158#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 19423#L1049-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 19429#L468-27 assume 1 == ~t4_pc~0; 19701#L469-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 19494#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 19306#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 19050#L1057-27 assume !(0 != activate_threads_~tmp___3~0); 19024#L1057-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 18886#L487-27 assume !(1 == ~t5_pc~0); 18861#L487-29 is_transmit5_triggered_~__retres1~5 := 0; 18887#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 19449#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 19450#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 19657#L1065-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 19252#L506-27 assume 1 == ~t6_pc~0; 19040#L507-9 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 19042#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 19585#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 19495#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 19334#L1073-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 19335#L525-27 assume 1 == ~t7_pc~0; 19238#L526-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 19239#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 19668#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 19098#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 19099#L1081-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 19103#L544-27 assume 1 == ~t8_pc~0; 19488#L545-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 18980#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 18900#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 18901#L1089-27 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 19677#L1089-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19283#L921-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19284#L921-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19020#L926-3 assume !(1 == ~T2_E~0); 19021#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 19675#L936-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19533#L941-3 assume !(1 == ~T5_E~0); 19277#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18809#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 18810#L956-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19475#L961-3 assume 1 == ~E_1~0;~E_1~0 := 2; 19360#L966-3 assume !(1 == ~E_2~0); 19135#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19136#L976-3 assume 1 == ~E_4~0;~E_4~0 := 2; 19574#L981-3 assume !(1 == ~E_5~0); 19330#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19257#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 18956#L996-3 assume 1 == ~E_8~0;~E_8~0 := 2; 18957#L1001-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 19688#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 18938#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 19673#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 18848#L1281 assume !(0 == start_simulation_~tmp~3); 18849#L1281-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 18859#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 18941#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 19595#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 19095#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 19096#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 19635#L1244 start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 19486#L1294 assume !(0 != start_simulation_~tmp___0~1); 19487#L1262-3 [2018-11-18 14:32:31,246 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:31,246 INFO L82 PathProgramCache]: Analyzing trace with hash 650457954, now seen corresponding path program 1 times [2018-11-18 14:32:31,246 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:31,246 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:31,247 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:31,247 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:31,247 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:31,251 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:31,273 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:31,273 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:31,273 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 14:32:31,273 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 14:32:31,274 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:31,274 INFO L82 PathProgramCache]: Analyzing trace with hash 895219345, now seen corresponding path program 1 times [2018-11-18 14:32:31,274 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:31,274 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:31,275 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:31,275 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:31,275 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:31,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:31,298 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:31,298 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:31,298 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:32:31,298 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 14:32:31,299 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 14:32:31,299 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 14:32:31,299 INFO L87 Difference]: Start difference. First operand 936 states and 1364 transitions. cyclomatic complexity: 429 Second operand 3 states. [2018-11-18 14:32:31,378 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:32:31,379 INFO L93 Difference]: Finished difference Result 1683 states and 2435 transitions. [2018-11-18 14:32:31,380 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 14:32:31,380 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1683 states and 2435 transitions. [2018-11-18 14:32:31,384 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1569 [2018-11-18 14:32:31,388 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1683 states to 1683 states and 2435 transitions. [2018-11-18 14:32:31,388 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1683 [2018-11-18 14:32:31,389 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1683 [2018-11-18 14:32:31,389 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1683 states and 2435 transitions. [2018-11-18 14:32:31,391 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:32:31,391 INFO L705 BuchiCegarLoop]: Abstraction has 1683 states and 2435 transitions. [2018-11-18 14:32:31,393 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1683 states and 2435 transitions. [2018-11-18 14:32:31,407 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1683 to 1680. [2018-11-18 14:32:31,407 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1680 states. [2018-11-18 14:32:31,409 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1680 states to 1680 states and 2432 transitions. [2018-11-18 14:32:31,410 INFO L728 BuchiCegarLoop]: Abstraction has 1680 states and 2432 transitions. [2018-11-18 14:32:31,410 INFO L608 BuchiCegarLoop]: Abstraction has 1680 states and 2432 transitions. [2018-11-18 14:32:31,410 INFO L442 BuchiCegarLoop]: ======== Iteration 12============ [2018-11-18 14:32:31,410 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1680 states and 2432 transitions. [2018-11-18 14:32:31,414 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1566 [2018-11-18 14:32:31,414 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:32:31,414 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:32:31,415 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:31,415 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:31,415 INFO L794 eck$LassoCheckResult]: Stem: 21898#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 21795#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 21796#L1225 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 22256#L564 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21832#L571 assume 1 == ~m_i~0;~m_st~0 := 0; 21813#L571-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21514#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21515#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 22258#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22024#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 21636#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 21637#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 22250#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 22144#L611-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22145#L828 assume !(0 == ~M_E~0); 22265#L828-2 assume !(0 == ~T1_E~0); 21919#L833-1 assume !(0 == ~T2_E~0); 21651#L838-1 assume !(0 == ~T3_E~0); 21652#L843-1 assume !(0 == ~T4_E~0); 22330#L848-1 assume !(0 == ~T5_E~0); 22154#L853-1 assume !(0 == ~T6_E~0); 21902#L858-1 assume !(0 == ~T7_E~0); 21437#L863-1 assume !(0 == ~T8_E~0); 21438#L868-1 assume !(0 == ~E_1~0); 22105#L873-1 assume !(0 == ~E_2~0); 21997#L878-1 assume !(0 == ~E_3~0); 21766#L883-1 assume !(0 == ~E_4~0); 21767#L888-1 assume !(0 == ~E_5~0); 22228#L893-1 assume !(0 == ~E_6~0); 21963#L898-1 assume !(0 == ~E_7~0); 21889#L903-1 assume !(0 == ~E_8~0); 21588#L908-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 21589#L392 assume !(1 == ~m_pc~0); 21942#L392-2 is_master_triggered_~__retres1~0 := 0; 21949#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 22364#L404 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 22235#L1025 assume !(0 != activate_threads_~tmp~1); 22236#L1025-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 22093#L411 assume !(1 == ~t1_pc~0); 22063#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 21498#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 21499#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 21618#L1033 assume !(0 != activate_threads_~tmp___0~0); 21839#L1033-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 21840#L430 assume 1 == ~t2_pc~0; 22214#L431 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 21687#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 21638#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 21639#L1041 assume !(0 != activate_threads_~tmp___1~0); 22382#L1041-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 22383#L449 assume !(1 == ~t3_pc~0); 22295#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 21981#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 21814#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 21815#L1049 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 22254#L1049-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 21534#L468 assume 1 == ~t4_pc~0; 21535#L469 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 21545#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 21956#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 21894#L1057 assume !(0 != activate_threads_~tmp___3~0); 21895#L1057-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 21751#L487 assume !(1 == ~t5_pc~0); 21492#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 21753#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 22081#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 22082#L1065 assume !(0 != activate_threads_~tmp___4~0); 22396#L1065-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 21901#L506 assume 1 == ~t6_pc~0; 21713#L507 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 21714#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 22252#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 22174#L1073 assume !(0 != activate_threads_~tmp___5~0); 22175#L1073-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 22025#L525 assume !(1 == ~t7_pc~0); 21974#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 21973#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 22384#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 21772#L1081 assume !(0 != activate_threads_~tmp___6~0); 21773#L1081-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 21774#L544 assume 1 == ~t8_pc~0; 22038#L545 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 21431#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 21432#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 21570#L1089 assume !(0 != activate_threads_~tmp___7~0); 22280#L1089-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21909#L921 assume !(1 == ~M_E~0); 21910#L921-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21647#L926-1 assume !(1 == ~T2_E~0); 21648#L931-1 assume !(1 == ~T3_E~0); 22328#L936-1 assume !(1 == ~T4_E~0); 22164#L941-1 assume !(1 == ~T5_E~0); 21907#L946-1 assume !(1 == ~T6_E~0); 21449#L951-1 assume !(1 == ~T7_E~0); 21450#L956-1 assume !(1 == ~T8_E~0); 22255#L961-1 assume 1 == ~E_1~0;~E_1~0 := 2; 22002#L966-1 assume !(1 == ~E_2~0); 21777#L971-1 assume !(1 == ~E_3~0); 21778#L976-1 assume !(1 == ~E_4~0); 22224#L981-1 assume !(1 == ~E_5~0); 21961#L986-1 assume !(1 == ~E_6~0); 21883#L991-1 assume !(1 == ~E_7~0); 21578#L996-1 assume !(1 == ~E_8~0); 21579#L1001-1 assume { :end_inline_reset_delta_events } true; 22115#L1262-3 [2018-11-18 14:32:31,416 INFO L796 eck$LassoCheckResult]: Loop: 22115#L1262-3 assume true; 22352#L1262-1 assume !false; 22353#L1263 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 21921#L803 assume true; 21828#L681-1 assume !false; 21829#L682 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 21905#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 21562#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 22342#L672 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 21506#L686 assume !(0 != eval_~tmp~0); 21508#L818 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 21518#L564-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 22260#L828-3 assume 0 == ~M_E~0;~M_E~0 := 1; 22261#L828-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22028#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21643#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21644#L843-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 22323#L848-3 assume !(0 == ~T5_E~0); 22157#L853-3 assume !(0 == ~T6_E~0); 21904#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 21442#L863-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 21443#L868-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22106#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21998#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 21769#L883-3 assume 0 == ~E_4~0;~E_4~0 := 1; 21770#L888-3 assume !(0 == ~E_5~0); 22232#L893-3 assume !(0 == ~E_6~0); 21964#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 21873#L903-3 assume 0 == ~E_8~0;~E_8~0 := 1; 21574#L908-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 21575#L392-27 assume 1 == ~m_pc~0; 22012#L393-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 22013#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 22363#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 22273#L1025-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 22267#L1025-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 22036#L411-27 assume !(1 == ~t1_pc~0); 22037#L411-29 is_transmit1_triggered_~__retres1~1 := 0; 23110#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 23109#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 23108#L1033-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 23107#L1033-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 23106#L430-27 assume 1 == ~t2_pc~0; 23104#L431-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2 := 1; 23103#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 23102#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 23101#L1041-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 23100#L1041-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 23099#L449-27 assume !(1 == ~t3_pc~0); 23097#L449-29 is_transmit3_triggered_~__retres1~3 := 0; 23096#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 23095#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 23094#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 23093#L1049-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 23092#L468-27 assume 1 == ~t4_pc~0; 23090#L469-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 23089#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 23088#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 23087#L1057-27 assume !(0 != activate_threads_~tmp___3~0); 23086#L1057-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 23085#L487-27 assume !(1 == ~t5_pc~0); 23083#L487-29 is_transmit5_triggered_~__retres1~5 := 0; 23082#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 23081#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 23080#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 23079#L1065-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 23078#L506-27 assume !(1 == ~t6_pc~0); 23076#L506-29 is_transmit6_triggered_~__retres1~6 := 0; 23075#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 22919#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 22918#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 22917#L1073-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 22916#L525-27 assume 1 == ~t7_pc~0; 21868#L526-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 21869#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 22321#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 21727#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 21728#L1081-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 21732#L544-27 assume 1 == ~t8_pc~0; 22117#L545-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 21608#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 21609#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 22883#L1089-27 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 22331#L1089-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21914#L921-3 assume 1 == ~M_E~0;~M_E~0 := 2; 21915#L921-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21649#L926-3 assume !(1 == ~T2_E~0); 21650#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22329#L936-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22166#L941-3 assume !(1 == ~T5_E~0); 21908#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21435#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 21436#L956-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 22104#L961-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21995#L966-3 assume !(1 == ~E_2~0); 21764#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 21765#L976-3 assume 1 == ~E_4~0;~E_4~0 := 2; 22227#L981-3 assume !(1 == ~E_5~0); 21962#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 21887#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 21583#L996-3 assume 1 == ~E_8~0;~E_8~0 := 2; 21584#L1001-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 22344#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 21565#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 22327#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 21474#L1281 assume !(0 == start_simulation_~tmp~3); 21475#L1281-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 21485#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 21568#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 22248#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 21724#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 21725#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 22288#L1244 start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 22114#L1294 assume !(0 != start_simulation_~tmp___0~1); 22115#L1262-3 [2018-11-18 14:32:31,416 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:31,416 INFO L82 PathProgramCache]: Analyzing trace with hash -527516607, now seen corresponding path program 1 times [2018-11-18 14:32:31,416 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:31,416 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:31,417 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:31,417 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:31,417 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:31,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:31,449 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:31,449 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:31,449 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 14:32:31,449 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 14:32:31,450 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:31,450 INFO L82 PathProgramCache]: Analyzing trace with hash 1150079503, now seen corresponding path program 1 times [2018-11-18 14:32:31,450 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:31,450 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:31,451 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:31,451 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:31,451 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:31,459 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:31,482 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:31,482 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:31,482 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:32:31,483 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 14:32:31,483 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 14:32:31,483 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 14:32:31,483 INFO L87 Difference]: Start difference. First operand 1680 states and 2432 transitions. cyclomatic complexity: 754 Second operand 3 states. [2018-11-18 14:32:31,547 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:32:31,547 INFO L93 Difference]: Finished difference Result 3099 states and 4460 transitions. [2018-11-18 14:32:31,548 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 14:32:31,549 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3099 states and 4460 transitions. [2018-11-18 14:32:31,556 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2980 [2018-11-18 14:32:31,563 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3099 states to 3099 states and 4460 transitions. [2018-11-18 14:32:31,563 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3099 [2018-11-18 14:32:31,565 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3099 [2018-11-18 14:32:31,565 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3099 states and 4460 transitions. [2018-11-18 14:32:31,568 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:32:31,568 INFO L705 BuchiCegarLoop]: Abstraction has 3099 states and 4460 transitions. [2018-11-18 14:32:31,570 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3099 states and 4460 transitions. [2018-11-18 14:32:31,590 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3099 to 3093. [2018-11-18 14:32:31,590 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3093 states. [2018-11-18 14:32:31,594 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3093 states to 3093 states and 4454 transitions. [2018-11-18 14:32:31,594 INFO L728 BuchiCegarLoop]: Abstraction has 3093 states and 4454 transitions. [2018-11-18 14:32:31,595 INFO L608 BuchiCegarLoop]: Abstraction has 3093 states and 4454 transitions. [2018-11-18 14:32:31,595 INFO L442 BuchiCegarLoop]: ======== Iteration 13============ [2018-11-18 14:32:31,595 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3093 states and 4454 transitions. [2018-11-18 14:32:31,601 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2974 [2018-11-18 14:32:31,601 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:32:31,601 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:32:31,602 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:31,602 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:31,603 INFO L794 eck$LassoCheckResult]: Stem: 26680#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 26579#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 26580#L1225 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 27029#L564 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26616#L571 assume 1 == ~m_i~0;~m_st~0 := 0; 26597#L571-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 26301#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 26302#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27031#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 26804#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 26420#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 26421#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 27023#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 26928#L611-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 26929#L828 assume !(0 == ~M_E~0); 27038#L828-2 assume !(0 == ~T1_E~0); 26701#L833-1 assume !(0 == ~T2_E~0); 26435#L838-1 assume !(0 == ~T3_E~0); 26436#L843-1 assume !(0 == ~T4_E~0); 27104#L848-1 assume !(0 == ~T5_E~0); 26938#L853-1 assume !(0 == ~T6_E~0); 26684#L858-1 assume !(0 == ~T7_E~0); 26223#L863-1 assume !(0 == ~T8_E~0); 26224#L868-1 assume !(0 == ~E_1~0); 26889#L873-1 assume !(0 == ~E_2~0); 26775#L878-1 assume !(0 == ~E_3~0); 26550#L883-1 assume !(0 == ~E_4~0); 26551#L888-1 assume !(0 == ~E_5~0); 26997#L893-1 assume !(0 == ~E_6~0); 26744#L898-1 assume !(0 == ~E_7~0); 26672#L903-1 assume !(0 == ~E_8~0); 26374#L908-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 26375#L392 assume !(1 == ~m_pc~0); 26724#L392-2 is_master_triggered_~__retres1~0 := 0; 26730#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 27139#L404 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 27005#L1025 assume !(0 != activate_threads_~tmp~1); 27006#L1025-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 26877#L411 assume !(1 == ~t1_pc~0); 26845#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 26284#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 26285#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 26402#L1033 assume !(0 != activate_threads_~tmp___0~0); 26623#L1033-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 26624#L430 assume !(1 == ~t2_pc~0); 27014#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 26471#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 26422#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 26423#L1041 assume !(0 != activate_threads_~tmp___1~0); 27158#L1041-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 27159#L449 assume !(1 == ~t3_pc~0); 27070#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 26761#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 26598#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 26599#L1049 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 27027#L1049-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 26321#L468 assume 1 == ~t4_pc~0; 26322#L469 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 26331#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 26737#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 26676#L1057 assume !(0 != activate_threads_~tmp___3~0); 26677#L1057-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 26535#L487 assume !(1 == ~t5_pc~0); 26278#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 26537#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 26865#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 26866#L1065 assume !(0 != activate_threads_~tmp___4~0); 27172#L1065-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 26683#L506 assume 1 == ~t6_pc~0; 26497#L507 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 26498#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 27025#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 26951#L1073 assume !(0 != activate_threads_~tmp___5~0); 26952#L1073-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 26805#L525 assume !(1 == ~t7_pc~0); 26754#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 26753#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 27160#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 26556#L1081 assume !(0 != activate_threads_~tmp___6~0); 26557#L1081-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 26558#L544 assume 1 == ~t8_pc~0; 26820#L545 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 26217#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 26218#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 26356#L1089 assume !(0 != activate_threads_~tmp___7~0); 27054#L1089-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26691#L921 assume !(1 == ~M_E~0); 26692#L921-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 26431#L926-1 assume !(1 == ~T2_E~0); 26432#L931-1 assume !(1 == ~T3_E~0); 27102#L936-1 assume !(1 == ~T4_E~0); 26946#L941-1 assume !(1 == ~T5_E~0); 26689#L946-1 assume !(1 == ~T6_E~0); 26235#L951-1 assume !(1 == ~T7_E~0); 26236#L956-1 assume !(1 == ~T8_E~0); 27028#L961-1 assume 1 == ~E_1~0;~E_1~0 := 2; 26780#L966-1 assume !(1 == ~E_2~0); 26561#L971-1 assume !(1 == ~E_3~0); 26562#L976-1 assume !(1 == ~E_4~0); 26993#L981-1 assume !(1 == ~E_5~0); 26742#L986-1 assume !(1 == ~E_6~0); 26666#L991-1 assume !(1 == ~E_7~0); 26364#L996-1 assume !(1 == ~E_8~0); 26365#L1001-1 assume { :end_inline_reset_delta_events } true; 27117#L1262-3 [2018-11-18 14:32:31,603 INFO L796 eck$LassoCheckResult]: Loop: 27117#L1262-3 assume true; 28534#L1262-1 assume !false; 28525#L1263 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 28478#L803 assume true; 28475#L681-1 assume !false; 28473#L682 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 28419#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 28410#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 28203#L672 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 28199#L686 assume !(0 != eval_~tmp~0); 28200#L818 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 29090#L564-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 29088#L828-3 assume 0 == ~M_E~0;~M_E~0 := 1; 29086#L828-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29083#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 29081#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 29079#L843-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 29077#L848-3 assume !(0 == ~T5_E~0); 29075#L853-3 assume !(0 == ~T6_E~0); 29073#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 29070#L863-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 29068#L868-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29067#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29066#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29065#L883-3 assume 0 == ~E_4~0;~E_4~0 := 1; 29064#L888-3 assume !(0 == ~E_5~0); 28873#L893-3 assume !(0 == ~E_6~0); 28870#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 28868#L903-3 assume 0 == ~E_8~0;~E_8~0 := 1; 28866#L908-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 28864#L392-27 assume 1 == ~m_pc~0; 28861#L393-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 28859#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 28857#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 28855#L1025-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 28853#L1025-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 28851#L411-27 assume !(1 == ~t1_pc~0); 28849#L411-29 is_transmit1_triggered_~__retres1~1 := 0; 28847#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 28845#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 28843#L1033-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 28841#L1033-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 28839#L430-27 assume !(1 == ~t2_pc~0); 28837#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 28835#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 28832#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 28830#L1041-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 28828#L1041-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 28826#L449-27 assume !(1 == ~t3_pc~0); 28823#L449-29 is_transmit3_triggered_~__retres1~3 := 0; 28821#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 28818#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 28816#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 28814#L1049-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 28812#L468-27 assume 1 == ~t4_pc~0; 28809#L469-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4 := 1; 28806#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 28804#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 28802#L1057-27 assume !(0 != activate_threads_~tmp___3~0); 28800#L1057-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 28798#L487-27 assume !(1 == ~t5_pc~0); 28795#L487-29 is_transmit5_triggered_~__retres1~5 := 0; 28793#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 28790#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 28788#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 28786#L1065-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 28784#L506-27 assume !(1 == ~t6_pc~0); 28781#L506-29 is_transmit6_triggered_~__retres1~6 := 0; 28779#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 28776#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 28774#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 28772#L1073-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 28770#L525-27 assume !(1 == ~t7_pc~0); 28768#L525-29 is_transmit7_triggered_~__retres1~7 := 0; 28765#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 28762#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 28760#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 28758#L1081-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 28756#L544-27 assume !(1 == ~t8_pc~0); 28753#L544-29 is_transmit8_triggered_~__retres1~8 := 0; 28751#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 28749#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 28747#L1089-27 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 28745#L1089-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28743#L921-3 assume 1 == ~M_E~0;~M_E~0 := 2; 28741#L921-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28739#L926-3 assume !(1 == ~T2_E~0); 28737#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 28735#L936-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28733#L941-3 assume !(1 == ~T5_E~0); 28731#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 28729#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 28727#L956-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 28725#L961-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28723#L966-3 assume !(1 == ~E_2~0); 28721#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 28719#L976-3 assume 1 == ~E_4~0;~E_4~0 := 2; 28718#L981-3 assume !(1 == ~E_5~0); 28717#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 28716#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 28715#L996-3 assume 1 == ~E_8~0;~E_8~0 := 2; 28714#L1001-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 28660#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 28651#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 28649#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 28646#L1281 assume !(0 == start_simulation_~tmp~3); 28642#L1281-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 28567#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 28557#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 28554#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 28552#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 28550#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 28548#L1244 start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 28546#L1294 assume !(0 != start_simulation_~tmp___0~1); 27117#L1262-3 [2018-11-18 14:32:31,603 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:31,603 INFO L82 PathProgramCache]: Analyzing trace with hash 1860966496, now seen corresponding path program 1 times [2018-11-18 14:32:31,603 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:31,603 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:31,604 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:31,604 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:31,604 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:31,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:31,633 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:31,633 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:31,634 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 14:32:31,634 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 14:32:31,634 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:31,634 INFO L82 PathProgramCache]: Analyzing trace with hash 1039300268, now seen corresponding path program 1 times [2018-11-18 14:32:31,634 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:31,634 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:31,635 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:31,635 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:31,635 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:31,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:31,679 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:31,679 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:31,679 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:32:31,679 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 14:32:31,680 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 14:32:31,680 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 14:32:31,680 INFO L87 Difference]: Start difference. First operand 3093 states and 4454 transitions. cyclomatic complexity: 1365 Second operand 3 states. [2018-11-18 14:32:31,755 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:32:31,755 INFO L93 Difference]: Finished difference Result 5782 states and 8281 transitions. [2018-11-18 14:32:31,756 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 14:32:31,756 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5782 states and 8281 transitions. [2018-11-18 14:32:31,768 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5648 [2018-11-18 14:32:31,783 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5782 states to 5782 states and 8281 transitions. [2018-11-18 14:32:31,783 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5782 [2018-11-18 14:32:31,787 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5782 [2018-11-18 14:32:31,787 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5782 states and 8281 transitions. [2018-11-18 14:32:31,792 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:32:31,792 INFO L705 BuchiCegarLoop]: Abstraction has 5782 states and 8281 transitions. [2018-11-18 14:32:31,796 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5782 states and 8281 transitions. [2018-11-18 14:32:31,834 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5782 to 5770. [2018-11-18 14:32:31,834 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5770 states. [2018-11-18 14:32:31,840 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5770 states to 5770 states and 8269 transitions. [2018-11-18 14:32:31,841 INFO L728 BuchiCegarLoop]: Abstraction has 5770 states and 8269 transitions. [2018-11-18 14:32:31,841 INFO L608 BuchiCegarLoop]: Abstraction has 5770 states and 8269 transitions. [2018-11-18 14:32:31,841 INFO L442 BuchiCegarLoop]: ======== Iteration 14============ [2018-11-18 14:32:31,841 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5770 states and 8269 transitions. [2018-11-18 14:32:31,852 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5636 [2018-11-18 14:32:31,852 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:32:31,852 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:32:31,853 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:31,853 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:31,853 INFO L794 eck$LassoCheckResult]: Stem: 35568#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 35466#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 35467#L1225 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 35934#L564 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 35503#L571 assume 1 == ~m_i~0;~m_st~0 := 0; 35484#L571-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 35183#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 35184#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 35937#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 35696#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 35303#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 35304#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 35928#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 35821#L611-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 35822#L828 assume !(0 == ~M_E~0); 35944#L828-2 assume !(0 == ~T1_E~0); 35589#L833-1 assume !(0 == ~T2_E~0); 35318#L838-1 assume !(0 == ~T3_E~0); 35319#L843-1 assume !(0 == ~T4_E~0); 36026#L848-1 assume !(0 == ~T5_E~0); 35831#L853-1 assume !(0 == ~T6_E~0); 35572#L858-1 assume !(0 == ~T7_E~0); 35105#L863-1 assume !(0 == ~T8_E~0); 35106#L868-1 assume !(0 == ~E_1~0); 35779#L873-1 assume !(0 == ~E_2~0); 35666#L878-1 assume !(0 == ~E_3~0); 35436#L883-1 assume !(0 == ~E_4~0); 35437#L888-1 assume !(0 == ~E_5~0); 35903#L893-1 assume !(0 == ~E_6~0); 35633#L898-1 assume !(0 == ~E_7~0); 35560#L903-1 assume !(0 == ~E_8~0); 35254#L908-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 35255#L392 assume !(1 == ~m_pc~0); 35613#L392-2 is_master_triggered_~__retres1~0 := 0; 35619#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 36074#L404 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 35909#L1025 assume !(0 != activate_threads_~tmp~1); 35910#L1025-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 35767#L411 assume !(1 == ~t1_pc~0); 35735#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 35166#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 35167#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 35284#L1033 assume !(0 != activate_threads_~tmp___0~0); 35510#L1033-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 35511#L430 assume !(1 == ~t2_pc~0); 35919#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 35356#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 35305#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 35306#L1041 assume !(0 != activate_threads_~tmp___1~0); 36105#L1041-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 36106#L449 assume !(1 == ~t3_pc~0); 35992#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 35650#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 35485#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 35486#L1049 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 35932#L1049-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 35202#L468 assume !(1 == ~t4_pc~0); 35203#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 35212#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 35626#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 35564#L1057 assume !(0 != activate_threads_~tmp___3~0); 35565#L1057-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 35421#L487 assume !(1 == ~t5_pc~0); 35160#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 35423#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 35755#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 35756#L1065 assume !(0 != activate_threads_~tmp___4~0); 36118#L1065-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 35571#L506 assume 1 == ~t6_pc~0; 35382#L507 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6 := 1; 35383#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 35930#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 35849#L1073 assume !(0 != activate_threads_~tmp___5~0); 35850#L1073-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 35697#L525 assume !(1 == ~t7_pc~0); 35643#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 35642#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 36107#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 35442#L1081 assume !(0 != activate_threads_~tmp___6~0); 35443#L1081-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 35444#L544 assume 1 == ~t8_pc~0; 35709#L545 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 35099#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 35100#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 35236#L1089 assume !(0 != activate_threads_~tmp___7~0); 35974#L1089-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35579#L921 assume !(1 == ~M_E~0); 35580#L921-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 35314#L926-1 assume !(1 == ~T2_E~0); 35315#L931-1 assume !(1 == ~T3_E~0); 36024#L936-1 assume !(1 == ~T4_E~0); 35840#L941-1 assume !(1 == ~T5_E~0); 35577#L946-1 assume !(1 == ~T6_E~0); 35117#L951-1 assume !(1 == ~T7_E~0); 35118#L956-1 assume !(1 == ~T8_E~0); 35933#L961-1 assume 1 == ~E_1~0;~E_1~0 := 2; 35671#L966-1 assume !(1 == ~E_2~0); 35447#L971-1 assume !(1 == ~E_3~0); 35448#L976-1 assume !(1 == ~E_4~0); 35898#L981-1 assume !(1 == ~E_5~0); 35631#L986-1 assume !(1 == ~E_6~0); 35554#L991-1 assume !(1 == ~E_7~0); 35244#L996-1 assume !(1 == ~E_8~0); 35245#L1001-1 assume { :end_inline_reset_delta_events } true; 35789#L1262-3 [2018-11-18 14:32:31,854 INFO L796 eck$LassoCheckResult]: Loop: 35789#L1262-3 assume true; 36051#L1262-1 assume !false; 36052#L1263 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 35591#L803 assume true; 35499#L681-1 assume !false; 35500#L682 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 35575#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 35228#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 36022#L672 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 35175#L686 assume !(0 != eval_~tmp~0); 35177#L818 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 40696#L564-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 40694#L828-3 assume 0 == ~M_E~0;~M_E~0 := 1; 40692#L828-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 40690#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 40687#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 40686#L843-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36020#L848-3 assume !(0 == ~T5_E~0); 35836#L853-3 assume !(0 == ~T6_E~0); 35574#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 35110#L863-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 35111#L868-3 assume 0 == ~E_1~0;~E_1~0 := 1; 35780#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 35667#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 35439#L883-3 assume 0 == ~E_4~0;~E_4~0 := 1; 35440#L888-3 assume !(0 == ~E_5~0); 35906#L893-3 assume !(0 == ~E_6~0); 35634#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 35546#L903-3 assume 0 == ~E_8~0;~E_8~0 := 1; 35240#L908-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 35241#L392-27 assume 1 == ~m_pc~0; 35682#L393-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 35683#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 36065#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 35964#L1025-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 35946#L1025-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 35711#L411-27 assume !(1 == ~t1_pc~0); 35712#L411-29 is_transmit1_triggered_~__retres1~1 := 0; 35123#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 35124#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 35258#L1033-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 35458#L1033-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 35464#L430-27 assume !(1 == ~t2_pc~0); 35888#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 35349#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 35350#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 35452#L1041-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 36042#L1041-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 36001#L449-27 assume 1 == ~t3_pc~0; 35968#L450-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 35517#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 35456#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 35457#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 35727#L1049-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 35732#L468-27 assume !(1 == ~t4_pc~0); 36092#L468-29 is_transmit4_triggered_~__retres1~4 := 0; 36094#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 40625#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 40623#L1057-27 assume !(0 != activate_threads_~tmp___3~0); 40621#L1057-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 40619#L487-27 assume !(1 == ~t5_pc~0); 40615#L487-29 is_transmit5_triggered_~__retres1~5 := 0; 40613#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 40612#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 40611#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 40610#L1065-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 40516#L506-27 assume !(1 == ~t6_pc~0); 40514#L506-29 is_transmit6_triggered_~__retres1~6 := 0; 40513#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 35915#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 35799#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 35636#L1073-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 35637#L525-27 assume 1 == ~t7_pc~0; 35539#L526-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 35540#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 36018#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 35396#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 35397#L1081-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 35401#L544-27 assume 1 == ~t8_pc~0; 35790#L545-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 35273#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 35195#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 35196#L1089-27 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 36027#L1089-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35584#L921-3 assume 1 == ~M_E~0;~M_E~0 := 2; 35585#L921-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 35316#L926-3 assume !(1 == ~T2_E~0); 35317#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 36025#L936-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35842#L941-3 assume !(1 == ~T5_E~0); 35578#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 35103#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 35104#L956-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 35777#L961-3 assume 1 == ~E_1~0;~E_1~0 := 2; 35664#L966-3 assume !(1 == ~E_2~0); 35434#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 35435#L976-3 assume 1 == ~E_4~0;~E_4~0 := 2; 35902#L981-3 assume !(1 == ~E_5~0); 35632#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 35558#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 35249#L996-3 assume 1 == ~E_8~0;~E_8~0 := 2; 35250#L1001-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 36041#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 35231#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 36023#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 35142#L1281 assume !(0 == start_simulation_~tmp~3); 35143#L1281-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 35153#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 35234#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 35926#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 35393#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 35394#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 35984#L1244 start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 35788#L1294 assume !(0 != start_simulation_~tmp___0~1); 35789#L1262-3 [2018-11-18 14:32:31,854 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:31,854 INFO L82 PathProgramCache]: Analyzing trace with hash -1001166081, now seen corresponding path program 1 times [2018-11-18 14:32:31,854 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:31,854 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:31,855 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:31,855 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:31,855 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:31,860 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:31,894 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:31,894 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:31,894 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 14:32:31,895 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 14:32:31,895 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:31,895 INFO L82 PathProgramCache]: Analyzing trace with hash -63845650, now seen corresponding path program 1 times [2018-11-18 14:32:31,895 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:31,895 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:31,896 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:31,896 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:31,896 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:31,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:31,926 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:31,926 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:31,926 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:32:31,927 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 14:32:31,927 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 14:32:31,927 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 14:32:31,927 INFO L87 Difference]: Start difference. First operand 5770 states and 8269 transitions. cyclomatic complexity: 2507 Second operand 3 states. [2018-11-18 14:32:32,019 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:32:32,019 INFO L93 Difference]: Finished difference Result 10853 states and 15486 transitions. [2018-11-18 14:32:32,021 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 14:32:32,021 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10853 states and 15486 transitions. [2018-11-18 14:32:32,048 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 10680 [2018-11-18 14:32:32,082 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10853 states to 10853 states and 15486 transitions. [2018-11-18 14:32:32,083 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10853 [2018-11-18 14:32:32,089 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10853 [2018-11-18 14:32:32,089 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10853 states and 15486 transitions. [2018-11-18 14:32:32,100 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:32:32,100 INFO L705 BuchiCegarLoop]: Abstraction has 10853 states and 15486 transitions. [2018-11-18 14:32:32,107 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10853 states and 15486 transitions. [2018-11-18 14:32:32,189 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10853 to 10829. [2018-11-18 14:32:32,190 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 10829 states. [2018-11-18 14:32:32,259 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10829 states to 10829 states and 15462 transitions. [2018-11-18 14:32:32,260 INFO L728 BuchiCegarLoop]: Abstraction has 10829 states and 15462 transitions. [2018-11-18 14:32:32,260 INFO L608 BuchiCegarLoop]: Abstraction has 10829 states and 15462 transitions. [2018-11-18 14:32:32,260 INFO L442 BuchiCegarLoop]: ======== Iteration 15============ [2018-11-18 14:32:32,260 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10829 states and 15462 transitions. [2018-11-18 14:32:32,279 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 10656 [2018-11-18 14:32:32,279 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:32:32,279 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:32:32,280 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:32,280 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:32,280 INFO L794 eck$LassoCheckResult]: Stem: 52210#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 52098#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 52099#L1225 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 52577#L564 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 52135#L571 assume 1 == ~m_i~0;~m_st~0 := 0; 52116#L571-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 51815#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 51816#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 52580#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 52342#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 51933#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 51934#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 52571#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 52471#L611-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 52472#L828 assume !(0 == ~M_E~0); 52588#L828-2 assume !(0 == ~T1_E~0); 52239#L833-1 assume !(0 == ~T2_E~0); 51948#L838-1 assume !(0 == ~T3_E~0); 51949#L843-1 assume !(0 == ~T4_E~0); 52673#L848-1 assume !(0 == ~T5_E~0); 52480#L853-1 assume !(0 == ~T6_E~0); 52221#L858-1 assume !(0 == ~T7_E~0); 51735#L863-1 assume !(0 == ~T8_E~0); 51736#L868-1 assume !(0 == ~E_1~0); 52429#L873-1 assume !(0 == ~E_2~0); 52313#L878-1 assume !(0 == ~E_3~0); 52067#L883-1 assume !(0 == ~E_4~0); 52068#L888-1 assume !(0 == ~E_5~0); 52543#L893-1 assume !(0 == ~E_6~0); 52282#L898-1 assume !(0 == ~E_7~0); 52196#L903-1 assume !(0 == ~E_8~0); 51886#L908-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 51887#L392 assume !(1 == ~m_pc~0); 52262#L392-2 is_master_triggered_~__retres1~0 := 0; 52268#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 52728#L404 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 52550#L1025 assume !(0 != activate_threads_~tmp~1); 52551#L1025-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 52417#L411 assume !(1 == ~t1_pc~0); 52385#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 51795#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 51796#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 51915#L1033 assume !(0 != activate_threads_~tmp___0~0); 52142#L1033-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 52143#L430 assume !(1 == ~t2_pc~0); 52562#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 51982#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 51935#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 51936#L1041 assume !(0 != activate_threads_~tmp___1~0); 52755#L1041-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 52756#L449 assume !(1 == ~t3_pc~0); 52633#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 52296#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 52117#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 52118#L1049 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 52575#L1049-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 51835#L468 assume !(1 == ~t4_pc~0); 51836#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 51844#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 52275#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 52204#L1057 assume !(0 != activate_threads_~tmp___3~0); 52205#L1057-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 52052#L487 assume !(1 == ~t5_pc~0); 51791#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 52054#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 52405#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 52406#L1065 assume !(0 != activate_threads_~tmp___4~0); 52772#L1065-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 52220#L506 assume !(1 == ~t6_pc~0); 52215#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 52216#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 52573#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 52493#L1073 assume !(0 != activate_threads_~tmp___5~0); 52494#L1073-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 52343#L525 assume !(1 == ~t7_pc~0); 52292#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 52291#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 52757#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 52073#L1081 assume !(0 != activate_threads_~tmp___6~0); 52074#L1081-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 52075#L544 assume 1 == ~t8_pc~0; 52355#L545 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8 := 1; 51729#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 51730#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 51868#L1089 assume !(0 != activate_threads_~tmp___7~0); 52617#L1089-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 52228#L921 assume !(1 == ~M_E~0); 52229#L921-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 51944#L926-1 assume !(1 == ~T2_E~0); 51945#L931-1 assume !(1 == ~T3_E~0); 52671#L936-1 assume !(1 == ~T4_E~0); 52488#L941-1 assume !(1 == ~T5_E~0); 52226#L946-1 assume !(1 == ~T6_E~0); 51747#L951-1 assume !(1 == ~T7_E~0); 51748#L956-1 assume !(1 == ~T8_E~0); 52576#L961-1 assume 1 == ~E_1~0;~E_1~0 := 2; 52318#L966-1 assume !(1 == ~E_2~0); 52079#L971-1 assume !(1 == ~E_3~0); 52080#L976-1 assume !(1 == ~E_4~0); 52538#L981-1 assume !(1 == ~E_5~0); 52280#L986-1 assume !(1 == ~E_6~0); 52190#L991-1 assume !(1 == ~E_7~0); 51876#L996-1 assume !(1 == ~E_8~0); 51877#L1001-1 assume { :end_inline_reset_delta_events } true; 52692#L1262-3 [2018-11-18 14:32:32,281 INFO L796 eck$LassoCheckResult]: Loop: 52692#L1262-3 assume true; 60472#L1262-1 assume !false; 60326#L1263 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 60324#L803 assume true; 60322#L681-1 assume !false; 60320#L682 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 60313#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 60304#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 60302#L672 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 60299#L686 assume !(0 != eval_~tmp~0); 60300#L818 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 60677#L564-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 60676#L828-3 assume 0 == ~M_E~0;~M_E~0 := 1; 60675#L828-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 60674#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 60673#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 60672#L843-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 60671#L848-3 assume !(0 == ~T5_E~0); 60670#L853-3 assume !(0 == ~T6_E~0); 60669#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 60668#L863-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 60667#L868-3 assume 0 == ~E_1~0;~E_1~0 := 1; 60666#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 60665#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 60664#L883-3 assume 0 == ~E_4~0;~E_4~0 := 1; 60663#L888-3 assume !(0 == ~E_5~0); 60662#L893-3 assume !(0 == ~E_6~0); 60661#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 60660#L903-3 assume 0 == ~E_8~0;~E_8~0 := 1; 60659#L908-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 60658#L392-27 assume 1 == ~m_pc~0; 60656#L393-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 60655#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 60654#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 60653#L1025-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 60652#L1025-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 60651#L411-27 assume !(1 == ~t1_pc~0); 60649#L411-29 is_transmit1_triggered_~__retres1~1 := 0; 60646#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 60644#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 60642#L1033-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 60640#L1033-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 60638#L430-27 assume !(1 == ~t2_pc~0); 60636#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 60634#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 60632#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 60630#L1041-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 60628#L1041-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 60626#L449-27 assume 1 == ~t3_pc~0; 60624#L450-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 60621#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 60619#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 60617#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 60615#L1049-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 60613#L468-27 assume !(1 == ~t4_pc~0); 60611#L468-29 is_transmit4_triggered_~__retres1~4 := 0; 60608#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 60606#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 60604#L1057-27 assume !(0 != activate_threads_~tmp___3~0); 60602#L1057-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 60600#L487-27 assume !(1 == ~t5_pc~0); 60597#L487-29 is_transmit5_triggered_~__retres1~5 := 0; 60595#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 60593#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 60591#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 60589#L1065-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 60587#L506-27 assume !(1 == ~t6_pc~0); 60584#L506-29 is_transmit6_triggered_~__retres1~6 := 0; 60582#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 60580#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 60578#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 60576#L1073-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 60574#L525-27 assume 1 == ~t7_pc~0; 60571#L526-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 60569#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 60567#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 60565#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 60563#L1081-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 60561#L544-27 assume !(1 == ~t8_pc~0); 60558#L544-29 is_transmit8_triggered_~__retres1~8 := 0; 60555#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 60553#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 60551#L1089-27 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 60549#L1089-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 60547#L921-3 assume 1 == ~M_E~0;~M_E~0 := 2; 60545#L921-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 60542#L926-3 assume !(1 == ~T2_E~0); 60540#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 60538#L936-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 60536#L941-3 assume !(1 == ~T5_E~0); 60534#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 60532#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 60530#L956-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 60528#L961-3 assume 1 == ~E_1~0;~E_1~0 := 2; 60526#L966-3 assume !(1 == ~E_2~0); 60524#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 60522#L976-3 assume 1 == ~E_4~0;~E_4~0 := 2; 60520#L981-3 assume !(1 == ~E_5~0); 60518#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 60516#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 60514#L996-3 assume 1 == ~E_8~0;~E_8~0 := 2; 60512#L1001-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 60506#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 60497#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 60495#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 60493#L1281 assume !(0 == start_simulation_~tmp~3); 60491#L1281-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 60490#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 60481#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 60480#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 60479#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 60478#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 60477#L1244 start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 60475#L1294 assume !(0 != start_simulation_~tmp___0~1); 52692#L1262-3 [2018-11-18 14:32:32,281 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:32,281 INFO L82 PathProgramCache]: Analyzing trace with hash 1528984606, now seen corresponding path program 1 times [2018-11-18 14:32:32,281 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:32,281 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:32,282 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:32,282 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:32,282 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:32,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:32,318 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:32,318 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:32,318 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 14:32:32,318 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 14:32:32,319 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:32,319 INFO L82 PathProgramCache]: Analyzing trace with hash -1828662259, now seen corresponding path program 1 times [2018-11-18 14:32:32,319 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:32,319 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:32,319 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:32,320 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:32,320 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:32,325 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:32,350 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:32,350 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:32,350 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:32:32,351 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 14:32:32,351 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 14:32:32,351 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 14:32:32,351 INFO L87 Difference]: Start difference. First operand 10829 states and 15462 transitions. cyclomatic complexity: 4649 Second operand 3 states. [2018-11-18 14:32:32,488 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:32:32,488 INFO L93 Difference]: Finished difference Result 21404 states and 30363 transitions. [2018-11-18 14:32:32,490 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 14:32:32,490 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21404 states and 30363 transitions. [2018-11-18 14:32:32,545 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 21136 [2018-11-18 14:32:32,588 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21404 states to 21404 states and 30363 transitions. [2018-11-18 14:32:32,588 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21404 [2018-11-18 14:32:32,600 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21404 [2018-11-18 14:32:32,600 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21404 states and 30363 transitions. [2018-11-18 14:32:32,615 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:32:32,615 INFO L705 BuchiCegarLoop]: Abstraction has 21404 states and 30363 transitions. [2018-11-18 14:32:32,629 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21404 states and 30363 transitions. [2018-11-18 14:32:32,752 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21404 to 21324. [2018-11-18 14:32:32,753 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21324 states. [2018-11-18 14:32:32,777 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21324 states to 21324 states and 30267 transitions. [2018-11-18 14:32:32,777 INFO L728 BuchiCegarLoop]: Abstraction has 21324 states and 30267 transitions. [2018-11-18 14:32:32,777 INFO L608 BuchiCegarLoop]: Abstraction has 21324 states and 30267 transitions. [2018-11-18 14:32:32,777 INFO L442 BuchiCegarLoop]: ======== Iteration 16============ [2018-11-18 14:32:32,777 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21324 states and 30267 transitions. [2018-11-18 14:32:32,817 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 21088 [2018-11-18 14:32:32,817 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:32:32,817 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:32:32,818 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:32,818 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:32,819 INFO L794 eck$LassoCheckResult]: Stem: 84430#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 84326#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 84327#L1225 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 84812#L564 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 84364#L571 assume 1 == ~m_i~0;~m_st~0 := 0; 84344#L571-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 84052#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 84053#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 84816#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 84560#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 84169#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 84170#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 84806#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 84685#L611-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 84686#L828 assume !(0 == ~M_E~0); 84822#L828-2 assume !(0 == ~T1_E~0); 84455#L833-1 assume !(0 == ~T2_E~0); 84184#L838-1 assume !(0 == ~T3_E~0); 84185#L843-1 assume !(0 == ~T4_E~0); 84890#L848-1 assume !(0 == ~T5_E~0); 84695#L853-1 assume !(0 == ~T6_E~0); 84437#L858-1 assume !(0 == ~T7_E~0); 83975#L863-1 assume !(0 == ~T8_E~0); 83976#L868-1 assume !(0 == ~E_1~0); 84646#L873-1 assume !(0 == ~E_2~0); 84530#L878-1 assume !(0 == ~E_3~0); 84297#L883-1 assume !(0 == ~E_4~0); 84298#L888-1 assume !(0 == ~E_5~0); 84780#L893-1 assume !(0 == ~E_6~0); 84499#L898-1 assume !(0 == ~E_7~0); 84420#L903-1 assume !(0 == ~E_8~0); 84123#L908-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 84124#L392 assume !(1 == ~m_pc~0); 84478#L392-2 is_master_triggered_~__retres1~0 := 0; 84484#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 84942#L404 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 84787#L1025 assume !(0 != activate_threads_~tmp~1); 84788#L1025-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 84633#L411 assume !(1 == ~t1_pc~0); 84602#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 84036#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 84037#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 84151#L1033 assume !(0 != activate_threads_~tmp___0~0); 84371#L1033-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 84372#L430 assume !(1 == ~t2_pc~0); 84797#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 84221#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 84171#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 84172#L1041 assume !(0 != activate_threads_~tmp___1~0); 84969#L1041-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 84970#L449 assume !(1 == ~t3_pc~0); 84856#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 84516#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 84347#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 84348#L1049 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 84810#L1049-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 84072#L468 assume !(1 == ~t4_pc~0); 84073#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 84082#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 84492#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 84424#L1057 assume !(0 != activate_threads_~tmp___3~0); 84425#L1057-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 84282#L487 assume !(1 == ~t5_pc~0); 84030#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 84284#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 84621#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 84622#L1065 assume !(0 != activate_threads_~tmp___4~0); 84983#L1065-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 84436#L506 assume !(1 == ~t6_pc~0); 84433#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 84434#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 84808#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 84716#L1073 assume !(0 != activate_threads_~tmp___5~0); 84717#L1073-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 84562#L525 assume !(1 == ~t7_pc~0); 84509#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 84508#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 84971#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 84303#L1081 assume !(0 != activate_threads_~tmp___6~0); 84304#L1081-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 84305#L544 assume !(1 == ~t8_pc~0); 84578#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 83969#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 83970#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 84105#L1089 assume !(0 != activate_threads_~tmp___7~0); 84841#L1089-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 84447#L921 assume !(1 == ~M_E~0); 84448#L921-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 84180#L926-1 assume !(1 == ~T2_E~0); 84181#L931-1 assume !(1 == ~T3_E~0); 84888#L936-1 assume !(1 == ~T4_E~0); 84702#L941-1 assume !(1 == ~T5_E~0); 84443#L946-1 assume !(1 == ~T6_E~0); 83987#L951-1 assume !(1 == ~T7_E~0); 83988#L956-1 assume !(1 == ~T8_E~0); 84811#L961-1 assume 1 == ~E_1~0;~E_1~0 := 2; 84537#L966-1 assume !(1 == ~E_2~0); 84308#L971-1 assume !(1 == ~E_3~0); 84309#L976-1 assume !(1 == ~E_4~0); 84773#L981-1 assume !(1 == ~E_5~0); 84497#L986-1 assume !(1 == ~E_6~0); 84414#L991-1 assume !(1 == ~E_7~0); 84113#L996-1 assume !(1 == ~E_8~0); 84114#L1001-1 assume { :end_inline_reset_delta_events } true; 84908#L1262-3 [2018-11-18 14:32:32,819 INFO L796 eck$LassoCheckResult]: Loop: 84908#L1262-3 assume true; 89340#L1262-1 assume !false; 89322#L1263 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 89320#L803 assume true; 89318#L681-1 assume !false; 89316#L682 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 89310#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 89301#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 89299#L672 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 89296#L686 assume !(0 != eval_~tmp~0); 89297#L818 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 89571#L564-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 89569#L828-3 assume 0 == ~M_E~0;~M_E~0 := 1; 89567#L828-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 89565#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 89563#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 89561#L843-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 89559#L848-3 assume !(0 == ~T5_E~0); 89557#L853-3 assume !(0 == ~T6_E~0); 89555#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 89552#L863-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 89550#L868-3 assume 0 == ~E_1~0;~E_1~0 := 1; 89548#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 89546#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 89544#L883-3 assume 0 == ~E_4~0;~E_4~0 := 1; 89542#L888-3 assume !(0 == ~E_5~0); 89540#L893-3 assume !(0 == ~E_6~0); 89538#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 89536#L903-3 assume 0 == ~E_8~0;~E_8~0 := 1; 89534#L908-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 89532#L392-27 assume 1 == ~m_pc~0; 89529#L393-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 89527#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 89524#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 89522#L1025-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 89520#L1025-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 89518#L411-27 assume !(1 == ~t1_pc~0); 89516#L411-29 is_transmit1_triggered_~__retres1~1 := 0; 89514#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 89512#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 89510#L1033-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 89508#L1033-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 89506#L430-27 assume !(1 == ~t2_pc~0); 89504#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 89502#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 89500#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 89498#L1041-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 89496#L1041-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 89494#L449-27 assume !(1 == ~t3_pc~0); 89491#L449-29 is_transmit3_triggered_~__retres1~3 := 0; 89489#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 89487#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 89485#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 89483#L1049-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 89481#L468-27 assume !(1 == ~t4_pc~0); 89479#L468-29 is_transmit4_triggered_~__retres1~4 := 0; 89477#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 89475#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 89473#L1057-27 assume !(0 != activate_threads_~tmp___3~0); 89471#L1057-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 89469#L487-27 assume !(1 == ~t5_pc~0); 89467#L487-29 is_transmit5_triggered_~__retres1~5 := 0; 89466#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 89465#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 89464#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 89463#L1065-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 89461#L506-27 assume !(1 == ~t6_pc~0); 89458#L506-29 is_transmit6_triggered_~__retres1~6 := 0; 89456#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 89454#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 89452#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 89450#L1073-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 89448#L525-27 assume 1 == ~t7_pc~0; 89445#L526-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 89443#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 89441#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 89439#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 89437#L1081-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 89435#L544-27 assume !(1 == ~t8_pc~0); 89433#L544-29 is_transmit8_triggered_~__retres1~8 := 0; 89431#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 89429#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 89427#L1089-27 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 89425#L1089-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 89423#L921-3 assume 1 == ~M_E~0;~M_E~0 := 2; 89420#L921-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 89418#L926-3 assume !(1 == ~T2_E~0); 89416#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 89414#L936-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 89412#L941-3 assume !(1 == ~T5_E~0); 89410#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 89408#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 89406#L956-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 89404#L961-3 assume 1 == ~E_1~0;~E_1~0 := 2; 89402#L966-3 assume !(1 == ~E_2~0); 89400#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 89397#L976-3 assume 1 == ~E_4~0;~E_4~0 := 2; 89395#L981-3 assume !(1 == ~E_5~0); 89393#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 89391#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 89389#L996-3 assume 1 == ~E_8~0;~E_8~0 := 2; 89387#L1001-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 89384#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 89375#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 89373#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 89370#L1281 assume !(0 == start_simulation_~tmp~3); 89367#L1281-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 89364#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 89353#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 89351#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 89349#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 89347#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 89345#L1244 start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 89343#L1294 assume !(0 != start_simulation_~tmp___0~1); 84908#L1262-3 [2018-11-18 14:32:32,819 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:32,819 INFO L82 PathProgramCache]: Analyzing trace with hash -61410371, now seen corresponding path program 1 times [2018-11-18 14:32:32,819 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:32,819 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:32,820 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:32,820 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:32,820 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:32,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:32,854 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:32,854 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:32,854 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 14:32:32,854 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 14:32:32,855 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:32,855 INFO L82 PathProgramCache]: Analyzing trace with hash 1288330476, now seen corresponding path program 1 times [2018-11-18 14:32:32,855 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:32,855 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:32,855 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:32,856 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:32,856 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:32,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:32,894 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:32,895 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:32,895 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:32:32,895 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 14:32:32,895 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 14:32:32,895 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 14:32:32,895 INFO L87 Difference]: Start difference. First operand 21324 states and 30267 transitions. cyclomatic complexity: 8975 Second operand 3 states. [2018-11-18 14:32:32,973 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:32:32,973 INFO L93 Difference]: Finished difference Result 21324 states and 30169 transitions. [2018-11-18 14:32:32,975 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 14:32:32,975 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21324 states and 30169 transitions. [2018-11-18 14:32:33,026 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 21088 [2018-11-18 14:32:33,066 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21324 states to 21324 states and 30169 transitions. [2018-11-18 14:32:33,067 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21324 [2018-11-18 14:32:33,079 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21324 [2018-11-18 14:32:33,079 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21324 states and 30169 transitions. [2018-11-18 14:32:33,092 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:32:33,092 INFO L705 BuchiCegarLoop]: Abstraction has 21324 states and 30169 transitions. [2018-11-18 14:32:33,103 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21324 states and 30169 transitions. [2018-11-18 14:32:33,358 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21324 to 21324. [2018-11-18 14:32:33,358 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21324 states. [2018-11-18 14:32:33,397 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21324 states to 21324 states and 30169 transitions. [2018-11-18 14:32:33,397 INFO L728 BuchiCegarLoop]: Abstraction has 21324 states and 30169 transitions. [2018-11-18 14:32:33,397 INFO L608 BuchiCegarLoop]: Abstraction has 21324 states and 30169 transitions. [2018-11-18 14:32:33,397 INFO L442 BuchiCegarLoop]: ======== Iteration 17============ [2018-11-18 14:32:33,397 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21324 states and 30169 transitions. [2018-11-18 14:32:33,451 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 21088 [2018-11-18 14:32:33,452 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:32:33,452 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:32:33,453 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:33,453 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:33,453 INFO L794 eck$LassoCheckResult]: Stem: 127089#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 126986#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 126987#L1225 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 127448#L564 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 127023#L571 assume 1 == ~m_i~0;~m_st~0 := 0; 127004#L571-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 126708#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 126709#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 127450#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 127216#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 126825#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 126826#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 127442#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 127339#L611-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 127340#L828 assume !(0 == ~M_E~0); 127457#L828-2 assume !(0 == ~T1_E~0); 127113#L833-1 assume !(0 == ~T2_E~0); 126840#L838-1 assume !(0 == ~T3_E~0); 126841#L843-1 assume !(0 == ~T4_E~0); 127536#L848-1 assume !(0 == ~T5_E~0); 127350#L853-1 assume !(0 == ~T6_E~0); 127096#L858-1 assume !(0 == ~T7_E~0); 126630#L863-1 assume !(0 == ~T8_E~0); 126631#L868-1 assume !(0 == ~E_1~0); 127301#L873-1 assume !(0 == ~E_2~0); 127187#L878-1 assume !(0 == ~E_3~0); 126956#L883-1 assume !(0 == ~E_4~0); 126957#L888-1 assume !(0 == ~E_5~0); 127418#L893-1 assume !(0 == ~E_6~0); 127156#L898-1 assume !(0 == ~E_7~0); 127078#L903-1 assume !(0 == ~E_8~0); 126777#L908-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 126778#L392 assume !(1 == ~m_pc~0); 127136#L392-2 is_master_triggered_~__retres1~0 := 0; 127142#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 127582#L404 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 127425#L1025 assume !(0 != activate_threads_~tmp~1); 127426#L1025-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 127289#L411 assume !(1 == ~t1_pc~0); 127257#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 126689#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 126690#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 126805#L1033 assume !(0 != activate_threads_~tmp___0~0); 127030#L1033-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 127031#L430 assume !(1 == ~t2_pc~0); 127433#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 126874#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 126827#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 126828#L1041 assume !(0 != activate_threads_~tmp___1~0); 127615#L1041-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 127616#L449 assume !(1 == ~t3_pc~0); 127499#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 127170#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 127005#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 127006#L1049 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 127446#L1049-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 126726#L468 assume !(1 == ~t4_pc~0); 126727#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 126736#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 127149#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 127083#L1057 assume !(0 != activate_threads_~tmp___3~0); 127084#L1057-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 126941#L487 assume !(1 == ~t5_pc~0); 126685#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 126943#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 127277#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 127278#L1065 assume !(0 != activate_threads_~tmp___4~0); 127628#L1065-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 127095#L506 assume !(1 == ~t6_pc~0); 127092#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 127093#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 127444#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 127364#L1073 assume !(0 != activate_threads_~tmp___5~0); 127365#L1073-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 127217#L525 assume !(1 == ~t7_pc~0); 127166#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 127165#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 127617#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 126962#L1081 assume !(0 != activate_threads_~tmp___6~0); 126963#L1081-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 126964#L544 assume !(1 == ~t8_pc~0); 127229#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 126624#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 126625#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 126759#L1089 assume !(0 != activate_threads_~tmp___7~0); 127484#L1089-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 127103#L921 assume !(1 == ~M_E~0); 127104#L921-2 assume !(1 == ~T1_E~0); 126836#L926-1 assume !(1 == ~T2_E~0); 126837#L931-1 assume !(1 == ~T3_E~0); 127534#L936-1 assume !(1 == ~T4_E~0); 127358#L941-1 assume !(1 == ~T5_E~0); 127101#L946-1 assume !(1 == ~T6_E~0); 126642#L951-1 assume !(1 == ~T7_E~0); 126643#L956-1 assume !(1 == ~T8_E~0); 127447#L961-1 assume 1 == ~E_1~0;~E_1~0 := 2; 127192#L966-1 assume !(1 == ~E_2~0); 126967#L971-1 assume !(1 == ~E_3~0); 126968#L976-1 assume !(1 == ~E_4~0); 127413#L981-1 assume !(1 == ~E_5~0); 127154#L986-1 assume !(1 == ~E_6~0); 127073#L991-1 assume !(1 == ~E_7~0); 126765#L996-1 assume !(1 == ~E_8~0); 126766#L1001-1 assume { :end_inline_reset_delta_events } true; 127549#L1262-3 [2018-11-18 14:32:33,453 INFO L796 eck$LassoCheckResult]: Loop: 127549#L1262-3 assume true; 131987#L1262-1 assume !false; 131968#L1263 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 131966#L803 assume true; 131964#L681-1 assume !false; 131962#L682 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 131956#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 131947#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 131945#L672 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 131942#L686 assume !(0 != eval_~tmp~0); 131943#L818 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 132218#L564-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 132216#L828-3 assume 0 == ~M_E~0;~M_E~0 := 1; 132214#L828-5 assume !(0 == ~T1_E~0); 132212#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 132210#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 132208#L843-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 132206#L848-3 assume !(0 == ~T5_E~0); 132204#L853-3 assume !(0 == ~T6_E~0); 132202#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 132199#L863-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 132197#L868-3 assume 0 == ~E_1~0;~E_1~0 := 1; 132195#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 132193#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 132191#L883-3 assume 0 == ~E_4~0;~E_4~0 := 1; 132189#L888-3 assume !(0 == ~E_5~0); 132187#L893-3 assume !(0 == ~E_6~0); 132185#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 132183#L903-3 assume 0 == ~E_8~0;~E_8~0 := 1; 132181#L908-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 132179#L392-27 assume 1 == ~m_pc~0; 132176#L393-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 132174#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 132171#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 132169#L1025-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 132167#L1025-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 132165#L411-27 assume !(1 == ~t1_pc~0); 132163#L411-29 is_transmit1_triggered_~__retres1~1 := 0; 132161#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 132159#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 132157#L1033-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 132155#L1033-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 132153#L430-27 assume !(1 == ~t2_pc~0); 132151#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 132149#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 132147#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 132145#L1041-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 132143#L1041-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 132141#L449-27 assume !(1 == ~t3_pc~0); 132138#L449-29 is_transmit3_triggered_~__retres1~3 := 0; 132136#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 132134#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 132132#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 132130#L1049-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 132128#L468-27 assume !(1 == ~t4_pc~0); 132126#L468-29 is_transmit4_triggered_~__retres1~4 := 0; 132124#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 132122#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 132120#L1057-27 assume !(0 != activate_threads_~tmp___3~0); 132118#L1057-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 132116#L487-27 assume !(1 == ~t5_pc~0); 132114#L487-29 is_transmit5_triggered_~__retres1~5 := 0; 132113#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 132112#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 132111#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 132110#L1065-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 132108#L506-27 assume !(1 == ~t6_pc~0); 132105#L506-29 is_transmit6_triggered_~__retres1~6 := 0; 132103#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 132101#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 132099#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 132097#L1073-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 132095#L525-27 assume 1 == ~t7_pc~0; 132092#L526-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 132090#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 132088#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 132086#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 132084#L1081-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 132082#L544-27 assume !(1 == ~t8_pc~0); 132080#L544-29 is_transmit8_triggered_~__retres1~8 := 0; 132078#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 132076#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 132074#L1089-27 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 132072#L1089-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 132070#L921-3 assume 1 == ~M_E~0;~M_E~0 := 2; 132067#L921-5 assume !(1 == ~T1_E~0); 132065#L926-3 assume !(1 == ~T2_E~0); 132063#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 132061#L936-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 132059#L941-3 assume !(1 == ~T5_E~0); 132057#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 132055#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 132053#L956-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 132051#L961-3 assume 1 == ~E_1~0;~E_1~0 := 2; 132049#L966-3 assume !(1 == ~E_2~0); 132047#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 132044#L976-3 assume 1 == ~E_4~0;~E_4~0 := 2; 132042#L981-3 assume !(1 == ~E_5~0); 132040#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 132038#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 132036#L996-3 assume 1 == ~E_8~0;~E_8~0 := 2; 132034#L1001-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 132031#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 132022#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 132020#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 132017#L1281 assume !(0 == start_simulation_~tmp~3); 132014#L1281-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 132011#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 132000#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 131998#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 131996#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 131994#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 131992#L1244 start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 131990#L1294 assume !(0 != start_simulation_~tmp___0~1); 127549#L1262-3 [2018-11-18 14:32:33,454 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:33,454 INFO L82 PathProgramCache]: Analyzing trace with hash -1649758273, now seen corresponding path program 1 times [2018-11-18 14:32:33,454 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:33,454 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:33,455 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:33,455 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:33,455 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:33,460 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:33,494 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:33,494 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:33,494 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 14:32:33,495 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 14:32:33,495 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:33,495 INFO L82 PathProgramCache]: Analyzing trace with hash 1367391472, now seen corresponding path program 1 times [2018-11-18 14:32:33,495 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:33,495 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:33,496 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:33,496 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:33,496 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:33,501 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:33,521 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:33,522 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:33,522 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:32:33,522 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 14:32:33,522 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 14:32:33,523 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 14:32:33,523 INFO L87 Difference]: Start difference. First operand 21324 states and 30169 transitions. cyclomatic complexity: 8877 Second operand 3 states. [2018-11-18 14:32:33,619 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:32:33,620 INFO L93 Difference]: Finished difference Result 21324 states and 29951 transitions. [2018-11-18 14:32:33,621 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 14:32:33,622 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21324 states and 29951 transitions. [2018-11-18 14:32:33,694 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 21088 [2018-11-18 14:32:33,756 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21324 states to 21324 states and 29951 transitions. [2018-11-18 14:32:33,756 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21324 [2018-11-18 14:32:33,768 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21324 [2018-11-18 14:32:33,768 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21324 states and 29951 transitions. [2018-11-18 14:32:33,781 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:32:33,781 INFO L705 BuchiCegarLoop]: Abstraction has 21324 states and 29951 transitions. [2018-11-18 14:32:33,795 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21324 states and 29951 transitions. [2018-11-18 14:32:33,940 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21324 to 21324. [2018-11-18 14:32:33,941 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21324 states. [2018-11-18 14:32:33,978 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21324 states to 21324 states and 29951 transitions. [2018-11-18 14:32:33,978 INFO L728 BuchiCegarLoop]: Abstraction has 21324 states and 29951 transitions. [2018-11-18 14:32:33,979 INFO L608 BuchiCegarLoop]: Abstraction has 21324 states and 29951 transitions. [2018-11-18 14:32:33,979 INFO L442 BuchiCegarLoop]: ======== Iteration 18============ [2018-11-18 14:32:33,979 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21324 states and 29951 transitions. [2018-11-18 14:32:34,030 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 21088 [2018-11-18 14:32:34,030 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:32:34,030 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:32:34,032 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:34,032 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:34,032 INFO L794 eck$LassoCheckResult]: Stem: 169759#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 169645#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 169646#L1225 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 170137#L564 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 169683#L571 assume 1 == ~m_i~0;~m_st~0 := 0; 169663#L571-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 169363#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 169364#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 170141#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 169895#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 169481#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 169482#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 170131#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 170022#L611-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 170023#L828 assume !(0 == ~M_E~0); 170149#L828-2 assume !(0 == ~T1_E~0); 169787#L833-1 assume !(0 == ~T2_E~0); 169496#L838-1 assume !(0 == ~T3_E~0); 169497#L843-1 assume !(0 == ~T4_E~0); 170222#L848-1 assume !(0 == ~T5_E~0); 170032#L853-1 assume !(0 == ~T6_E~0); 169770#L858-1 assume !(0 == ~T7_E~0); 169285#L863-1 assume !(0 == ~T8_E~0); 169286#L868-1 assume !(0 == ~E_1~0); 169980#L873-1 assume !(0 == ~E_2~0); 169864#L878-1 assume !(0 == ~E_3~0); 169614#L883-1 assume !(0 == ~E_4~0); 169615#L888-1 assume !(0 == ~E_5~0); 170104#L893-1 assume !(0 == ~E_6~0); 169832#L898-1 assume !(0 == ~E_7~0); 169747#L903-1 assume !(0 == ~E_8~0); 169435#L908-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 169436#L392 assume !(1 == ~m_pc~0); 169810#L392-2 is_master_triggered_~__retres1~0 := 0; 169817#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 170274#L404 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 170113#L1025 assume !(0 != activate_threads_~tmp~1); 170114#L1025-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 169966#L411 assume !(1 == ~t1_pc~0); 169934#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 169344#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 169345#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 169463#L1033 assume !(0 != activate_threads_~tmp___0~0); 169691#L1033-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 169692#L430 assume !(1 == ~t2_pc~0); 170122#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 169530#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 169483#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 169484#L1041 assume !(0 != activate_threads_~tmp___1~0); 170305#L1041-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 170306#L449 assume !(1 == ~t3_pc~0); 170183#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 169849#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 169664#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 169665#L1049 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 170135#L1049-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 169384#L468 assume !(1 == ~t4_pc~0); 169385#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 169394#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 169825#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 169753#L1057 assume !(0 != activate_threads_~tmp___3~0); 169754#L1057-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 169599#L487 assume !(1 == ~t5_pc~0); 169340#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 169601#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 169954#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 169955#L1065 assume !(0 != activate_threads_~tmp___4~0); 170320#L1065-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 169769#L506 assume !(1 == ~t6_pc~0); 169764#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 169765#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 170133#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 170050#L1073 assume !(0 != activate_threads_~tmp___5~0); 170051#L1073-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 169896#L525 assume !(1 == ~t7_pc~0); 169842#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 169841#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 170307#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 169620#L1081 assume !(0 != activate_threads_~tmp___6~0); 169621#L1081-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 169622#L544 assume !(1 == ~t8_pc~0); 169909#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 169279#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 169280#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 169417#L1089 assume !(0 != activate_threads_~tmp___7~0); 170167#L1089-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 169777#L921 assume !(1 == ~M_E~0); 169778#L921-2 assume !(1 == ~T1_E~0); 169492#L926-1 assume !(1 == ~T2_E~0); 169493#L931-1 assume !(1 == ~T3_E~0); 170220#L936-1 assume !(1 == ~T4_E~0); 170039#L941-1 assume !(1 == ~T5_E~0); 169775#L946-1 assume !(1 == ~T6_E~0); 169297#L951-1 assume !(1 == ~T7_E~0); 169298#L956-1 assume !(1 == ~T8_E~0); 170136#L961-1 assume !(1 == ~E_1~0); 169869#L966-1 assume !(1 == ~E_2~0); 169626#L971-1 assume !(1 == ~E_3~0); 169627#L976-1 assume !(1 == ~E_4~0); 170100#L981-1 assume !(1 == ~E_5~0); 169830#L986-1 assume !(1 == ~E_6~0); 169740#L991-1 assume !(1 == ~E_7~0); 169425#L996-1 assume !(1 == ~E_8~0); 169426#L1001-1 assume { :end_inline_reset_delta_events } true; 170244#L1262-3 [2018-11-18 14:32:34,032 INFO L796 eck$LassoCheckResult]: Loop: 170244#L1262-3 assume true; 175492#L1262-1 assume !false; 175251#L1263 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 175249#L803 assume true; 175247#L681-1 assume !false; 175245#L682 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 175237#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 175228#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 175226#L672 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 175223#L686 assume !(0 != eval_~tmp~0); 175224#L818 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 175700#L564-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 175699#L828-3 assume 0 == ~M_E~0;~M_E~0 := 1; 175698#L828-5 assume !(0 == ~T1_E~0); 175697#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 175696#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 175695#L843-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 175694#L848-3 assume !(0 == ~T5_E~0); 175693#L853-3 assume !(0 == ~T6_E~0); 175692#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 175691#L863-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 175690#L868-3 assume !(0 == ~E_1~0); 175689#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 175688#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 175687#L883-3 assume 0 == ~E_4~0;~E_4~0 := 1; 175686#L888-3 assume !(0 == ~E_5~0); 175685#L893-3 assume !(0 == ~E_6~0); 175684#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 175683#L903-3 assume 0 == ~E_8~0;~E_8~0 := 1; 175682#L908-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 175681#L392-27 assume !(1 == ~m_pc~0); 175680#L392-29 is_master_triggered_~__retres1~0 := 0; 175678#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 175677#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 175676#L1025-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 175675#L1025-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 175674#L411-27 assume !(1 == ~t1_pc~0); 175672#L411-29 is_transmit1_triggered_~__retres1~1 := 0; 175669#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 175667#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 175665#L1033-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 175663#L1033-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 175661#L430-27 assume !(1 == ~t2_pc~0); 175659#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 175657#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 175655#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 175653#L1041-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 175651#L1041-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 175649#L449-27 assume !(1 == ~t3_pc~0); 175646#L449-29 is_transmit3_triggered_~__retres1~3 := 0; 175644#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 175642#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 175640#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 175638#L1049-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 175636#L468-27 assume !(1 == ~t4_pc~0); 175634#L468-29 is_transmit4_triggered_~__retres1~4 := 0; 175631#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 175629#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 175627#L1057-27 assume !(0 != activate_threads_~tmp___3~0); 175625#L1057-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 175623#L487-27 assume !(1 == ~t5_pc~0); 175620#L487-29 is_transmit5_triggered_~__retres1~5 := 0; 175618#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 175616#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 175614#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 175612#L1065-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 175610#L506-27 assume !(1 == ~t6_pc~0); 175607#L506-29 is_transmit6_triggered_~__retres1~6 := 0; 175605#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 175603#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 175601#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 175599#L1073-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 175597#L525-27 assume 1 == ~t7_pc~0; 175594#L526-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 175592#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 175590#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 175588#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 175586#L1081-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 175584#L544-27 assume !(1 == ~t8_pc~0); 175582#L544-29 is_transmit8_triggered_~__retres1~8 := 0; 175579#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 175577#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 175575#L1089-27 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 175573#L1089-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 175571#L921-3 assume 1 == ~M_E~0;~M_E~0 := 2; 175569#L921-5 assume !(1 == ~T1_E~0); 175567#L926-3 assume !(1 == ~T2_E~0); 175565#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 175563#L936-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 175561#L941-3 assume !(1 == ~T5_E~0); 175559#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 175557#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 175555#L956-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 175553#L961-3 assume !(1 == ~E_1~0); 175551#L966-3 assume !(1 == ~E_2~0); 175549#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 175547#L976-3 assume 1 == ~E_4~0;~E_4~0 := 2; 175545#L981-3 assume !(1 == ~E_5~0); 175543#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 175541#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 175539#L996-3 assume 1 == ~E_8~0;~E_8~0 := 2; 175537#L1001-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 175531#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 175522#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 175520#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 175518#L1281 assume !(0 == start_simulation_~tmp~3); 175516#L1281-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 175515#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 175506#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 175504#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 175501#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 175499#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 175497#L1244 start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 175495#L1294 assume !(0 != start_simulation_~tmp___0~1); 170244#L1262-3 [2018-11-18 14:32:34,032 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:34,033 INFO L82 PathProgramCache]: Analyzing trace with hash -969699903, now seen corresponding path program 1 times [2018-11-18 14:32:34,033 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:34,033 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:34,034 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:34,034 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:34,034 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:34,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:34,110 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:34,110 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:34,110 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 14:32:34,110 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 14:32:34,110 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:34,111 INFO L82 PathProgramCache]: Analyzing trace with hash 451678227, now seen corresponding path program 1 times [2018-11-18 14:32:34,111 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:34,111 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:34,111 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:34,112 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:34,112 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:34,118 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:34,146 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:34,147 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:34,147 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:32:34,147 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 14:32:34,147 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 14:32:34,147 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 14:32:34,147 INFO L87 Difference]: Start difference. First operand 21324 states and 29951 transitions. cyclomatic complexity: 8659 Second operand 5 states. [2018-11-18 14:32:34,480 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:32:34,480 INFO L93 Difference]: Finished difference Result 56421 states and 79018 transitions. [2018-11-18 14:32:34,482 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 14:32:34,482 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 56421 states and 79018 transitions. [2018-11-18 14:32:34,689 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 55824 [2018-11-18 14:32:34,873 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 56421 states to 56421 states and 79018 transitions. [2018-11-18 14:32:34,873 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 56421 [2018-11-18 14:32:34,906 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 56421 [2018-11-18 14:32:34,906 INFO L73 IsDeterministic]: Start isDeterministic. Operand 56421 states and 79018 transitions. [2018-11-18 14:32:35,092 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:32:35,093 INFO L705 BuchiCegarLoop]: Abstraction has 56421 states and 79018 transitions. [2018-11-18 14:32:35,114 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 56421 states and 79018 transitions. [2018-11-18 14:32:35,283 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 56421 to 22095. [2018-11-18 14:32:35,283 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22095 states. [2018-11-18 14:32:35,302 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22095 states to 22095 states and 30722 transitions. [2018-11-18 14:32:35,302 INFO L728 BuchiCegarLoop]: Abstraction has 22095 states and 30722 transitions. [2018-11-18 14:32:35,302 INFO L608 BuchiCegarLoop]: Abstraction has 22095 states and 30722 transitions. [2018-11-18 14:32:35,303 INFO L442 BuchiCegarLoop]: ======== Iteration 19============ [2018-11-18 14:32:35,303 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22095 states and 30722 transitions. [2018-11-18 14:32:35,340 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 21856 [2018-11-18 14:32:35,340 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:32:35,340 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:32:35,341 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:35,341 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:35,341 INFO L794 eck$LassoCheckResult]: Stem: 247513#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 247402#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 247403#L1225 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 247905#L564 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 247439#L571 assume 1 == ~m_i~0;~m_st~0 := 0; 247420#L571-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 247121#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 247122#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 247907#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 247647#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 247243#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 247244#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 247897#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 247785#L611-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 247786#L828 assume !(0 == ~M_E~0); 247915#L828-2 assume !(0 == ~T1_E~0); 247541#L833-1 assume !(0 == ~T2_E~0); 247258#L838-1 assume !(0 == ~T3_E~0); 247259#L843-1 assume !(0 == ~T4_E~0); 248012#L848-1 assume !(0 == ~T5_E~0); 247797#L853-1 assume !(0 == ~T6_E~0); 247522#L858-1 assume !(0 == ~T7_E~0); 247043#L863-1 assume !(0 == ~T8_E~0); 247044#L868-1 assume !(0 == ~E_1~0); 247739#L873-1 assume !(0 == ~E_2~0); 247618#L878-1 assume !(0 == ~E_3~0); 247372#L883-1 assume !(0 == ~E_4~0); 247373#L888-1 assume !(0 == ~E_5~0); 247871#L893-1 assume !(0 == ~E_6~0); 247585#L898-1 assume !(0 == ~E_7~0); 247501#L903-1 assume !(0 == ~E_8~0); 247194#L908-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 247195#L392 assume !(1 == ~m_pc~0); 247564#L392-2 is_master_triggered_~__retres1~0 := 0; 247571#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 248058#L404 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 247878#L1025 assume !(0 != activate_threads_~tmp~1); 247879#L1025-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 247723#L411 assume !(1 == ~t1_pc~0); 247690#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 247102#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 247103#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 247224#L1033 assume !(0 != activate_threads_~tmp___0~0); 247446#L1033-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 247447#L430 assume !(1 == ~t2_pc~0); 247888#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 247292#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 247245#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 247246#L1041 assume !(0 != activate_threads_~tmp___1~0); 248089#L1041-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 248090#L449 assume !(1 == ~t3_pc~0); 247962#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 247599#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 247600#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 247901#L1049 assume !(0 != activate_threads_~tmp___2~0); 247902#L1049-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 247142#L468 assume !(1 == ~t4_pc~0); 247143#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 247152#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 247578#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 247507#L1057 assume !(0 != activate_threads_~tmp___3~0); 247508#L1057-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 247357#L487 assume !(1 == ~t5_pc~0); 247098#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 247359#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 247710#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 247711#L1065 assume !(0 != activate_threads_~tmp___4~0); 248103#L1065-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 247521#L506 assume !(1 == ~t6_pc~0); 247518#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 247519#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 247899#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 247813#L1073 assume !(0 != activate_threads_~tmp___5~0); 247814#L1073-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 247648#L525 assume !(1 == ~t7_pc~0); 247595#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 247594#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 248091#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 247378#L1081 assume !(0 != activate_threads_~tmp___6~0); 247379#L1081-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 247380#L544 assume !(1 == ~t8_pc~0); 247662#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 247037#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 247038#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 247176#L1089 assume !(0 != activate_threads_~tmp___7~0); 247940#L1089-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 247530#L921 assume !(1 == ~M_E~0); 247531#L921-2 assume !(1 == ~T1_E~0); 247254#L926-1 assume !(1 == ~T2_E~0); 247255#L931-1 assume !(1 == ~T3_E~0); 248010#L936-1 assume !(1 == ~T4_E~0); 247808#L941-1 assume !(1 == ~T5_E~0); 247528#L946-1 assume !(1 == ~T6_E~0); 247055#L951-1 assume !(1 == ~T7_E~0); 247056#L956-1 assume !(1 == ~T8_E~0); 247904#L961-1 assume !(1 == ~E_1~0); 247623#L966-1 assume !(1 == ~E_2~0); 247383#L971-1 assume !(1 == ~E_3~0); 247384#L976-1 assume !(1 == ~E_4~0); 247867#L981-1 assume !(1 == ~E_5~0); 247583#L986-1 assume !(1 == ~E_6~0); 247496#L991-1 assume !(1 == ~E_7~0); 247182#L996-1 assume !(1 == ~E_8~0); 247183#L1001-1 assume { :end_inline_reset_delta_events } true; 248029#L1262-3 [2018-11-18 14:32:35,342 INFO L796 eck$LassoCheckResult]: Loop: 248029#L1262-3 assume true; 254371#L1262-1 assume !false; 254093#L1263 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 254091#L803 assume true; 254089#L681-1 assume !false; 254087#L682 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 254077#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 254068#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 254066#L672 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 254064#L686 assume !(0 != eval_~tmp~0); 254065#L818 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 254586#L564-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 254584#L828-3 assume 0 == ~M_E~0;~M_E~0 := 1; 254582#L828-5 assume !(0 == ~T1_E~0); 254580#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 254578#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 254576#L843-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 254574#L848-3 assume !(0 == ~T5_E~0); 254572#L853-3 assume !(0 == ~T6_E~0); 254570#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 254568#L863-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 254567#L868-3 assume !(0 == ~E_1~0); 254566#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 254565#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 254564#L883-3 assume 0 == ~E_4~0;~E_4~0 := 1; 254563#L888-3 assume !(0 == ~E_5~0); 254562#L893-3 assume !(0 == ~E_6~0); 254561#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 254560#L903-3 assume 0 == ~E_8~0;~E_8~0 := 1; 254559#L908-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 254558#L392-27 assume !(1 == ~m_pc~0); 254557#L392-29 is_master_triggered_~__retres1~0 := 0; 254555#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 254554#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 254553#L1025-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 254552#L1025-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 254551#L411-27 assume !(1 == ~t1_pc~0); 254550#L411-29 is_transmit1_triggered_~__retres1~1 := 0; 254549#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 254548#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 254547#L1033-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 254546#L1033-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 254545#L430-27 assume !(1 == ~t2_pc~0); 254544#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 254543#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 254542#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 254541#L1041-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 254540#L1041-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 254539#L449-27 assume !(1 == ~t3_pc~0); 254538#L449-29 is_transmit3_triggered_~__retres1~3 := 0; 254536#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 254534#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 254532#L1049-27 assume !(0 != activate_threads_~tmp___2~0); 254530#L1049-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 254529#L468-27 assume !(1 == ~t4_pc~0); 254528#L468-29 is_transmit4_triggered_~__retres1~4 := 0; 254527#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 254526#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 254525#L1057-27 assume !(0 != activate_threads_~tmp___3~0); 254496#L1057-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 254494#L487-27 assume !(1 == ~t5_pc~0); 254491#L487-29 is_transmit5_triggered_~__retres1~5 := 0; 254489#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 254487#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 254485#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 254483#L1065-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 254481#L506-27 assume !(1 == ~t6_pc~0); 254478#L506-29 is_transmit6_triggered_~__retres1~6 := 0; 254476#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 254474#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 254472#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 254470#L1073-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 254468#L525-27 assume !(1 == ~t7_pc~0); 254466#L525-29 is_transmit7_triggered_~__retres1~7 := 0; 254463#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 254461#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 254459#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 254457#L1081-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 254455#L544-27 assume !(1 == ~t8_pc~0); 254453#L544-29 is_transmit8_triggered_~__retres1~8 := 0; 254450#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 254448#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 254446#L1089-27 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 254444#L1089-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 254442#L921-3 assume 1 == ~M_E~0;~M_E~0 := 2; 254440#L921-5 assume !(1 == ~T1_E~0); 254438#L926-3 assume !(1 == ~T2_E~0); 254436#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 254434#L936-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 254432#L941-3 assume !(1 == ~T5_E~0); 254430#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 254428#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 254426#L956-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 254424#L961-3 assume !(1 == ~E_1~0); 254422#L966-3 assume !(1 == ~E_2~0); 254420#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 254418#L976-3 assume 1 == ~E_4~0;~E_4~0 := 2; 254416#L981-3 assume !(1 == ~E_5~0); 254414#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 254412#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 254410#L996-3 assume 1 == ~E_8~0;~E_8~0 := 2; 254408#L1001-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 254402#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 254393#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 254391#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 254389#L1281 assume !(0 == start_simulation_~tmp~3); 254387#L1281-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 254386#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 254377#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 254376#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 254375#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 254374#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 254373#L1244 start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 254372#L1294 assume !(0 != start_simulation_~tmp___0~1); 248029#L1262-3 [2018-11-18 14:32:35,342 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:35,342 INFO L82 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 1 times [2018-11-18 14:32:35,342 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:35,342 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:35,343 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:35,343 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:35,343 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:35,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:32:35,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:32:35,389 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:35,389 INFO L82 PathProgramCache]: Analyzing trace with hash -1024563920, now seen corresponding path program 1 times [2018-11-18 14:32:35,390 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:35,390 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:35,390 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:35,390 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:35,390 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:35,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:35,422 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:35,423 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:35,423 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:32:35,423 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 14:32:35,423 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 14:32:35,423 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 14:32:35,424 INFO L87 Difference]: Start difference. First operand 22095 states and 30722 transitions. cyclomatic complexity: 8659 Second operand 3 states. [2018-11-18 14:32:35,488 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:32:35,488 INFO L93 Difference]: Finished difference Result 24782 states and 34477 transitions. [2018-11-18 14:32:35,489 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 14:32:35,489 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 24782 states and 34477 transitions. [2018-11-18 14:32:35,548 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 24464 [2018-11-18 14:32:35,590 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 24782 states to 24782 states and 34477 transitions. [2018-11-18 14:32:35,590 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 24782 [2018-11-18 14:32:35,601 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 24782 [2018-11-18 14:32:35,601 INFO L73 IsDeterministic]: Start isDeterministic. Operand 24782 states and 34477 transitions. [2018-11-18 14:32:35,611 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:32:35,611 INFO L705 BuchiCegarLoop]: Abstraction has 24782 states and 34477 transitions. [2018-11-18 14:32:35,622 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24782 states and 34477 transitions. [2018-11-18 14:32:35,744 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24782 to 24782. [2018-11-18 14:32:35,744 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24782 states. [2018-11-18 14:32:35,768 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24782 states to 24782 states and 34477 transitions. [2018-11-18 14:32:35,768 INFO L728 BuchiCegarLoop]: Abstraction has 24782 states and 34477 transitions. [2018-11-18 14:32:35,769 INFO L608 BuchiCegarLoop]: Abstraction has 24782 states and 34477 transitions. [2018-11-18 14:32:35,769 INFO L442 BuchiCegarLoop]: ======== Iteration 20============ [2018-11-18 14:32:35,769 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24782 states and 34477 transitions. [2018-11-18 14:32:35,812 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 24464 [2018-11-18 14:32:35,813 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:32:35,813 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:32:35,814 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:35,814 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:35,814 INFO L794 eck$LassoCheckResult]: Stem: 294402#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 294289#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 294290#L1225 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 294822#L564 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 294326#L571 assume 1 == ~m_i~0;~m_st~0 := 0; 294307#L571-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 294004#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 294005#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 294826#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 294544#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 294124#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 294125#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 294812#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 294690#L611-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 294691#L828 assume !(0 == ~M_E~0); 294834#L828-2 assume !(0 == ~T1_E~0); 294430#L833-1 assume 0 == ~T2_E~0;~T2_E~0 := 1; 294139#L838-1 assume !(0 == ~T3_E~0); 294140#L843-1 assume !(0 == ~T4_E~0); 294925#L848-1 assume !(0 == ~T5_E~0); 294926#L853-1 assume !(0 == ~T6_E~0); 294412#L858-1 assume !(0 == ~T7_E~0); 294413#L863-1 assume !(0 == ~T8_E~0); 294890#L868-1 assume !(0 == ~E_1~0); 294891#L873-1 assume !(0 == ~E_2~0); 294513#L878-1 assume !(0 == ~E_3~0); 294514#L883-1 assume !(0 == ~E_4~0); 294944#L888-1 assume !(0 == ~E_5~0); 294945#L893-1 assume !(0 == ~E_6~0); 294478#L898-1 assume !(0 == ~E_7~0); 294479#L903-1 assume !(0 == ~E_8~0); 294076#L908-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 294077#L392 assume !(1 == ~m_pc~0); 294461#L392-2 is_master_triggered_~__retres1~0 := 0; 294462#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 295028#L404 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 295029#L1025 assume !(0 != activate_threads_~tmp~1); 294791#L1025-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 294792#L411 assume !(1 == ~t1_pc~0); 294591#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 294592#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 294103#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 294104#L1033 assume !(0 != activate_threads_~tmp___0~0); 294333#L1033-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 294799#L430 assume !(1 == ~t2_pc~0); 294800#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 294173#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 294174#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 295004#L1041 assume !(0 != activate_threads_~tmp___1~0); 295005#L1041-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 295013#L449 assume !(1 == ~t3_pc~0); 294877#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 295062#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 295063#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 294816#L1049 assume !(0 != activate_threads_~tmp___2~0); 294817#L1049-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 294023#L468 assume !(1 == ~t4_pc~0); 294024#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 294698#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 294699#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 294394#L1057 assume !(0 != activate_threads_~tmp___3~0); 294395#L1057-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 294241#L487 assume !(1 == ~t5_pc~0); 293981#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 294829#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 294612#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 294613#L1065 assume !(0 != activate_threads_~tmp___4~0); 295025#L1065-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 294411#L506 assume !(1 == ~t6_pc~0); 294406#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 294407#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 294814#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 294723#L1073 assume !(0 != activate_threads_~tmp___5~0); 294724#L1073-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 294545#L525 assume !(1 == ~t7_pc~0); 294490#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 294489#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 295008#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 294264#L1081 assume !(0 != activate_threads_~tmp___6~0); 294265#L1081-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 294266#L544 assume !(1 == ~t8_pc~0); 294559#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 293920#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 293921#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 294057#L1089 assume !(0 != activate_threads_~tmp___7~0); 294856#L1089-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 294420#L921 assume !(1 == ~M_E~0); 294421#L921-2 assume !(1 == ~T1_E~0); 294135#L926-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 294136#L931-1 assume !(1 == ~T3_E~0); 294923#L936-1 assume !(1 == ~T4_E~0); 294715#L941-1 assume !(1 == ~T5_E~0); 294418#L946-1 assume !(1 == ~T6_E~0); 293938#L951-1 assume !(1 == ~T7_E~0); 293939#L956-1 assume !(1 == ~T8_E~0); 294821#L961-1 assume !(1 == ~E_1~0); 294519#L966-1 assume !(1 == ~E_2~0); 294269#L971-1 assume !(1 == ~E_3~0); 294270#L976-1 assume !(1 == ~E_4~0); 294774#L981-1 assume !(1 == ~E_5~0); 294475#L986-1 assume !(1 == ~E_6~0); 294381#L991-1 assume !(1 == ~E_7~0); 294063#L996-1 assume !(1 == ~E_8~0); 294064#L1001-1 assume { :end_inline_reset_delta_events } true; 294941#L1262-3 [2018-11-18 14:32:35,815 INFO L796 eck$LassoCheckResult]: Loop: 294941#L1262-3 assume true; 301194#L1262-1 assume !false; 301187#L1263 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 298890#L803 assume true; 301176#L681-1 assume !false; 301174#L682 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 301075#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 301057#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 301047#L672 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 301036#L686 assume !(0 != eval_~tmp~0); 301037#L818 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 301803#L564-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 301797#L828-3 assume 0 == ~M_E~0;~M_E~0 := 1; 301789#L828-5 assume !(0 == ~T1_E~0); 301782#L833-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 301783#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 302227#L843-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 302224#L848-3 assume !(0 == ~T5_E~0); 302222#L853-3 assume !(0 == ~T6_E~0); 302220#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 302217#L863-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 302215#L868-3 assume !(0 == ~E_1~0); 302213#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 302211#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 302209#L883-3 assume 0 == ~E_4~0;~E_4~0 := 1; 302207#L888-3 assume !(0 == ~E_5~0); 302204#L893-3 assume !(0 == ~E_6~0); 302202#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 302200#L903-3 assume 0 == ~E_8~0;~E_8~0 := 1; 301904#L908-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 301895#L392-27 assume !(1 == ~m_pc~0); 301892#L392-29 is_master_triggered_~__retres1~0 := 0; 301889#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 301887#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 301885#L1025-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 301883#L1025-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 301881#L411-27 assume !(1 == ~t1_pc~0); 301879#L411-29 is_transmit1_triggered_~__retres1~1 := 0; 301877#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 301875#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 301873#L1033-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 301871#L1033-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 301869#L430-27 assume !(1 == ~t2_pc~0); 301863#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 301859#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 301855#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 301851#L1041-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 301847#L1041-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 301840#L449-27 assume 1 == ~t3_pc~0; 301828#L450-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 301821#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 301815#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 301809#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 301804#L1049-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 301798#L468-27 assume !(1 == ~t4_pc~0); 301790#L468-29 is_transmit4_triggered_~__retres1~4 := 0; 301784#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 301776#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 301770#L1057-27 assume !(0 != activate_threads_~tmp___3~0); 301764#L1057-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 301758#L487-27 assume !(1 == ~t5_pc~0); 301749#L487-29 is_transmit5_triggered_~__retres1~5 := 0; 301743#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 301737#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 301730#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 301724#L1065-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 301718#L506-27 assume !(1 == ~t6_pc~0); 301712#L506-29 is_transmit6_triggered_~__retres1~6 := 0; 301705#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 301699#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 301691#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 301683#L1073-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 301677#L525-27 assume 1 == ~t7_pc~0; 301670#L526-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 301663#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 301658#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 301652#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 301647#L1081-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 301641#L544-27 assume !(1 == ~t8_pc~0); 301635#L544-29 is_transmit8_triggered_~__retres1~8 := 0; 301629#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 301622#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 301618#L1089-27 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 301505#L1089-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 301476#L921-3 assume 1 == ~M_E~0;~M_E~0 := 2; 301470#L921-5 assume !(1 == ~T1_E~0); 301464#L926-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 301458#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 301451#L936-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 301445#L941-3 assume !(1 == ~T5_E~0); 301439#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 301433#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 301427#L956-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 301422#L961-3 assume !(1 == ~E_1~0); 301417#L966-3 assume !(1 == ~E_2~0); 301412#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 301407#L976-3 assume 1 == ~E_4~0;~E_4~0 := 2; 301402#L981-3 assume !(1 == ~E_5~0); 301396#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 301388#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 301383#L996-3 assume 1 == ~E_8~0;~E_8~0 := 2; 301378#L1001-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 301286#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 301277#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 301274#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 301271#L1281 assume !(0 == start_simulation_~tmp~3); 301268#L1281-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 301265#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 301242#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 301233#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 301226#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 301219#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 301213#L1244 start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 301206#L1294 assume !(0 != start_simulation_~tmp___0~1); 294941#L1262-3 [2018-11-18 14:32:35,815 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:35,815 INFO L82 PathProgramCache]: Analyzing trace with hash 564981891, now seen corresponding path program 1 times [2018-11-18 14:32:35,815 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:35,815 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:35,816 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:35,816 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:35,816 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:35,820 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:35,844 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:35,845 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:35,845 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 14:32:35,845 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 14:32:35,845 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:35,845 INFO L82 PathProgramCache]: Analyzing trace with hash 2139125878, now seen corresponding path program 1 times [2018-11-18 14:32:35,845 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:35,845 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:35,846 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:35,846 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:35,846 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:35,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:35,883 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:35,883 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:35,883 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:32:35,883 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 14:32:35,883 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 14:32:35,883 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 14:32:35,884 INFO L87 Difference]: Start difference. First operand 24782 states and 34477 transitions. cyclomatic complexity: 9727 Second operand 3 states. [2018-11-18 14:32:35,939 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:32:35,939 INFO L93 Difference]: Finished difference Result 22095 states and 30624 transitions. [2018-11-18 14:32:35,940 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 14:32:35,940 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22095 states and 30624 transitions. [2018-11-18 14:32:35,989 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 21856 [2018-11-18 14:32:36,021 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22095 states to 22095 states and 30624 transitions. [2018-11-18 14:32:36,021 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22095 [2018-11-18 14:32:36,030 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22095 [2018-11-18 14:32:36,030 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22095 states and 30624 transitions. [2018-11-18 14:32:36,039 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:32:36,039 INFO L705 BuchiCegarLoop]: Abstraction has 22095 states and 30624 transitions. [2018-11-18 14:32:36,049 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22095 states and 30624 transitions. [2018-11-18 14:32:36,353 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22095 to 22095. [2018-11-18 14:32:36,353 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22095 states. [2018-11-18 14:32:36,374 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22095 states to 22095 states and 30624 transitions. [2018-11-18 14:32:36,374 INFO L728 BuchiCegarLoop]: Abstraction has 22095 states and 30624 transitions. [2018-11-18 14:32:36,374 INFO L608 BuchiCegarLoop]: Abstraction has 22095 states and 30624 transitions. [2018-11-18 14:32:36,374 INFO L442 BuchiCegarLoop]: ======== Iteration 21============ [2018-11-18 14:32:36,374 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22095 states and 30624 transitions. [2018-11-18 14:32:36,412 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 21856 [2018-11-18 14:32:36,412 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:32:36,412 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:32:36,414 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:36,414 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:36,414 INFO L794 eck$LassoCheckResult]: Stem: 341282#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 341170#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 341171#L1225 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 341657#L564 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 341207#L571 assume 1 == ~m_i~0;~m_st~0 := 0; 341188#L571-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 340888#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 340889#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 341665#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 341414#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 341005#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 341006#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 341648#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 341548#L611-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 341549#L828 assume !(0 == ~M_E~0); 341673#L828-2 assume !(0 == ~T1_E~0); 341309#L833-1 assume !(0 == ~T2_E~0); 341020#L838-1 assume !(0 == ~T3_E~0); 341021#L843-1 assume !(0 == ~T4_E~0); 341761#L848-1 assume !(0 == ~T5_E~0); 341558#L853-1 assume !(0 == ~T6_E~0); 341292#L858-1 assume !(0 == ~T7_E~0); 340810#L863-1 assume !(0 == ~T8_E~0); 340811#L868-1 assume !(0 == ~E_1~0); 341508#L873-1 assume !(0 == ~E_2~0); 341385#L878-1 assume !(0 == ~E_3~0); 341139#L883-1 assume !(0 == ~E_4~0); 341140#L888-1 assume !(0 == ~E_5~0); 341624#L893-1 assume !(0 == ~E_6~0); 341352#L898-1 assume !(0 == ~E_7~0); 341271#L903-1 assume !(0 == ~E_8~0); 340957#L908-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 340958#L392 assume !(1 == ~m_pc~0); 341332#L392-2 is_master_triggered_~__retres1~0 := 0; 341338#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 341811#L404 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 341630#L1025 assume !(0 != activate_threads_~tmp~1); 341631#L1025-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 341493#L411 assume !(1 == ~t1_pc~0); 341462#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 340871#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 340872#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 340987#L1033 assume !(0 != activate_threads_~tmp___0~0); 341215#L1033-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 341216#L430 assume !(1 == ~t2_pc~0); 341639#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 341059#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 341007#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 341008#L1041 assume !(0 != activate_threads_~tmp___1~0); 341844#L1041-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 341845#L449 assume !(1 == ~t3_pc~0); 341718#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 341854#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 341869#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 341652#L1049 assume !(0 != activate_threads_~tmp___2~0); 341653#L1049-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 340907#L468 assume !(1 == ~t4_pc~0); 340908#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 340916#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 341345#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 341277#L1057 assume !(0 != activate_threads_~tmp___3~0); 341278#L1057-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 341124#L487 assume !(1 == ~t5_pc~0); 340865#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 341126#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 341481#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 341482#L1065 assume !(0 != activate_threads_~tmp___4~0); 341860#L1065-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 341291#L506 assume !(1 == ~t6_pc~0); 341286#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 341287#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 341650#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 341571#L1073 assume !(0 != activate_threads_~tmp___5~0); 341572#L1073-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 341415#L525 assume !(1 == ~t7_pc~0); 341362#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 341361#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 341846#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 341145#L1081 assume !(0 != activate_threads_~tmp___6~0); 341146#L1081-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 341147#L544 assume !(1 == ~t8_pc~0); 341431#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 340804#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 340805#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 340939#L1089 assume !(0 != activate_threads_~tmp___7~0); 341698#L1089-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 341299#L921 assume !(1 == ~M_E~0); 341300#L921-2 assume !(1 == ~T1_E~0); 341016#L926-1 assume !(1 == ~T2_E~0); 341017#L931-1 assume !(1 == ~T3_E~0); 341759#L936-1 assume !(1 == ~T4_E~0); 341565#L941-1 assume !(1 == ~T5_E~0); 341297#L946-1 assume !(1 == ~T6_E~0); 340822#L951-1 assume !(1 == ~T7_E~0); 340823#L956-1 assume !(1 == ~T8_E~0); 341656#L961-1 assume !(1 == ~E_1~0); 341390#L966-1 assume !(1 == ~E_2~0); 341150#L971-1 assume !(1 == ~E_3~0); 341151#L976-1 assume !(1 == ~E_4~0); 341619#L981-1 assume !(1 == ~E_5~0); 341350#L986-1 assume !(1 == ~E_6~0); 341263#L991-1 assume !(1 == ~E_7~0); 340947#L996-1 assume !(1 == ~E_8~0); 340948#L1001-1 assume { :end_inline_reset_delta_events } true; 341778#L1262-3 [2018-11-18 14:32:36,414 INFO L796 eck$LassoCheckResult]: Loop: 341778#L1262-3 assume true; 349241#L1262-1 assume !false; 348970#L1263 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 348968#L803 assume true; 348966#L681-1 assume !false; 348964#L682 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 348956#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 348947#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 348945#L672 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 348942#L686 assume !(0 != eval_~tmp~0); 348943#L818 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 349459#L564-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 349457#L828-3 assume 0 == ~M_E~0;~M_E~0 := 1; 349455#L828-5 assume !(0 == ~T1_E~0); 349453#L833-3 assume !(0 == ~T2_E~0); 349451#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 349449#L843-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 349447#L848-3 assume !(0 == ~T5_E~0); 349445#L853-3 assume !(0 == ~T6_E~0); 349443#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 349441#L863-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 349439#L868-3 assume !(0 == ~E_1~0); 349437#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 349435#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 349433#L883-3 assume 0 == ~E_4~0;~E_4~0 := 1; 349431#L888-3 assume !(0 == ~E_5~0); 349429#L893-3 assume !(0 == ~E_6~0); 349427#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 349425#L903-3 assume 0 == ~E_8~0;~E_8~0 := 1; 349423#L908-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 349421#L392-27 assume !(1 == ~m_pc~0); 349419#L392-29 is_master_triggered_~__retres1~0 := 0; 349416#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 349415#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 349414#L1025-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 349413#L1025-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 349412#L411-27 assume !(1 == ~t1_pc~0); 349411#L411-29 is_transmit1_triggered_~__retres1~1 := 0; 349410#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 349409#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 349408#L1033-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 349407#L1033-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 349405#L430-27 assume !(1 == ~t2_pc~0); 349404#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 349403#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 349402#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 349401#L1041-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 349400#L1041-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 349399#L449-27 assume !(1 == ~t3_pc~0); 349396#L449-29 is_transmit3_triggered_~__retres1~3 := 0; 349394#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 349393#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 349392#L1049-27 assume !(0 != activate_threads_~tmp___2~0); 349390#L1049-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 349388#L468-27 assume !(1 == ~t4_pc~0); 349386#L468-29 is_transmit4_triggered_~__retres1~4 := 0; 349384#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 349381#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 349379#L1057-27 assume !(0 != activate_threads_~tmp___3~0); 349377#L1057-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 349375#L487-27 assume !(1 == ~t5_pc~0); 349372#L487-29 is_transmit5_triggered_~__retres1~5 := 0; 349370#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 349368#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 349366#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 349364#L1065-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 349362#L506-27 assume !(1 == ~t6_pc~0); 349360#L506-29 is_transmit6_triggered_~__retres1~6 := 0; 349358#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 349356#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 349354#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 349352#L1073-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 349350#L525-27 assume !(1 == ~t7_pc~0); 349348#L525-29 is_transmit7_triggered_~__retres1~7 := 0; 349343#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 349341#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 349339#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 349337#L1081-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 349334#L544-27 assume !(1 == ~t8_pc~0); 349332#L544-29 is_transmit8_triggered_~__retres1~8 := 0; 349330#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 349328#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 349326#L1089-27 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 349324#L1089-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 349322#L921-3 assume 1 == ~M_E~0;~M_E~0 := 2; 349320#L921-5 assume !(1 == ~T1_E~0); 349317#L926-3 assume !(1 == ~T2_E~0); 349315#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 349313#L936-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 349311#L941-3 assume !(1 == ~T5_E~0); 349309#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 349307#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 349305#L956-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 349303#L961-3 assume !(1 == ~E_1~0); 349301#L966-3 assume !(1 == ~E_2~0); 349299#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 349297#L976-3 assume 1 == ~E_4~0;~E_4~0 := 2; 349295#L981-3 assume !(1 == ~E_5~0); 349293#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 349290#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 349288#L996-3 assume 1 == ~E_8~0;~E_8~0 := 2; 349286#L1001-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 349280#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 349271#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 349269#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 349266#L1281 assume !(0 == start_simulation_~tmp~3); 349263#L1281-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 349258#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 349248#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 349246#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 349245#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 349244#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 349243#L1244 start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 349242#L1294 assume !(0 != start_simulation_~tmp___0~1); 341778#L1262-3 [2018-11-18 14:32:36,414 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:36,415 INFO L82 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 2 times [2018-11-18 14:32:36,415 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:36,415 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:36,415 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:36,415 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:36,415 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:36,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:32:36,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:32:36,456 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:36,456 INFO L82 PathProgramCache]: Analyzing trace with hash 872932846, now seen corresponding path program 1 times [2018-11-18 14:32:36,456 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:36,456 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:36,457 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:36,457 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 14:32:36,457 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:36,462 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:36,486 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:36,486 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:36,486 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:32:36,487 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 14:32:36,487 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 14:32:36,487 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 14:32:36,487 INFO L87 Difference]: Start difference. First operand 22095 states and 30624 transitions. cyclomatic complexity: 8561 Second operand 3 states. [2018-11-18 14:32:36,629 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:32:36,629 INFO L93 Difference]: Finished difference Result 33558 states and 46218 transitions. [2018-11-18 14:32:36,630 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 14:32:36,630 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 33558 states and 46218 transitions. [2018-11-18 14:32:36,708 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 33192 [2018-11-18 14:32:36,758 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 33558 states to 33558 states and 46218 transitions. [2018-11-18 14:32:36,758 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 33558 [2018-11-18 14:32:36,772 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 33558 [2018-11-18 14:32:36,772 INFO L73 IsDeterministic]: Start isDeterministic. Operand 33558 states and 46218 transitions. [2018-11-18 14:32:36,785 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:32:36,785 INFO L705 BuchiCegarLoop]: Abstraction has 33558 states and 46218 transitions. [2018-11-18 14:32:36,798 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33558 states and 46218 transitions. [2018-11-18 14:32:36,945 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33558 to 33550. [2018-11-18 14:32:36,946 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 33550 states. [2018-11-18 14:32:36,985 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33550 states to 33550 states and 46210 transitions. [2018-11-18 14:32:36,985 INFO L728 BuchiCegarLoop]: Abstraction has 33550 states and 46210 transitions. [2018-11-18 14:32:36,985 INFO L608 BuchiCegarLoop]: Abstraction has 33550 states and 46210 transitions. [2018-11-18 14:32:36,985 INFO L442 BuchiCegarLoop]: ======== Iteration 22============ [2018-11-18 14:32:36,985 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 33550 states and 46210 transitions. [2018-11-18 14:32:37,054 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 33184 [2018-11-18 14:32:37,054 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:32:37,054 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:32:37,055 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:37,055 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:37,056 INFO L794 eck$LassoCheckResult]: Stem: 396935#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 396828#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 396829#L1225 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 397332#L564 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 396865#L571 assume 1 == ~m_i~0;~m_st~0 := 0; 396846#L571-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 396546#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 396547#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 397334#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 397068#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 396667#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 396668#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 397321#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 397196#L611-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 397197#L828 assume !(0 == ~M_E~0); 397342#L828-2 assume !(0 == ~T1_E~0); 396960#L833-1 assume !(0 == ~T2_E~0); 396682#L838-1 assume !(0 == ~T3_E~0); 396683#L843-1 assume !(0 == ~T4_E~0); 397427#L848-1 assume !(0 == ~T5_E~0); 397207#L853-1 assume !(0 == ~T6_E~0); 396943#L858-1 assume !(0 == ~T7_E~0); 396469#L863-1 assume !(0 == ~T8_E~0); 396470#L868-1 assume !(0 == ~E_1~0); 397153#L873-1 assume 0 == ~E_2~0;~E_2~0 := 1; 397154#L878-1 assume !(0 == ~E_3~0); 396796#L883-1 assume !(0 == ~E_4~0); 396797#L888-1 assume !(0 == ~E_5~0); 397284#L893-1 assume !(0 == ~E_6~0); 397285#L898-1 assume !(0 == ~E_7~0); 396922#L903-1 assume !(0 == ~E_8~0); 396923#L908-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 396983#L392 assume !(1 == ~m_pc~0); 396984#L392-2 is_master_triggered_~__retres1~0 := 0; 397474#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 397475#L404 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 397295#L1025 assume !(0 != activate_threads_~tmp~1); 397296#L1025-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 397139#L411 assume !(1 == ~t1_pc~0); 397140#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 396528#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 396529#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 397560#L1033 assume !(0 != activate_threads_~tmp___0~0); 396874#L1033-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 396875#L430 assume !(1 == ~t2_pc~0); 397312#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 397313#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 397559#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 397508#L1041 assume !(0 != activate_threads_~tmp___1~0); 397509#L1041-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 397518#L449 assume !(1 == ~t3_pc~0); 397519#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 397523#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 397550#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 397551#L1049 assume !(0 != activate_threads_~tmp___2~0); 397328#L1049-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 397329#L468 assume !(1 == ~t4_pc~0); 396576#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 396577#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 396998#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 396999#L1057 assume !(0 != activate_threads_~tmp___3~0); 396931#L1057-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 396932#L487 assume !(1 == ~t5_pc~0); 396782#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 396783#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 397556#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 397555#L1065 assume !(0 != activate_threads_~tmp___4~0); 397529#L1065-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 397530#L506 assume !(1 == ~t6_pc~0); 396938#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 396939#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 397323#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 397324#L1073 assume !(0 != activate_threads_~tmp___5~0); 397228#L1073-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 397229#L525 assume !(1 == ~t7_pc~0); 397017#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 397016#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 397536#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 396802#L1081 assume !(0 != activate_threads_~tmp___6~0); 396803#L1081-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 397082#L544 assume !(1 == ~t8_pc~0); 397083#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 396463#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 396464#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 397548#L1089 assume !(0 != activate_threads_~tmp___7~0); 397547#L1089-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 397546#L921 assume !(1 == ~M_E~0); 397545#L921-2 assume !(1 == ~T1_E~0); 397544#L926-1 assume !(1 == ~T2_E~0); 397543#L931-1 assume !(1 == ~T3_E~0); 397542#L936-1 assume !(1 == ~T4_E~0); 397215#L941-1 assume !(1 == ~T5_E~0); 396948#L946-1 assume !(1 == ~T6_E~0); 396481#L951-1 assume !(1 == ~T7_E~0); 396482#L956-1 assume !(1 == ~T8_E~0); 397331#L961-1 assume !(1 == ~E_1~0); 397045#L966-1 assume 1 == ~E_2~0;~E_2~0 := 2; 396808#L971-1 assume !(1 == ~E_3~0); 396809#L976-1 assume !(1 == ~E_4~0); 397279#L981-1 assume !(1 == ~E_5~0); 397004#L986-1 assume !(1 == ~E_6~0); 396917#L991-1 assume !(1 == ~E_7~0); 396607#L996-1 assume !(1 == ~E_8~0); 396608#L1001-1 assume { :end_inline_reset_delta_events } true; 397443#L1262-3 [2018-11-18 14:32:37,056 INFO L796 eck$LassoCheckResult]: Loop: 397443#L1262-3 assume true; 403277#L1262-1 assume !false; 403166#L1263 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 403164#L803 assume true; 403162#L681-1 assume !false; 403160#L682 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 403154#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 403144#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 403142#L672 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 403139#L686 assume !(0 != eval_~tmp~0); 403140#L818 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 403500#L564-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 403498#L828-3 assume 0 == ~M_E~0;~M_E~0 := 1; 403496#L828-5 assume !(0 == ~T1_E~0); 403494#L833-3 assume !(0 == ~T2_E~0); 403492#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 403490#L843-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 403488#L848-3 assume !(0 == ~T5_E~0); 403486#L853-3 assume !(0 == ~T6_E~0); 403484#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 403482#L863-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 403481#L868-3 assume !(0 == ~E_1~0); 403479#L873-3 assume 0 == ~E_2~0;~E_2~0 := 1; 403478#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 403477#L883-3 assume 0 == ~E_4~0;~E_4~0 := 1; 403476#L888-3 assume !(0 == ~E_5~0); 403475#L893-3 assume !(0 == ~E_6~0); 403473#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 403472#L903-3 assume 0 == ~E_8~0;~E_8~0 := 1; 403471#L908-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 403470#L392-27 assume 1 == ~m_pc~0; 403468#L393-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 403466#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 403465#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 403464#L1025-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 403463#L1025-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 403462#L411-27 assume !(1 == ~t1_pc~0); 403460#L411-29 is_transmit1_triggered_~__retres1~1 := 0; 403457#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 403455#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 403453#L1033-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 403451#L1033-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 403449#L430-27 assume !(1 == ~t2_pc~0); 403447#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 403445#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 403443#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 403441#L1041-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 403439#L1041-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 403437#L449-27 assume 1 == ~t3_pc~0; 403435#L450-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 403436#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 403467#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 403426#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 403424#L1049-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 403422#L468-27 assume !(1 == ~t4_pc~0); 403418#L468-29 is_transmit4_triggered_~__retres1~4 := 0; 403416#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 403414#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 403412#L1057-27 assume !(0 != activate_threads_~tmp___3~0); 403409#L1057-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 403407#L487-27 assume !(1 == ~t5_pc~0); 403404#L487-29 is_transmit5_triggered_~__retres1~5 := 0; 403402#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 403400#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 403398#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 403396#L1065-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 403394#L506-27 assume !(1 == ~t6_pc~0); 403391#L506-29 is_transmit6_triggered_~__retres1~6 := 0; 403389#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 403387#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 403385#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 403383#L1073-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 403381#L525-27 assume 1 == ~t7_pc~0; 403378#L526-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 403376#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 403374#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 403372#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 403370#L1081-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 403368#L544-27 assume !(1 == ~t8_pc~0); 403366#L544-29 is_transmit8_triggered_~__retres1~8 := 0; 403363#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 403361#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 403359#L1089-27 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 403357#L1089-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 403355#L921-3 assume 1 == ~M_E~0;~M_E~0 := 2; 403353#L921-5 assume !(1 == ~T1_E~0); 403351#L926-3 assume !(1 == ~T2_E~0); 403349#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 403347#L936-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 403345#L941-3 assume !(1 == ~T5_E~0); 403343#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 403341#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 403339#L956-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 403337#L961-3 assume !(1 == ~E_1~0); 403335#L966-3 assume 1 == ~E_2~0;~E_2~0 := 2; 403332#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 403330#L976-3 assume 1 == ~E_4~0;~E_4~0 := 2; 403328#L981-3 assume !(1 == ~E_5~0); 403326#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 403324#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 403322#L996-3 assume 1 == ~E_8~0;~E_8~0 := 2; 403320#L1001-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 403314#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 403305#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 403303#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 403301#L1281 assume !(0 == start_simulation_~tmp~3); 403299#L1281-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 403298#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 403289#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 403288#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 403287#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 403285#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 403282#L1244 start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 403280#L1294 assume !(0 != start_simulation_~tmp___0~1); 397443#L1262-3 [2018-11-18 14:32:37,056 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:37,056 INFO L82 PathProgramCache]: Analyzing trace with hash 501068931, now seen corresponding path program 1 times [2018-11-18 14:32:37,056 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:37,056 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:37,057 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:37,057 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:37,057 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:37,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:37,093 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:37,093 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:37,093 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 14:32:37,093 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 14:32:37,093 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:37,094 INFO L82 PathProgramCache]: Analyzing trace with hash 504736789, now seen corresponding path program 1 times [2018-11-18 14:32:37,094 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:37,094 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:37,095 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:37,095 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:37,095 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:37,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:37,137 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:37,137 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:37,137 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 14:32:37,138 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 14:32:37,138 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 14:32:37,138 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 14:32:37,138 INFO L87 Difference]: Start difference. First operand 33550 states and 46210 transitions. cyclomatic complexity: 12692 Second operand 3 states. [2018-11-18 14:32:37,214 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:32:37,214 INFO L93 Difference]: Finished difference Result 22095 states and 30390 transitions. [2018-11-18 14:32:37,215 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 14:32:37,215 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22095 states and 30390 transitions. [2018-11-18 14:32:37,269 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 21856 [2018-11-18 14:32:37,303 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22095 states to 22095 states and 30390 transitions. [2018-11-18 14:32:37,303 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22095 [2018-11-18 14:32:37,313 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22095 [2018-11-18 14:32:37,313 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22095 states and 30390 transitions. [2018-11-18 14:32:37,323 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:32:37,323 INFO L705 BuchiCegarLoop]: Abstraction has 22095 states and 30390 transitions. [2018-11-18 14:32:37,333 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22095 states and 30390 transitions. [2018-11-18 14:32:37,422 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22095 to 22095. [2018-11-18 14:32:37,423 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22095 states. [2018-11-18 14:32:37,441 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22095 states to 22095 states and 30390 transitions. [2018-11-18 14:32:37,441 INFO L728 BuchiCegarLoop]: Abstraction has 22095 states and 30390 transitions. [2018-11-18 14:32:37,441 INFO L608 BuchiCegarLoop]: Abstraction has 22095 states and 30390 transitions. [2018-11-18 14:32:37,441 INFO L442 BuchiCegarLoop]: ======== Iteration 23============ [2018-11-18 14:32:37,442 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22095 states and 30390 transitions. [2018-11-18 14:32:37,478 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 21856 [2018-11-18 14:32:37,479 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:32:37,479 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:32:37,480 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:37,480 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:37,480 INFO L794 eck$LassoCheckResult]: Stem: 452592#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 452480#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 452481#L1225 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 452973#L564 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 452517#L571 assume 1 == ~m_i~0;~m_st~0 := 0; 452498#L571-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 452202#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 452203#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 452976#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 452728#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 452318#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 452319#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 452966#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 452861#L611-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 452862#L828 assume !(0 == ~M_E~0); 452984#L828-2 assume !(0 == ~T1_E~0); 452620#L833-1 assume !(0 == ~T2_E~0); 452333#L838-1 assume !(0 == ~T3_E~0); 452334#L843-1 assume !(0 == ~T4_E~0); 453071#L848-1 assume !(0 == ~T5_E~0); 452872#L853-1 assume !(0 == ~T6_E~0); 452603#L858-1 assume !(0 == ~T7_E~0); 452123#L863-1 assume !(0 == ~T8_E~0); 452124#L868-1 assume !(0 == ~E_1~0); 452819#L873-1 assume !(0 == ~E_2~0); 452695#L878-1 assume !(0 == ~E_3~0); 452451#L883-1 assume !(0 == ~E_4~0); 452452#L888-1 assume !(0 == ~E_5~0); 452936#L893-1 assume !(0 == ~E_6~0); 452663#L898-1 assume !(0 == ~E_7~0); 452577#L903-1 assume !(0 == ~E_8~0); 452271#L908-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 452272#L392 assume !(1 == ~m_pc~0); 452643#L392-2 is_master_triggered_~__retres1~0 := 0; 452649#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 453119#L404 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 452947#L1025 assume !(0 != activate_threads_~tmp~1); 452948#L1025-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 452805#L411 assume !(1 == ~t1_pc~0); 452771#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 452182#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 452183#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 452299#L1033 assume !(0 != activate_threads_~tmp___0~0); 452524#L1033-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 452525#L430 assume !(1 == ~t2_pc~0); 452957#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 452368#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 452320#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 452321#L1041 assume !(0 != activate_threads_~tmp___1~0); 453151#L1041-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 453152#L449 assume !(1 == ~t3_pc~0); 453028#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 453160#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 453173#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 452970#L1049 assume !(0 != activate_threads_~tmp___2~0); 452971#L1049-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 452221#L468 assume !(1 == ~t4_pc~0); 452222#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 452230#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 452656#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 452585#L1057 assume !(0 != activate_threads_~tmp___3~0); 452586#L1057-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 452436#L487 assume !(1 == ~t5_pc~0); 452178#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 452438#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 452793#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 452794#L1065 assume !(0 != activate_threads_~tmp___4~0); 453166#L1065-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 452602#L506 assume !(1 == ~t6_pc~0); 452597#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 452598#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 452968#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 452889#L1073 assume !(0 != activate_threads_~tmp___5~0); 452890#L1073-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 452729#L525 assume !(1 == ~t7_pc~0); 452674#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 452673#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 453153#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 452457#L1081 assume !(0 != activate_threads_~tmp___6~0); 452458#L1081-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 452459#L544 assume !(1 == ~t8_pc~0); 452741#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 452117#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 452118#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 452253#L1089 assume !(0 != activate_threads_~tmp___7~0); 453008#L1089-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 452610#L921 assume !(1 == ~M_E~0); 452611#L921-2 assume !(1 == ~T1_E~0); 452329#L926-1 assume !(1 == ~T2_E~0); 452330#L931-1 assume !(1 == ~T3_E~0); 453069#L936-1 assume !(1 == ~T4_E~0); 452882#L941-1 assume !(1 == ~T5_E~0); 452608#L946-1 assume !(1 == ~T6_E~0); 452135#L951-1 assume !(1 == ~T7_E~0); 452136#L956-1 assume !(1 == ~T8_E~0); 452972#L961-1 assume !(1 == ~E_1~0); 452702#L966-1 assume !(1 == ~E_2~0); 452462#L971-1 assume !(1 == ~E_3~0); 452463#L976-1 assume !(1 == ~E_4~0); 452931#L981-1 assume !(1 == ~E_5~0); 452661#L986-1 assume !(1 == ~E_6~0); 452571#L991-1 assume !(1 == ~E_7~0); 452259#L996-1 assume !(1 == ~E_8~0); 452260#L1001-1 assume { :end_inline_reset_delta_events } true; 453085#L1262-3 [2018-11-18 14:32:37,480 INFO L796 eck$LassoCheckResult]: Loop: 453085#L1262-3 assume true; 457058#L1262-1 assume !false; 456922#L1263 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 456920#L803 assume true; 456918#L681-1 assume !false; 456916#L682 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 456908#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 456899#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 456897#L672 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 456894#L686 assume !(0 != eval_~tmp~0); 456895#L818 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 457458#L564-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 457457#L828-3 assume 0 == ~M_E~0;~M_E~0 := 1; 457456#L828-5 assume !(0 == ~T1_E~0); 457455#L833-3 assume !(0 == ~T2_E~0); 457454#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 457452#L843-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 457451#L848-3 assume !(0 == ~T5_E~0); 457450#L853-3 assume !(0 == ~T6_E~0); 457449#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 457447#L863-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 457446#L868-3 assume !(0 == ~E_1~0); 457445#L873-3 assume !(0 == ~E_2~0); 457444#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 457443#L883-3 assume 0 == ~E_4~0;~E_4~0 := 1; 457442#L888-3 assume !(0 == ~E_5~0); 457440#L893-3 assume !(0 == ~E_6~0); 457437#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 457435#L903-3 assume 0 == ~E_8~0;~E_8~0 := 1; 457433#L908-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 457431#L392-27 assume 1 == ~m_pc~0; 457428#L393-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 457426#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 457424#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 457422#L1025-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 457420#L1025-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 457418#L411-27 assume !(1 == ~t1_pc~0); 457416#L411-29 is_transmit1_triggered_~__retres1~1 := 0; 457414#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 457412#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 457410#L1033-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 457408#L1033-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 457406#L430-27 assume !(1 == ~t2_pc~0); 457404#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 457400#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 457398#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 457396#L1041-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 457394#L1041-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 457391#L449-27 assume 1 == ~t3_pc~0; 457389#L450-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 457390#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 457453#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 457380#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 457378#L1049-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 457376#L468-27 assume !(1 == ~t4_pc~0); 457374#L468-29 is_transmit4_triggered_~__retres1~4 := 0; 457371#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 457369#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 457367#L1057-27 assume !(0 != activate_threads_~tmp___3~0); 457365#L1057-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 457363#L487-27 assume !(1 == ~t5_pc~0); 457360#L487-29 is_transmit5_triggered_~__retres1~5 := 0; 457358#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 457356#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 457354#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 457352#L1065-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 457350#L506-27 assume !(1 == ~t6_pc~0); 457348#L506-29 is_transmit6_triggered_~__retres1~6 := 0; 457346#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 457343#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 457341#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 457339#L1073-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 457337#L525-27 assume 1 == ~t7_pc~0; 457334#L526-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 457332#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 457330#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 457328#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 457326#L1081-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 457324#L544-27 assume !(1 == ~t8_pc~0); 457322#L544-29 is_transmit8_triggered_~__retres1~8 := 0; 457320#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 457318#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 457316#L1089-27 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 457314#L1089-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 457312#L921-3 assume 1 == ~M_E~0;~M_E~0 := 2; 457310#L921-5 assume !(1 == ~T1_E~0); 457308#L926-3 assume !(1 == ~T2_E~0); 457306#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 457304#L936-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 457302#L941-3 assume !(1 == ~T5_E~0); 457300#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 457298#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 457296#L956-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 457294#L961-3 assume !(1 == ~E_1~0); 457292#L966-3 assume !(1 == ~E_2~0); 457290#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 457288#L976-3 assume 1 == ~E_4~0;~E_4~0 := 2; 457287#L981-3 assume !(1 == ~E_5~0); 457286#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 457285#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 457284#L996-3 assume 1 == ~E_8~0;~E_8~0 := 2; 457283#L1001-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 457102#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 457093#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 457091#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 457088#L1281 assume !(0 == start_simulation_~tmp~3); 457085#L1281-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 457082#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 457072#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 457069#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 457067#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 457065#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 457063#L1244 start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 457061#L1294 assume !(0 != start_simulation_~tmp___0~1); 453085#L1262-3 [2018-11-18 14:32:37,480 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:37,481 INFO L82 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 3 times [2018-11-18 14:32:37,481 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:37,481 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:37,481 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:37,482 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:37,482 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:37,487 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:32:37,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:32:37,516 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:37,516 INFO L82 PathProgramCache]: Analyzing trace with hash -341411951, now seen corresponding path program 1 times [2018-11-18 14:32:37,516 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:37,516 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:37,517 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:37,517 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 14:32:37,517 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:37,522 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:37,561 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:37,561 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:37,561 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 14:32:37,561 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 14:32:37,561 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 14:32:37,562 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 14:32:37,562 INFO L87 Difference]: Start difference. First operand 22095 states and 30390 transitions. cyclomatic complexity: 8327 Second operand 5 states. [2018-11-18 14:32:37,731 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:32:37,731 INFO L93 Difference]: Finished difference Result 40479 states and 55078 transitions. [2018-11-18 14:32:37,732 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-18 14:32:37,732 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 40479 states and 55078 transitions. [2018-11-18 14:32:37,848 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 40112 [2018-11-18 14:32:37,917 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 40479 states to 40479 states and 55078 transitions. [2018-11-18 14:32:37,917 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 40479 [2018-11-18 14:32:37,936 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 40479 [2018-11-18 14:32:37,936 INFO L73 IsDeterministic]: Start isDeterministic. Operand 40479 states and 55078 transitions. [2018-11-18 14:32:37,953 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:32:37,953 INFO L705 BuchiCegarLoop]: Abstraction has 40479 states and 55078 transitions. [2018-11-18 14:32:37,971 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40479 states and 55078 transitions. [2018-11-18 14:32:38,360 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40479 to 22191. [2018-11-18 14:32:38,360 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22191 states. [2018-11-18 14:32:38,382 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22191 states to 22191 states and 30486 transitions. [2018-11-18 14:32:38,383 INFO L728 BuchiCegarLoop]: Abstraction has 22191 states and 30486 transitions. [2018-11-18 14:32:38,383 INFO L608 BuchiCegarLoop]: Abstraction has 22191 states and 30486 transitions. [2018-11-18 14:32:38,383 INFO L442 BuchiCegarLoop]: ======== Iteration 24============ [2018-11-18 14:32:38,383 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22191 states and 30486 transitions. [2018-11-18 14:32:38,415 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 21952 [2018-11-18 14:32:38,415 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:32:38,415 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:32:38,415 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:38,415 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:38,416 INFO L794 eck$LassoCheckResult]: Stem: 515191#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 515080#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 515081#L1225 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 515589#L564 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 515118#L571 assume 1 == ~m_i~0;~m_st~0 := 0; 515099#L571-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 514791#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 514792#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 515592#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 515327#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 514913#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 514914#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 515582#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 515464#L611-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 515465#L828 assume !(0 == ~M_E~0); 515599#L828-2 assume !(0 == ~T1_E~0); 515219#L833-1 assume !(0 == ~T2_E~0); 514928#L838-1 assume !(0 == ~T3_E~0); 514929#L843-1 assume !(0 == ~T4_E~0); 515688#L848-1 assume !(0 == ~T5_E~0); 515477#L853-1 assume !(0 == ~T6_E~0); 515201#L858-1 assume !(0 == ~T7_E~0); 514713#L863-1 assume !(0 == ~T8_E~0); 514714#L868-1 assume !(0 == ~E_1~0); 515418#L873-1 assume !(0 == ~E_2~0); 515296#L878-1 assume !(0 == ~E_3~0); 515047#L883-1 assume !(0 == ~E_4~0); 515048#L888-1 assume !(0 == ~E_5~0); 515553#L893-1 assume !(0 == ~E_6~0); 515264#L898-1 assume !(0 == ~E_7~0); 515180#L903-1 assume !(0 == ~E_8~0); 514864#L908-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 514865#L392 assume !(1 == ~m_pc~0); 515243#L392-2 is_master_triggered_~__retres1~0 := 0; 515249#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 515737#L404 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 515562#L1025 assume !(0 != activate_threads_~tmp~1); 515563#L1025-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 515404#L411 assume !(1 == ~t1_pc~0); 515371#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 514773#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 514774#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 514893#L1033 assume !(0 != activate_threads_~tmp___0~0); 515128#L1033-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 515129#L430 assume !(1 == ~t2_pc~0); 515573#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 514963#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 514915#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 514916#L1041 assume !(0 != activate_threads_~tmp___1~0); 515769#L1041-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 515770#L449 assume !(1 == ~t3_pc~0); 515647#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 515778#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 515789#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 515586#L1049 assume !(0 != activate_threads_~tmp___2~0); 515587#L1049-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 514812#L468 assume !(1 == ~t4_pc~0); 514813#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 514822#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 515256#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 515185#L1057 assume !(0 != activate_threads_~tmp___3~0); 515186#L1057-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 515032#L487 assume !(1 == ~t5_pc~0); 514769#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 515034#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 515391#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 515392#L1065 assume !(0 != activate_threads_~tmp___4~0); 515783#L1065-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 515200#L506 assume !(1 == ~t6_pc~0); 515195#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 515196#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 515584#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 515504#L1073 assume !(0 != activate_threads_~tmp___5~0); 515505#L1073-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 515328#L525 assume !(1 == ~t7_pc~0); 515274#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 515273#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 515771#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 515053#L1081 assume !(0 != activate_threads_~tmp___6~0); 515054#L1081-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 515055#L544 assume !(1 == ~t8_pc~0); 515342#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 514707#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 514708#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 514846#L1089 assume !(0 != activate_threads_~tmp___7~0); 515626#L1089-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 515209#L921 assume !(1 == ~M_E~0); 515210#L921-2 assume !(1 == ~T1_E~0); 514924#L926-1 assume !(1 == ~T2_E~0); 514925#L931-1 assume !(1 == ~T3_E~0); 515686#L936-1 assume !(1 == ~T4_E~0); 515493#L941-1 assume !(1 == ~T5_E~0); 515207#L946-1 assume !(1 == ~T6_E~0); 514725#L951-1 assume !(1 == ~T7_E~0); 514726#L956-1 assume !(1 == ~T8_E~0); 515588#L961-1 assume !(1 == ~E_1~0); 515302#L966-1 assume !(1 == ~E_2~0); 515058#L971-1 assume !(1 == ~E_3~0); 515059#L976-1 assume !(1 == ~E_4~0); 515548#L981-1 assume !(1 == ~E_5~0); 515262#L986-1 assume !(1 == ~E_6~0); 515175#L991-1 assume !(1 == ~E_7~0); 514852#L996-1 assume !(1 == ~E_8~0); 514853#L1001-1 assume { :end_inline_reset_delta_events } true; 515707#L1262-3 [2018-11-18 14:32:38,416 INFO L796 eck$LassoCheckResult]: Loop: 515707#L1262-3 assume true; 529172#L1262-1 assume !false; 529171#L1263 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 526538#L803 assume true; 529170#L681-1 assume !false; 529169#L682 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 529167#L624 assume !(0 == ~m_st~0); 529168#L628 assume !(0 == ~t1_st~0); 529163#L632 assume !(0 == ~t2_st~0); 529164#L636 assume !(0 == ~t3_st~0); 529166#L640 assume !(0 == ~t4_st~0); 529161#L644 assume !(0 == ~t5_st~0); 529162#L648 assume !(0 == ~t6_st~0); 529165#L652 assume !(0 == ~t7_st~0); 529159#L656 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9 := 0; 529160#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 518899#L672 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 518900#L686 assume !(0 != eval_~tmp~0); 529304#L818 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 529303#L564-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 529302#L828-3 assume 0 == ~M_E~0;~M_E~0 := 1; 529301#L828-5 assume !(0 == ~T1_E~0); 529300#L833-3 assume !(0 == ~T2_E~0); 529299#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 529298#L843-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 529297#L848-3 assume !(0 == ~T5_E~0); 529296#L853-3 assume !(0 == ~T6_E~0); 529295#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 529294#L863-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 529293#L868-3 assume !(0 == ~E_1~0); 529292#L873-3 assume !(0 == ~E_2~0); 529291#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 529290#L883-3 assume 0 == ~E_4~0;~E_4~0 := 1; 529289#L888-3 assume !(0 == ~E_5~0); 529288#L893-3 assume !(0 == ~E_6~0); 529287#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 529286#L903-3 assume 0 == ~E_8~0;~E_8~0 := 1; 529285#L908-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 529284#L392-27 assume 1 == ~m_pc~0; 529282#L393-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 529281#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 529280#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 529279#L1025-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 529278#L1025-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 529277#L411-27 assume !(1 == ~t1_pc~0); 529276#L411-29 is_transmit1_triggered_~__retres1~1 := 0; 529275#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 529274#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 529273#L1033-27 assume 0 != activate_threads_~tmp___0~0;~t1_st~0 := 0; 529272#L1033-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 529271#L430-27 assume !(1 == ~t2_pc~0); 529270#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 529269#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 529268#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 529267#L1041-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 529266#L1041-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 529265#L449-27 assume 1 == ~t3_pc~0; 529263#L450-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 529261#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 529259#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 529257#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 529256#L1049-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 529255#L468-27 assume !(1 == ~t4_pc~0); 529254#L468-29 is_transmit4_triggered_~__retres1~4 := 0; 529253#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 529252#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 529251#L1057-27 assume !(0 != activate_threads_~tmp___3~0); 529250#L1057-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 529249#L487-27 assume !(1 == ~t5_pc~0); 529247#L487-29 is_transmit5_triggered_~__retres1~5 := 0; 529246#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 529245#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 529244#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 529243#L1065-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 529242#L506-27 assume !(1 == ~t6_pc~0); 529241#L506-29 is_transmit6_triggered_~__retres1~6 := 0; 529240#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 529239#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 529238#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 529237#L1073-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 529236#L525-27 assume 1 == ~t7_pc~0; 529234#L526-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 529233#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 529232#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 529231#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 529230#L1081-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 529229#L544-27 assume !(1 == ~t8_pc~0); 529228#L544-29 is_transmit8_triggered_~__retres1~8 := 0; 529227#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 529226#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 529225#L1089-27 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 529224#L1089-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 529223#L921-3 assume 1 == ~M_E~0;~M_E~0 := 2; 529222#L921-5 assume !(1 == ~T1_E~0); 529221#L926-3 assume !(1 == ~T2_E~0); 529220#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 529219#L936-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 529218#L941-3 assume !(1 == ~T5_E~0); 529217#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 529216#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 529215#L956-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 529214#L961-3 assume !(1 == ~E_1~0); 529213#L966-3 assume !(1 == ~E_2~0); 529212#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 529211#L976-3 assume 1 == ~E_4~0;~E_4~0 := 2; 529210#L981-3 assume !(1 == ~E_5~0); 529209#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 529208#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 529207#L996-3 assume 1 == ~E_8~0;~E_8~0 := 2; 529206#L1001-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 529204#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 529195#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 529193#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 529190#L1281 assume !(0 == start_simulation_~tmp~3); 529188#L1281-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 529187#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 529178#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 529177#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 529176#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 529175#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 529174#L1244 start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 529173#L1294 assume !(0 != start_simulation_~tmp___0~1); 515707#L1262-3 [2018-11-18 14:32:38,416 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:38,416 INFO L82 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 4 times [2018-11-18 14:32:38,416 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:38,417 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:38,417 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:38,417 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:38,417 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:38,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:32:38,429 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:32:38,462 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:38,462 INFO L82 PathProgramCache]: Analyzing trace with hash -277107781, now seen corresponding path program 1 times [2018-11-18 14:32:38,462 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:38,462 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:38,463 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:38,463 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 14:32:38,463 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:38,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:38,541 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:38,541 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:38,541 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 14:32:38,542 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 14:32:38,542 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 14:32:38,542 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 14:32:38,542 INFO L87 Difference]: Start difference. First operand 22191 states and 30486 transitions. cyclomatic complexity: 8327 Second operand 5 states. [2018-11-18 14:32:38,826 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:32:38,826 INFO L93 Difference]: Finished difference Result 28247 states and 38885 transitions. [2018-11-18 14:32:38,826 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 14:32:38,826 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 28247 states and 38885 transitions. [2018-11-18 14:32:38,915 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 27912 [2018-11-18 14:32:38,959 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 28247 states to 28247 states and 38885 transitions. [2018-11-18 14:32:38,959 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28247 [2018-11-18 14:32:38,970 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28247 [2018-11-18 14:32:38,970 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28247 states and 38885 transitions. [2018-11-18 14:32:38,979 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:32:38,979 INFO L705 BuchiCegarLoop]: Abstraction has 28247 states and 38885 transitions. [2018-11-18 14:32:38,990 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28247 states and 38885 transitions. [2018-11-18 14:32:39,086 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28247 to 22239. [2018-11-18 14:32:39,086 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22239 states. [2018-11-18 14:32:39,103 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22239 states to 22239 states and 30293 transitions. [2018-11-18 14:32:39,104 INFO L728 BuchiCegarLoop]: Abstraction has 22239 states and 30293 transitions. [2018-11-18 14:32:39,104 INFO L608 BuchiCegarLoop]: Abstraction has 22239 states and 30293 transitions. [2018-11-18 14:32:39,104 INFO L442 BuchiCegarLoop]: ======== Iteration 25============ [2018-11-18 14:32:39,104 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22239 states and 30293 transitions. [2018-11-18 14:32:39,139 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 22000 [2018-11-18 14:32:39,139 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:32:39,139 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:32:39,139 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:39,140 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:39,140 INFO L794 eck$LassoCheckResult]: Stem: 565676#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 565555#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 565556#L1225 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 566103#L564 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 565597#L571 assume 1 == ~m_i~0;~m_st~0 := 0; 565576#L571-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 565245#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 565246#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 566112#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 565822#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 565375#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 565376#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 566096#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 565974#L611-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 565975#L828 assume !(0 == ~M_E~0); 566123#L828-2 assume !(0 == ~T1_E~0); 565706#L833-1 assume !(0 == ~T2_E~0); 565390#L838-1 assume !(0 == ~T3_E~0); 565391#L843-1 assume !(0 == ~T4_E~0); 566233#L848-1 assume !(0 == ~T5_E~0); 565986#L853-1 assume !(0 == ~T6_E~0); 565687#L858-1 assume !(0 == ~T7_E~0); 565165#L863-1 assume !(0 == ~T8_E~0); 565166#L868-1 assume !(0 == ~E_1~0); 565922#L873-1 assume !(0 == ~E_2~0); 565788#L878-1 assume !(0 == ~E_3~0); 565519#L883-1 assume !(0 == ~E_4~0); 565520#L888-1 assume !(0 == ~E_5~0); 566066#L893-1 assume !(0 == ~E_6~0); 565755#L898-1 assume !(0 == ~E_7~0); 565662#L903-1 assume !(0 == ~E_8~0); 565316#L908-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 565317#L392 assume !(1 == ~m_pc~0); 565733#L392-2 is_master_triggered_~__retres1~0 := 0; 565740#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 566313#L404 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 566072#L1025 assume !(0 != activate_threads_~tmp~1); 566073#L1025-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 565907#L411 assume !(1 == ~t1_pc~0); 565873#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 565226#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 565227#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 565352#L1033 assume !(0 != activate_threads_~tmp___0~0); 565606#L1033-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 565607#L430 assume !(1 == ~t2_pc~0); 566083#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 565430#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 565377#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 565378#L1041 assume !(0 != activate_threads_~tmp___1~0); 566353#L1041-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 566356#L449 assume !(1 == ~t3_pc~0); 566178#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 566365#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 566389#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 566100#L1049 assume !(0 != activate_threads_~tmp___2~0); 566101#L1049-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 565265#L468 assume !(1 == ~t4_pc~0); 565266#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 565275#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 565747#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 565671#L1057 assume !(0 != activate_threads_~tmp___3~0); 565672#L1057-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 565503#L487 assume !(1 == ~t5_pc~0); 565221#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 565505#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 565894#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 565895#L1065 assume !(0 != activate_threads_~tmp___4~0); 566375#L1065-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 565686#L506 assume !(1 == ~t6_pc~0); 565681#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 565682#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 566098#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 566005#L1073 assume !(0 != activate_threads_~tmp___5~0); 566006#L1073-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 565823#L525 assume !(1 == ~t7_pc~0); 565765#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 565764#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 566357#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 565527#L1081 assume !(0 != activate_threads_~tmp___6~0); 565528#L1081-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 565529#L544 assume !(1 == ~t8_pc~0); 565839#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 565159#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 565160#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 565298#L1089 assume !(0 != activate_threads_~tmp___7~0); 566154#L1089-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 565696#L921 assume !(1 == ~M_E~0); 565697#L921-2 assume !(1 == ~T1_E~0); 565386#L926-1 assume !(1 == ~T2_E~0); 565387#L931-1 assume !(1 == ~T3_E~0); 566231#L936-1 assume !(1 == ~T4_E~0); 565998#L941-1 assume !(1 == ~T5_E~0); 565694#L946-1 assume !(1 == ~T6_E~0); 565177#L951-1 assume !(1 == ~T7_E~0); 565178#L956-1 assume !(1 == ~T8_E~0); 566102#L961-1 assume !(1 == ~E_1~0); 565796#L966-1 assume !(1 == ~E_2~0); 565532#L971-1 assume !(1 == ~E_3~0); 565533#L976-1 assume !(1 == ~E_4~0); 566062#L981-1 assume !(1 == ~E_5~0); 565753#L986-1 assume !(1 == ~E_6~0); 565656#L991-1 assume !(1 == ~E_7~0); 565304#L996-1 assume !(1 == ~E_8~0); 565305#L1001-1 assume { :end_inline_reset_delta_events } true; 566272#L1262-3 [2018-11-18 14:32:39,140 INFO L796 eck$LassoCheckResult]: Loop: 566272#L1262-3 assume true; 572825#L1262-1 assume !false; 572817#L1263 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 572812#L803 assume true; 572806#L681-1 assume !false; 572802#L682 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 572747#L624 assume !(0 == ~m_st~0); 572748#L628 assume !(0 == ~t1_st~0); 572743#L632 assume !(0 == ~t2_st~0); 572744#L636 assume !(0 == ~t3_st~0); 572746#L640 assume !(0 == ~t4_st~0); 572741#L644 assume !(0 == ~t5_st~0); 572742#L648 assume !(0 == ~t6_st~0); 572745#L652 assume !(0 == ~t7_st~0); 572739#L656 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9 := 0; 572740#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 572374#L672 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 572375#L686 assume !(0 != eval_~tmp~0); 573367#L818 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 573363#L564-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 573359#L828-3 assume 0 == ~M_E~0;~M_E~0 := 1; 573355#L828-5 assume !(0 == ~T1_E~0); 573350#L833-3 assume !(0 == ~T2_E~0); 573345#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 573338#L843-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 573333#L848-3 assume !(0 == ~T5_E~0); 573328#L853-3 assume !(0 == ~T6_E~0); 573321#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 573316#L863-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 573310#L868-3 assume !(0 == ~E_1~0); 573304#L873-3 assume !(0 == ~E_2~0); 573295#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 573288#L883-3 assume 0 == ~E_4~0;~E_4~0 := 1; 573284#L888-3 assume !(0 == ~E_5~0); 573275#L893-3 assume !(0 == ~E_6~0); 573273#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 573269#L903-3 assume 0 == ~E_8~0;~E_8~0 := 1; 573266#L908-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 573264#L392-27 assume 1 == ~m_pc~0; 573258#L393-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 573257#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 573256#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 573255#L1025-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 573253#L1025-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 573250#L411-27 assume !(1 == ~t1_pc~0); 573248#L411-29 is_transmit1_triggered_~__retres1~1 := 0; 573246#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 573244#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 573242#L1033-27 assume !(0 != activate_threads_~tmp___0~0); 573240#L1033-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 573238#L430-27 assume !(1 == ~t2_pc~0); 573236#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 573234#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 573232#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 573230#L1041-27 assume 0 != activate_threads_~tmp___1~0;~t2_st~0 := 0; 573228#L1041-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 573226#L449-27 assume !(1 == ~t3_pc~0); 573224#L449-29 is_transmit3_triggered_~__retres1~3 := 0; 573221#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 573218#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 573215#L1049-27 assume !(0 != activate_threads_~tmp___2~0); 573212#L1049-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 573209#L468-27 assume !(1 == ~t4_pc~0); 573205#L468-29 is_transmit4_triggered_~__retres1~4 := 0; 573200#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 573196#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 573193#L1057-27 assume !(0 != activate_threads_~tmp___3~0); 573190#L1057-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 573187#L487-27 assume !(1 == ~t5_pc~0); 573183#L487-29 is_transmit5_triggered_~__retres1~5 := 0; 573180#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 573177#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 573174#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 573170#L1065-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 573167#L506-27 assume !(1 == ~t6_pc~0); 573164#L506-29 is_transmit6_triggered_~__retres1~6 := 0; 573161#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 573158#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 573155#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 573152#L1073-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 573149#L525-27 assume 1 == ~t7_pc~0; 573145#L526-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 573141#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 573137#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 573133#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 573129#L1081-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 573125#L544-27 assume !(1 == ~t8_pc~0); 573122#L544-29 is_transmit8_triggered_~__retres1~8 := 0; 573119#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 573116#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 573113#L1089-27 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 573110#L1089-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 573107#L921-3 assume 1 == ~M_E~0;~M_E~0 := 2; 573103#L921-5 assume !(1 == ~T1_E~0); 573100#L926-3 assume !(1 == ~T2_E~0); 573097#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 573094#L936-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 573091#L941-3 assume !(1 == ~T5_E~0); 573088#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 573085#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 573082#L956-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 573079#L961-3 assume !(1 == ~E_1~0); 573076#L966-3 assume !(1 == ~E_2~0); 573073#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 573069#L976-3 assume 1 == ~E_4~0;~E_4~0 := 2; 573064#L981-3 assume !(1 == ~E_5~0); 573059#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 573055#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 573051#L996-3 assume 1 == ~E_8~0;~E_8~0 := 2; 573047#L1001-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 573042#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 573031#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 573026#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 573019#L1281 assume !(0 == start_simulation_~tmp~3); 573016#L1281-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 572890#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 572876#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 572868#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 572862#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 572854#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 572848#L1244 start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 572840#L1294 assume !(0 != start_simulation_~tmp___0~1); 566272#L1262-3 [2018-11-18 14:32:39,140 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:39,140 INFO L82 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 5 times [2018-11-18 14:32:39,140 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:39,140 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:39,141 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:39,141 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:39,141 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:39,145 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:32:39,150 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:32:39,173 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:39,173 INFO L82 PathProgramCache]: Analyzing trace with hash 111412758, now seen corresponding path program 1 times [2018-11-18 14:32:39,173 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:39,173 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:39,174 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:39,174 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 14:32:39,174 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:39,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:39,223 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:39,224 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:39,224 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 14:32:39,224 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 14:32:39,224 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 14:32:39,224 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 14:32:39,224 INFO L87 Difference]: Start difference. First operand 22239 states and 30293 transitions. cyclomatic complexity: 8086 Second operand 5 states. [2018-11-18 14:32:39,396 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:32:39,396 INFO L93 Difference]: Finished difference Result 25703 states and 34876 transitions. [2018-11-18 14:32:39,397 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 14:32:39,397 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 25703 states and 34876 transitions. [2018-11-18 14:32:39,453 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 25432 [2018-11-18 14:32:39,490 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 25703 states to 25703 states and 34876 transitions. [2018-11-18 14:32:39,490 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25703 [2018-11-18 14:32:39,500 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25703 [2018-11-18 14:32:39,500 INFO L73 IsDeterministic]: Start isDeterministic. Operand 25703 states and 34876 transitions. [2018-11-18 14:32:39,510 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:32:39,510 INFO L705 BuchiCegarLoop]: Abstraction has 25703 states and 34876 transitions. [2018-11-18 14:32:39,519 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25703 states and 34876 transitions. [2018-11-18 14:32:39,609 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25703 to 22263. [2018-11-18 14:32:39,610 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22263 states. [2018-11-18 14:32:39,628 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22263 states to 22263 states and 30068 transitions. [2018-11-18 14:32:39,628 INFO L728 BuchiCegarLoop]: Abstraction has 22263 states and 30068 transitions. [2018-11-18 14:32:39,628 INFO L608 BuchiCegarLoop]: Abstraction has 22263 states and 30068 transitions. [2018-11-18 14:32:39,628 INFO L442 BuchiCegarLoop]: ======== Iteration 26============ [2018-11-18 14:32:39,628 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22263 states and 30068 transitions. [2018-11-18 14:32:39,663 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 22024 [2018-11-18 14:32:39,663 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:32:39,663 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:32:39,664 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:39,664 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:39,664 INFO L794 eck$LassoCheckResult]: Stem: 613650#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 613517#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 613518#L1225 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 614122#L564 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 613558#L571 assume 1 == ~m_i~0;~m_st~0 := 0; 613538#L571-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 613200#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 613201#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 614137#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 613810#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 613326#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 613327#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 614114#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 613974#L611-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 613975#L828 assume !(0 == ~M_E~0); 614144#L828-2 assume !(0 == ~T1_E~0); 613679#L833-1 assume !(0 == ~T2_E~0); 613341#L838-1 assume !(0 == ~T3_E~0); 613342#L843-1 assume !(0 == ~T4_E~0); 614263#L848-1 assume !(0 == ~T5_E~0); 613988#L853-1 assume !(0 == ~T6_E~0); 613661#L858-1 assume !(0 == ~T7_E~0); 613121#L863-1 assume !(0 == ~T8_E~0); 613122#L868-1 assume !(0 == ~E_1~0); 613916#L873-1 assume !(0 == ~E_2~0); 613773#L878-1 assume !(0 == ~E_3~0); 613478#L883-1 assume !(0 == ~E_4~0); 613479#L888-1 assume !(0 == ~E_5~0); 614077#L893-1 assume !(0 == ~E_6~0); 613732#L898-1 assume !(0 == ~E_7~0); 613635#L903-1 assume !(0 == ~E_8~0); 613272#L908-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 613273#L392 assume !(1 == ~m_pc~0); 613708#L392-2 is_master_triggered_~__retres1~0 := 0; 613715#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 614360#L404 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 614085#L1025 assume !(0 != activate_threads_~tmp~1); 614086#L1025-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 613902#L411 assume !(1 == ~t1_pc~0); 613867#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 613183#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 613184#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 613305#L1033 assume !(0 != activate_threads_~tmp___0~0); 613566#L1033-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 613567#L430 assume !(1 == ~t2_pc~0); 614101#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 613383#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 613328#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 613329#L1041 assume !(0 != activate_threads_~tmp___1~0); 614407#L1041-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 614412#L449 assume !(1 == ~t3_pc~0); 614192#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 614424#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 614458#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 614118#L1049 assume !(0 != activate_threads_~tmp___2~0); 614119#L1049-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 613221#L468 assume !(1 == ~t4_pc~0); 613222#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 613230#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 613724#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 613645#L1057 assume !(0 != activate_threads_~tmp___3~0); 613646#L1057-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 613461#L487 assume !(1 == ~t5_pc~0); 613177#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 613464#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 613890#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 613891#L1065 assume !(0 != activate_threads_~tmp___4~0); 614432#L1065-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 613660#L506 assume !(1 == ~t6_pc~0); 613655#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 613656#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 614116#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 614011#L1073 assume !(0 != activate_threads_~tmp___5~0); 614012#L1073-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 613811#L525 assume !(1 == ~t7_pc~0); 613744#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 613743#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 614413#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 613485#L1081 assume !(0 != activate_threads_~tmp___6~0); 613486#L1081-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 613487#L544 assume !(1 == ~t8_pc~0); 613831#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 613115#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 613116#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 613254#L1089 assume !(0 != activate_threads_~tmp___7~0); 614166#L1089-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 613671#L921 assume !(1 == ~M_E~0); 613672#L921-2 assume !(1 == ~T1_E~0); 613337#L926-1 assume !(1 == ~T2_E~0); 613338#L931-1 assume !(1 == ~T3_E~0); 614261#L936-1 assume !(1 == ~T4_E~0); 614004#L941-1 assume !(1 == ~T5_E~0); 613667#L946-1 assume !(1 == ~T6_E~0); 613133#L951-1 assume !(1 == ~T7_E~0); 613134#L956-1 assume !(1 == ~T8_E~0); 614121#L961-1 assume !(1 == ~E_1~0); 613780#L966-1 assume !(1 == ~E_2~0); 613490#L971-1 assume !(1 == ~E_3~0); 613491#L976-1 assume !(1 == ~E_4~0); 614070#L981-1 assume !(1 == ~E_5~0); 613730#L986-1 assume !(1 == ~E_6~0); 613625#L991-1 assume !(1 == ~E_7~0); 613262#L996-1 assume !(1 == ~E_8~0); 613263#L1001-1 assume { :end_inline_reset_delta_events } true; 614315#L1262-3 [2018-11-18 14:32:39,665 INFO L796 eck$LassoCheckResult]: Loop: 614315#L1262-3 assume true; 622451#L1262-1 assume !false; 622318#L1263 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 622312#L803 assume true; 622307#L681-1 assume !false; 622302#L682 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 622001#L624 assume !(0 == ~m_st~0); 622002#L628 assume !(0 == ~t1_st~0); 621997#L632 assume !(0 == ~t2_st~0); 621998#L636 assume !(0 == ~t3_st~0); 622000#L640 assume !(0 == ~t4_st~0); 621995#L644 assume !(0 == ~t5_st~0); 621996#L648 assume !(0 == ~t6_st~0); 621999#L652 assume !(0 == ~t7_st~0); 621993#L656 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9 := 0; 621994#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 617034#L672 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 617035#L686 assume !(0 != eval_~tmp~0); 622695#L818 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 622690#L564-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 622685#L828-3 assume 0 == ~M_E~0;~M_E~0 := 1; 622681#L828-5 assume !(0 == ~T1_E~0); 622678#L833-3 assume !(0 == ~T2_E~0); 622677#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 622676#L843-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 622675#L848-3 assume !(0 == ~T5_E~0); 622674#L853-3 assume !(0 == ~T6_E~0); 622673#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 622672#L863-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 622671#L868-3 assume !(0 == ~E_1~0); 622670#L873-3 assume !(0 == ~E_2~0); 622669#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 622668#L883-3 assume 0 == ~E_4~0;~E_4~0 := 1; 622667#L888-3 assume !(0 == ~E_5~0); 622666#L893-3 assume !(0 == ~E_6~0); 622664#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 622663#L903-3 assume 0 == ~E_8~0;~E_8~0 := 1; 622662#L908-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 622661#L392-27 assume 1 == ~m_pc~0; 622659#L393-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 622657#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 622656#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 622655#L1025-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 622654#L1025-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 622653#L411-27 assume !(1 == ~t1_pc~0); 622651#L411-29 is_transmit1_triggered_~__retres1~1 := 0; 622648#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 622646#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 622644#L1033-27 assume !(0 != activate_threads_~tmp___0~0); 622642#L1033-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 622640#L430-27 assume !(1 == ~t2_pc~0); 622638#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 622636#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 622634#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 622632#L1041-27 assume !(0 != activate_threads_~tmp___1~0); 622630#L1041-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 622628#L449-27 assume !(1 == ~t3_pc~0); 622624#L449-29 is_transmit3_triggered_~__retres1~3 := 0; 622622#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 622620#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 622618#L1049-27 assume !(0 != activate_threads_~tmp___2~0); 622615#L1049-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 622613#L468-27 assume !(1 == ~t4_pc~0); 622609#L468-29 is_transmit4_triggered_~__retres1~4 := 0; 622607#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 622605#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 622603#L1057-27 assume !(0 != activate_threads_~tmp___3~0); 622600#L1057-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 622598#L487-27 assume !(1 == ~t5_pc~0); 622595#L487-29 is_transmit5_triggered_~__retres1~5 := 0; 622593#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 622591#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 622589#L1065-27 assume 0 != activate_threads_~tmp___4~0;~t5_st~0 := 0; 622587#L1065-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 622585#L506-27 assume !(1 == ~t6_pc~0); 622582#L506-29 is_transmit6_triggered_~__retres1~6 := 0; 622580#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 622578#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 622576#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 622574#L1073-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 622572#L525-27 assume 1 == ~t7_pc~0; 622569#L526-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 622567#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 622565#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 622563#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 622561#L1081-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 622559#L544-27 assume !(1 == ~t8_pc~0); 622557#L544-29 is_transmit8_triggered_~__retres1~8 := 0; 622554#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 622552#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 622550#L1089-27 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 622548#L1089-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 622546#L921-3 assume 1 == ~M_E~0;~M_E~0 := 2; 622544#L921-5 assume !(1 == ~T1_E~0); 622542#L926-3 assume !(1 == ~T2_E~0); 622540#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 622538#L936-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 622536#L941-3 assume !(1 == ~T5_E~0); 622534#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 622532#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 622530#L956-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 622528#L961-3 assume !(1 == ~E_1~0); 622526#L966-3 assume !(1 == ~E_2~0); 622524#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 622522#L976-3 assume 1 == ~E_4~0;~E_4~0 := 2; 622520#L981-3 assume !(1 == ~E_5~0); 622518#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 622516#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 622514#L996-3 assume 1 == ~E_8~0;~E_8~0 := 2; 622512#L1001-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 622506#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 622497#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 622495#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 622493#L1281 assume !(0 == start_simulation_~tmp~3); 622491#L1281-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 622490#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 622476#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 622472#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 622468#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 622463#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 622462#L1244 start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 622461#L1294 assume !(0 != start_simulation_~tmp___0~1); 614315#L1262-3 [2018-11-18 14:32:39,665 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:39,665 INFO L82 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 6 times [2018-11-18 14:32:39,665 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:39,665 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:39,666 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:39,666 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:39,666 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:39,670 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:32:39,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:32:39,695 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:39,695 INFO L82 PathProgramCache]: Analyzing trace with hash 1065352916, now seen corresponding path program 1 times [2018-11-18 14:32:39,695 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:39,695 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:39,696 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:39,696 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 14:32:39,696 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:39,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:39,749 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:39,749 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:39,749 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 14:32:39,750 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 14:32:39,750 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 14:32:39,750 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 14:32:39,750 INFO L87 Difference]: Start difference. First operand 22263 states and 30068 transitions. cyclomatic complexity: 7837 Second operand 5 states. [2018-11-18 14:32:39,934 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:32:39,934 INFO L93 Difference]: Finished difference Result 31003 states and 41747 transitions. [2018-11-18 14:32:39,934 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 14:32:39,935 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 31003 states and 41747 transitions. [2018-11-18 14:32:39,999 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 30668 [2018-11-18 14:32:40,041 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 31003 states to 31003 states and 41747 transitions. [2018-11-18 14:32:40,041 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 31003 [2018-11-18 14:32:40,053 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 31003 [2018-11-18 14:32:40,053 INFO L73 IsDeterministic]: Start isDeterministic. Operand 31003 states and 41747 transitions. [2018-11-18 14:32:40,064 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:32:40,064 INFO L705 BuchiCegarLoop]: Abstraction has 31003 states and 41747 transitions. [2018-11-18 14:32:40,075 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31003 states and 41747 transitions. [2018-11-18 14:32:40,178 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31003 to 22311. [2018-11-18 14:32:40,178 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22311 states. [2018-11-18 14:32:40,195 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22311 states to 22311 states and 29875 transitions. [2018-11-18 14:32:40,195 INFO L728 BuchiCegarLoop]: Abstraction has 22311 states and 29875 transitions. [2018-11-18 14:32:40,195 INFO L608 BuchiCegarLoop]: Abstraction has 22311 states and 29875 transitions. [2018-11-18 14:32:40,195 INFO L442 BuchiCegarLoop]: ======== Iteration 27============ [2018-11-18 14:32:40,195 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22311 states and 29875 transitions. [2018-11-18 14:32:40,230 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 22072 [2018-11-18 14:32:40,230 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:32:40,230 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:32:40,231 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:40,231 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:40,231 INFO L794 eck$LassoCheckResult]: Stem: 666890#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 666777#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 666778#L1225 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 667303#L564 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 666815#L571 assume 1 == ~m_i~0;~m_st~0 := 0; 666796#L571-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 666478#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 666479#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 667308#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 667033#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 666600#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 666601#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 667296#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 667165#L611-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 667166#L828 assume !(0 == ~M_E~0); 667317#L828-2 assume !(0 == ~T1_E~0); 666916#L833-1 assume !(0 == ~T2_E~0); 666615#L838-1 assume !(0 == ~T3_E~0); 666616#L843-1 assume !(0 == ~T4_E~0); 667405#L848-1 assume !(0 == ~T5_E~0); 667176#L853-1 assume !(0 == ~T6_E~0); 666898#L858-1 assume !(0 == ~T7_E~0); 666401#L863-1 assume !(0 == ~T8_E~0); 666402#L868-1 assume !(0 == ~E_1~0); 667120#L873-1 assume !(0 == ~E_2~0); 666998#L878-1 assume !(0 == ~E_3~0); 666741#L883-1 assume !(0 == ~E_4~0); 666742#L888-1 assume !(0 == ~E_5~0); 667267#L893-1 assume !(0 == ~E_6~0); 666961#L898-1 assume !(0 == ~E_7~0); 666878#L903-1 assume !(0 == ~E_8~0); 666551#L908-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 666552#L392 assume !(1 == ~m_pc~0); 666940#L392-2 is_master_triggered_~__retres1~0 := 0; 666946#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 667465#L404 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 667274#L1025 assume !(0 != activate_threads_~tmp~1); 667275#L1025-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 667107#L411 assume !(1 == ~t1_pc~0); 667076#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 666460#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 666461#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 666580#L1033 assume !(0 != activate_threads_~tmp___0~0); 666824#L1033-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 666825#L430 assume !(1 == ~t2_pc~0); 667286#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 666650#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 666602#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 666603#L1041 assume !(0 != activate_threads_~tmp___1~0); 667489#L1041-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 667490#L449 assume !(1 == ~t3_pc~0); 667362#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 667501#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 667527#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 667300#L1049 assume !(0 != activate_threads_~tmp___2~0); 667301#L1049-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 666499#L468 assume !(1 == ~t4_pc~0); 666500#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 666509#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 666953#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 666885#L1057 assume !(0 != activate_threads_~tmp___3~0); 666886#L1057-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 666725#L487 assume !(1 == ~t5_pc~0); 666456#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 666727#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 667094#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 667095#L1065 assume !(0 != activate_threads_~tmp___4~0); 667510#L1065-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 666897#L506 assume !(1 == ~t6_pc~0); 666894#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 666895#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 667298#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 667202#L1073 assume !(0 != activate_threads_~tmp___5~0); 667203#L1073-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 667034#L525 assume !(1 == ~t7_pc~0); 666973#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 666972#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 667491#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 666749#L1081 assume !(0 != activate_threads_~tmp___6~0); 666750#L1081-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 666751#L544 assume !(1 == ~t8_pc~0); 667048#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 666395#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 666396#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 666533#L1089 assume !(0 != activate_threads_~tmp___7~0); 667339#L1089-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 666908#L921 assume !(1 == ~M_E~0); 666909#L921-2 assume !(1 == ~T1_E~0); 666611#L926-1 assume !(1 == ~T2_E~0); 666612#L931-1 assume !(1 == ~T3_E~0); 667403#L936-1 assume !(1 == ~T4_E~0); 667190#L941-1 assume !(1 == ~T5_E~0); 666904#L946-1 assume !(1 == ~T6_E~0); 666413#L951-1 assume !(1 == ~T7_E~0); 666414#L956-1 assume !(1 == ~T8_E~0); 667302#L961-1 assume !(1 == ~E_1~0); 667003#L966-1 assume !(1 == ~E_2~0); 666755#L971-1 assume !(1 == ~E_3~0); 666756#L976-1 assume !(1 == ~E_4~0); 667259#L981-1 assume !(1 == ~E_5~0); 666959#L986-1 assume !(1 == ~E_6~0); 666872#L991-1 assume !(1 == ~E_7~0); 666539#L996-1 assume !(1 == ~E_8~0); 666540#L1001-1 assume { :end_inline_reset_delta_events } true; 667437#L1262-3 [2018-11-18 14:32:40,231 INFO L796 eck$LassoCheckResult]: Loop: 667437#L1262-3 assume true; 672355#L1262-1 assume !false; 672349#L1263 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 672346#L803 assume true; 672115#L681-1 assume !false; 672114#L682 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 672112#L624 assume !(0 == ~m_st~0); 672113#L628 assume !(0 == ~t1_st~0); 672108#L632 assume !(0 == ~t2_st~0); 672109#L636 assume !(0 == ~t3_st~0); 672111#L640 assume !(0 == ~t4_st~0); 672106#L644 assume !(0 == ~t5_st~0); 672107#L648 assume !(0 == ~t6_st~0); 672110#L652 assume !(0 == ~t7_st~0); 672104#L656 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9 := 0; 672105#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 672626#L672 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 672624#L686 assume !(0 != eval_~tmp~0); 672622#L818 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 672621#L564-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 672620#L828-3 assume 0 == ~M_E~0;~M_E~0 := 1; 672619#L828-5 assume !(0 == ~T1_E~0); 672618#L833-3 assume !(0 == ~T2_E~0); 672617#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 672616#L843-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 672615#L848-3 assume !(0 == ~T5_E~0); 672614#L853-3 assume !(0 == ~T6_E~0); 672612#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 672610#L863-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 672608#L868-3 assume !(0 == ~E_1~0); 672605#L873-3 assume !(0 == ~E_2~0); 672603#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 672601#L883-3 assume 0 == ~E_4~0;~E_4~0 := 1; 672600#L888-3 assume !(0 == ~E_5~0); 672599#L893-3 assume !(0 == ~E_6~0); 672598#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 672597#L903-3 assume 0 == ~E_8~0;~E_8~0 := 1; 672596#L908-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 672595#L392-27 assume 1 == ~m_pc~0; 672592#L393-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 672589#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 672587#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 672585#L1025-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 672583#L1025-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 672581#L411-27 assume !(1 == ~t1_pc~0); 672579#L411-29 is_transmit1_triggered_~__retres1~1 := 0; 672577#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 672575#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 672573#L1033-27 assume !(0 != activate_threads_~tmp___0~0); 672571#L1033-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 672569#L430-27 assume !(1 == ~t2_pc~0); 672566#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 672564#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 672562#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 672560#L1041-27 assume !(0 != activate_threads_~tmp___1~0); 672559#L1041-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 672558#L449-27 assume 1 == ~t3_pc~0; 672556#L450-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 672555#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 672554#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 672550#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 672548#L1049-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 672546#L468-27 assume !(1 == ~t4_pc~0); 672544#L468-29 is_transmit4_triggered_~__retres1~4 := 0; 672542#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 672540#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 672538#L1057-27 assume !(0 != activate_threads_~tmp___3~0); 672536#L1057-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 672534#L487-27 assume !(1 == ~t5_pc~0); 672531#L487-29 is_transmit5_triggered_~__retres1~5 := 0; 672529#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 672525#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 672523#L1065-27 assume !(0 != activate_threads_~tmp___4~0); 672521#L1065-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 672519#L506-27 assume !(1 == ~t6_pc~0); 672518#L506-29 is_transmit6_triggered_~__retres1~6 := 0; 672515#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 672513#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 672511#L1073-27 assume 0 != activate_threads_~tmp___5~0;~t6_st~0 := 0; 672509#L1073-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 672507#L525-27 assume 1 == ~t7_pc~0; 672504#L526-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 672502#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 672500#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 672497#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 672495#L1081-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 672493#L544-27 assume !(1 == ~t8_pc~0); 672491#L544-29 is_transmit8_triggered_~__retres1~8 := 0; 672489#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 672487#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 672485#L1089-27 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 672483#L1089-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 672481#L921-3 assume 1 == ~M_E~0;~M_E~0 := 2; 672479#L921-5 assume !(1 == ~T1_E~0); 672477#L926-3 assume !(1 == ~T2_E~0); 672475#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 672473#L936-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 672472#L941-3 assume !(1 == ~T5_E~0); 672471#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 672469#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 672466#L956-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 672464#L961-3 assume !(1 == ~E_1~0); 672462#L966-3 assume !(1 == ~E_2~0); 672460#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 672458#L976-3 assume 1 == ~E_4~0;~E_4~0 := 2; 672456#L981-3 assume !(1 == ~E_5~0); 672454#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 672452#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 672450#L996-3 assume 1 == ~E_8~0;~E_8~0 := 2; 672448#L1001-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 672445#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 672437#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 672435#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 672430#L1281 assume !(0 == start_simulation_~tmp~3); 672427#L1281-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 672422#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 672412#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 672410#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 672408#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 672384#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 672376#L1244 start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 672368#L1294 assume !(0 != start_simulation_~tmp___0~1); 667437#L1262-3 [2018-11-18 14:32:40,232 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:40,232 INFO L82 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 7 times [2018-11-18 14:32:40,232 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:40,232 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:40,232 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:40,233 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:40,233 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:40,237 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:32:40,241 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:32:40,264 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:40,264 INFO L82 PathProgramCache]: Analyzing trace with hash 1082974965, now seen corresponding path program 1 times [2018-11-18 14:32:40,265 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:40,265 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:40,265 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:40,265 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:40,265 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:40,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:40,476 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:40,477 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:40,477 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 14:32:40,477 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 14:32:40,477 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 14:32:40,477 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 14:32:40,477 INFO L87 Difference]: Start difference. First operand 22311 states and 29875 transitions. cyclomatic complexity: 7596 Second operand 5 states. [2018-11-18 14:32:40,731 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:32:40,731 INFO L93 Difference]: Finished difference Result 38539 states and 51826 transitions. [2018-11-18 14:32:40,731 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 14:32:40,731 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 38539 states and 51826 transitions. [2018-11-18 14:32:40,816 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 38204 [2018-11-18 14:32:40,872 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 38539 states to 38539 states and 51826 transitions. [2018-11-18 14:32:40,872 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 38539 [2018-11-18 14:32:40,889 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 38539 [2018-11-18 14:32:40,889 INFO L73 IsDeterministic]: Start isDeterministic. Operand 38539 states and 51826 transitions. [2018-11-18 14:32:40,904 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:32:40,904 INFO L705 BuchiCegarLoop]: Abstraction has 38539 states and 51826 transitions. [2018-11-18 14:32:40,919 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38539 states and 51826 transitions. [2018-11-18 14:32:41,039 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38539 to 22719. [2018-11-18 14:32:41,039 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22719 states. [2018-11-18 14:32:41,059 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22719 states to 22719 states and 30162 transitions. [2018-11-18 14:32:41,059 INFO L728 BuchiCegarLoop]: Abstraction has 22719 states and 30162 transitions. [2018-11-18 14:32:41,059 INFO L608 BuchiCegarLoop]: Abstraction has 22719 states and 30162 transitions. [2018-11-18 14:32:41,059 INFO L442 BuchiCegarLoop]: ======== Iteration 28============ [2018-11-18 14:32:41,059 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22719 states and 30162 transitions. [2018-11-18 14:32:41,097 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 22480 [2018-11-18 14:32:41,097 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:32:41,097 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:32:41,098 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:41,098 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:41,099 INFO L794 eck$LassoCheckResult]: Stem: 727758#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 727635#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 727636#L1225 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 728162#L564 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 727674#L571 assume 1 == ~m_i~0;~m_st~0 := 0; 727653#L571-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 727342#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 727343#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 728167#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 727896#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 727462#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 727463#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 728155#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 728036#L611-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 728037#L828 assume !(0 == ~M_E~0); 728174#L828-2 assume !(0 == ~T1_E~0); 727789#L833-1 assume !(0 == ~T2_E~0); 727477#L838-1 assume !(0 == ~T3_E~0); 727478#L843-1 assume !(0 == ~T4_E~0); 728269#L848-1 assume !(0 == ~T5_E~0); 728046#L853-1 assume !(0 == ~T6_E~0); 727770#L858-1 assume !(0 == ~T7_E~0); 727265#L863-1 assume !(0 == ~T8_E~0); 727266#L868-1 assume !(0 == ~E_1~0); 727988#L873-1 assume !(0 == ~E_2~0); 727867#L878-1 assume !(0 == ~E_3~0); 727603#L883-1 assume !(0 == ~E_4~0); 727604#L888-1 assume !(0 == ~E_5~0); 728120#L893-1 assume !(0 == ~E_6~0); 727835#L898-1 assume !(0 == ~E_7~0); 727744#L903-1 assume !(0 == ~E_8~0); 727412#L908-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 727413#L392 assume !(1 == ~m_pc~0); 727814#L392-2 is_master_triggered_~__retres1~0 := 0; 727820#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 728324#L404 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 728131#L1025 assume !(0 != activate_threads_~tmp~1); 728132#L1025-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 727973#L411 assume !(1 == ~t1_pc~0); 727939#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 727327#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 727328#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 727442#L1033 assume !(0 != activate_threads_~tmp___0~0); 727685#L1033-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 727686#L430 assume !(1 == ~t2_pc~0); 728143#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 727513#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 727464#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 727465#L1041 assume !(0 != activate_threads_~tmp___1~0); 728370#L1041-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 728376#L449 assume !(1 == ~t3_pc~0); 728219#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 728386#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 728402#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 728159#L1049 assume !(0 != activate_threads_~tmp___2~0); 728160#L1049-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 727361#L468 assume !(1 == ~t4_pc~0); 727362#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 727371#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 727827#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 727751#L1057 assume !(0 != activate_threads_~tmp___3~0); 727752#L1057-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 727588#L487 assume !(1 == ~t5_pc~0); 727321#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 727590#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 727959#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 727960#L1065 assume !(0 != activate_threads_~tmp___4~0); 728396#L1065-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 727769#L506 assume !(1 == ~t6_pc~0); 727763#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 727764#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 728157#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 728065#L1073 assume !(0 != activate_threads_~tmp___5~0); 728066#L1073-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 727897#L525 assume !(1 == ~t7_pc~0); 727845#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 727844#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 728377#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 727609#L1081 assume !(0 != activate_threads_~tmp___6~0); 727610#L1081-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 727611#L544 assume !(1 == ~t8_pc~0); 727910#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 727259#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 727260#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 727394#L1089 assume !(0 != activate_threads_~tmp___7~0); 728200#L1089-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 727779#L921 assume !(1 == ~M_E~0); 727780#L921-2 assume !(1 == ~T1_E~0); 727473#L926-1 assume !(1 == ~T2_E~0); 727474#L931-1 assume !(1 == ~T3_E~0); 728267#L936-1 assume !(1 == ~T4_E~0); 728056#L941-1 assume !(1 == ~T5_E~0); 727776#L946-1 assume !(1 == ~T6_E~0); 727277#L951-1 assume !(1 == ~T7_E~0); 727278#L956-1 assume !(1 == ~T8_E~0); 728161#L961-1 assume !(1 == ~E_1~0); 727872#L966-1 assume !(1 == ~E_2~0); 727614#L971-1 assume !(1 == ~E_3~0); 727615#L976-1 assume !(1 == ~E_4~0); 728114#L981-1 assume !(1 == ~E_5~0); 727833#L986-1 assume !(1 == ~E_6~0); 727738#L991-1 assume !(1 == ~E_7~0); 727400#L996-1 assume !(1 == ~E_8~0); 727401#L1001-1 assume { :end_inline_reset_delta_events } true; 728288#L1262-3 [2018-11-18 14:32:41,099 INFO L796 eck$LassoCheckResult]: Loop: 728288#L1262-3 assume true; 733419#L1262-1 assume !false; 733412#L1263 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 733407#L803 assume true; 733400#L681-1 assume !false; 733395#L682 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 733393#L624 assume !(0 == ~m_st~0); 733394#L628 assume !(0 == ~t1_st~0); 733389#L632 assume !(0 == ~t2_st~0); 733390#L636 assume !(0 == ~t3_st~0); 733392#L640 assume !(0 == ~t4_st~0); 733387#L644 assume !(0 == ~t5_st~0); 733388#L648 assume !(0 == ~t6_st~0); 733391#L652 assume !(0 == ~t7_st~0); 733385#L656 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9 := 0; 733386#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 733379#L672 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 733380#L686 assume !(0 != eval_~tmp~0); 737191#L818 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 737189#L564-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 737187#L828-3 assume 0 == ~M_E~0;~M_E~0 := 1; 737185#L828-5 assume !(0 == ~T1_E~0); 737183#L833-3 assume !(0 == ~T2_E~0); 737181#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 737179#L843-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 737177#L848-3 assume !(0 == ~T5_E~0); 737175#L853-3 assume !(0 == ~T6_E~0); 737173#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 737170#L863-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 737168#L868-3 assume !(0 == ~E_1~0); 737166#L873-3 assume !(0 == ~E_2~0); 737164#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 737162#L883-3 assume 0 == ~E_4~0;~E_4~0 := 1; 737160#L888-3 assume !(0 == ~E_5~0); 737158#L893-3 assume !(0 == ~E_6~0); 737155#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 737152#L903-3 assume 0 == ~E_8~0;~E_8~0 := 1; 737149#L908-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 737146#L392-27 assume !(1 == ~m_pc~0); 737144#L392-29 is_master_triggered_~__retres1~0 := 0; 737141#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 737139#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 737138#L1025-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 737137#L1025-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 737135#L411-27 assume !(1 == ~t1_pc~0); 737132#L411-29 is_transmit1_triggered_~__retres1~1 := 0; 737130#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 737128#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 737126#L1033-27 assume !(0 != activate_threads_~tmp___0~0); 737124#L1033-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 737122#L430-27 assume !(1 == ~t2_pc~0); 737120#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 737118#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 737116#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 737114#L1041-27 assume !(0 != activate_threads_~tmp___1~0); 737112#L1041-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 737110#L449-27 assume 1 == ~t3_pc~0; 737107#L450-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 737104#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 737101#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 737098#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 737096#L1049-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 737094#L468-27 assume !(1 == ~t4_pc~0); 737091#L468-29 is_transmit4_triggered_~__retres1~4 := 0; 737088#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 737085#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 737082#L1057-27 assume !(0 != activate_threads_~tmp___3~0); 737080#L1057-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 737078#L487-27 assume !(1 == ~t5_pc~0); 737075#L487-29 is_transmit5_triggered_~__retres1~5 := 0; 737074#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 737073#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 737071#L1065-27 assume !(0 != activate_threads_~tmp___4~0); 737068#L1065-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 737066#L506-27 assume !(1 == ~t6_pc~0); 737064#L506-29 is_transmit6_triggered_~__retres1~6 := 0; 737062#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 737060#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 737058#L1073-27 assume !(0 != activate_threads_~tmp___5~0); 737056#L1073-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 737054#L525-27 assume 1 == ~t7_pc~0; 737051#L526-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 737049#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 737047#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 737045#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 737043#L1081-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 737041#L544-27 assume !(1 == ~t8_pc~0); 737039#L544-29 is_transmit8_triggered_~__retres1~8 := 0; 737037#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 733795#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 733791#L1089-27 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 733788#L1089-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 733785#L921-3 assume 1 == ~M_E~0;~M_E~0 := 2; 733781#L921-5 assume !(1 == ~T1_E~0); 733778#L926-3 assume !(1 == ~T2_E~0); 733775#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 733772#L936-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 733769#L941-3 assume !(1 == ~T5_E~0); 733765#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 733762#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 733759#L956-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 733756#L961-3 assume !(1 == ~E_1~0); 733753#L966-3 assume !(1 == ~E_2~0); 733750#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 733747#L976-3 assume 1 == ~E_4~0;~E_4~0 := 2; 733744#L981-3 assume !(1 == ~E_5~0); 733740#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 733736#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 733732#L996-3 assume 1 == ~E_8~0;~E_8~0 := 2; 733729#L1001-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 733598#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 733584#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 733577#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 733569#L1281 assume !(0 == start_simulation_~tmp~3); 733562#L1281-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 733539#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 733525#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 733517#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 733510#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 733455#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 733445#L1244 start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 733435#L1294 assume !(0 != start_simulation_~tmp___0~1); 728288#L1262-3 [2018-11-18 14:32:41,099 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:41,099 INFO L82 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 8 times [2018-11-18 14:32:41,099 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:41,099 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:41,100 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:41,100 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:41,100 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:41,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:32:41,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:32:41,132 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:41,132 INFO L82 PathProgramCache]: Analyzing trace with hash -1421318958, now seen corresponding path program 1 times [2018-11-18 14:32:41,133 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:41,133 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:41,133 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:41,133 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 14:32:41,133 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:41,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:41,197 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:41,197 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:41,197 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 14:32:41,197 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 14:32:41,197 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 14:32:41,197 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 14:32:41,198 INFO L87 Difference]: Start difference. First operand 22719 states and 30162 transitions. cyclomatic complexity: 7475 Second operand 5 states. [2018-11-18 14:32:41,419 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:32:41,420 INFO L93 Difference]: Finished difference Result 65780 states and 86543 transitions. [2018-11-18 14:32:41,420 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 14:32:41,420 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 65780 states and 86543 transitions. [2018-11-18 14:32:41,560 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 65136 [2018-11-18 14:32:41,653 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 65780 states to 65780 states and 86543 transitions. [2018-11-18 14:32:41,653 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 65780 [2018-11-18 14:32:41,679 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 65780 [2018-11-18 14:32:41,679 INFO L73 IsDeterministic]: Start isDeterministic. Operand 65780 states and 86543 transitions. [2018-11-18 14:32:41,701 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:32:41,701 INFO L705 BuchiCegarLoop]: Abstraction has 65780 states and 86543 transitions. [2018-11-18 14:32:41,723 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65780 states and 86543 transitions. [2018-11-18 14:32:41,878 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65780 to 23490. [2018-11-18 14:32:41,878 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 23490 states. [2018-11-18 14:32:41,897 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23490 states to 23490 states and 30933 transitions. [2018-11-18 14:32:41,898 INFO L728 BuchiCegarLoop]: Abstraction has 23490 states and 30933 transitions. [2018-11-18 14:32:41,898 INFO L608 BuchiCegarLoop]: Abstraction has 23490 states and 30933 transitions. [2018-11-18 14:32:41,898 INFO L442 BuchiCegarLoop]: ======== Iteration 29============ [2018-11-18 14:32:41,898 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23490 states and 30933 transitions. [2018-11-18 14:32:41,936 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 23248 [2018-11-18 14:32:41,936 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:32:41,936 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:32:41,937 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:41,937 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:41,937 INFO L794 eck$LassoCheckResult]: Stem: 816255#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 816141#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 816142#L1225 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 816665#L564 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 816178#L571 assume 1 == ~m_i~0;~m_st~0 := 0; 816159#L571-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 815854#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 815855#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 816670#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 816406#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 815972#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 815973#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 816658#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 816551#L611-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 816552#L828 assume !(0 == ~M_E~0); 816678#L828-2 assume !(0 == ~T1_E~0); 816285#L833-1 assume !(0 == ~T2_E~0); 815987#L838-1 assume !(0 == ~T3_E~0); 815988#L843-1 assume !(0 == ~T4_E~0); 816768#L848-1 assume !(0 == ~T5_E~0); 816562#L853-1 assume !(0 == ~T6_E~0); 816266#L858-1 assume !(0 == ~T7_E~0); 815777#L863-1 assume !(0 == ~T8_E~0); 815778#L868-1 assume !(0 == ~E_1~0); 816510#L873-1 assume !(0 == ~E_2~0); 816366#L878-1 assume !(0 == ~E_3~0); 816110#L883-1 assume !(0 == ~E_4~0); 816111#L888-1 assume !(0 == ~E_5~0); 816628#L893-1 assume !(0 == ~E_6~0); 816334#L898-1 assume !(0 == ~E_7~0); 816244#L903-1 assume !(0 == ~E_8~0); 815924#L908-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 815925#L392 assume !(1 == ~m_pc~0); 816313#L392-2 is_master_triggered_~__retres1~0 := 0; 816319#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 816820#L404 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 816638#L1025 assume !(0 != activate_threads_~tmp~1); 816639#L1025-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 816496#L411 assume !(1 == ~t1_pc~0); 816464#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 815838#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 815839#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 815954#L1033 assume !(0 != activate_threads_~tmp___0~0); 816187#L1033-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 816188#L430 assume !(1 == ~t2_pc~0); 816649#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 816026#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 815974#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 815975#L1041 assume !(0 != activate_threads_~tmp___1~0); 816850#L1041-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 816851#L449 assume !(1 == ~t3_pc~0); 816726#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 816860#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 816884#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 816662#L1049 assume !(0 != activate_threads_~tmp___2~0); 816663#L1049-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 815873#L468 assume !(1 == ~t4_pc~0); 815874#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 815883#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 816326#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 816249#L1057 assume !(0 != activate_threads_~tmp___3~0); 816250#L1057-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 816095#L487 assume !(1 == ~t5_pc~0); 815832#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 816097#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 816483#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 816484#L1065 assume !(0 != activate_threads_~tmp___4~0); 816866#L1065-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 816265#L506 assume !(1 == ~t6_pc~0); 816260#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 816261#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 816660#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 816576#L1073 assume !(0 != activate_threads_~tmp___5~0); 816577#L1073-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 816408#L525 assume !(1 == ~t7_pc~0); 816344#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 816343#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 816852#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 816116#L1081 assume !(0 != activate_threads_~tmp___6~0); 816117#L1081-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 816118#L544 assume !(1 == ~t8_pc~0); 816436#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 815771#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 815772#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 815906#L1089 assume !(0 != activate_threads_~tmp___7~0); 816705#L1089-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 816273#L921 assume !(1 == ~M_E~0); 816274#L921-2 assume !(1 == ~T1_E~0); 815983#L926-1 assume !(1 == ~T2_E~0); 815984#L931-1 assume !(1 == ~T3_E~0); 816766#L936-1 assume !(1 == ~T4_E~0); 816570#L941-1 assume !(1 == ~T5_E~0); 816271#L946-1 assume !(1 == ~T6_E~0); 815789#L951-1 assume !(1 == ~T7_E~0); 815790#L956-1 assume !(1 == ~T8_E~0); 816664#L961-1 assume !(1 == ~E_1~0); 816371#L966-1 assume !(1 == ~E_2~0); 816121#L971-1 assume !(1 == ~E_3~0); 816122#L976-1 assume !(1 == ~E_4~0); 816623#L981-1 assume !(1 == ~E_5~0); 816332#L986-1 assume !(1 == ~E_6~0); 816236#L991-1 assume !(1 == ~E_7~0); 815914#L996-1 assume !(1 == ~E_8~0); 815915#L1001-1 assume { :end_inline_reset_delta_events } true; 816785#L1262-3 [2018-11-18 14:32:41,937 INFO L796 eck$LassoCheckResult]: Loop: 816785#L1262-3 assume true; 826523#L1262-1 assume !false; 826514#L1263 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 825879#L803 assume true; 826488#L681-1 assume !false; 826485#L682 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 826385#L624 assume !(0 == ~m_st~0); 826386#L628 assume !(0 == ~t1_st~0); 826381#L632 assume !(0 == ~t2_st~0); 826382#L636 assume !(0 == ~t3_st~0); 826384#L640 assume !(0 == ~t4_st~0); 826379#L644 assume !(0 == ~t5_st~0); 826380#L648 assume !(0 == ~t6_st~0); 826383#L652 assume !(0 == ~t7_st~0); 826377#L656 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9 := 0; 826373#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 826374#L672 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 827758#L686 assume !(0 != eval_~tmp~0); 827751#L818 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 827745#L564-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 827740#L828-3 assume 0 == ~M_E~0;~M_E~0 := 1; 827734#L828-5 assume !(0 == ~T1_E~0); 827729#L833-3 assume !(0 == ~T2_E~0); 827724#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 827718#L843-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 827712#L848-3 assume !(0 == ~T5_E~0); 827705#L853-3 assume !(0 == ~T6_E~0); 827699#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 827693#L863-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 827687#L868-3 assume !(0 == ~E_1~0); 827681#L873-3 assume !(0 == ~E_2~0); 827673#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 827666#L883-3 assume 0 == ~E_4~0;~E_4~0 := 1; 827659#L888-3 assume !(0 == ~E_5~0); 827652#L893-3 assume !(0 == ~E_6~0); 827645#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 827639#L903-3 assume 0 == ~E_8~0;~E_8~0 := 1; 827633#L908-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 827632#L392-27 assume 1 == ~m_pc~0; 827630#L393-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 827628#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 827626#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 827624#L1025-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 827619#L1025-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 827613#L411-27 assume !(1 == ~t1_pc~0); 827607#L411-29 is_transmit1_triggered_~__retres1~1 := 0; 827602#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 827595#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 827589#L1033-27 assume !(0 != activate_threads_~tmp___0~0); 827585#L1033-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 827581#L430-27 assume !(1 == ~t2_pc~0); 827578#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 827573#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 827559#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 827554#L1041-27 assume !(0 != activate_threads_~tmp___1~0); 827549#L1041-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 827545#L449-27 assume 1 == ~t3_pc~0; 827540#L450-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 827534#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 827529#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 827524#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 827520#L1049-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 827516#L468-27 assume !(1 == ~t4_pc~0); 827503#L468-29 is_transmit4_triggered_~__retres1~4 := 0; 827498#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 827493#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 827488#L1057-27 assume !(0 != activate_threads_~tmp___3~0); 827484#L1057-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 827257#L487-27 assume !(1 == ~t5_pc~0); 827254#L487-29 is_transmit5_triggered_~__retres1~5 := 0; 827252#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 827250#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 827232#L1065-27 assume !(0 != activate_threads_~tmp___4~0); 827225#L1065-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 827218#L506-27 assume !(1 == ~t6_pc~0); 827212#L506-29 is_transmit6_triggered_~__retres1~6 := 0; 827207#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 827193#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 827191#L1073-27 assume !(0 != activate_threads_~tmp___5~0); 827189#L1073-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 827187#L525-27 assume 1 == ~t7_pc~0; 827184#L526-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 827182#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 827180#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 827178#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 827176#L1081-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 827174#L544-27 assume !(1 == ~t8_pc~0); 827172#L544-29 is_transmit8_triggered_~__retres1~8 := 0; 827170#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 827168#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 827166#L1089-27 assume 0 != activate_threads_~tmp___7~0;~t8_st~0 := 0; 827162#L1089-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 827160#L921-3 assume 1 == ~M_E~0;~M_E~0 := 2; 827158#L921-5 assume !(1 == ~T1_E~0); 827156#L926-3 assume !(1 == ~T2_E~0); 827153#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 827151#L936-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 827149#L941-3 assume !(1 == ~T5_E~0); 827147#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 827145#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 827143#L956-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 827141#L961-3 assume !(1 == ~E_1~0); 827139#L966-3 assume !(1 == ~E_2~0); 827136#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 827134#L976-3 assume 1 == ~E_4~0;~E_4~0 := 2; 827132#L981-3 assume !(1 == ~E_5~0); 827130#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 826803#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 826760#L996-3 assume 1 == ~E_8~0;~E_8~0 := 2; 826749#L1001-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 826577#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 826568#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 826566#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 826563#L1281 assume !(0 == start_simulation_~tmp~3); 826560#L1281-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 826557#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 826547#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 826545#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 826543#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 826540#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 826538#L1244 start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 826536#L1294 assume !(0 != start_simulation_~tmp___0~1); 816785#L1262-3 [2018-11-18 14:32:41,938 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:41,938 INFO L82 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 9 times [2018-11-18 14:32:41,938 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:41,938 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:41,938 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:41,938 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:41,939 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:41,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:32:41,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:32:41,968 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:41,968 INFO L82 PathProgramCache]: Analyzing trace with hash -966412877, now seen corresponding path program 1 times [2018-11-18 14:32:41,968 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:41,968 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:41,969 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:41,969 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 14:32:41,969 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:41,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:42,038 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:42,038 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:42,038 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 14:32:42,039 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 14:32:42,039 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 14:32:42,039 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 14:32:42,039 INFO L87 Difference]: Start difference. First operand 23490 states and 30933 transitions. cyclomatic complexity: 7475 Second operand 5 states. [2018-11-18 14:32:42,237 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:32:42,238 INFO L93 Difference]: Finished difference Result 37978 states and 50284 transitions. [2018-11-18 14:32:42,238 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 14:32:42,238 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 37978 states and 50284 transitions. [2018-11-18 14:32:42,324 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 37608 [2018-11-18 14:32:42,379 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 37978 states to 37978 states and 50284 transitions. [2018-11-18 14:32:42,379 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 37978 [2018-11-18 14:32:42,395 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 37978 [2018-11-18 14:32:42,395 INFO L73 IsDeterministic]: Start isDeterministic. Operand 37978 states and 50284 transitions. [2018-11-18 14:32:42,410 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:32:42,410 INFO L705 BuchiCegarLoop]: Abstraction has 37978 states and 50284 transitions. [2018-11-18 14:32:42,425 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37978 states and 50284 transitions. [2018-11-18 14:32:42,544 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37978 to 23874. [2018-11-18 14:32:42,544 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 23874 states. [2018-11-18 14:32:42,564 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23874 states to 23874 states and 31188 transitions. [2018-11-18 14:32:42,564 INFO L728 BuchiCegarLoop]: Abstraction has 23874 states and 31188 transitions. [2018-11-18 14:32:42,564 INFO L608 BuchiCegarLoop]: Abstraction has 23874 states and 31188 transitions. [2018-11-18 14:32:42,564 INFO L442 BuchiCegarLoop]: ======== Iteration 30============ [2018-11-18 14:32:42,564 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23874 states and 31188 transitions. [2018-11-18 14:32:42,604 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 23632 [2018-11-18 14:32:42,604 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:32:42,604 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:32:42,605 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:42,605 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:42,605 INFO L794 eck$LassoCheckResult]: Stem: 877754#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 877631#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 877632#L1225 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 878195#L564 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 877673#L571 assume 1 == ~m_i~0;~m_st~0 := 0; 877653#L571-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 877337#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 877338#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 878202#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 877902#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 877457#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 877458#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 878186#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 878048#L611-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 878049#L828 assume !(0 == ~M_E~0); 878208#L828-2 assume !(0 == ~T1_E~0); 877781#L833-1 assume !(0 == ~T2_E~0); 877472#L838-1 assume !(0 == ~T3_E~0); 877473#L843-1 assume !(0 == ~T4_E~0); 878303#L848-1 assume !(0 == ~T5_E~0); 878060#L853-1 assume !(0 == ~T6_E~0); 877764#L858-1 assume !(0 == ~T7_E~0); 877259#L863-1 assume !(0 == ~T8_E~0); 877260#L868-1 assume !(0 == ~E_1~0); 877999#L873-1 assume !(0 == ~E_2~0); 877861#L878-1 assume !(0 == ~E_3~0); 877596#L883-1 assume !(0 == ~E_4~0); 877597#L888-1 assume !(0 == ~E_5~0); 878154#L893-1 assume !(0 == ~E_6~0); 877828#L898-1 assume !(0 == ~E_7~0); 877741#L903-1 assume !(0 == ~E_8~0); 877407#L908-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 877408#L392 assume !(1 == ~m_pc~0); 877806#L392-2 is_master_triggered_~__retres1~0 := 0; 877812#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 878438#L404 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 878161#L1025 assume !(0 != activate_threads_~tmp~1); 878162#L1025-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 877982#L411 assume !(1 == ~t1_pc~0); 877948#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 877320#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 877321#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 877438#L1033 assume !(0 != activate_threads_~tmp___0~0); 877681#L1033-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 877682#L430 assume !(1 == ~t2_pc~0); 878174#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 877511#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 877459#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 877460#L1041 assume !(0 != activate_threads_~tmp___1~0); 878406#L1041-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 878410#L449 assume !(1 == ~t3_pc~0); 878252#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 878420#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 878439#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 878191#L1049 assume !(0 != activate_threads_~tmp___2~0); 878192#L1049-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 877356#L468 assume !(1 == ~t4_pc~0); 877357#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 877365#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 877820#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 877748#L1057 assume !(0 != activate_threads_~tmp___3~0); 877749#L1057-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 877581#L487 assume !(1 == ~t5_pc~0); 877314#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 877583#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 877968#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 877969#L1065 assume !(0 != activate_threads_~tmp___4~0); 878426#L1065-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 877763#L506 assume !(1 == ~t6_pc~0); 877759#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 877760#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 878188#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 878089#L1073 assume !(0 != activate_threads_~tmp___5~0); 878090#L1073-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 877903#L525 assume !(1 == ~t7_pc~0); 877838#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 877837#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 878411#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 877604#L1081 assume !(0 != activate_threads_~tmp___6~0); 877605#L1081-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 877606#L544 assume !(1 == ~t8_pc~0); 877922#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 877253#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 877254#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 877389#L1089 assume !(0 != activate_threads_~tmp___7~0); 878232#L1089-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 877773#L921 assume !(1 == ~M_E~0); 877774#L921-2 assume !(1 == ~T1_E~0); 877468#L926-1 assume !(1 == ~T2_E~0); 877469#L931-1 assume !(1 == ~T3_E~0); 878301#L936-1 assume !(1 == ~T4_E~0); 878078#L941-1 assume !(1 == ~T5_E~0); 877769#L946-1 assume !(1 == ~T6_E~0); 877271#L951-1 assume !(1 == ~T7_E~0); 877272#L956-1 assume !(1 == ~T8_E~0); 878194#L961-1 assume !(1 == ~E_1~0); 877868#L966-1 assume !(1 == ~E_2~0); 877609#L971-1 assume !(1 == ~E_3~0); 877610#L976-1 assume !(1 == ~E_4~0); 878148#L981-1 assume !(1 == ~E_5~0); 877826#L986-1 assume !(1 == ~E_6~0); 877733#L991-1 assume !(1 == ~E_7~0); 877397#L996-1 assume !(1 == ~E_8~0); 877398#L1001-1 assume { :end_inline_reset_delta_events } true; 878331#L1262-3 [2018-11-18 14:32:42,605 INFO L796 eck$LassoCheckResult]: Loop: 878331#L1262-3 assume true; 884339#L1262-1 assume !false; 884335#L1263 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 884334#L803 assume true; 884333#L681-1 assume !false; 884331#L682 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 884325#L624 assume !(0 == ~m_st~0); 884326#L628 assume !(0 == ~t1_st~0); 884321#L632 assume !(0 == ~t2_st~0); 884322#L636 assume !(0 == ~t3_st~0); 884324#L640 assume !(0 == ~t4_st~0); 884319#L644 assume !(0 == ~t5_st~0); 884320#L648 assume !(0 == ~t6_st~0); 884323#L652 assume !(0 == ~t7_st~0); 884317#L656 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9 := 0; 884318#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 884313#L672 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 884314#L686 assume !(0 != eval_~tmp~0); 884658#L818 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 884656#L564-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 884654#L828-3 assume 0 == ~M_E~0;~M_E~0 := 1; 884652#L828-5 assume !(0 == ~T1_E~0); 884650#L833-3 assume !(0 == ~T2_E~0); 884648#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 884646#L843-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 884644#L848-3 assume !(0 == ~T5_E~0); 884642#L853-3 assume !(0 == ~T6_E~0); 884640#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 884638#L863-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 884634#L868-3 assume !(0 == ~E_1~0); 884632#L873-3 assume !(0 == ~E_2~0); 884630#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 884626#L883-3 assume 0 == ~E_4~0;~E_4~0 := 1; 884621#L888-3 assume !(0 == ~E_5~0); 884617#L893-3 assume !(0 == ~E_6~0); 884612#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 884608#L903-3 assume 0 == ~E_8~0;~E_8~0 := 1; 884607#L908-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 884606#L392-27 assume 1 == ~m_pc~0; 884605#L393-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 884603#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 884601#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 884598#L1025-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 884597#L1025-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 884596#L411-27 assume !(1 == ~t1_pc~0); 884594#L411-29 is_transmit1_triggered_~__retres1~1 := 0; 884591#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 884588#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 884585#L1033-27 assume !(0 != activate_threads_~tmp___0~0); 884582#L1033-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 884580#L430-27 assume !(1 == ~t2_pc~0); 884578#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 884576#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 884574#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 884572#L1041-27 assume !(0 != activate_threads_~tmp___1~0); 884570#L1041-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 884568#L449-27 assume 1 == ~t3_pc~0; 884565#L450-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 884562#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 884559#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 884555#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 884552#L1049-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 884550#L468-27 assume !(1 == ~t4_pc~0); 884548#L468-29 is_transmit4_triggered_~__retres1~4 := 0; 884544#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 884539#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 884534#L1057-27 assume !(0 != activate_threads_~tmp___3~0); 884529#L1057-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 884525#L487-27 assume !(1 == ~t5_pc~0); 884521#L487-29 is_transmit5_triggered_~__retres1~5 := 0; 884518#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 884515#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 884512#L1065-27 assume !(0 != activate_threads_~tmp___4~0); 884509#L1065-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 884506#L506-27 assume !(1 == ~t6_pc~0); 884502#L506-29 is_transmit6_triggered_~__retres1~6 := 0; 884499#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 884496#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 884493#L1073-27 assume !(0 != activate_threads_~tmp___5~0); 884490#L1073-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 884487#L525-27 assume !(1 == ~t7_pc~0); 884484#L525-29 is_transmit7_triggered_~__retres1~7 := 0; 884480#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 884476#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 884473#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 884470#L1081-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 884466#L544-27 assume !(1 == ~t8_pc~0); 884463#L544-29 is_transmit8_triggered_~__retres1~8 := 0; 884459#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 884456#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 884453#L1089-27 assume !(0 != activate_threads_~tmp___7~0); 884450#L1089-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 884447#L921-3 assume 1 == ~M_E~0;~M_E~0 := 2; 884444#L921-5 assume !(1 == ~T1_E~0); 884440#L926-3 assume !(1 == ~T2_E~0); 884437#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 884434#L936-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 884431#L941-3 assume !(1 == ~T5_E~0); 884428#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 884425#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 884422#L956-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 884419#L961-3 assume !(1 == ~E_1~0); 884416#L966-3 assume !(1 == ~E_2~0); 884413#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 884410#L976-3 assume 1 == ~E_4~0;~E_4~0 := 2; 884407#L981-3 assume !(1 == ~E_5~0); 884404#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 884400#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 884397#L996-3 assume 1 == ~E_8~0;~E_8~0 := 2; 884394#L1001-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 884388#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 884378#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 884375#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 884371#L1281 assume !(0 == start_simulation_~tmp~3); 884368#L1281-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 884366#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 884356#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 884354#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 884350#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 884348#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 884346#L1244 start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 884344#L1294 assume !(0 != start_simulation_~tmp___0~1); 878331#L1262-3 [2018-11-18 14:32:42,606 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:42,606 INFO L82 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 10 times [2018-11-18 14:32:42,606 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:42,606 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:42,606 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:42,607 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:42,607 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:42,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:32:42,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:32:42,640 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:42,640 INFO L82 PathProgramCache]: Analyzing trace with hash 1447799632, now seen corresponding path program 1 times [2018-11-18 14:32:42,640 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:42,640 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:42,641 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:42,641 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 14:32:42,641 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:42,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:42,709 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:42,709 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:42,709 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-18 14:32:42,709 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 14:32:42,709 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-18 14:32:42,709 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-18 14:32:42,709 INFO L87 Difference]: Start difference. First operand 23874 states and 31188 transitions. cyclomatic complexity: 7346 Second operand 5 states. [2018-11-18 14:32:42,910 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:32:42,910 INFO L93 Difference]: Finished difference Result 55015 states and 72303 transitions. [2018-11-18 14:32:42,910 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-18 14:32:42,910 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 55015 states and 72303 transitions. [2018-11-18 14:32:43,052 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 54464 [2018-11-18 14:32:43,288 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 55015 states to 55015 states and 72303 transitions. [2018-11-18 14:32:43,288 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 55015 [2018-11-18 14:32:43,300 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 55015 [2018-11-18 14:32:43,300 INFO L73 IsDeterministic]: Start isDeterministic. Operand 55015 states and 72303 transitions. [2018-11-18 14:32:43,311 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:32:43,312 INFO L705 BuchiCegarLoop]: Abstraction has 55015 states and 72303 transitions. [2018-11-18 14:32:43,324 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55015 states and 72303 transitions. [2018-11-18 14:32:43,477 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55015 to 24645. [2018-11-18 14:32:43,478 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24645 states. [2018-11-18 14:32:43,499 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24645 states to 24645 states and 31959 transitions. [2018-11-18 14:32:43,499 INFO L728 BuchiCegarLoop]: Abstraction has 24645 states and 31959 transitions. [2018-11-18 14:32:43,499 INFO L608 BuchiCegarLoop]: Abstraction has 24645 states and 31959 transitions. [2018-11-18 14:32:43,499 INFO L442 BuchiCegarLoop]: ======== Iteration 31============ [2018-11-18 14:32:43,499 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24645 states and 31959 transitions. [2018-11-18 14:32:43,539 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 24400 [2018-11-18 14:32:43,539 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:32:43,539 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:32:43,540 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:43,540 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:43,540 INFO L794 eck$LassoCheckResult]: Stem: 956651#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 956532#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 956533#L1225 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 957123#L564 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 956573#L571 assume 1 == ~m_i~0;~m_st~0 := 0; 956552#L571-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 956241#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 956242#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 957127#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 956830#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 956362#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 956363#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 957114#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 956991#L611-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 956992#L828 assume !(0 == ~M_E~0); 957135#L828-2 assume !(0 == ~T1_E~0); 956678#L833-1 assume !(0 == ~T2_E~0); 956377#L838-1 assume !(0 == ~T3_E~0); 956378#L843-1 assume !(0 == ~T4_E~0); 957236#L848-1 assume !(0 == ~T5_E~0); 957006#L853-1 assume !(0 == ~T6_E~0); 956661#L858-1 assume !(0 == ~T7_E~0); 956162#L863-1 assume !(0 == ~T8_E~0); 956163#L868-1 assume !(0 == ~E_1~0); 956934#L873-1 assume !(0 == ~E_2~0); 956771#L878-1 assume !(0 == ~E_3~0); 956501#L883-1 assume !(0 == ~E_4~0); 956502#L888-1 assume !(0 == ~E_5~0); 957084#L893-1 assume !(0 == ~E_6~0); 956726#L898-1 assume !(0 == ~E_7~0); 956640#L903-1 assume !(0 == ~E_8~0); 956310#L908-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 956311#L392 assume !(1 == ~m_pc~0); 956704#L392-2 is_master_triggered_~__retres1~0 := 0; 956710#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 957291#L404 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 957093#L1025 assume !(0 != activate_threads_~tmp~1); 957094#L1025-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 956920#L411 assume !(1 == ~t1_pc~0); 956886#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 956224#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 956225#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 956343#L1033 assume !(0 != activate_threads_~tmp___0~0); 956583#L1033-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 956584#L430 assume !(1 == ~t2_pc~0); 957104#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 956418#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 956364#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 956365#L1041 assume !(0 != activate_threads_~tmp___1~0); 957331#L1041-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 957335#L449 assume !(1 == ~t3_pc~0); 957185#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 957348#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 957377#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 957119#L1049 assume !(0 != activate_threads_~tmp___2~0); 957120#L1049-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 956260#L468 assume !(1 == ~t4_pc~0); 956261#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 956269#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 956718#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 956645#L1057 assume !(0 != activate_threads_~tmp___3~0); 956646#L1057-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 956486#L487 assume !(1 == ~t5_pc~0); 956217#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 956488#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 956907#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 956908#L1065 assume !(0 != activate_threads_~tmp___4~0); 957355#L1065-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 956660#L506 assume !(1 == ~t6_pc~0); 956656#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 956657#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 957116#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 957026#L1073 assume !(0 != activate_threads_~tmp___5~0); 957027#L1073-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 956831#L525 assume !(1 == ~t7_pc~0); 956737#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 956833#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 957373#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 956507#L1081 assume !(0 != activate_threads_~tmp___6~0); 956508#L1081-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 956509#L544 assume !(1 == ~t8_pc~0); 956854#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 956156#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 956157#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 956292#L1089 assume !(0 != activate_threads_~tmp___7~0); 957165#L1089-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 956670#L921 assume !(1 == ~M_E~0); 956671#L921-2 assume !(1 == ~T1_E~0); 956373#L926-1 assume !(1 == ~T2_E~0); 956374#L931-1 assume !(1 == ~T3_E~0); 957234#L936-1 assume !(1 == ~T4_E~0); 957016#L941-1 assume !(1 == ~T5_E~0); 956666#L946-1 assume !(1 == ~T6_E~0); 956174#L951-1 assume !(1 == ~T7_E~0); 956175#L956-1 assume !(1 == ~T8_E~0); 957122#L961-1 assume !(1 == ~E_1~0); 956784#L966-1 assume !(1 == ~E_2~0); 956512#L971-1 assume !(1 == ~E_3~0); 956513#L976-1 assume !(1 == ~E_4~0); 957077#L981-1 assume !(1 == ~E_5~0); 956724#L986-1 assume !(1 == ~E_6~0); 956631#L991-1 assume !(1 == ~E_7~0); 956300#L996-1 assume !(1 == ~E_8~0); 956301#L1001-1 assume { :end_inline_reset_delta_events } true; 957255#L1262-3 [2018-11-18 14:32:43,540 INFO L796 eck$LassoCheckResult]: Loop: 957255#L1262-3 assume true; 962275#L1262-1 assume !false; 962267#L1263 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 962265#L803 assume true; 962262#L681-1 assume !false; 962260#L682 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 962254#L624 assume !(0 == ~m_st~0); 962255#L628 assume !(0 == ~t1_st~0); 962250#L632 assume !(0 == ~t2_st~0); 962251#L636 assume !(0 == ~t3_st~0); 962253#L640 assume !(0 == ~t4_st~0); 962248#L644 assume !(0 == ~t5_st~0); 962249#L648 assume !(0 == ~t6_st~0); 962252#L652 assume !(0 == ~t7_st~0); 962246#L656 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9 := 0; 962247#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 960206#L672 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 960207#L686 assume !(0 != eval_~tmp~0); 962735#L818 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 962734#L564-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 962733#L828-3 assume 0 == ~M_E~0;~M_E~0 := 1; 962732#L828-5 assume !(0 == ~T1_E~0); 962731#L833-3 assume !(0 == ~T2_E~0); 962730#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 962729#L843-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 962728#L848-3 assume !(0 == ~T5_E~0); 962727#L853-3 assume !(0 == ~T6_E~0); 962726#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 962725#L863-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 962724#L868-3 assume !(0 == ~E_1~0); 962723#L873-3 assume !(0 == ~E_2~0); 962722#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 962721#L883-3 assume 0 == ~E_4~0;~E_4~0 := 1; 962720#L888-3 assume !(0 == ~E_5~0); 962719#L893-3 assume !(0 == ~E_6~0); 962718#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 962717#L903-3 assume 0 == ~E_8~0;~E_8~0 := 1; 962716#L908-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 962715#L392-27 assume !(1 == ~m_pc~0); 962714#L392-29 is_master_triggered_~__retres1~0 := 0; 962712#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 962710#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 962708#L1025-27 assume !(0 != activate_threads_~tmp~1); 962706#L1025-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 962705#L411-27 assume !(1 == ~t1_pc~0); 962704#L411-29 is_transmit1_triggered_~__retres1~1 := 0; 962703#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 962702#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 962701#L1033-27 assume !(0 != activate_threads_~tmp___0~0); 962700#L1033-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 962699#L430-27 assume !(1 == ~t2_pc~0); 962698#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 962697#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 962696#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 962695#L1041-27 assume !(0 != activate_threads_~tmp___1~0); 962694#L1041-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 962693#L449-27 assume !(1 == ~t3_pc~0); 962692#L449-29 is_transmit3_triggered_~__retres1~3 := 0; 962690#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 962688#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 962686#L1049-27 assume !(0 != activate_threads_~tmp___2~0); 962684#L1049-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 962683#L468-27 assume !(1 == ~t4_pc~0); 962682#L468-29 is_transmit4_triggered_~__retres1~4 := 0; 962681#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 962680#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 962679#L1057-27 assume !(0 != activate_threads_~tmp___3~0); 962678#L1057-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 962677#L487-27 assume !(1 == ~t5_pc~0); 962675#L487-29 is_transmit5_triggered_~__retres1~5 := 0; 962674#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 962673#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 962672#L1065-27 assume !(0 != activate_threads_~tmp___4~0); 962671#L1065-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 962670#L506-27 assume !(1 == ~t6_pc~0); 962669#L506-29 is_transmit6_triggered_~__retres1~6 := 0; 962668#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 962667#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 962666#L1073-27 assume !(0 != activate_threads_~tmp___5~0); 962665#L1073-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 962664#L525-27 assume 1 == ~t7_pc~0; 962662#L526-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 962660#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 962658#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 962656#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 962655#L1081-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 962594#L544-27 assume !(1 == ~t8_pc~0); 962592#L544-29 is_transmit8_triggered_~__retres1~8 := 0; 962590#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 962588#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 962586#L1089-27 assume !(0 != activate_threads_~tmp___7~0); 962584#L1089-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 962582#L921-3 assume 1 == ~M_E~0;~M_E~0 := 2; 962580#L921-5 assume !(1 == ~T1_E~0); 962578#L926-3 assume !(1 == ~T2_E~0); 962576#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 962574#L936-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 962572#L941-3 assume !(1 == ~T5_E~0); 962570#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 962568#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 962566#L956-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 962564#L961-3 assume !(1 == ~E_1~0); 962562#L966-3 assume !(1 == ~E_2~0); 962560#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 962558#L976-3 assume 1 == ~E_4~0;~E_4~0 := 2; 962556#L981-3 assume !(1 == ~E_5~0); 962554#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 962552#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 962551#L996-3 assume 1 == ~E_8~0;~E_8~0 := 2; 962550#L1001-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 962488#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 962478#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 962446#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 962411#L1281 assume !(0 == start_simulation_~tmp~3); 962408#L1281-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 962330#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 962317#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 962310#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 962305#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 962299#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 962293#L1244 start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 962287#L1294 assume !(0 != start_simulation_~tmp___0~1); 957255#L1262-3 [2018-11-18 14:32:43,540 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:43,540 INFO L82 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 11 times [2018-11-18 14:32:43,540 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:43,541 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:43,541 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:43,541 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:43,541 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:43,544 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:32:43,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:32:43,559 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:43,559 INFO L82 PathProgramCache]: Analyzing trace with hash 1507203179, now seen corresponding path program 1 times [2018-11-18 14:32:43,559 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:43,559 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:43,560 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:43,560 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 14:32:43,560 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:43,563 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:43,599 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:43,599 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:43,599 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:32:43,600 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 14:32:43,600 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 14:32:43,600 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 14:32:43,600 INFO L87 Difference]: Start difference. First operand 24645 states and 31959 transitions. cyclomatic complexity: 7346 Second operand 3 states. [2018-11-18 14:32:43,717 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:32:43,717 INFO L93 Difference]: Finished difference Result 46869 states and 59895 transitions. [2018-11-18 14:32:43,717 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 14:32:43,717 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 46869 states and 59895 transitions. [2018-11-18 14:32:43,813 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 46496 [2018-11-18 14:32:43,873 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 46869 states to 46869 states and 59895 transitions. [2018-11-18 14:32:43,873 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 46869 [2018-11-18 14:32:43,890 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 46869 [2018-11-18 14:32:43,890 INFO L73 IsDeterministic]: Start isDeterministic. Operand 46869 states and 59895 transitions. [2018-11-18 14:32:43,904 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:32:43,904 INFO L705 BuchiCegarLoop]: Abstraction has 46869 states and 59895 transitions. [2018-11-18 14:32:43,919 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46869 states and 59895 transitions. [2018-11-18 14:32:44,087 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46869 to 44661. [2018-11-18 14:32:44,087 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 44661 states. [2018-11-18 14:32:44,122 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44661 states to 44661 states and 57239 transitions. [2018-11-18 14:32:44,122 INFO L728 BuchiCegarLoop]: Abstraction has 44661 states and 57239 transitions. [2018-11-18 14:32:44,122 INFO L608 BuchiCegarLoop]: Abstraction has 44661 states and 57239 transitions. [2018-11-18 14:32:44,122 INFO L442 BuchiCegarLoop]: ======== Iteration 32============ [2018-11-18 14:32:44,122 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 44661 states and 57239 transitions. [2018-11-18 14:32:44,191 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 44288 [2018-11-18 14:32:44,191 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:32:44,191 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:32:44,192 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:44,192 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:44,192 INFO L794 eck$LassoCheckResult]: Stem: 1028160#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 1028045#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1028046#L1225 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 1028595#L564 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1028082#L571 assume 1 == ~m_i~0;~m_st~0 := 0; 1028063#L571-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1027759#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1027760#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1028601#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1028323#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1027878#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1027879#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1028588#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1028465#L611-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1028466#L828 assume !(0 == ~M_E~0); 1028613#L828-2 assume !(0 == ~T1_E~0); 1028191#L833-1 assume !(0 == ~T2_E~0); 1027893#L838-1 assume !(0 == ~T3_E~0); 1027894#L843-1 assume !(0 == ~T4_E~0); 1028708#L848-1 assume !(0 == ~T5_E~0); 1028476#L853-1 assume !(0 == ~T6_E~0); 1028172#L858-1 assume !(0 == ~T7_E~0); 1027682#L863-1 assume !(0 == ~T8_E~0); 1027683#L868-1 assume !(0 == ~E_1~0); 1028421#L873-1 assume !(0 == ~E_2~0); 1028277#L878-1 assume !(0 == ~E_3~0); 1028014#L883-1 assume !(0 == ~E_4~0); 1028015#L888-1 assume !(0 == ~E_5~0); 1028553#L893-1 assume !(0 == ~E_6~0); 1028240#L898-1 assume !(0 == ~E_7~0); 1028149#L903-1 assume !(0 == ~E_8~0); 1027830#L908-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1027831#L392 assume !(1 == ~m_pc~0); 1028216#L392-2 is_master_triggered_~__retres1~0 := 0; 1028223#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1028832#L404 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1028560#L1025 assume !(0 != activate_threads_~tmp~1); 1028561#L1025-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1028408#L411 assume !(1 == ~t1_pc~0); 1028375#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 1027743#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1027744#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1027860#L1033 assume !(0 != activate_threads_~tmp___0~0); 1028091#L1033-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1028092#L430 assume !(1 == ~t2_pc~0); 1028575#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 1027931#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1027880#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1027881#L1041 assume !(0 != activate_threads_~tmp___1~0); 1028794#L1041-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1028797#L449 assume !(1 == ~t3_pc~0); 1028660#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 1028809#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1028833#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1028592#L1049 assume !(0 != activate_threads_~tmp___2~0); 1028593#L1049-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1027778#L468 assume !(1 == ~t4_pc~0); 1027779#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 1027787#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1028231#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1028154#L1057 assume !(0 != activate_threads_~tmp___3~0); 1028155#L1057-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1027998#L487 assume !(1 == ~t5_pc~0); 1027737#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 1028000#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1028394#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1028395#L1065 assume !(0 != activate_threads_~tmp___4~0); 1028816#L1065-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1028171#L506 assume !(1 == ~t6_pc~0); 1028166#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 1028167#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1028590#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1028496#L1073 assume !(0 != activate_threads_~tmp___5~0); 1028497#L1073-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1028324#L525 assume !(1 == ~t7_pc~0); 1028251#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 1028326#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1028834#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1028020#L1081 assume !(0 != activate_threads_~tmp___6~0); 1028021#L1081-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1028022#L544 assume !(1 == ~t8_pc~0); 1028345#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 1027676#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1027677#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1027811#L1089 assume !(0 != activate_threads_~tmp___7~0); 1028639#L1089-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1028182#L921 assume !(1 == ~M_E~0); 1028183#L921-2 assume !(1 == ~T1_E~0); 1027889#L926-1 assume !(1 == ~T2_E~0); 1027890#L931-1 assume !(1 == ~T3_E~0); 1028706#L936-1 assume !(1 == ~T4_E~0); 1028484#L941-1 assume !(1 == ~T5_E~0); 1028178#L946-1 assume !(1 == ~T6_E~0); 1027694#L951-1 assume !(1 == ~T7_E~0); 1027695#L956-1 assume !(1 == ~T8_E~0); 1028594#L961-1 assume !(1 == ~E_1~0); 1028285#L966-1 assume !(1 == ~E_2~0); 1028025#L971-1 assume !(1 == ~E_3~0); 1028026#L976-1 assume !(1 == ~E_4~0); 1028547#L981-1 assume !(1 == ~E_5~0); 1028238#L986-1 assume !(1 == ~E_6~0); 1028142#L991-1 assume !(1 == ~E_7~0); 1027819#L996-1 assume !(1 == ~E_8~0); 1027820#L1001-1 assume { :end_inline_reset_delta_events } true; 1028729#L1262-3 [2018-11-18 14:32:44,192 INFO L796 eck$LassoCheckResult]: Loop: 1028729#L1262-3 assume true; 1050472#L1262-1 assume !false; 1050470#L1263 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 1050411#L803 assume true; 1050467#L681-1 assume !false; 1050465#L682 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1050463#L624 assume !(0 == ~m_st~0); 1050464#L628 assume !(0 == ~t1_st~0); 1050717#L632 assume !(0 == ~t2_st~0); 1050715#L636 assume !(0 == ~t3_st~0); 1050713#L640 assume !(0 == ~t4_st~0); 1050711#L644 assume !(0 == ~t5_st~0); 1050707#L648 assume !(0 == ~t6_st~0); 1050705#L652 assume !(0 == ~t7_st~0); 1050702#L656 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9 := 0; 1050700#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1050697#L672 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 1050695#L686 assume !(0 != eval_~tmp~0); 1050693#L818 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 1050691#L564-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 1050689#L828-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1050687#L828-5 assume !(0 == ~T1_E~0); 1050685#L833-3 assume !(0 == ~T2_E~0); 1050683#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1050680#L843-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1050678#L848-3 assume !(0 == ~T5_E~0); 1050676#L853-3 assume !(0 == ~T6_E~0); 1050674#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1050672#L863-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1050670#L868-3 assume !(0 == ~E_1~0); 1050668#L873-3 assume !(0 == ~E_2~0); 1050666#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1050664#L883-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1050662#L888-3 assume !(0 == ~E_5~0); 1050660#L893-3 assume !(0 == ~E_6~0); 1050658#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1050654#L903-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1050652#L908-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1050650#L392-27 assume 1 == ~m_pc~0; 1050647#L393-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 1050644#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1050642#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1050639#L1025-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1050637#L1025-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1050635#L411-27 assume !(1 == ~t1_pc~0); 1050633#L411-29 is_transmit1_triggered_~__retres1~1 := 0; 1050631#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1050629#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1050627#L1033-27 assume !(0 != activate_threads_~tmp___0~0); 1050625#L1033-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1050623#L430-27 assume !(1 == ~t2_pc~0); 1050621#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 1050619#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1050617#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1050615#L1041-27 assume !(0 != activate_threads_~tmp___1~0); 1050613#L1041-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1050611#L449-27 assume 1 == ~t3_pc~0; 1050609#L450-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 1050610#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1050935#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1050600#L1049-27 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 1050598#L1049-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1050596#L468-27 assume !(1 == ~t4_pc~0); 1050594#L468-29 is_transmit4_triggered_~__retres1~4 := 0; 1050592#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1050591#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1050590#L1057-27 assume !(0 != activate_threads_~tmp___3~0); 1050589#L1057-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1050587#L487-27 assume !(1 == ~t5_pc~0); 1050584#L487-29 is_transmit5_triggered_~__retres1~5 := 0; 1050583#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1050582#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1050580#L1065-27 assume !(0 != activate_threads_~tmp___4~0); 1050577#L1065-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1050575#L506-27 assume !(1 == ~t6_pc~0); 1050573#L506-29 is_transmit6_triggered_~__retres1~6 := 0; 1050572#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1050571#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1050569#L1073-27 assume !(0 != activate_threads_~tmp___5~0); 1050568#L1073-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1050567#L525-27 assume !(1 == ~t7_pc~0); 1050564#L525-29 is_transmit7_triggered_~__retres1~7 := 0; 1050562#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1050561#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1050560#L1081-27 assume !(0 != activate_threads_~tmp___6~0); 1050558#L1081-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1050554#L544-27 assume !(1 == ~t8_pc~0); 1050552#L544-29 is_transmit8_triggered_~__retres1~8 := 0; 1050550#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1050548#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1050544#L1089-27 assume !(0 != activate_threads_~tmp___7~0); 1050542#L1089-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1050540#L921-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1050538#L921-5 assume !(1 == ~T1_E~0); 1050536#L926-3 assume !(1 == ~T2_E~0); 1050534#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1050532#L936-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1050530#L941-3 assume !(1 == ~T5_E~0); 1050528#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1050526#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1050524#L956-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1050522#L961-3 assume !(1 == ~E_1~0); 1050520#L966-3 assume !(1 == ~E_2~0); 1050518#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1050516#L976-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1050513#L981-3 assume !(1 == ~E_5~0); 1050511#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1050509#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1050506#L996-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1050504#L1001-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1050501#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 1050499#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1050497#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 1050494#L1281 assume !(0 == start_simulation_~tmp~3); 1050491#L1281-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1050488#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 1050485#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1050483#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 1050481#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1050479#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 1050477#L1244 start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 1050475#L1294 assume !(0 != start_simulation_~tmp___0~1); 1028729#L1262-3 [2018-11-18 14:32:44,192 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:44,192 INFO L82 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 12 times [2018-11-18 14:32:44,192 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:44,193 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:44,193 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:44,193 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:44,193 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:44,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:32:44,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:32:44,214 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:44,214 INFO L82 PathProgramCache]: Analyzing trace with hash 418440334, now seen corresponding path program 1 times [2018-11-18 14:32:44,214 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:44,214 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:44,215 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:44,215 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 14:32:44,215 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:44,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:32:44,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:32:44,249 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:44,250 INFO L82 PathProgramCache]: Analyzing trace with hash -1943751412, now seen corresponding path program 1 times [2018-11-18 14:32:44,250 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:44,250 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:44,250 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:44,250 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:44,251 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:44,255 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:44,295 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:44,295 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:44,295 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:32:44,919 WARN L180 SmtUtils]: Spent 615.00 ms on a formula simplification. DAG size of input: 258 DAG size of output: 237 [2018-11-18 14:32:45,127 WARN L180 SmtUtils]: Spent 198.00 ms on a formula simplification that was a NOOP. DAG size: 207 [2018-11-18 14:32:45,137 INFO L216 LassoAnalysis]: Preferences: [2018-11-18 14:32:45,138 INFO L124 ssoRankerPreferences]: Compute integeral hull: false [2018-11-18 14:32:45,138 INFO L125 ssoRankerPreferences]: Enable LassoPartitioneer: true [2018-11-18 14:32:45,138 INFO L126 ssoRankerPreferences]: Term annotations enabled: false [2018-11-18 14:32:45,138 INFO L127 ssoRankerPreferences]: Use exernal solver: true [2018-11-18 14:32:45,139 INFO L128 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 14:32:45,139 INFO L129 ssoRankerPreferences]: Dump SMT script to file: false [2018-11-18 14:32:45,139 INFO L130 ssoRankerPreferences]: Path of dumped script: [2018-11-18 14:32:45,139 INFO L131 ssoRankerPreferences]: Filename of dumped script: transmitter.08_false-unreach-call_false-termination.cil.c_Iteration32_Loop [2018-11-18 14:32:45,139 INFO L132 ssoRankerPreferences]: MapElimAlgo: Frank [2018-11-18 14:32:45,139 INFO L282 LassoAnalysis]: Starting lasso preprocessing... [2018-11-18 14:32:45,160 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,167 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,175 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,184 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,186 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,189 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,196 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,199 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,202 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,205 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,208 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,211 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,214 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,217 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,221 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,229 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,232 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,234 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,238 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,241 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,246 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,249 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,253 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,255 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,257 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,260 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,265 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,268 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,269 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,272 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,275 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,277 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,280 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,281 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,283 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,284 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,287 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,289 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,291 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,292 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,294 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,296 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,302 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,306 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,309 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,312 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,314 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,315 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,317 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,320 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,321 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,323 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,326 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,327 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,328 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,331 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,335 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,337 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,339 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,339 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,340 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,341 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,344 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,345 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,346 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,347 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,350 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,351 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,355 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,356 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,356 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,359 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,360 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,363 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,366 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,367 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,370 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,370 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,372 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,373 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,376 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,380 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,382 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:45,819 INFO L300 LassoAnalysis]: Preprocessing complete. [2018-11-18 14:32:45,820 INFO L412 LassoAnalysis]: Checking for nontermination... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a1d43ee8-d7c4-46fe-b4be-e0cabd484ca0/bin-2019/uautomizer/z3 Starting monitored process 2 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 14:32:45,832 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-18 14:32:45,832 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-18 14:32:45,852 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-18 14:32:45,852 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_7~0=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_7~0=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a1d43ee8-d7c4-46fe-b4be-e0cabd484ca0/bin-2019/uautomizer/z3 Starting monitored process 3 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 14:32:45,930 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-18 14:32:45,930 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-18 14:32:45,934 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-18 14:32:45,934 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t4_st~0=-1} Honda state: {~t4_st~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a1d43ee8-d7c4-46fe-b4be-e0cabd484ca0/bin-2019/uautomizer/z3 Starting monitored process 4 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 14:32:45,950 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-18 14:32:45,950 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-18 14:32:45,954 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-18 14:32:45,954 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_stop_simulation_~__retres2~0=0, ULTIMATE.start_start_simulation_~tmp___0~1=0, ULTIMATE.start_stop_simulation_#res=0} Honda state: {ULTIMATE.start_stop_simulation_~__retres2~0=0, ULTIMATE.start_start_simulation_~tmp___0~1=0, ULTIMATE.start_stop_simulation_#res=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a1d43ee8-d7c4-46fe-b4be-e0cabd484ca0/bin-2019/uautomizer/z3 Starting monitored process 5 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 14:32:45,986 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-18 14:32:45,987 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-18 14:32:45,990 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-18 14:32:45,990 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t8_st~0=7} Honda state: {~t8_st~0=7} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a1d43ee8-d7c4-46fe-b4be-e0cabd484ca0/bin-2019/uautomizer/z3 Starting monitored process 6 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 14:32:46,024 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-18 14:32:46,024 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-18 14:32:46,030 INFO L445 LassoAnalysis]: Proved nontermination for one component. [2018-11-18 14:32:46,030 INFO L448 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_stop_simulation_#t~ret19=0} Honda state: {ULTIMATE.start_stop_simulation_#t~ret19=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a1d43ee8-d7c4-46fe-b4be-e0cabd484ca0/bin-2019/uautomizer/z3 Starting monitored process 7 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 14:32:46,049 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2018-11-18 14:32:46,050 INFO L163 nArgumentSynthesizer]: Using integer mode. No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a1d43ee8-d7c4-46fe-b4be-e0cabd484ca0/bin-2019/uautomizer/z3 Starting monitored process 8 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 14:32:46,079 INFO L151 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2018-11-18 14:32:46,079 INFO L163 nArgumentSynthesizer]: Using integer mode. [2018-11-18 14:32:46,081 INFO L452 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2018-11-18 14:32:46,096 INFO L216 LassoAnalysis]: Preferences: [2018-11-18 14:32:46,096 INFO L124 ssoRankerPreferences]: Compute integeral hull: false [2018-11-18 14:32:46,096 INFO L125 ssoRankerPreferences]: Enable LassoPartitioneer: true [2018-11-18 14:32:46,096 INFO L126 ssoRankerPreferences]: Term annotations enabled: false [2018-11-18 14:32:46,096 INFO L127 ssoRankerPreferences]: Use exernal solver: false [2018-11-18 14:32:46,096 INFO L128 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2018-11-18 14:32:46,096 INFO L129 ssoRankerPreferences]: Dump SMT script to file: false [2018-11-18 14:32:46,096 INFO L130 ssoRankerPreferences]: Path of dumped script: [2018-11-18 14:32:46,096 INFO L131 ssoRankerPreferences]: Filename of dumped script: transmitter.08_false-unreach-call_false-termination.cil.c_Iteration32_Loop [2018-11-18 14:32:46,096 INFO L132 ssoRankerPreferences]: MapElimAlgo: Frank [2018-11-18 14:32:46,096 INFO L282 LassoAnalysis]: Starting lasso preprocessing... [2018-11-18 14:32:46,100 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,110 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,114 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,119 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,123 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,138 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,141 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,145 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,147 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,150 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,153 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,154 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,166 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,176 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,178 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,179 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,181 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,184 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,186 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,190 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,193 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,194 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,195 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,214 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,218 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,219 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,221 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,222 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,229 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,233 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,240 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,244 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,245 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,250 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,253 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,256 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,257 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,258 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,259 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,263 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,266 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,268 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,269 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,273 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,274 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,276 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,284 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,288 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,294 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,297 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,304 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,307 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,311 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,312 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,313 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,316 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,317 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,320 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,322 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,323 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,324 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,326 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,329 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,330 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,332 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,333 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,338 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,341 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,343 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,344 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,345 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,348 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,350 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,354 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,358 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,363 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,367 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,373 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,379 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,382 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,386 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,392 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,396 INFO L141 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2018-11-18 14:32:46,834 INFO L300 LassoAnalysis]: Preprocessing complete. [2018-11-18 14:32:46,838 INFO L497 LassoAnalysis]: Using template 'affine'. [2018-11-18 14:32:46,839 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-18 14:32:46,841 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-18 14:32:46,841 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-18 14:32:46,841 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-18 14:32:46,841 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-18 14:32:46,842 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-18 14:32:46,843 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-18 14:32:46,843 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-18 14:32:46,846 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-18 14:32:46,846 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-18 14:32:46,846 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-18 14:32:46,846 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-18 14:32:46,847 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-18 14:32:46,847 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-18 14:32:46,847 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-18 14:32:46,847 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-18 14:32:46,847 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-18 14:32:46,848 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-18 14:32:46,848 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-18 14:32:46,848 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-18 14:32:46,848 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-18 14:32:46,849 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-18 14:32:46,849 INFO L206 nArgumentSynthesizer]: 2 loop disjuncts [2018-11-18 14:32:46,849 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-18 14:32:46,849 INFO L402 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2018-11-18 14:32:46,849 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-18 14:32:46,850 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-18 14:32:46,850 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-18 14:32:46,851 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-18 14:32:46,851 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-18 14:32:46,851 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-18 14:32:46,851 INFO L206 nArgumentSynthesizer]: 2 loop disjuncts [2018-11-18 14:32:46,853 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-18 14:32:46,854 INFO L402 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2018-11-18 14:32:46,854 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-18 14:32:46,854 INFO L530 LassoAnalysis]: Proving termination failed for this template and these settings. [2018-11-18 14:32:46,855 INFO L122 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSES Number of strict supporting invariants: 0 Number of non-strict supporting invariants: 1 Consider only non-deceasing supporting invariants: true Simplify termination arguments: true Simplify supporting invariants: trueOverapproximate stem: false [2018-11-18 14:32:46,855 INFO L339 nArgumentSynthesizer]: Template has degree 0. [2018-11-18 14:32:46,855 INFO L352 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2018-11-18 14:32:46,855 INFO L205 nArgumentSynthesizer]: 1 stem disjuncts [2018-11-18 14:32:46,855 INFO L206 nArgumentSynthesizer]: 1 loop disjuncts [2018-11-18 14:32:46,855 INFO L207 nArgumentSynthesizer]: 2 template conjuncts. [2018-11-18 14:32:46,856 INFO L402 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2018-11-18 14:32:46,856 INFO L403 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2018-11-18 14:32:46,858 INFO L421 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2018-11-18 14:32:46,860 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2018-11-18 14:32:46,860 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2018-11-18 14:32:46,862 INFO L437 nArgumentSynthesizer]: Simplifying supporting invariants... [2018-11-18 14:32:46,862 INFO L440 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2018-11-18 14:32:46,862 INFO L518 LassoAnalysis]: Proved termination. [2018-11-18 14:32:46,863 INFO L520 LassoAnalysis]: Termination argument consisting of: Ranking function f(~M_E~0) = -1*~M_E~0 + 1 Supporting invariants [] [2018-11-18 14:32:46,863 INFO L297 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2018-11-18 14:32:46,900 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:46,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:46,962 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 14:32:47,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:47,011 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-18 14:32:47,077 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:47,083 INFO L152 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2018-11-18 14:32:47,084 INFO L72 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 44661 states and 57239 transitions. cyclomatic complexity: 12610 Second operand 5 states. [2018-11-18 14:32:47,758 INFO L76 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 44661 states and 57239 transitions. cyclomatic complexity: 12610. Second operand 5 states. Result 122231 states and 156378 transitions. Complement of second has 5 states. [2018-11-18 14:32:47,759 INFO L142 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2018-11-18 14:32:47,759 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 5 states. [2018-11-18 14:32:47,761 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 1166 transitions. [2018-11-18 14:32:47,762 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1166 transitions. Stem has 104 letters. Loop has 122 letters. [2018-11-18 14:32:47,766 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2018-11-18 14:32:47,766 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1166 transitions. Stem has 226 letters. Loop has 122 letters. [2018-11-18 14:32:47,767 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2018-11-18 14:32:47,767 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1166 transitions. Stem has 104 letters. Loop has 244 letters. [2018-11-18 14:32:47,770 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2018-11-18 14:32:47,771 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 122231 states and 156378 transitions. [2018-11-18 14:32:48,199 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 82720 [2018-11-18 14:32:48,428 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 122231 states to 122231 states and 156378 transitions. [2018-11-18 14:32:48,428 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 83350 [2018-11-18 14:32:48,480 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 83447 [2018-11-18 14:32:48,480 INFO L73 IsDeterministic]: Start isDeterministic. Operand 122231 states and 156378 transitions. [2018-11-18 14:32:48,480 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-18 14:32:48,480 INFO L705 BuchiCegarLoop]: Abstraction has 122231 states and 156378 transitions. [2018-11-18 14:32:48,538 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 122231 states and 156378 transitions. [2018-11-18 14:32:49,484 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 122231 to 122134. [2018-11-18 14:32:49,484 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 122134 states. [2018-11-18 14:32:49,615 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 122134 states to 122134 states and 156281 transitions. [2018-11-18 14:32:49,615 INFO L728 BuchiCegarLoop]: Abstraction has 122134 states and 156281 transitions. [2018-11-18 14:32:49,615 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 14:32:49,615 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 14:32:49,615 INFO L87 Difference]: Start difference. First operand 122134 states and 156281 transitions. Second operand 3 states. [2018-11-18 14:32:49,948 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:32:49,948 INFO L93 Difference]: Finished difference Result 128758 states and 163865 transitions. [2018-11-18 14:32:49,949 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 14:32:49,949 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 128758 states and 163865 transitions. [2018-11-18 14:32:50,267 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 87136 [2018-11-18 14:32:52,793 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 128758 states to 128758 states and 163865 transitions. [2018-11-18 14:32:52,793 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 87766 [2018-11-18 14:32:52,813 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 87766 [2018-11-18 14:32:52,813 INFO L73 IsDeterministic]: Start isDeterministic. Operand 128758 states and 163865 transitions. [2018-11-18 14:32:52,814 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-18 14:32:52,814 INFO L705 BuchiCegarLoop]: Abstraction has 128758 states and 163865 transitions. [2018-11-18 14:32:52,848 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 128758 states and 163865 transitions. [2018-11-18 14:32:53,357 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 128758 to 122134. [2018-11-18 14:32:53,358 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 122134 states. [2018-11-18 14:32:53,472 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 122134 states to 122134 states and 155897 transitions. [2018-11-18 14:32:53,472 INFO L728 BuchiCegarLoop]: Abstraction has 122134 states and 155897 transitions. [2018-11-18 14:32:53,472 INFO L608 BuchiCegarLoop]: Abstraction has 122134 states and 155897 transitions. [2018-11-18 14:32:53,472 INFO L442 BuchiCegarLoop]: ======== Iteration 33============ [2018-11-18 14:32:53,472 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 122134 states and 155897 transitions. [2018-11-18 14:32:53,661 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 82720 [2018-11-18 14:32:53,661 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:32:53,661 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:32:53,662 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:53,662 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:53,662 INFO L794 eck$LassoCheckResult]: Stem: 1447049#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 1446830#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1446831#L1225 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 1447853#L564 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1446903#L571 assume 1 == ~m_i~0;~m_st~0 := 0; 1446866#L571-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1446308#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1446309#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1447862#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1447339#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1446536#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1446537#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1447842#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1447634#L611-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1447635#L828 assume !(0 == ~M_E~0); 1447880#L828-2 assume !(0 == ~T1_E~0); 1447099#L833-1 assume !(0 == ~T2_E~0); 1446560#L838-1 assume !(0 == ~T3_E~0); 1446561#L843-1 assume !(0 == ~T4_E~0); 1448051#L848-1 assume !(0 == ~T5_E~0); 1447655#L853-1 assume !(0 == ~T6_E~0); 1447067#L858-1 assume !(0 == ~T7_E~0); 1446171#L863-1 assume !(0 == ~T8_E~0); 1446172#L868-1 assume !(0 == ~E_1~0); 1447535#L873-1 assume !(0 == ~E_2~0); 1447254#L878-1 assume !(0 == ~E_3~0); 1446781#L883-1 assume !(0 == ~E_4~0); 1446782#L888-1 assume !(0 == ~E_5~0); 1447775#L893-1 assume !(0 == ~E_6~0); 1447191#L898-1 assume !(0 == ~E_7~0); 1447026#L903-1 assume !(0 == ~E_8~0); 1446442#L908-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1446443#L392 assume !(1 == ~m_pc~0); 1447149#L392-2 is_master_triggered_~__retres1~0 := 0; 1447160#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1448150#L404 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1447796#L1025 assume !(0 != activate_threads_~tmp~1); 1447797#L1025-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1447508#L411 assume !(1 == ~t1_pc~0); 1447442#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 1446275#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1446276#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1446495#L1033 assume !(0 != activate_threads_~tmp___0~0); 1446919#L1033-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1446920#L430 assume !(1 == ~t2_pc~0); 1447818#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 1446621#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1446538#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1446539#L1041 assume !(0 != activate_threads_~tmp___1~0); 1448219#L1041-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1448224#L449 assume !(1 == ~t3_pc~0); 1447960#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 1448243#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1448288#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1447848#L1049 assume !(0 != activate_threads_~tmp___2~0); 1447849#L1049-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1446345#L468 assume !(1 == ~t4_pc~0); 1446346#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 1446362#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1447175#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1447038#L1057 assume !(0 != activate_threads_~tmp___3~0); 1447039#L1057-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1446753#L487 assume !(1 == ~t5_pc~0); 1446269#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 1446756#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1447486#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1447487#L1065 assume !(0 != activate_threads_~tmp___4~0); 1448257#L1065-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1447066#L506 assume !(1 == ~t6_pc~0); 1447058#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 1447059#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1447845#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1447685#L1073 assume !(0 != activate_threads_~tmp___5~0); 1447686#L1073-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1447344#L525 assume !(1 == ~t7_pc~0); 1447204#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 1447347#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1448280#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1446791#L1081 assume !(0 != activate_threads_~tmp___6~0); 1446792#L1081-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1446793#L544 assume !(1 == ~t8_pc~0); 1447381#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 1446161#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1446162#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1446408#L1089 assume !(0 != activate_threads_~tmp___7~0); 1447921#L1089-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1447078#L921 assume !(1 == ~M_E~0); 1447079#L921-2 assume !(1 == ~T1_E~0); 1446554#L926-1 assume !(1 == ~T2_E~0); 1446555#L931-1 assume !(1 == ~T3_E~0); 1448047#L936-1 assume !(1 == ~T4_E~0); 1447674#L941-1 assume !(1 == ~T5_E~0); 1447075#L946-1 assume !(1 == ~T6_E~0); 1446193#L951-1 assume !(1 == ~T7_E~0); 1446194#L956-1 assume !(1 == ~T8_E~0); 1447852#L961-1 assume !(1 == ~E_1~0); 1447268#L966-1 assume !(1 == ~E_2~0); 1446798#L971-1 assume !(1 == ~E_3~0); 1446799#L976-1 assume !(1 == ~E_4~0); 1447766#L981-1 assume !(1 == ~E_5~0); 1447188#L986-1 assume !(1 == ~E_6~0); 1447014#L991-1 assume !(1 == ~E_7~0); 1446419#L996-1 assume !(1 == ~E_8~0); 1446420#L1001-1 assume { :end_inline_reset_delta_events } true; 1448095#L1262-3 assume true; 1452119#L1262-1 [2018-11-18 14:32:53,662 INFO L796 eck$LassoCheckResult]: Loop: 1452119#L1262-1 assume !false; 1495343#L1263 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 1495341#L803 assume true; 1495337#L681-1 assume !false; 1495335#L682 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1495333#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 1495331#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1495322#L672 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 1495317#L686 assume 0 != eval_~tmp~0; 1495311#L686-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 1495304#L694 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1;assume { :begin_inline_master } true; 1495305#L73 assume !(0 == ~m_pc~0); 1495941#L76 assume 1 == ~m_pc~0; 1495938#L77 assume true; 1495936#L92-1 assume !false; 1492444#L93 ~m_pc~0 := 1;~m_st~0 := 2; 1492438#L103 assume { :end_inline_master } true; 1492433#L691 assume !(0 == ~t1_st~0); 1492428#L705 assume !(0 == ~t2_st~0); 1492424#L719 assume !(0 == ~t3_st~0); 1492417#L733 assume !(0 == ~t4_st~0); 1492415#L747 assume !(0 == ~t5_st~0); 1492411#L761 assume !(0 == ~t6_st~0); 1492410#L775 assume !(0 == ~t7_st~0); 1493304#L789 assume !(0 == ~t8_st~0); 1493299#L803 assume true; 1493297#L681-1 assume !false; 1493295#L682 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1493293#L624 assume !(0 == ~m_st~0); 1493290#L628 assume !(0 == ~t1_st~0); 1493288#L632 assume !(0 == ~t2_st~0); 1493286#L636 assume !(0 == ~t3_st~0); 1493284#L640 assume !(0 == ~t4_st~0); 1493282#L644 assume !(0 == ~t5_st~0); 1493280#L648 assume !(0 == ~t6_st~0); 1493278#L652 assume !(0 == ~t7_st~0); 1493275#L656 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9 := 0; 1493273#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1493271#L672 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 1493269#L686 assume !(0 != eval_~tmp~0); 1493267#L818 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 1493265#L564-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 1493262#L828-3 assume !(0 == ~M_E~0); 1493259#L828-5 assume !(0 == ~T1_E~0); 1493256#L833-3 assume !(0 == ~T2_E~0); 1493253#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1493251#L843-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1493249#L848-3 assume !(0 == ~T5_E~0); 1493247#L853-3 assume !(0 == ~T6_E~0); 1493245#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1493243#L863-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1493241#L868-3 assume !(0 == ~E_1~0); 1493239#L873-3 assume !(0 == ~E_2~0); 1493237#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1493235#L883-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1493233#L888-3 assume !(0 == ~E_5~0); 1493231#L893-3 assume !(0 == ~E_6~0); 1493229#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1493227#L903-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1493225#L908-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1493223#L392-27 assume 1 == ~m_pc~0; 1493220#L393-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 1493218#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1493216#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1493213#L1025-27 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 1493211#L1025-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1493209#L411-27 assume !(1 == ~t1_pc~0); 1493207#L411-29 is_transmit1_triggered_~__retres1~1 := 0; 1493205#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1493203#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1493201#L1033-27 assume !(0 != activate_threads_~tmp___0~0); 1493199#L1033-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1493190#L430-27 assume !(1 == ~t2_pc~0); 1493188#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 1493186#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1493182#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1493180#L1041-27 assume !(0 != activate_threads_~tmp___1~0); 1493178#L1041-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1493177#L449-27 assume !(1 == ~t3_pc~0); 1493174#L449-29 is_transmit3_triggered_~__retres1~3 := 0; 1493171#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1493167#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1493166#L1049-27 assume !(0 != activate_threads_~tmp___2~0); 1493134#L1049-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1493131#L468-27 assume !(1 == ~t4_pc~0); 1493129#L468-29 is_transmit4_triggered_~__retres1~4 := 0; 1493127#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1493125#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1493123#L1057-27 assume !(0 != activate_threads_~tmp___3~0); 1493121#L1057-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1493119#L487-27 assume !(1 == ~t5_pc~0); 1493116#L487-29 is_transmit5_triggered_~__retres1~5 := 0; 1493114#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1493113#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1493111#L1065-27 assume !(0 != activate_threads_~tmp___4~0); 1493109#L1065-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1493107#L506-27 assume !(1 == ~t6_pc~0); 1493103#L506-29 is_transmit6_triggered_~__retres1~6 := 0; 1493101#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1493099#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1493097#L1073-27 assume !(0 != activate_threads_~tmp___5~0); 1493095#L1073-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1493093#L525-27 assume 1 == ~t7_pc~0; 1493091#L526-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 1493092#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1493487#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1493082#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 1493080#L1081-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1493078#L544-27 assume !(1 == ~t8_pc~0); 1493075#L544-29 is_transmit8_triggered_~__retres1~8 := 0; 1493073#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1493071#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1493069#L1089-27 assume !(0 != activate_threads_~tmp___7~0); 1493067#L1089-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1493065#L921-3 assume !(1 == ~M_E~0); 1493063#L921-5 assume !(1 == ~T1_E~0); 1493061#L926-3 assume !(1 == ~T2_E~0); 1493059#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1493057#L936-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1493055#L941-3 assume !(1 == ~T5_E~0); 1493053#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1493051#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1493049#L956-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1493047#L961-3 assume !(1 == ~E_1~0); 1493045#L966-3 assume !(1 == ~E_2~0); 1493043#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1493041#L976-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1493039#L981-3 assume !(1 == ~E_5~0); 1493037#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1493035#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1493033#L996-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1493031#L1001-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1493029#L624-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 1493027#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1493024#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 1493021#L1281 assume !(0 == start_simulation_~tmp~3); 1493022#L1281-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1495443#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 1495441#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1495439#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 1495437#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 1495425#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 1495416#L1244 start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 1495408#L1294 assume !(0 != start_simulation_~tmp___0~1); 1495402#L1262-3 assume true; 1452119#L1262-1 [2018-11-18 14:32:53,663 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:53,663 INFO L82 PathProgramCache]: Analyzing trace with hash -2024511549, now seen corresponding path program 1 times [2018-11-18 14:32:53,663 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:53,663 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:53,663 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:53,664 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:53,664 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:53,669 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:32:53,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:32:53,691 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:53,691 INFO L82 PathProgramCache]: Analyzing trace with hash -1818184444, now seen corresponding path program 1 times [2018-11-18 14:32:53,692 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:53,692 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:53,692 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:53,692 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:53,692 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:53,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:53,736 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-11-18 14:32:53,736 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:53,736 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:32:53,736 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 14:32:53,737 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 14:32:53,737 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 14:32:53,737 INFO L87 Difference]: Start difference. First operand 122134 states and 155897 transitions. cyclomatic complexity: 33859 Second operand 3 states. [2018-11-18 14:32:54,235 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:32:54,235 INFO L93 Difference]: Finished difference Result 220888 states and 278798 transitions. [2018-11-18 14:32:54,238 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 14:32:54,238 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 220888 states and 278798 transitions. [2018-11-18 14:32:54,844 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 139360 [2018-11-18 14:32:55,190 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 220888 states to 215832 states and 272494 transitions. [2018-11-18 14:32:55,190 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 144168 [2018-11-18 14:32:55,247 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 144168 [2018-11-18 14:32:55,247 INFO L73 IsDeterministic]: Start isDeterministic. Operand 215832 states and 272494 transitions. [2018-11-18 14:32:55,298 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2018-11-18 14:32:55,298 INFO L705 BuchiCegarLoop]: Abstraction has 215832 states and 272494 transitions. [2018-11-18 14:32:55,373 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 215832 states and 272494 transitions. [2018-11-18 14:32:56,650 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 215832 to 215704. [2018-11-18 14:32:56,650 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 215704 states. [2018-11-18 14:32:56,838 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 215704 states to 215704 states and 272366 transitions. [2018-11-18 14:32:56,838 INFO L728 BuchiCegarLoop]: Abstraction has 215704 states and 272366 transitions. [2018-11-18 14:32:56,838 INFO L608 BuchiCegarLoop]: Abstraction has 215704 states and 272366 transitions. [2018-11-18 14:32:56,838 INFO L442 BuchiCegarLoop]: ======== Iteration 34============ [2018-11-18 14:32:56,838 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 215704 states and 272366 transitions. [2018-11-18 14:32:57,163 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 139264 [2018-11-18 14:32:57,163 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:32:57,163 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:32:57,164 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:57,164 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:57,164 INFO L794 eck$LassoCheckResult]: Stem: 1790071#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 1789856#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1789857#L1225 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 1790872#L564 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1789926#L571 assume 1 == ~m_i~0;~m_st~0 := 0; 1789891#L571-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1789337#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1789338#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1790882#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1790362#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1789563#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1789564#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1790861#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1790653#L611-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1790654#L828 assume 0 == ~M_E~0;~M_E~0 := 1; 1790899#L828-2 assume !(0 == ~T1_E~0); 1790903#L833-1 assume !(0 == ~T2_E~0); 1791313#L838-1 assume !(0 == ~T3_E~0); 1791312#L843-1 assume !(0 == ~T4_E~0); 1791076#L848-1 assume !(0 == ~T5_E~0); 1790676#L853-1 assume !(0 == ~T6_E~0); 1790677#L858-1 assume !(0 == ~T7_E~0); 1791309#L863-1 assume !(0 == ~T8_E~0); 1791012#L868-1 assume !(0 == ~E_1~0); 1790562#L873-1 assume !(0 == ~E_2~0); 1790563#L878-1 assume !(0 == ~E_3~0); 1789809#L883-1 assume !(0 == ~E_4~0); 1789810#L888-1 assume !(0 == ~E_5~0); 1790803#L893-1 assume !(0 == ~E_6~0); 1790804#L898-1 assume !(0 == ~E_7~0); 1790051#L903-1 assume !(0 == ~E_8~0); 1790052#L908-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 1790170#L392 assume !(1 == ~m_pc~0); 1790171#L392-2 is_master_triggered_~__retres1~0 := 0; 1791172#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 1791173#L404 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 1790816#L1025 assume !(0 != activate_threads_~tmp~1); 1790817#L1025-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 1790536#L411 assume !(1 == ~t1_pc~0); 1790537#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 1789307#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 1789308#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 1791324#L1033 assume !(0 != activate_threads_~tmp___0~0); 1791323#L1033-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 1790839#L430 assume !(1 == ~t2_pc~0); 1790840#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 1789653#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 1789654#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 1791226#L1041 assume !(0 != activate_threads_~tmp___1~0); 1791227#L1041-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 1791241#L449 assume !(1 == ~t3_pc~0); 1790983#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 1791319#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 1791320#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 1790867#L1049 assume !(0 != activate_threads_~tmp___2~0); 1790868#L1049-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 1789373#L468 assume !(1 == ~t4_pc~0); 1789374#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 1789389#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 1790673#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 1790061#L1057 assume !(0 != activate_threads_~tmp___3~0); 1790062#L1057-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 1789780#L487 assume !(1 == ~t5_pc~0); 1789297#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 1790887#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 1790512#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 1790513#L1065 assume !(0 != activate_threads_~tmp___4~0); 1791314#L1065-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 1790088#L506 assume !(1 == ~t6_pc~0); 1790089#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 1791106#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 1791107#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 1791310#L1073 assume !(0 != activate_threads_~tmp___5~0); 1791308#L1073-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 1790365#L525 assume !(1 == ~t7_pc~0); 1790366#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 1791306#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 1791231#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 1789819#L1081 assume !(0 != activate_threads_~tmp___6~0); 1789820#L1081-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 1790413#L544 assume !(1 == ~t8_pc~0); 1790414#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 1789189#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 1789190#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 1789436#L1089 assume !(0 != activate_threads_~tmp___7~0); 1790944#L1089-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1790105#L921 assume 1 == ~M_E~0;~M_E~0 := 2; 1790106#L921-2 assume !(1 == ~T1_E~0); 1789581#L926-1 assume !(1 == ~T2_E~0); 1789582#L931-1 assume !(1 == ~T3_E~0); 1791073#L936-1 assume !(1 == ~T4_E~0); 1790700#L941-1 assume !(1 == ~T5_E~0); 1790098#L946-1 assume !(1 == ~T6_E~0); 1789221#L951-1 assume !(1 == ~T7_E~0); 1789222#L956-1 assume !(1 == ~T8_E~0); 1790871#L961-1 assume !(1 == ~E_1~0); 1790294#L966-1 assume !(1 == ~E_2~0); 1789827#L971-1 assume !(1 == ~E_3~0); 1789828#L976-1 assume !(1 == ~E_4~0); 1790792#L981-1 assume !(1 == ~E_5~0); 1790211#L986-1 assume !(1 == ~E_6~0); 1790037#L991-1 assume !(1 == ~E_7~0); 1789451#L996-1 assume !(1 == ~E_8~0); 1789452#L1001-1 assume { :end_inline_reset_delta_events } true; 1791122#L1262-3 assume true; 1795726#L1262-1 assume !false; 1876212#L1263 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 1876210#L803 [2018-11-18 14:32:57,164 INFO L796 eck$LassoCheckResult]: Loop: 1876210#L803 assume true; 1876208#L681-1 assume !false; 1876205#L682 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 1876203#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 1876201#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 1876198#L672 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 1876196#L686 assume 0 != eval_~tmp~0; 1876194#L686-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 1876190#L694 assume !(0 != eval_~tmp_ndt_1~0); 1876185#L691 assume !(0 == ~t1_st~0); 1876183#L705 assume !(0 == ~t2_st~0); 1876181#L719 assume !(0 == ~t3_st~0); 1876342#L733 assume !(0 == ~t4_st~0); 1876340#L747 assume !(0 == ~t5_st~0); 1876335#L761 assume !(0 == ~t6_st~0); 1876217#L775 assume !(0 == ~t7_st~0); 1876215#L789 assume !(0 == ~t8_st~0); 1876210#L803 [2018-11-18 14:32:57,164 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:57,164 INFO L82 PathProgramCache]: Analyzing trace with hash 525409281, now seen corresponding path program 1 times [2018-11-18 14:32:57,164 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:57,165 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:57,165 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:57,165 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:57,165 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:57,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:57,207 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:57,207 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:57,207 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 14:32:57,207 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 14:32:57,207 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:57,207 INFO L82 PathProgramCache]: Analyzing trace with hash 1871721886, now seen corresponding path program 1 times [2018-11-18 14:32:57,208 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:57,208 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:57,208 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:57,208 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:57,208 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:57,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:32:57,217 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:32:57,297 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 14:32:57,297 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 14:32:57,297 INFO L87 Difference]: Start difference. First operand 215704 states and 272366 transitions. cyclomatic complexity: 56822 Second operand 3 states. [2018-11-18 14:32:57,543 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:32:57,543 INFO L93 Difference]: Finished difference Result 109351 states and 137990 transitions. [2018-11-18 14:32:57,543 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 14:32:57,543 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 109351 states and 137990 transitions. [2018-11-18 14:32:57,747 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 71680 [2018-11-18 14:32:57,845 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 109351 states to 74901 states and 94547 transitions. [2018-11-18 14:32:57,845 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 74901 [2018-11-18 14:32:57,871 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 74901 [2018-11-18 14:32:57,871 INFO L73 IsDeterministic]: Start isDeterministic. Operand 74901 states and 94547 transitions. [2018-11-18 14:32:57,892 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:32:57,892 INFO L705 BuchiCegarLoop]: Abstraction has 74901 states and 94547 transitions. [2018-11-18 14:32:57,919 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74901 states and 94547 transitions. [2018-11-18 14:32:58,134 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74901 to 40450. [2018-11-18 14:32:58,134 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 40450 states. [2018-11-18 14:32:58,165 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40450 states to 40450 states and 51072 transitions. [2018-11-18 14:32:58,165 INFO L728 BuchiCegarLoop]: Abstraction has 40450 states and 51072 transitions. [2018-11-18 14:32:58,165 INFO L608 BuchiCegarLoop]: Abstraction has 40450 states and 51072 transitions. [2018-11-18 14:32:58,165 INFO L442 BuchiCegarLoop]: ======== Iteration 35============ [2018-11-18 14:32:58,165 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 40450 states and 51072 transitions. [2018-11-18 14:32:58,228 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 40080 [2018-11-18 14:32:58,228 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:32:58,228 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:32:58,229 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:58,229 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:58,229 INFO L794 eck$LassoCheckResult]: Stem: 2114744#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 2114630#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 2114631#L1225 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 2115154#L564 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2114667#L571 assume 1 == ~m_i~0;~m_st~0 := 0; 2114648#L571-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2114334#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2114335#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2115157#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2114884#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2114456#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2114457#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2115145#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2115028#L611-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2115029#L828 assume !(0 == ~M_E~0); 2115165#L828-2 assume !(0 == ~T1_E~0); 2114771#L833-1 assume !(0 == ~T2_E~0); 2114471#L838-1 assume !(0 == ~T3_E~0); 2114472#L843-1 assume !(0 == ~T4_E~0); 2115255#L848-1 assume !(0 == ~T5_E~0); 2115043#L853-1 assume !(0 == ~T6_E~0); 2114754#L858-1 assume !(0 == ~T7_E~0); 2114256#L863-1 assume !(0 == ~T8_E~0); 2114257#L868-1 assume !(0 == ~E_1~0); 2114981#L873-1 assume !(0 == ~E_2~0); 2114852#L878-1 assume !(0 == ~E_3~0); 2114594#L883-1 assume !(0 == ~E_4~0); 2114595#L888-1 assume !(0 == ~E_5~0); 2115115#L893-1 assume !(0 == ~E_6~0); 2114815#L898-1 assume !(0 == ~E_7~0); 2114733#L903-1 assume !(0 == ~E_8~0); 2114406#L908-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2114407#L392 assume !(1 == ~m_pc~0); 2114794#L392-2 is_master_triggered_~__retres1~0 := 0; 2114800#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2115307#L404 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2115122#L1025 assume !(0 != activate_threads_~tmp~1); 2115123#L1025-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2114969#L411 assume !(1 == ~t1_pc~0); 2114938#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 2114319#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2114320#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2114438#L1033 assume !(0 != activate_threads_~tmp___0~0); 2114675#L1033-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2114676#L430 assume !(1 == ~t2_pc~0); 2115135#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 2114511#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2114458#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2114459#L1041 assume !(0 != activate_threads_~tmp___1~0); 2115342#L1041-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2115343#L449 assume !(1 == ~t3_pc~0); 2115211#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 2115353#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2115366#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2115150#L1049 assume !(0 != activate_threads_~tmp___2~0); 2115151#L1049-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2114354#L468 assume !(1 == ~t4_pc~0); 2114355#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 2114364#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2114807#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2114738#L1057 assume !(0 != activate_threads_~tmp___3~0); 2114739#L1057-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2114579#L487 assume !(1 == ~t5_pc~0); 2114312#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 2114581#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2114957#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2114958#L1065 assume !(0 != activate_threads_~tmp___4~0); 2115359#L1065-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2114753#L506 assume !(1 == ~t6_pc~0); 2114749#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 2114750#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2115147#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2115060#L1073 assume !(0 != activate_threads_~tmp___5~0); 2115061#L1073-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 2114886#L525 assume !(1 == ~t7_pc~0); 2114826#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 2114888#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 2115367#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2114600#L1081 assume !(0 != activate_threads_~tmp___6~0); 2114601#L1081-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 2114602#L544 assume !(1 == ~t8_pc~0); 2114906#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 2114250#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 2114251#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2114387#L1089 assume !(0 != activate_threads_~tmp___7~0); 2115190#L1089-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2114761#L921 assume !(1 == ~M_E~0); 2114762#L921-2 assume !(1 == ~T1_E~0); 2114467#L926-1 assume !(1 == ~T2_E~0); 2114468#L931-1 assume !(1 == ~T3_E~0); 2115253#L936-1 assume !(1 == ~T4_E~0); 2115050#L941-1 assume !(1 == ~T5_E~0); 2114759#L946-1 assume !(1 == ~T6_E~0); 2114268#L951-1 assume !(1 == ~T7_E~0); 2114269#L956-1 assume !(1 == ~T8_E~0); 2115153#L961-1 assume !(1 == ~E_1~0); 2114859#L966-1 assume !(1 == ~E_2~0); 2114606#L971-1 assume !(1 == ~E_3~0); 2114607#L976-1 assume !(1 == ~E_4~0); 2115110#L981-1 assume !(1 == ~E_5~0); 2114813#L986-1 assume !(1 == ~E_6~0); 2114726#L991-1 assume !(1 == ~E_7~0); 2114396#L996-1 assume !(1 == ~E_8~0); 2114397#L1001-1 assume { :end_inline_reset_delta_events } true; 2115272#L1262-3 [2018-11-18 14:32:58,229 INFO L796 eck$LassoCheckResult]: Loop: 2115272#L1262-3 assume true; 2121509#L1262-1 assume !false; 2121341#L1263 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 2121340#L803 assume true; 2121339#L681-1 assume !false; 2121338#L682 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 2121336#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 2121335#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 2121334#L672 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 2121332#L686 assume 0 != eval_~tmp~0; 2121331#L686-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 2121329#L694 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1;assume { :begin_inline_master } true; 2121328#L73 assume !(0 == ~m_pc~0); 2121174#L76 assume 1 == ~m_pc~0; 2121172#L77 assume true; 2121168#L92-1 assume !false; 2121166#L93 ~m_pc~0 := 1;~m_st~0 := 2; 2120338#L103 assume { :end_inline_master } true; 2120336#L691 assume !(0 == ~t1_st~0); 2120335#L705 assume !(0 == ~t2_st~0); 2124661#L719 assume !(0 == ~t3_st~0); 2124654#L733 assume !(0 == ~t4_st~0); 2124652#L747 assume !(0 == ~t5_st~0); 2124646#L761 assume !(0 == ~t6_st~0); 2124619#L775 assume !(0 == ~t7_st~0); 2124617#L789 assume !(0 == ~t8_st~0); 2124615#L803 assume true; 2125541#L681-1 assume !false; 2125536#L682 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 2121971#L624 assume !(0 == ~m_st~0); 2120357#L628 assume !(0 == ~t1_st~0); 2120353#L632 assume !(0 == ~t2_st~0); 2120354#L636 assume !(0 == ~t3_st~0); 2120356#L640 assume !(0 == ~t4_st~0); 2120351#L644 assume !(0 == ~t5_st~0); 2120352#L648 assume !(0 == ~t6_st~0); 2120355#L652 assume !(0 == ~t7_st~0); 2120349#L656 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9 := 0; 2120350#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 2121207#L672 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 2120341#L686 assume !(0 != eval_~tmp~0); 2120342#L818 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 2125817#L564-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 2125815#L828-3 assume !(0 == ~M_E~0); 2122077#L828-5 assume !(0 == ~T1_E~0); 2122075#L833-3 assume !(0 == ~T2_E~0); 2122073#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2122071#L843-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2122069#L848-3 assume !(0 == ~T5_E~0); 2122067#L853-3 assume !(0 == ~T6_E~0); 2122065#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2122063#L863-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2121785#L868-3 assume !(0 == ~E_1~0); 2121783#L873-3 assume !(0 == ~E_2~0); 2121781#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2121779#L883-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2121777#L888-3 assume !(0 == ~E_5~0); 2121775#L893-3 assume !(0 == ~E_6~0); 2121773#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2121771#L903-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2121769#L908-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2121767#L392-27 assume !(1 == ~m_pc~0); 2121764#L392-29 is_master_triggered_~__retres1~0 := 0; 2121762#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2121760#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2121758#L1025-27 assume !(0 != activate_threads_~tmp~1); 2121754#L1025-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2121752#L411-27 assume !(1 == ~t1_pc~0); 2121750#L411-29 is_transmit1_triggered_~__retres1~1 := 0; 2121748#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2121745#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2121743#L1033-27 assume !(0 != activate_threads_~tmp___0~0); 2121741#L1033-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2121739#L430-27 assume !(1 == ~t2_pc~0); 2121737#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 2121735#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2121733#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2121731#L1041-27 assume !(0 != activate_threads_~tmp___1~0); 2121728#L1041-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2121726#L449-27 assume !(1 == ~t3_pc~0); 2121722#L449-29 is_transmit3_triggered_~__retres1~3 := 0; 2121720#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2121718#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2121716#L1049-27 assume !(0 != activate_threads_~tmp___2~0); 2121713#L1049-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2121711#L468-27 assume !(1 == ~t4_pc~0); 2121709#L468-29 is_transmit4_triggered_~__retres1~4 := 0; 2121707#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2121705#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2121703#L1057-27 assume !(0 != activate_threads_~tmp___3~0); 2121699#L1057-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2121697#L487-27 assume !(1 == ~t5_pc~0); 2121694#L487-29 is_transmit5_triggered_~__retres1~5 := 0; 2121692#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2121689#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2121687#L1065-27 assume !(0 != activate_threads_~tmp___4~0); 2121685#L1065-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2121683#L506-27 assume !(1 == ~t6_pc~0); 2121681#L506-29 is_transmit6_triggered_~__retres1~6 := 0; 2121679#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2121677#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2121675#L1073-27 assume !(0 != activate_threads_~tmp___5~0); 2121674#L1073-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 2121673#L525-27 assume !(1 == ~t7_pc~0); 2121671#L525-29 is_transmit7_triggered_~__retres1~7 := 0; 2121669#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 2121667#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2121666#L1081-27 assume !(0 != activate_threads_~tmp___6~0); 2121664#L1081-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 2121661#L544-27 assume !(1 == ~t8_pc~0); 2121659#L544-29 is_transmit8_triggered_~__retres1~8 := 0; 2121657#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 2121655#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2121653#L1089-27 assume !(0 != activate_threads_~tmp___7~0); 2121651#L1089-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2121650#L921-3 assume !(1 == ~M_E~0); 2121647#L921-5 assume !(1 == ~T1_E~0); 2121645#L926-3 assume !(1 == ~T2_E~0); 2121643#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2121641#L936-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2121639#L941-3 assume !(1 == ~T5_E~0); 2121637#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2121636#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2121635#L956-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2121634#L961-3 assume !(1 == ~E_1~0); 2121633#L966-3 assume !(1 == ~E_2~0); 2121632#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2121631#L976-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2121630#L981-3 assume !(1 == ~E_5~0); 2121629#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2121628#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2121627#L996-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2121624#L1001-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 2121622#L624-1 assume !(0 == ~m_st~0); 2121620#L628-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~9 := 1; 2121611#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 2121609#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 2121606#L1281 assume 0 == start_simulation_~tmp~3;start_simulation_~kernel_st~0 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 2121605#L1115 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2121603#L392-30 assume 1 == ~m_pc~0; 2121602#L393-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 2121601#L403-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2121600#L404-10 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2121598#L1025-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2121597#L1025-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2121596#L411-30 assume !(1 == ~t1_pc~0); 2121595#L411-32 is_transmit1_triggered_~__retres1~1 := 0; 2121594#L422-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2121593#L423-10 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2121592#L1033-30 assume !(0 != activate_threads_~tmp___0~0); 2121591#L1033-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2121590#L430-30 assume !(1 == ~t2_pc~0); 2121589#L430-32 is_transmit2_triggered_~__retres1~2 := 0; 2121588#L441-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2121587#L442-10 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2121586#L1041-30 assume !(0 != activate_threads_~tmp___1~0); 2121585#L1041-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2121584#L449-30 assume 1 == ~t3_pc~0; 2121582#L450-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3 := 1; 2121580#L460-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2121578#L461-10 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2121576#L1049-30 assume 0 != activate_threads_~tmp___2~0;~t3_st~0 := 0; 2121575#L1049-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2121574#L468-30 assume !(1 == ~t4_pc~0); 2121573#L468-32 is_transmit4_triggered_~__retres1~4 := 0; 2121572#L479-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2121571#L480-10 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2121570#L1057-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 2121569#L1057-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2121568#L487-30 assume !(1 == ~t5_pc~0); 2121566#L487-32 is_transmit5_triggered_~__retres1~5 := 0; 2121565#L498-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2121564#L499-10 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2121563#L1065-30 assume !(0 != activate_threads_~tmp___4~0); 2121562#L1065-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2121561#L506-30 assume !(1 == ~t6_pc~0); 2121560#L506-32 is_transmit6_triggered_~__retres1~6 := 0; 2121559#L517-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2121558#L518-10 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2121557#L1073-30 assume !(0 != activate_threads_~tmp___5~0); 2121556#L1073-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 2121555#L525-30 assume 1 == ~t7_pc~0; 2121553#L526-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 2121551#L536-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 2121549#L537-10 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2121547#L1081-30 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 2121546#L1081-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 2121545#L544-30 assume !(1 == ~t8_pc~0); 2121544#L544-32 is_transmit8_triggered_~__retres1~8 := 0; 2121543#L555-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 2121542#L556-10 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2121541#L1089-30 assume !(0 != activate_threads_~tmp___7~0); 2121540#L1089-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 2121539#L1122 assume 1 == ~M_E~0;~M_E~0 := 2; 2121538#L1122-2 assume !(1 == ~T1_E~0); 2121537#L1127-1 assume !(1 == ~T2_E~0); 2121536#L1132-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2121535#L1137-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2121534#L1142-1 assume !(1 == ~T5_E~0); 2121533#L1147-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2121532#L1152-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2121531#L1157-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2121530#L1162-1 assume !(1 == ~E_1~0); 2121529#L1167-1 assume !(1 == ~E_2~0); 2121528#L1172-1 assume 1 == ~E_3~0;~E_3~0 := 2; 2121527#L1177-1 assume 1 == ~E_4~0;~E_4~0 := 2; 2121526#L1182-1 assume !(1 == ~E_5~0); 2121525#L1187-1 assume 1 == ~E_6~0;~E_6~0 := 2; 2121524#L1192-1 assume 1 == ~E_7~0;~E_7~0 := 2; 2121523#L1197-1 assume 1 == ~E_8~0;~E_8~0 := 2; 2121522#L1202-1 assume { :end_inline_reset_time_events } true; 2121521#L1281-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 2121520#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 2121519#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 2121518#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 2121517#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2121516#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 2121515#L1244 start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 2121514#L1294 assume !(0 != start_simulation_~tmp___0~1); 2115272#L1262-3 [2018-11-18 14:32:58,229 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:58,230 INFO L82 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 13 times [2018-11-18 14:32:58,230 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:58,230 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:58,230 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:58,230 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:58,230 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:58,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:32:58,242 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:32:58,256 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:58,257 INFO L82 PathProgramCache]: Analyzing trace with hash 1077357871, now seen corresponding path program 1 times [2018-11-18 14:32:58,257 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:58,257 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:58,257 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:58,257 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:58,258 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:58,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:58,309 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:58,310 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:58,310 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:32:58,310 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 14:32:58,310 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 14:32:58,310 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 14:32:58,310 INFO L87 Difference]: Start difference. First operand 40450 states and 51072 transitions. cyclomatic complexity: 10654 Second operand 3 states. [2018-11-18 14:32:58,422 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:32:58,422 INFO L93 Difference]: Finished difference Result 56197 states and 70181 transitions. [2018-11-18 14:32:58,422 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 14:32:58,422 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 56197 states and 70181 transitions. [2018-11-18 14:32:58,536 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 50816 [2018-11-18 14:32:58,623 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 56197 states to 56197 states and 70181 transitions. [2018-11-18 14:32:58,623 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 56197 [2018-11-18 14:32:58,643 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 56197 [2018-11-18 14:32:58,644 INFO L73 IsDeterministic]: Start isDeterministic. Operand 56197 states and 70181 transitions. [2018-11-18 14:32:58,662 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:32:58,662 INFO L705 BuchiCegarLoop]: Abstraction has 56197 states and 70181 transitions. [2018-11-18 14:32:58,680 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 56197 states and 70181 transitions. [2018-11-18 14:32:58,885 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 56197 to 53861. [2018-11-18 14:32:58,886 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 53861 states. [2018-11-18 14:32:58,931 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53861 states to 53861 states and 67397 transitions. [2018-11-18 14:32:58,931 INFO L728 BuchiCegarLoop]: Abstraction has 53861 states and 67397 transitions. [2018-11-18 14:32:58,931 INFO L608 BuchiCegarLoop]: Abstraction has 53861 states and 67397 transitions. [2018-11-18 14:32:58,931 INFO L442 BuchiCegarLoop]: ======== Iteration 36============ [2018-11-18 14:32:58,932 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 53861 states and 67397 transitions. [2018-11-18 14:32:59,018 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 50816 [2018-11-18 14:32:59,018 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:32:59,018 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:32:59,019 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:59,019 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:32:59,019 INFO L794 eck$LassoCheckResult]: Stem: 2211393#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 2211276#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 2211277#L1225 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 2211805#L564 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2211315#L571 assume 1 == ~m_i~0;~m_st~0 := 0; 2211296#L571-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2210987#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2210988#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2211812#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2211540#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2211111#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2211112#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2211797#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2211682#L611-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2211683#L828 assume !(0 == ~M_E~0); 2211819#L828-2 assume !(0 == ~T1_E~0); 2211420#L833-1 assume !(0 == ~T2_E~0); 2211126#L838-1 assume !(0 == ~T3_E~0); 2211127#L843-1 assume !(0 == ~T4_E~0); 2211912#L848-1 assume !(0 == ~T5_E~0); 2211694#L853-1 assume !(0 == ~T6_E~0); 2211404#L858-1 assume !(0 == ~T7_E~0); 2210909#L863-1 assume !(0 == ~T8_E~0); 2210910#L868-1 assume !(0 == ~E_1~0); 2211636#L873-1 assume !(0 == ~E_2~0); 2211506#L878-1 assume !(0 == ~E_3~0); 2211245#L883-1 assume !(0 == ~E_4~0); 2211246#L888-1 assume !(0 == ~E_5~0); 2211767#L893-1 assume !(0 == ~E_6~0); 2211470#L898-1 assume !(0 == ~E_7~0); 2211379#L903-1 assume !(0 == ~E_8~0); 2211058#L908-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2211059#L392 assume 1 == ~m_pc~0; 2211447#L393 assume !(1 == ~M_E~0); 2211453#L392-2 is_master_triggered_~__retres1~0 := 0; 2211454#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2211965#L404 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2211776#L1025 assume !(0 != activate_threads_~tmp~1); 2211777#L1025-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2211624#L411 assume !(1 == ~t1_pc~0); 2211592#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 2210969#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2210970#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2211090#L1033 assume !(0 != activate_threads_~tmp___0~0); 2211323#L1033-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2211324#L430 assume !(1 == ~t2_pc~0); 2211787#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 2211162#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2211113#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2211114#L1041 assume !(0 != activate_threads_~tmp___1~0); 2211992#L1041-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2211993#L449 assume !(1 == ~t3_pc~0); 2211860#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 2212004#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2212018#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2211802#L1049 assume !(0 != activate_threads_~tmp___2~0); 2211803#L1049-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2211007#L468 assume !(1 == ~t4_pc~0); 2211008#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 2211016#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2211461#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2211387#L1057 assume !(0 != activate_threads_~tmp___3~0); 2211388#L1057-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2211230#L487 assume !(1 == ~t5_pc~0); 2210964#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 2211232#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2211612#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2211613#L1065 assume !(0 != activate_threads_~tmp___4~0); 2212010#L1065-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2211403#L506 assume !(1 == ~t6_pc~0); 2211398#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 2211399#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2211799#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2211712#L1073 assume !(0 != activate_threads_~tmp___5~0); 2211713#L1073-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 2211542#L525 assume !(1 == ~t7_pc~0); 2211481#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 2211543#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 2212019#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2211251#L1081 assume !(0 != activate_threads_~tmp___6~0); 2211252#L1081-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 2211253#L544 assume !(1 == ~t8_pc~0); 2211561#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 2210903#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 2210904#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2211039#L1089 assume !(0 != activate_threads_~tmp___7~0); 2211840#L1089-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2211411#L921 assume !(1 == ~M_E~0); 2211412#L921-2 assume !(1 == ~T1_E~0); 2211122#L926-1 assume !(1 == ~T2_E~0); 2211123#L931-1 assume !(1 == ~T3_E~0); 2211910#L936-1 assume !(1 == ~T4_E~0); 2211703#L941-1 assume !(1 == ~T5_E~0); 2211409#L946-1 assume !(1 == ~T6_E~0); 2210921#L951-1 assume !(1 == ~T7_E~0); 2210922#L956-1 assume !(1 == ~T8_E~0); 2211804#L961-1 assume !(1 == ~E_1~0); 2211513#L966-1 assume !(1 == ~E_2~0); 2211256#L971-1 assume !(1 == ~E_3~0); 2211257#L976-1 assume !(1 == ~E_4~0); 2211763#L981-1 assume !(1 == ~E_5~0); 2211468#L986-1 assume !(1 == ~E_6~0); 2211374#L991-1 assume !(1 == ~E_7~0); 2211045#L996-1 assume !(1 == ~E_8~0); 2211046#L1001-1 assume { :end_inline_reset_delta_events } true; 2211930#L1262-3 [2018-11-18 14:32:59,019 INFO L796 eck$LassoCheckResult]: Loop: 2211930#L1262-3 assume true; 2217556#L1262-1 assume !false; 2217451#L1263 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 2216566#L803 assume true; 2217447#L681-1 assume !false; 2217445#L682 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 2217443#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 2217441#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 2217439#L672 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 2217437#L686 assume 0 != eval_~tmp~0; 2217435#L686-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 2217423#L694 assume 0 != eval_~tmp_ndt_1~0;~m_st~0 := 1;assume { :begin_inline_master } true; 2217424#L73 assume !(0 == ~m_pc~0); 2221079#L76 assume 1 == ~m_pc~0; 2221077#L77 assume true; 2221076#L92-1 assume !false; 2220428#L93 ~m_pc~0 := 1;~m_st~0 := 2; 2220416#L103 assume { :end_inline_master } true; 2220410#L691 assume !(0 == ~t1_st~0); 2220408#L705 assume !(0 == ~t2_st~0); 2220403#L719 assume !(0 == ~t3_st~0); 2220398#L733 assume !(0 == ~t4_st~0); 2220396#L747 assume !(0 == ~t5_st~0); 2220477#L761 assume !(0 == ~t6_st~0); 2220473#L775 assume !(0 == ~t7_st~0); 2221570#L789 assume !(0 == ~t8_st~0); 2221565#L803 assume true; 2221563#L681-1 assume !false; 2221561#L682 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 2221559#L624 assume !(0 == ~m_st~0); 2221557#L628 assume !(0 == ~t1_st~0); 2221555#L632 assume !(0 == ~t2_st~0); 2221553#L636 assume !(0 == ~t3_st~0); 2221551#L640 assume !(0 == ~t4_st~0); 2221547#L644 assume !(0 == ~t5_st~0); 2221545#L648 assume !(0 == ~t6_st~0); 2221543#L652 assume !(0 == ~t7_st~0); 2221540#L656 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9 := 0; 2221537#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 2221535#L672 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 2221533#L686 assume !(0 != eval_~tmp~0); 2221531#L818 assume { :end_inline_eval } true;start_simulation_~kernel_st~0 := 2;assume { :begin_inline_update_channels } true; 2221529#L564-1 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0 := 3;assume { :begin_inline_fire_delta_events } true; 2221527#L828-3 assume !(0 == ~M_E~0); 2221525#L828-5 assume !(0 == ~T1_E~0); 2221523#L833-3 assume !(0 == ~T2_E~0); 2221520#L838-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2221518#L843-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2221516#L848-3 assume !(0 == ~T5_E~0); 2221514#L853-3 assume !(0 == ~T6_E~0); 2221512#L858-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2221510#L863-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2221508#L868-3 assume !(0 == ~E_1~0); 2221506#L873-3 assume !(0 == ~E_2~0); 2221504#L878-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2221502#L883-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2221500#L888-3 assume !(0 == ~E_5~0); 2221498#L893-3 assume !(0 == ~E_6~0); 2221494#L898-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2221492#L903-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2221490#L908-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2221488#L392-27 assume 1 == ~m_pc~0; 2221485#L393-9 assume !(1 == ~M_E~0); 2221483#L392-29 is_master_triggered_~__retres1~0 := 0; 2221481#L403-9 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2221479#L404-9 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2221477#L1025-27 assume !(0 != activate_threads_~tmp~1); 2221475#L1025-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2221473#L411-27 assume !(1 == ~t1_pc~0); 2221471#L411-29 is_transmit1_triggered_~__retres1~1 := 0; 2221470#L422-9 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2221466#L423-9 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2221464#L1033-27 assume !(0 != activate_threads_~tmp___0~0); 2221462#L1033-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2221460#L430-27 assume !(1 == ~t2_pc~0); 2221459#L430-29 is_transmit2_triggered_~__retres1~2 := 0; 2221458#L441-9 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2221454#L442-9 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2220476#L1041-27 assume !(0 != activate_threads_~tmp___1~0); 2220471#L1041-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2220029#L449-27 assume !(1 == ~t3_pc~0); 2220024#L449-29 is_transmit3_triggered_~__retres1~3 := 0; 2220022#L460-9 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2220020#L461-9 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2220018#L1049-27 assume !(0 != activate_threads_~tmp___2~0); 2220015#L1049-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2220013#L468-27 assume !(1 == ~t4_pc~0); 2220009#L468-29 is_transmit4_triggered_~__retres1~4 := 0; 2220007#L479-9 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2220005#L480-9 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2220003#L1057-27 assume !(0 != activate_threads_~tmp___3~0); 2220000#L1057-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2219998#L487-27 assume !(1 == ~t5_pc~0); 2219995#L487-29 is_transmit5_triggered_~__retres1~5 := 0; 2219992#L498-9 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2219990#L499-9 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2219988#L1065-27 assume !(0 != activate_threads_~tmp___4~0); 2219987#L1065-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2219986#L506-27 assume !(1 == ~t6_pc~0); 2219756#L506-29 is_transmit6_triggered_~__retres1~6 := 0; 2219755#L517-9 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2219754#L518-9 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2219752#L1073-27 assume !(0 != activate_threads_~tmp___5~0); 2219750#L1073-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 2217874#L525-27 assume 1 == ~t7_pc~0; 2217872#L526-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7 := 1; 2217873#L536-9 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 2217875#L537-9 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2217864#L1081-27 assume 0 != activate_threads_~tmp___6~0;~t7_st~0 := 0; 2217862#L1081-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 2217860#L544-27 assume !(1 == ~t8_pc~0); 2217858#L544-29 is_transmit8_triggered_~__retres1~8 := 0; 2217856#L555-9 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 2217854#L556-9 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2217852#L1089-27 assume !(0 != activate_threads_~tmp___7~0); 2217850#L1089-29 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2217848#L921-3 assume !(1 == ~M_E~0); 2217846#L921-5 assume !(1 == ~T1_E~0); 2217842#L926-3 assume !(1 == ~T2_E~0); 2217840#L931-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2217838#L936-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2217836#L941-3 assume !(1 == ~T5_E~0); 2217833#L946-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2217831#L951-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2217829#L956-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2217826#L961-3 assume !(1 == ~E_1~0); 2217824#L966-3 assume !(1 == ~E_2~0); 2217822#L971-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2217820#L976-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2217818#L981-3 assume !(1 == ~E_5~0); 2217815#L986-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2217813#L991-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2217811#L996-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2217809#L1001-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 2217807#L624-1 assume !(0 == ~m_st~0); 2217805#L628-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~9 := 1; 2217797#L671-1 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 2217793#L672-1 start_simulation_#t~ret20 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3 := start_simulation_#t~ret20;havoc start_simulation_#t~ret20; 2217790#L1281 assume 0 == start_simulation_~tmp~3;start_simulation_~kernel_st~0 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 2217788#L1115 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2217786#L392-30 assume 1 == ~m_pc~0; 2217783#L393-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0 := 1; 2217781#L403-10 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2217777#L404-10 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2217774#L1025-30 assume 0 != activate_threads_~tmp~1;~m_st~0 := 0; 2217772#L1025-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2217770#L411-30 assume !(1 == ~t1_pc~0); 2217767#L411-32 is_transmit1_triggered_~__retres1~1 := 0; 2217765#L422-10 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2217763#L423-10 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2217761#L1033-30 assume !(0 != activate_threads_~tmp___0~0); 2217759#L1033-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2217757#L430-30 assume !(1 == ~t2_pc~0); 2217755#L430-32 is_transmit2_triggered_~__retres1~2 := 0; 2217753#L441-10 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2217751#L442-10 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2217749#L1041-30 assume !(0 != activate_threads_~tmp___1~0); 2217747#L1041-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2217745#L449-30 assume !(1 == ~t3_pc~0); 2217741#L449-32 is_transmit3_triggered_~__retres1~3 := 0; 2217739#L460-10 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2217737#L461-10 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2217735#L1049-30 assume !(0 != activate_threads_~tmp___2~0); 2217732#L1049-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2217730#L468-30 assume !(1 == ~t4_pc~0); 2217728#L468-32 is_transmit4_triggered_~__retres1~4 := 0; 2217726#L479-10 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2217724#L480-10 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2217722#L1057-30 assume 0 != activate_threads_~tmp___3~0;~t4_st~0 := 0; 2217720#L1057-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2217718#L487-30 assume !(1 == ~t5_pc~0); 2217715#L487-32 is_transmit5_triggered_~__retres1~5 := 0; 2217713#L498-10 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2217712#L499-10 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2217710#L1065-30 assume !(0 != activate_threads_~tmp___4~0); 2217709#L1065-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2217708#L506-30 assume !(1 == ~t6_pc~0); 2217707#L506-32 is_transmit6_triggered_~__retres1~6 := 0; 2217706#L517-10 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2217705#L518-10 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2217704#L1073-30 assume !(0 != activate_threads_~tmp___5~0); 2217695#L1073-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 2217693#L525-30 assume !(1 == ~t7_pc~0); 2217689#L525-32 is_transmit7_triggered_~__retres1~7 := 0; 2217687#L536-10 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 2217685#L537-10 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2217683#L1081-30 assume !(0 != activate_threads_~tmp___6~0); 2217680#L1081-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 2217678#L544-30 assume !(1 == ~t8_pc~0); 2217676#L544-32 is_transmit8_triggered_~__retres1~8 := 0; 2217672#L555-10 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 2217670#L556-10 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2217668#L1089-30 assume !(0 != activate_threads_~tmp___7~0); 2217666#L1089-32 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 2217663#L1122 assume 1 == ~M_E~0;~M_E~0 := 2; 2217661#L1122-2 assume !(1 == ~T1_E~0); 2217660#L1127-1 assume !(1 == ~T2_E~0); 2217656#L1132-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2217654#L1137-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2217652#L1142-1 assume !(1 == ~T5_E~0); 2217650#L1147-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2217647#L1152-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2217645#L1157-1 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2217643#L1162-1 assume !(1 == ~E_1~0); 2217641#L1167-1 assume !(1 == ~E_2~0); 2217639#L1172-1 assume 1 == ~E_3~0;~E_3~0 := 2; 2217637#L1177-1 assume 1 == ~E_4~0;~E_4~0 := 2; 2217635#L1182-1 assume !(1 == ~E_5~0); 2217633#L1187-1 assume 1 == ~E_6~0;~E_6~0 := 2; 2217629#L1192-1 assume 1 == ~E_7~0;~E_7~0 := 2; 2217627#L1197-1 assume 1 == ~E_8~0;~E_8~0 := 2; 2217625#L1202-1 assume { :end_inline_reset_time_events } true; 2217623#L1281-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res;havoc stop_simulation_#t~ret19, stop_simulation_~tmp~2, stop_simulation_~__retres2~0;havoc stop_simulation_~tmp~2;havoc stop_simulation_~__retres2~0;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 2217622#L624-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 2217617#L671-2 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 2217616#L672-2 stop_simulation_#t~ret19 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2 := stop_simulation_#t~ret19;havoc stop_simulation_#t~ret19; 2217615#L1236 assume 0 != stop_simulation_~tmp~2;stop_simulation_~__retres2~0 := 0; 2217614#L1243 stop_simulation_#res := stop_simulation_~__retres2~0; 2217612#L1244 start_simulation_#t~ret21 := stop_simulation_#res;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1 := start_simulation_#t~ret21;havoc start_simulation_#t~ret21; 2217611#L1294 assume !(0 != start_simulation_~tmp___0~1); 2211930#L1262-3 [2018-11-18 14:32:59,020 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:59,020 INFO L82 PathProgramCache]: Analyzing trace with hash -1641920416, now seen corresponding path program 1 times [2018-11-18 14:32:59,020 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:59,020 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:59,021 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:59,021 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:59,021 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:59,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:59,063 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:59,063 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:59,063 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 14:32:59,064 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 14:32:59,064 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:32:59,064 INFO L82 PathProgramCache]: Analyzing trace with hash -266047234, now seen corresponding path program 1 times [2018-11-18 14:32:59,064 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:32:59,064 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:32:59,065 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:59,065 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:32:59,065 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:32:59,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:32:59,116 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:32:59,116 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:32:59,116 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:32:59,117 INFO L811 eck$LassoCheckResult]: loop already infeasible [2018-11-18 14:32:59,117 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 14:32:59,117 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 14:32:59,117 INFO L87 Difference]: Start difference. First operand 53861 states and 67397 transitions. cyclomatic complexity: 13600 Second operand 3 states. [2018-11-18 14:32:59,249 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:32:59,249 INFO L93 Difference]: Finished difference Result 53844 states and 67137 transitions. [2018-11-18 14:32:59,249 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 14:32:59,249 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 53844 states and 67137 transitions. [2018-11-18 14:32:59,363 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 50816 [2018-11-18 14:32:59,444 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 53844 states to 53844 states and 67137 transitions. [2018-11-18 14:32:59,444 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 53844 [2018-11-18 14:32:59,465 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 53844 [2018-11-18 14:32:59,465 INFO L73 IsDeterministic]: Start isDeterministic. Operand 53844 states and 67137 transitions. [2018-11-18 14:32:59,486 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:32:59,486 INFO L705 BuchiCegarLoop]: Abstraction has 53844 states and 67137 transitions. [2018-11-18 14:32:59,505 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53844 states and 67137 transitions. [2018-11-18 14:32:59,765 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53844 to 53748. [2018-11-18 14:32:59,766 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 53748 states. [2018-11-18 14:32:59,821 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53748 states to 53748 states and 67041 transitions. [2018-11-18 14:32:59,821 INFO L728 BuchiCegarLoop]: Abstraction has 53748 states and 67041 transitions. [2018-11-18 14:32:59,821 INFO L608 BuchiCegarLoop]: Abstraction has 53748 states and 67041 transitions. [2018-11-18 14:32:59,821 INFO L442 BuchiCegarLoop]: ======== Iteration 37============ [2018-11-18 14:32:59,821 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 53748 states and 67041 transitions. [2018-11-18 14:33:00,165 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 50816 [2018-11-18 14:33:00,165 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:33:00,165 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:33:00,165 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:33:00,165 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:33:00,166 INFO L794 eck$LassoCheckResult]: Stem: 2319103#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 2318989#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 2318990#L1225 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 2319507#L564 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2319026#L571 assume 1 == ~m_i~0;~m_st~0 := 0; 2319007#L571-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2318697#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2318698#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2319510#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2319240#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2318821#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2318822#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2319498#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2319376#L611-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2319377#L828 assume !(0 == ~M_E~0); 2319517#L828-2 assume !(0 == ~T1_E~0); 2319131#L833-1 assume !(0 == ~T2_E~0); 2318836#L838-1 assume !(0 == ~T3_E~0); 2318837#L843-1 assume !(0 == ~T4_E~0); 2319613#L848-1 assume !(0 == ~T5_E~0); 2319389#L853-1 assume !(0 == ~T6_E~0); 2319114#L858-1 assume !(0 == ~T7_E~0); 2318621#L863-1 assume !(0 == ~T8_E~0); 2318622#L868-1 assume !(0 == ~E_1~0); 2319330#L873-1 assume !(0 == ~E_2~0); 2319209#L878-1 assume !(0 == ~E_3~0); 2318953#L883-1 assume !(0 == ~E_4~0); 2318954#L888-1 assume !(0 == ~E_5~0); 2319470#L893-1 assume !(0 == ~E_6~0); 2319174#L898-1 assume !(0 == ~E_7~0); 2319090#L903-1 assume !(0 == ~E_8~0); 2318771#L908-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2318772#L392 assume !(1 == ~m_pc~0); 2319154#L392-2 is_master_triggered_~__retres1~0 := 0; 2319159#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2319658#L404 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2319479#L1025 assume !(0 != activate_threads_~tmp~1); 2319480#L1025-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2319317#L411 assume !(1 == ~t1_pc~0); 2319284#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 2318680#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2318681#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2318801#L1033 assume !(0 != activate_threads_~tmp___0~0); 2319033#L1033-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2319034#L430 assume !(1 == ~t2_pc~0); 2319489#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 2318869#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2318823#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2318824#L1041 assume !(0 != activate_threads_~tmp___1~0); 2319678#L1041-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2319679#L449 assume !(1 == ~t3_pc~0); 2319561#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 2319689#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2319705#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2319503#L1049 assume !(0 != activate_threads_~tmp___2~0); 2319504#L1049-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2318718#L468 assume !(1 == ~t4_pc~0); 2318719#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 2318727#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2319165#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2319097#L1057 assume !(0 != activate_threads_~tmp___3~0); 2319098#L1057-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2318938#L487 assume !(1 == ~t5_pc~0); 2318676#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 2318940#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2319304#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2319305#L1065 assume !(0 != activate_threads_~tmp___4~0); 2319696#L1065-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2319113#L506 assume !(1 == ~t6_pc~0); 2319108#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 2319109#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2319500#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2319414#L1073 assume !(0 != activate_threads_~tmp___5~0); 2319415#L1073-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 2319242#L525 assume !(1 == ~t7_pc~0); 2319184#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 2319243#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 2319706#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2318959#L1081 assume !(0 != activate_threads_~tmp___6~0); 2318960#L1081-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 2318961#L544 assume !(1 == ~t8_pc~0); 2319257#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 2318615#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 2318616#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2318751#L1089 assume !(0 != activate_threads_~tmp___7~0); 2319541#L1089-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2319122#L921 assume !(1 == ~M_E~0); 2319123#L921-2 assume !(1 == ~T1_E~0); 2318832#L926-1 assume !(1 == ~T2_E~0); 2318833#L931-1 assume !(1 == ~T3_E~0); 2319611#L936-1 assume !(1 == ~T4_E~0); 2319402#L941-1 assume !(1 == ~T5_E~0); 2319120#L946-1 assume !(1 == ~T6_E~0); 2318633#L951-1 assume !(1 == ~T7_E~0); 2318634#L956-1 assume !(1 == ~T8_E~0); 2319506#L961-1 assume !(1 == ~E_1~0); 2319216#L966-1 assume !(1 == ~E_2~0); 2318965#L971-1 assume !(1 == ~E_3~0); 2318966#L976-1 assume !(1 == ~E_4~0); 2319466#L981-1 assume !(1 == ~E_5~0); 2319172#L986-1 assume !(1 == ~E_6~0); 2319084#L991-1 assume !(1 == ~E_7~0); 2318758#L996-1 assume !(1 == ~E_8~0); 2318759#L1001-1 assume { :end_inline_reset_delta_events } true; 2319631#L1262-3 assume true; 2321931#L1262-1 assume !false; 2321923#L1263 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 2321921#L803 [2018-11-18 14:33:00,166 INFO L796 eck$LassoCheckResult]: Loop: 2321921#L803 assume true; 2321919#L681-1 assume !false; 2321917#L682 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 2321915#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 2321913#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 2321911#L672 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 2321909#L686 assume 0 != eval_~tmp~0; 2321907#L686-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 2321904#L694 assume !(0 != eval_~tmp_ndt_1~0); 2321899#L691 assume !(0 == ~t1_st~0); 2321889#L705 assume !(0 == ~t2_st~0); 2321882#L719 assume !(0 == ~t3_st~0); 2321951#L733 assume !(0 == ~t4_st~0); 2321897#L747 assume !(0 == ~t5_st~0); 2321887#L761 assume !(0 == ~t6_st~0); 2321879#L775 assume !(0 == ~t7_st~0); 2321926#L789 assume !(0 == ~t8_st~0); 2321921#L803 [2018-11-18 14:33:00,166 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:33:00,166 INFO L82 PathProgramCache]: Analyzing trace with hash 64602117, now seen corresponding path program 1 times [2018-11-18 14:33:00,166 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:33:00,166 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:33:00,167 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:33:00,167 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:33:00,167 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:33:00,171 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:33:00,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:33:00,189 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:33:00,189 INFO L82 PathProgramCache]: Analyzing trace with hash 1871721886, now seen corresponding path program 2 times [2018-11-18 14:33:00,189 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:33:00,189 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:33:00,190 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:33:00,190 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:33:00,190 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:33:00,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:33:00,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:33:00,193 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:33:00,193 INFO L82 PathProgramCache]: Analyzing trace with hash -189399526, now seen corresponding path program 1 times [2018-11-18 14:33:00,194 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:33:00,194 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:33:00,194 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:33:00,194 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 14:33:00,194 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:33:00,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:33:00,245 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:33:00,245 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:33:00,245 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:33:00,329 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 14:33:00,329 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 14:33:00,329 INFO L87 Difference]: Start difference. First operand 53748 states and 67041 transitions. cyclomatic complexity: 13357 Second operand 3 states. [2018-11-18 14:33:00,482 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:33:00,482 INFO L93 Difference]: Finished difference Result 99226 states and 122947 transitions. [2018-11-18 14:33:00,482 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 14:33:00,482 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 99226 states and 122947 transitions. [2018-11-18 14:33:00,689 INFO L131 ngComponentsAnalysis]: Automaton has 112 accepting balls. 90264 [2018-11-18 14:33:00,837 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 99226 states to 99226 states and 122947 transitions. [2018-11-18 14:33:00,837 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 99226 [2018-11-18 14:33:00,878 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 99226 [2018-11-18 14:33:00,878 INFO L73 IsDeterministic]: Start isDeterministic. Operand 99226 states and 122947 transitions. [2018-11-18 14:33:00,913 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:33:00,913 INFO L705 BuchiCegarLoop]: Abstraction has 99226 states and 122947 transitions. [2018-11-18 14:33:00,950 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99226 states and 122947 transitions. [2018-11-18 14:33:01,336 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99226 to 99226. [2018-11-18 14:33:01,336 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 99226 states. [2018-11-18 14:33:01,427 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99226 states to 99226 states and 122947 transitions. [2018-11-18 14:33:01,427 INFO L728 BuchiCegarLoop]: Abstraction has 99226 states and 122947 transitions. [2018-11-18 14:33:01,427 INFO L608 BuchiCegarLoop]: Abstraction has 99226 states and 122947 transitions. [2018-11-18 14:33:01,427 INFO L442 BuchiCegarLoop]: ======== Iteration 38============ [2018-11-18 14:33:01,427 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 99226 states and 122947 transitions. [2018-11-18 14:33:01,592 INFO L131 ngComponentsAnalysis]: Automaton has 112 accepting balls. 90264 [2018-11-18 14:33:01,592 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:33:01,592 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:33:01,593 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:33:01,593 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:33:01,593 INFO L794 eck$LassoCheckResult]: Stem: 2472081#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 2471968#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 2471969#L1225 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 2472483#L564 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2472006#L571 assume 1 == ~m_i~0;~m_st~0 := 0; 2471986#L571-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 2471680#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2471681#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2472486#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2472223#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2471801#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2471802#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2472474#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2472361#L611-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2472362#L828 assume !(0 == ~M_E~0); 2472493#L828-2 assume !(0 == ~T1_E~0); 2472107#L833-1 assume !(0 == ~T2_E~0); 2471816#L838-1 assume !(0 == ~T3_E~0); 2471817#L843-1 assume !(0 == ~T4_E~0); 2472579#L848-1 assume !(0 == ~T5_E~0); 2472373#L853-1 assume !(0 == ~T6_E~0); 2472091#L858-1 assume !(0 == ~T7_E~0); 2471603#L863-1 assume !(0 == ~T8_E~0); 2471604#L868-1 assume !(0 == ~E_1~0); 2472314#L873-1 assume !(0 == ~E_2~0); 2472188#L878-1 assume !(0 == ~E_3~0); 2471937#L883-1 assume !(0 == ~E_4~0); 2471938#L888-1 assume !(0 == ~E_5~0); 2472444#L893-1 assume !(0 == ~E_6~0); 2472152#L898-1 assume !(0 == ~E_7~0); 2472068#L903-1 assume !(0 == ~E_8~0); 2471753#L908-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2471754#L392 assume !(1 == ~m_pc~0); 2472131#L392-2 is_master_triggered_~__retres1~0 := 0; 2472137#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2472632#L404 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2472453#L1025 assume !(0 != activate_threads_~tmp~1); 2472454#L1025-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2472302#L411 assume !(1 == ~t1_pc~0); 2472269#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 2471663#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2471664#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2471782#L1033 assume !(0 != activate_threads_~tmp___0~0); 2477852#L1033-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2477850#L430 assume !(1 == ~t2_pc~0); 2477848#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 2477846#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2471803#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2471804#L1041 assume !(0 != activate_threads_~tmp___1~0); 2472662#L1041-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2472663#L449 assume !(1 == ~t3_pc~0); 2472674#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 2472675#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2472692#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2472693#L1049 assume !(0 != activate_threads_~tmp___2~0); 2472481#L1049-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2471701#L468 assume !(1 == ~t4_pc~0); 2471702#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 2471711#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2472143#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2472144#L1057 assume !(0 != activate_threads_~tmp___3~0); 2477746#L1057-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2471921#L487 assume !(1 == ~t5_pc~0); 2471659#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 2471924#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2472290#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2472291#L1065 assume !(0 != activate_threads_~tmp___4~0); 2472682#L1065-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2472683#L506 assume !(1 == ~t6_pc~0); 2477561#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 2472596#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2472477#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2472393#L1073 assume !(0 != activate_threads_~tmp___5~0); 2472394#L1073-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 2472225#L525 assume !(1 == ~t7_pc~0); 2472162#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 2472226#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 2472695#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2472696#L1081 assume !(0 != activate_threads_~tmp___6~0); 2477441#L1081-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 2477440#L544 assume !(1 == ~t8_pc~0); 2477439#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 2477438#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 2477437#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2477436#L1089 assume !(0 != activate_threads_~tmp___7~0); 2477435#L1089-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2477434#L921 assume !(1 == ~M_E~0); 2477433#L921-2 assume !(1 == ~T1_E~0); 2477432#L926-1 assume !(1 == ~T2_E~0); 2477431#L931-1 assume !(1 == ~T3_E~0); 2477430#L936-1 assume !(1 == ~T4_E~0); 2477429#L941-1 assume !(1 == ~T5_E~0); 2477428#L946-1 assume !(1 == ~T6_E~0); 2477427#L951-1 assume !(1 == ~T7_E~0); 2477426#L956-1 assume !(1 == ~T8_E~0); 2477425#L961-1 assume !(1 == ~E_1~0); 2477424#L966-1 assume !(1 == ~E_2~0); 2477423#L971-1 assume !(1 == ~E_3~0); 2477422#L976-1 assume !(1 == ~E_4~0); 2477421#L981-1 assume !(1 == ~E_5~0); 2477420#L986-1 assume !(1 == ~E_6~0); 2477419#L991-1 assume !(1 == ~E_7~0); 2477418#L996-1 assume !(1 == ~E_8~0); 2477417#L1001-1 assume { :end_inline_reset_delta_events } true; 2477408#L1262-3 assume true; 2477401#L1262-1 assume !false; 2477067#L1263 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 2477058#L803 [2018-11-18 14:33:01,593 INFO L796 eck$LassoCheckResult]: Loop: 2477058#L803 assume true; 2477049#L681-1 assume !false; 2477043#L682 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 2477036#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 2477028#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 2477020#L672 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 2477012#L686 assume 0 != eval_~tmp~0; 2477004#L686-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 2476994#L694 assume !(0 != eval_~tmp_ndt_1~0); 2476987#L691 assume !(0 == ~t1_st~0); 2476980#L705 assume !(0 == ~t2_st~0); 2476971#L719 assume !(0 == ~t3_st~0); 2476962#L733 assume !(0 == ~t4_st~0); 2476955#L747 assume !(0 == ~t5_st~0); 2477127#L761 assume !(0 == ~t6_st~0); 2477092#L775 assume !(0 == ~t7_st~0); 2477070#L789 assume !(0 == ~t8_st~0); 2477058#L803 [2018-11-18 14:33:01,593 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:33:01,594 INFO L82 PathProgramCache]: Analyzing trace with hash -1802106557, now seen corresponding path program 1 times [2018-11-18 14:33:01,594 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:33:01,594 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:33:01,594 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:33:01,594 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:33:01,594 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:33:01,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:33:01,622 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:33:01,622 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:33:01,622 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:33:01,622 INFO L799 eck$LassoCheckResult]: stem already infeasible [2018-11-18 14:33:01,622 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:33:01,622 INFO L82 PathProgramCache]: Analyzing trace with hash 1871721886, now seen corresponding path program 3 times [2018-11-18 14:33:01,622 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:33:01,622 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:33:01,623 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:33:01,623 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:33:01,623 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:33:01,624 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:33:01,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:33:01,671 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 14:33:01,671 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 14:33:01,671 INFO L87 Difference]: Start difference. First operand 99226 states and 122947 transitions. cyclomatic complexity: 23833 Second operand 3 states. [2018-11-18 14:33:01,764 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:33:01,764 INFO L93 Difference]: Finished difference Result 65204 states and 80704 transitions. [2018-11-18 14:33:01,764 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 14:33:01,764 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 65204 states and 80704 transitions. [2018-11-18 14:33:01,893 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 60896 [2018-11-18 14:33:01,976 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 65204 states to 65204 states and 80704 transitions. [2018-11-18 14:33:01,976 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 65204 [2018-11-18 14:33:02,000 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 65204 [2018-11-18 14:33:02,000 INFO L73 IsDeterministic]: Start isDeterministic. Operand 65204 states and 80704 transitions. [2018-11-18 14:33:02,021 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:33:02,021 INFO L705 BuchiCegarLoop]: Abstraction has 65204 states and 80704 transitions. [2018-11-18 14:33:02,044 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65204 states and 80704 transitions. [2018-11-18 14:33:02,281 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65204 to 65204. [2018-11-18 14:33:02,281 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 65204 states. [2018-11-18 14:33:02,333 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65204 states to 65204 states and 80704 transitions. [2018-11-18 14:33:02,333 INFO L728 BuchiCegarLoop]: Abstraction has 65204 states and 80704 transitions. [2018-11-18 14:33:02,333 INFO L608 BuchiCegarLoop]: Abstraction has 65204 states and 80704 transitions. [2018-11-18 14:33:02,333 INFO L442 BuchiCegarLoop]: ======== Iteration 39============ [2018-11-18 14:33:02,333 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 65204 states and 80704 transitions. [2018-11-18 14:33:02,436 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 60896 [2018-11-18 14:33:02,436 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:33:02,436 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:33:02,436 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:33:02,436 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:33:02,437 INFO L794 eck$LassoCheckResult]: Stem: 2636519#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 2636406#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 2636407#L1225 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 2636938#L564 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2636443#L571 assume 1 == ~m_i~0;~m_st~0 := 0; 2636424#L571-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2636116#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2636117#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2636943#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2636666#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2636239#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2636240#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2636930#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2636809#L611-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2636810#L828 assume !(0 == ~M_E~0); 2636949#L828-2 assume !(0 == ~T1_E~0); 2636543#L833-1 assume !(0 == ~T2_E~0); 2636254#L838-1 assume !(0 == ~T3_E~0); 2636255#L843-1 assume !(0 == ~T4_E~0); 2637035#L848-1 assume !(0 == ~T5_E~0); 2636822#L853-1 assume !(0 == ~T6_E~0); 2636528#L858-1 assume !(0 == ~T7_E~0); 2636039#L863-1 assume !(0 == ~T8_E~0); 2636040#L868-1 assume !(0 == ~E_1~0); 2636762#L873-1 assume !(0 == ~E_2~0); 2636628#L878-1 assume !(0 == ~E_3~0); 2636374#L883-1 assume !(0 == ~E_4~0); 2636375#L888-1 assume !(0 == ~E_5~0); 2636899#L893-1 assume !(0 == ~E_6~0); 2636587#L898-1 assume !(0 == ~E_7~0); 2636510#L903-1 assume !(0 == ~E_8~0); 2636189#L908-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2636190#L392 assume !(1 == ~m_pc~0); 2636567#L392-2 is_master_triggered_~__retres1~0 := 0; 2636572#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2637084#L404 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2636905#L1025 assume !(0 != activate_threads_~tmp~1); 2636906#L1025-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2636749#L411 assume !(1 == ~t1_pc~0); 2636715#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 2636101#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2636102#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2636221#L1033 assume !(0 != activate_threads_~tmp___0~0); 2636451#L1033-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2636452#L430 assume !(1 == ~t2_pc~0); 2636916#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 2636292#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2636241#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2636242#L1041 assume !(0 != activate_threads_~tmp___1~0); 2637107#L1041-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2637108#L449 assume !(1 == ~t3_pc~0); 2636990#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 2637117#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2637129#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2636935#L1049 assume !(0 != activate_threads_~tmp___2~0); 2636936#L1049-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2636137#L468 assume !(1 == ~t4_pc~0); 2636138#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 2636147#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2636578#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2636515#L1057 assume !(0 != activate_threads_~tmp___3~0); 2636516#L1057-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2636359#L487 assume !(1 == ~t5_pc~0); 2636095#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 2636361#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2636736#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2636737#L1065 assume !(0 != activate_threads_~tmp___4~0); 2637122#L1065-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2636527#L506 assume !(1 == ~t6_pc~0); 2636523#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 2636524#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2636933#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2636837#L1073 assume !(0 != activate_threads_~tmp___5~0); 2636838#L1073-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 2636667#L525 assume !(1 == ~t7_pc~0); 2636599#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 2636668#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 2637130#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2636380#L1081 assume !(0 != activate_threads_~tmp___6~0); 2636381#L1081-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 2636382#L544 assume !(1 == ~t8_pc~0); 2636685#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 2636033#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 2636034#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2636171#L1089 assume !(0 != activate_threads_~tmp___7~0); 2636970#L1089-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2636536#L921 assume !(1 == ~M_E~0); 2636537#L921-2 assume !(1 == ~T1_E~0); 2636250#L926-1 assume !(1 == ~T2_E~0); 2636251#L931-1 assume !(1 == ~T3_E~0); 2637033#L936-1 assume !(1 == ~T4_E~0); 2636832#L941-1 assume !(1 == ~T5_E~0); 2636533#L946-1 assume !(1 == ~T6_E~0); 2636051#L951-1 assume !(1 == ~T7_E~0); 2636052#L956-1 assume !(1 == ~T8_E~0); 2636937#L961-1 assume !(1 == ~E_1~0); 2636636#L966-1 assume !(1 == ~E_2~0); 2636385#L971-1 assume !(1 == ~E_3~0); 2636386#L976-1 assume !(1 == ~E_4~0); 2636893#L981-1 assume !(1 == ~E_5~0); 2636585#L986-1 assume !(1 == ~E_6~0); 2636501#L991-1 assume !(1 == ~E_7~0); 2636179#L996-1 assume !(1 == ~E_8~0); 2636180#L1001-1 assume { :end_inline_reset_delta_events } true; 2637056#L1262-3 assume true; 2643323#L1262-1 assume !false; 2643227#L1263 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 2643219#L803 [2018-11-18 14:33:02,437 INFO L796 eck$LassoCheckResult]: Loop: 2643219#L803 assume true; 2643210#L681-1 assume !false; 2643203#L682 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 2643196#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 2643190#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 2643184#L672 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 2643178#L686 assume 0 != eval_~tmp~0; 2643172#L686-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 2643165#L694 assume !(0 != eval_~tmp_ndt_1~0); 2643158#L691 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 2643152#L708 assume !(0 != eval_~tmp_ndt_2~0); 2643147#L705 assume !(0 == ~t2_st~0); 2643138#L719 assume !(0 == ~t3_st~0); 2643131#L733 assume !(0 == ~t4_st~0); 2643130#L747 assume !(0 == ~t5_st~0); 2643343#L761 assume !(0 == ~t6_st~0); 2643324#L775 assume !(0 == ~t7_st~0); 2643230#L789 assume !(0 == ~t8_st~0); 2643219#L803 [2018-11-18 14:33:02,437 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:33:02,437 INFO L82 PathProgramCache]: Analyzing trace with hash 64602117, now seen corresponding path program 2 times [2018-11-18 14:33:02,437 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:33:02,437 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:33:02,438 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:33:02,438 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 14:33:02,438 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:33:02,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:33:02,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:33:02,459 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:33:02,459 INFO L82 PathProgramCache]: Analyzing trace with hash -894331846, now seen corresponding path program 1 times [2018-11-18 14:33:02,459 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:33:02,459 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:33:02,460 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:33:02,460 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 14:33:02,460 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:33:02,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:33:02,462 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:33:02,463 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:33:02,464 INFO L82 PathProgramCache]: Analyzing trace with hash -364586178, now seen corresponding path program 1 times [2018-11-18 14:33:02,464 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:33:02,464 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:33:02,464 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:33:02,464 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:33:02,464 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:33:02,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:33:02,516 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:33:02,516 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:33:02,516 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:33:02,589 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 14:33:02,589 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 14:33:02,589 INFO L87 Difference]: Start difference. First operand 65204 states and 80704 transitions. cyclomatic complexity: 15564 Second operand 3 states. [2018-11-18 14:33:02,727 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:33:02,727 INFO L93 Difference]: Finished difference Result 82432 states and 101608 transitions. [2018-11-18 14:33:02,728 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 14:33:02,728 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 82432 states and 101608 transitions. [2018-11-18 14:33:02,896 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 76080 [2018-11-18 14:33:03,004 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 82432 states to 82432 states and 101608 transitions. [2018-11-18 14:33:03,004 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 82432 [2018-11-18 14:33:03,036 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 82432 [2018-11-18 14:33:03,036 INFO L73 IsDeterministic]: Start isDeterministic. Operand 82432 states and 101608 transitions. [2018-11-18 14:33:03,064 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:33:03,064 INFO L705 BuchiCegarLoop]: Abstraction has 82432 states and 101608 transitions. [2018-11-18 14:33:03,094 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82432 states and 101608 transitions. [2018-11-18 14:33:03,381 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82432 to 82432. [2018-11-18 14:33:03,381 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 82432 states. [2018-11-18 14:33:03,445 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82432 states to 82432 states and 101608 transitions. [2018-11-18 14:33:03,445 INFO L728 BuchiCegarLoop]: Abstraction has 82432 states and 101608 transitions. [2018-11-18 14:33:03,445 INFO L608 BuchiCegarLoop]: Abstraction has 82432 states and 101608 transitions. [2018-11-18 14:33:03,445 INFO L442 BuchiCegarLoop]: ======== Iteration 40============ [2018-11-18 14:33:03,445 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 82432 states and 101608 transitions. [2018-11-18 14:33:03,576 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 76080 [2018-11-18 14:33:03,577 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:33:03,577 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:33:03,577 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:33:03,577 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:33:03,578 INFO L794 eck$LassoCheckResult]: Stem: 2784164#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 2784049#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 2784050#L1225 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 2784575#L564 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2784086#L571 assume 1 == ~m_i~0;~m_st~0 := 0; 2784067#L571-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2783761#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2783762#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2784578#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2784308#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2783885#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2783886#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2784566#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2784454#L611-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2784455#L828 assume !(0 == ~M_E~0); 2784585#L828-2 assume !(0 == ~T1_E~0); 2784193#L833-1 assume !(0 == ~T2_E~0); 2783900#L838-1 assume !(0 == ~T3_E~0); 2783901#L843-1 assume !(0 == ~T4_E~0); 2784673#L848-1 assume !(0 == ~T5_E~0); 2784467#L853-1 assume !(0 == ~T6_E~0); 2784176#L858-1 assume !(0 == ~T7_E~0); 2783683#L863-1 assume !(0 == ~T8_E~0); 2783684#L868-1 assume !(0 == ~E_1~0); 2784407#L873-1 assume !(0 == ~E_2~0); 2784272#L878-1 assume !(0 == ~E_3~0); 2784018#L883-1 assume !(0 == ~E_4~0); 2784019#L888-1 assume !(0 == ~E_5~0); 2784536#L893-1 assume !(0 == ~E_6~0); 2784237#L898-1 assume !(0 == ~E_7~0); 2784153#L903-1 assume !(0 == ~E_8~0); 2783834#L908-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 2783835#L392 assume !(1 == ~m_pc~0); 2784216#L392-2 is_master_triggered_~__retres1~0 := 0; 2784222#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 2784730#L404 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 2784543#L1025 assume !(0 != activate_threads_~tmp~1); 2784544#L1025-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 2784392#L411 assume !(1 == ~t1_pc~0); 2784360#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 2783745#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 2783746#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 2783866#L1033 assume !(0 != activate_threads_~tmp___0~0); 2784094#L1033-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 2784095#L430 assume !(1 == ~t2_pc~0); 2784554#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 2783937#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 2783887#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 2783888#L1041 assume !(0 != activate_threads_~tmp___1~0); 2784762#L1041-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 2784763#L449 assume !(1 == ~t3_pc~0); 2784624#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 2784775#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 2784796#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 2784571#L1049 assume !(0 != activate_threads_~tmp___2~0); 2784572#L1049-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 2783782#L468 assume !(1 == ~t4_pc~0); 2783783#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 2783792#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 2784228#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 2784159#L1057 assume !(0 != activate_threads_~tmp___3~0); 2784160#L1057-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 2784003#L487 assume !(1 == ~t5_pc~0); 2783739#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 2784005#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 2784380#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 2784381#L1065 assume !(0 != activate_threads_~tmp___4~0); 2784786#L1065-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 2784175#L506 assume !(1 == ~t6_pc~0); 2784170#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 2784171#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 2784569#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 2784483#L1073 assume !(0 != activate_threads_~tmp___5~0); 2784484#L1073-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 2784309#L525 assume !(1 == ~t7_pc~0); 2784247#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 2784311#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 2784797#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 2784024#L1081 assume !(0 != activate_threads_~tmp___6~0); 2784025#L1081-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 2784026#L544 assume !(1 == ~t8_pc~0); 2784332#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 2783677#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 2783678#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 2783816#L1089 assume !(0 != activate_threads_~tmp___7~0); 2784605#L1089-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2784185#L921 assume !(1 == ~M_E~0); 2784186#L921-2 assume !(1 == ~T1_E~0); 2783896#L926-1 assume !(1 == ~T2_E~0); 2783897#L931-1 assume !(1 == ~T3_E~0); 2784671#L936-1 assume !(1 == ~T4_E~0); 2784475#L941-1 assume !(1 == ~T5_E~0); 2784181#L946-1 assume !(1 == ~T6_E~0); 2783695#L951-1 assume !(1 == ~T7_E~0); 2783696#L956-1 assume !(1 == ~T8_E~0); 2784574#L961-1 assume !(1 == ~E_1~0); 2784279#L966-1 assume !(1 == ~E_2~0); 2784029#L971-1 assume !(1 == ~E_3~0); 2784030#L976-1 assume !(1 == ~E_4~0); 2784530#L981-1 assume !(1 == ~E_5~0); 2784235#L986-1 assume !(1 == ~E_6~0); 2784145#L991-1 assume !(1 == ~E_7~0); 2783824#L996-1 assume !(1 == ~E_8~0); 2783825#L1001-1 assume { :end_inline_reset_delta_events } true; 2784695#L1262-3 assume true; 2805641#L1262-1 assume !false; 2805631#L1263 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 2805625#L803 [2018-11-18 14:33:03,578 INFO L796 eck$LassoCheckResult]: Loop: 2805625#L803 assume true; 2805619#L681-1 assume !false; 2805613#L682 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 2805608#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 2805600#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 2805595#L672 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 2805589#L686 assume 0 != eval_~tmp~0; 2805582#L686-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 2805580#L694 assume !(0 != eval_~tmp_ndt_1~0); 2805053#L691 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 2805051#L708 assume !(0 != eval_~tmp_ndt_2~0); 2805052#L705 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 2805583#L722 assume !(0 != eval_~tmp_ndt_3~0); 2805584#L719 assume !(0 == ~t3_st~0); 2805832#L733 assume !(0 == ~t4_st~0); 2805663#L747 assume !(0 == ~t5_st~0); 2805658#L761 assume !(0 == ~t6_st~0); 2805642#L775 assume !(0 == ~t7_st~0); 2805634#L789 assume !(0 == ~t8_st~0); 2805625#L803 [2018-11-18 14:33:03,578 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:33:03,578 INFO L82 PathProgramCache]: Analyzing trace with hash 64602117, now seen corresponding path program 3 times [2018-11-18 14:33:03,578 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:33:03,578 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:33:03,579 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:33:03,579 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:33:03,579 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:33:03,583 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:33:03,586 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:33:03,600 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:33:03,600 INFO L82 PathProgramCache]: Analyzing trace with hash 439921515, now seen corresponding path program 1 times [2018-11-18 14:33:03,600 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:33:03,600 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:33:03,601 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:33:03,601 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 14:33:03,601 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:33:03,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:33:03,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:33:03,604 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:33:03,604 INFO L82 PathProgramCache]: Analyzing trace with hash -317831961, now seen corresponding path program 1 times [2018-11-18 14:33:03,604 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:33:03,604 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:33:03,605 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:33:03,605 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:33:03,605 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:33:03,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:33:03,656 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:33:03,656 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:33:03,656 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:33:03,723 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 14:33:03,723 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 14:33:03,724 INFO L87 Difference]: Start difference. First operand 82432 states and 101608 transitions. cyclomatic complexity: 19240 Second operand 3 states. [2018-11-18 14:33:04,090 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:33:04,090 INFO L93 Difference]: Finished difference Result 158212 states and 194776 transitions. [2018-11-18 14:33:04,091 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 14:33:04,091 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 158212 states and 194776 transitions. [2018-11-18 14:33:04,405 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 145624 [2018-11-18 14:33:04,618 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 158212 states to 158212 states and 194776 transitions. [2018-11-18 14:33:04,618 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 158212 [2018-11-18 14:33:04,675 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 158212 [2018-11-18 14:33:04,675 INFO L73 IsDeterministic]: Start isDeterministic. Operand 158212 states and 194776 transitions. [2018-11-18 14:33:04,725 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:33:04,725 INFO L705 BuchiCegarLoop]: Abstraction has 158212 states and 194776 transitions. [2018-11-18 14:33:04,781 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 158212 states and 194776 transitions. [2018-11-18 14:33:05,366 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 158212 to 150380. [2018-11-18 14:33:05,366 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 150380 states. [2018-11-18 14:33:05,491 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 150380 states to 150380 states and 185360 transitions. [2018-11-18 14:33:05,491 INFO L728 BuchiCegarLoop]: Abstraction has 150380 states and 185360 transitions. [2018-11-18 14:33:05,491 INFO L608 BuchiCegarLoop]: Abstraction has 150380 states and 185360 transitions. [2018-11-18 14:33:05,491 INFO L442 BuchiCegarLoop]: ======== Iteration 41============ [2018-11-18 14:33:05,491 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 150380 states and 185360 transitions. [2018-11-18 14:33:05,744 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 137792 [2018-11-18 14:33:05,744 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:33:05,744 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:33:05,745 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:33:05,745 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:33:05,745 INFO L794 eck$LassoCheckResult]: Stem: 3024823#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 3024709#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 3024710#L1225 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 3025257#L564 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3024746#L571 assume 1 == ~m_i~0;~m_st~0 := 0; 3024727#L571-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3024412#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3024413#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3025260#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3024978#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3024535#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3024536#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3025249#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 3025137#L611-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3025138#L828 assume !(0 == ~M_E~0); 3025271#L828-2 assume !(0 == ~T1_E~0); 3024850#L833-1 assume !(0 == ~T2_E~0); 3024552#L838-1 assume !(0 == ~T3_E~0); 3024553#L843-1 assume !(0 == ~T4_E~0); 3025382#L848-1 assume !(0 == ~T5_E~0); 3025150#L853-1 assume !(0 == ~T6_E~0); 3024834#L858-1 assume !(0 == ~T7_E~0); 3024335#L863-1 assume !(0 == ~T8_E~0); 3024336#L868-1 assume !(0 == ~E_1~0); 3025086#L873-1 assume !(0 == ~E_2~0); 3024936#L878-1 assume !(0 == ~E_3~0); 3024677#L883-1 assume !(0 == ~E_4~0); 3024678#L888-1 assume !(0 == ~E_5~0); 3025215#L893-1 assume !(0 == ~E_6~0); 3024895#L898-1 assume !(0 == ~E_7~0); 3024811#L903-1 assume !(0 == ~E_8~0); 3024486#L908-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3024487#L392 assume !(1 == ~m_pc~0); 3024873#L392-2 is_master_triggered_~__retres1~0 := 0; 3024879#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3025434#L404 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3025224#L1025 assume !(0 != activate_threads_~tmp~1); 3025225#L1025-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3025072#L411 assume !(1 == ~t1_pc~0); 3025037#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 3024397#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3024398#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3024516#L1033 assume !(0 != activate_threads_~tmp___0~0); 3024754#L1033-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3024755#L430 assume !(1 == ~t2_pc~0); 3025236#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 3024589#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3024537#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3024538#L1041 assume !(0 != activate_threads_~tmp___1~0); 3025464#L1041-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3025466#L449 assume !(1 == ~t3_pc~0); 3025314#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 3025480#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3025498#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3025254#L1049 assume !(0 != activate_threads_~tmp___2~0); 3025255#L1049-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3024433#L468 assume !(1 == ~t4_pc~0); 3024434#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 3024443#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3024886#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3024816#L1057 assume !(0 != activate_threads_~tmp___3~0); 3024817#L1057-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3024661#L487 assume !(1 == ~t5_pc~0); 3024391#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 3024663#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3025059#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3025060#L1065 assume !(0 != activate_threads_~tmp___4~0); 3025486#L1065-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 3024833#L506 assume !(1 == ~t6_pc~0); 3024828#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 3024829#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 3025252#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3025165#L1073 assume !(0 != activate_threads_~tmp___5~0); 3025166#L1073-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 3024981#L525 assume !(1 == ~t7_pc~0); 3024906#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 3024984#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 3025499#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3024683#L1081 assume !(0 != activate_threads_~tmp___6~0); 3024684#L1081-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 3024685#L544 assume !(1 == ~t8_pc~0); 3025005#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 3024329#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 3024330#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 3024467#L1089 assume !(0 != activate_threads_~tmp___7~0); 3025293#L1089-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3024842#L921 assume !(1 == ~M_E~0); 3024843#L921-2 assume !(1 == ~T1_E~0); 3024548#L926-1 assume !(1 == ~T2_E~0); 3024549#L931-1 assume !(1 == ~T3_E~0); 3025379#L936-1 assume !(1 == ~T4_E~0); 3025159#L941-1 assume !(1 == ~T5_E~0); 3024839#L946-1 assume !(1 == ~T6_E~0); 3024347#L951-1 assume !(1 == ~T7_E~0); 3024348#L956-1 assume !(1 == ~T8_E~0); 3025256#L961-1 assume !(1 == ~E_1~0); 3024946#L966-1 assume !(1 == ~E_2~0); 3024688#L971-1 assume !(1 == ~E_3~0); 3024689#L976-1 assume !(1 == ~E_4~0); 3025209#L981-1 assume !(1 == ~E_5~0); 3024893#L986-1 assume !(1 == ~E_6~0); 3024803#L991-1 assume !(1 == ~E_7~0); 3024476#L996-1 assume !(1 == ~E_8~0); 3024477#L1001-1 assume { :end_inline_reset_delta_events } true; 3025401#L1262-3 assume true; 3044370#L1262-1 assume !false; 3044361#L1263 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 3044362#L803 [2018-11-18 14:33:05,745 INFO L796 eck$LassoCheckResult]: Loop: 3044362#L803 assume true; 3045347#L681-1 assume !false; 3045346#L682 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 3044351#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 3044349#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 3044346#L672 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 3044347#L686 assume 0 != eval_~tmp~0; 3045316#L686-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 3045313#L694 assume !(0 != eval_~tmp_ndt_1~0); 3045311#L691 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 3045308#L708 assume !(0 != eval_~tmp_ndt_2~0); 3044328#L705 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 3044325#L722 assume !(0 != eval_~tmp_ndt_3~0); 3044326#L719 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 3044480#L736 assume !(0 != eval_~tmp_ndt_4~0); 3044474#L733 assume !(0 == ~t4_st~0); 3044472#L747 assume !(0 == ~t5_st~0); 3044467#L761 assume !(0 == ~t6_st~0); 3044466#L775 assume !(0 == ~t7_st~0); 3045350#L789 assume !(0 == ~t8_st~0); 3044362#L803 [2018-11-18 14:33:05,745 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:33:05,745 INFO L82 PathProgramCache]: Analyzing trace with hash 64602117, now seen corresponding path program 4 times [2018-11-18 14:33:05,745 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:33:05,745 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:33:05,746 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:33:05,746 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:33:05,746 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:33:05,749 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:33:05,753 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:33:05,766 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:33:05,766 INFO L82 PathProgramCache]: Analyzing trace with hash 1661196909, now seen corresponding path program 1 times [2018-11-18 14:33:05,766 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:33:05,767 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:33:05,767 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:33:05,767 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 14:33:05,767 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:33:05,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:33:05,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:33:05,771 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:33:05,771 INFO L82 PathProgramCache]: Analyzing trace with hash -354324367, now seen corresponding path program 1 times [2018-11-18 14:33:05,771 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:33:05,771 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:33:05,772 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:33:05,772 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:33:05,772 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:33:05,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:33:05,838 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:33:05,838 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:33:05,839 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:33:05,920 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 14:33:05,920 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 14:33:05,921 INFO L87 Difference]: Start difference. First operand 150380 states and 185360 transitions. cyclomatic complexity: 35044 Second operand 3 states. [2018-11-18 14:33:06,254 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:33:06,254 INFO L93 Difference]: Finished difference Result 208684 states and 257156 transitions. [2018-11-18 14:33:06,254 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 14:33:06,255 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 208684 states and 257156 transitions. [2018-11-18 14:33:06,707 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 189968 [2018-11-18 14:33:07,009 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 208684 states to 208684 states and 257156 transitions. [2018-11-18 14:33:07,009 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 208684 [2018-11-18 14:33:07,091 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 208684 [2018-11-18 14:33:07,091 INFO L73 IsDeterministic]: Start isDeterministic. Operand 208684 states and 257156 transitions. [2018-11-18 14:33:07,158 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:33:07,158 INFO L705 BuchiCegarLoop]: Abstraction has 208684 states and 257156 transitions. [2018-11-18 14:33:07,235 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 208684 states and 257156 transitions. [2018-11-18 14:33:08,177 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 208684 to 201468. [2018-11-18 14:33:08,177 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 201468 states. [2018-11-18 14:33:08,405 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 201468 states to 201468 states and 248356 transitions. [2018-11-18 14:33:08,405 INFO L728 BuchiCegarLoop]: Abstraction has 201468 states and 248356 transitions. [2018-11-18 14:33:08,405 INFO L608 BuchiCegarLoop]: Abstraction has 201468 states and 248356 transitions. [2018-11-18 14:33:08,405 INFO L442 BuchiCegarLoop]: ======== Iteration 42============ [2018-11-18 14:33:08,405 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 201468 states and 248356 transitions. [2018-11-18 14:33:08,813 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 182752 [2018-11-18 14:33:08,814 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:33:08,814 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:33:08,814 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:33:08,815 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:33:08,815 INFO L794 eck$LassoCheckResult]: Stem: 3383911#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 3383785#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 3383786#L1225 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 3384359#L564 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3383822#L571 assume 1 == ~m_i~0;~m_st~0 := 0; 3383803#L571-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3383486#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3383487#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3384366#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3384066#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3383608#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3383609#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3384350#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 3384227#L611-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3384228#L828 assume !(0 == ~M_E~0); 3384375#L828-2 assume !(0 == ~T1_E~0); 3383941#L833-1 assume !(0 == ~T2_E~0); 3383625#L838-1 assume !(0 == ~T3_E~0); 3383626#L843-1 assume !(0 == ~T4_E~0); 3384479#L848-1 assume !(0 == ~T5_E~0); 3384239#L853-1 assume !(0 == ~T6_E~0); 3383923#L858-1 assume !(0 == ~T7_E~0); 3383407#L863-1 assume !(0 == ~T8_E~0); 3383408#L868-1 assume !(0 == ~E_1~0); 3384178#L873-1 assume !(0 == ~E_2~0); 3384028#L878-1 assume !(0 == ~E_3~0); 3383751#L883-1 assume !(0 == ~E_4~0); 3383752#L888-1 assume !(0 == ~E_5~0); 3384311#L893-1 assume !(0 == ~E_6~0); 3383988#L898-1 assume !(0 == ~E_7~0); 3383895#L903-1 assume !(0 == ~E_8~0); 3383557#L908-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3383558#L392 assume !(1 == ~m_pc~0); 3383966#L392-2 is_master_triggered_~__retres1~0 := 0; 3383971#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3384544#L404 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3384322#L1025 assume !(0 != activate_threads_~tmp~1); 3384323#L1025-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3384161#L411 assume !(1 == ~t1_pc~0); 3384124#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 3383467#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3383468#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3383586#L1033 assume !(0 != activate_threads_~tmp___0~0); 3383834#L1033-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3383835#L430 assume !(1 == ~t2_pc~0); 3384336#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 3383662#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3383610#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3383611#L1041 assume !(0 != activate_threads_~tmp___1~0); 3384577#L1041-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3384579#L449 assume !(1 == ~t3_pc~0); 3384419#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 3384593#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3384619#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3384355#L1049 assume !(0 != activate_threads_~tmp___2~0); 3384356#L1049-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3383506#L468 assume !(1 == ~t4_pc~0); 3383507#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 3383516#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3383978#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3383903#L1057 assume !(0 != activate_threads_~tmp___3~0); 3383904#L1057-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3383736#L487 assume !(1 == ~t5_pc~0); 3383463#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 3383738#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3384147#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3384148#L1065 assume !(0 != activate_threads_~tmp___4~0); 3384604#L1065-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 3383922#L506 assume !(1 == ~t6_pc~0); 3383916#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 3383917#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 3384353#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3384258#L1073 assume !(0 != activate_threads_~tmp___5~0); 3384259#L1073-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 3384068#L525 assume !(1 == ~t7_pc~0); 3383999#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 3384069#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 3384620#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3383757#L1081 assume !(0 != activate_threads_~tmp___6~0); 3383758#L1081-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 3383759#L544 assume !(1 == ~t8_pc~0); 3384089#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 3383401#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 3383402#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 3383539#L1089 assume !(0 != activate_threads_~tmp___7~0); 3384395#L1089-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3383931#L921 assume !(1 == ~M_E~0); 3383932#L921-2 assume !(1 == ~T1_E~0); 3383621#L926-1 assume !(1 == ~T2_E~0); 3383622#L931-1 assume !(1 == ~T3_E~0); 3384477#L936-1 assume !(1 == ~T4_E~0); 3384249#L941-1 assume !(1 == ~T5_E~0); 3383929#L946-1 assume !(1 == ~T6_E~0); 3383419#L951-1 assume !(1 == ~T7_E~0); 3383420#L956-1 assume !(1 == ~T8_E~0); 3384358#L961-1 assume !(1 == ~E_1~0); 3384035#L966-1 assume !(1 == ~E_2~0); 3383762#L971-1 assume !(1 == ~E_3~0); 3383763#L976-1 assume !(1 == ~E_4~0); 3384305#L981-1 assume !(1 == ~E_5~0); 3383986#L986-1 assume !(1 == ~E_6~0); 3383887#L991-1 assume !(1 == ~E_7~0); 3383545#L996-1 assume !(1 == ~E_8~0); 3383546#L1001-1 assume { :end_inline_reset_delta_events } true; 3384511#L1262-3 assume true; 3441377#L1262-1 assume !false; 3439976#L1263 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 3439974#L803 [2018-11-18 14:33:08,815 INFO L796 eck$LassoCheckResult]: Loop: 3439974#L803 assume true; 3439971#L681-1 assume !false; 3439969#L682 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 3439967#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 3439965#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 3439963#L672 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 3439961#L686 assume 0 != eval_~tmp~0; 3439959#L686-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 3439956#L694 assume !(0 != eval_~tmp_ndt_1~0); 3439954#L691 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 3439951#L708 assume !(0 != eval_~tmp_ndt_2~0); 3439949#L705 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 3439946#L722 assume !(0 != eval_~tmp_ndt_3~0); 3439947#L719 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 3440429#L736 assume !(0 != eval_~tmp_ndt_4~0); 3440524#L733 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 3441247#L750 assume !(0 != eval_~tmp_ndt_5~0); 3441245#L747 assume !(0 == ~t5_st~0); 3441240#L761 assume !(0 == ~t6_st~0); 3439981#L775 assume !(0 == ~t7_st~0); 3439979#L789 assume !(0 == ~t8_st~0); 3439974#L803 [2018-11-18 14:33:08,815 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:33:08,815 INFO L82 PathProgramCache]: Analyzing trace with hash 64602117, now seen corresponding path program 5 times [2018-11-18 14:33:08,815 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:33:08,815 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:33:08,816 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:33:08,816 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:33:08,816 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:33:08,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:33:08,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:33:08,835 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:33:08,835 INFO L82 PathProgramCache]: Analyzing trace with hash 1233739064, now seen corresponding path program 1 times [2018-11-18 14:33:08,835 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:33:08,835 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:33:08,836 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:33:08,836 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 14:33:08,836 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:33:08,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:33:08,838 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:33:08,840 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:33:08,840 INFO L82 PathProgramCache]: Analyzing trace with hash -1117878348, now seen corresponding path program 1 times [2018-11-18 14:33:08,840 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:33:08,840 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:33:08,840 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:33:08,841 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:33:08,841 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:33:08,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:33:08,896 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:33:08,896 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:33:08,896 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:33:08,997 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 14:33:08,997 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 14:33:08,998 INFO L87 Difference]: Start difference. First operand 201468 states and 248356 transitions. cyclomatic complexity: 46952 Second operand 3 states. [2018-11-18 14:33:09,544 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:33:09,544 INFO L93 Difference]: Finished difference Result 355572 states and 438100 transitions. [2018-11-18 14:33:09,544 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 14:33:09,544 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 355572 states and 438100 transitions. [2018-11-18 14:33:10,335 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 318256 [2018-11-18 14:33:10,819 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 355572 states to 355572 states and 438100 transitions. [2018-11-18 14:33:10,819 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 355572 [2018-11-18 14:33:10,950 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 355572 [2018-11-18 14:33:10,950 INFO L73 IsDeterministic]: Start isDeterministic. Operand 355572 states and 438100 transitions. [2018-11-18 14:33:11,059 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:33:11,059 INFO L705 BuchiCegarLoop]: Abstraction has 355572 states and 438100 transitions. [2018-11-18 14:33:11,193 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 355572 states and 438100 transitions. [2018-11-18 14:33:12,616 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 355572 to 355572. [2018-11-18 14:33:12,617 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 355572 states. [2018-11-18 14:33:19,080 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 355572 states to 355572 states and 438100 transitions. [2018-11-18 14:33:19,080 INFO L728 BuchiCegarLoop]: Abstraction has 355572 states and 438100 transitions. [2018-11-18 14:33:19,080 INFO L608 BuchiCegarLoop]: Abstraction has 355572 states and 438100 transitions. [2018-11-18 14:33:19,080 INFO L442 BuchiCegarLoop]: ======== Iteration 43============ [2018-11-18 14:33:19,080 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 355572 states and 438100 transitions. [2018-11-18 14:33:19,468 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 318256 [2018-11-18 14:33:19,468 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:33:19,468 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:33:19,469 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:33:19,469 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:33:19,469 INFO L794 eck$LassoCheckResult]: Stem: 3940944#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 3940828#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 3940829#L1225 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 3941376#L564 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3940866#L571 assume 1 == ~m_i~0;~m_st~0 := 0; 3940846#L571-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3940533#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3940534#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3941381#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3941098#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3940654#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3940655#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3941367#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 3941255#L611-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3941256#L828 assume !(0 == ~M_E~0); 3941390#L828-2 assume !(0 == ~T1_E~0); 3940973#L833-1 assume !(0 == ~T2_E~0); 3940671#L838-1 assume !(0 == ~T3_E~0); 3940672#L843-1 assume !(0 == ~T4_E~0); 3941494#L848-1 assume !(0 == ~T5_E~0); 3941267#L853-1 assume !(0 == ~T6_E~0); 3940955#L858-1 assume !(0 == ~T7_E~0); 3940455#L863-1 assume !(0 == ~T8_E~0); 3940456#L868-1 assume !(0 == ~E_1~0); 3941202#L873-1 assume !(0 == ~E_2~0); 3941062#L878-1 assume !(0 == ~E_3~0); 3940795#L883-1 assume !(0 == ~E_4~0); 3940796#L888-1 assume !(0 == ~E_5~0); 3941339#L893-1 assume !(0 == ~E_6~0); 3941022#L898-1 assume !(0 == ~E_7~0); 3940934#L903-1 assume !(0 == ~E_8~0); 3940602#L908-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 3940603#L392 assume !(1 == ~m_pc~0); 3940997#L392-2 is_master_triggered_~__retres1~0 := 0; 3941002#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 3941547#L404 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 3941345#L1025 assume !(0 != activate_threads_~tmp~1); 3941346#L1025-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 3941189#L411 assume !(1 == ~t1_pc~0); 3941155#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 3940517#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 3940518#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 3940632#L1033 assume !(0 != activate_threads_~tmp___0~0); 3940873#L1033-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 3940874#L430 assume !(1 == ~t2_pc~0); 3941355#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 3940713#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 3940656#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 3940657#L1041 assume !(0 != activate_threads_~tmp___1~0); 3941581#L1041-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 3941582#L449 assume !(1 == ~t3_pc~0); 3941434#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 3941594#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 3941609#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 3941372#L1049 assume !(0 != activate_threads_~tmp___2~0); 3941373#L1049-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 3940552#L468 assume !(1 == ~t4_pc~0); 3940553#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 3940562#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 3941009#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 3940940#L1057 assume !(0 != activate_threads_~tmp___3~0); 3940941#L1057-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 3940780#L487 assume !(1 == ~t5_pc~0); 3940511#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 3940782#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 3941175#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 3941176#L1065 assume !(0 != activate_threads_~tmp___4~0); 3941601#L1065-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 3940954#L506 assume !(1 == ~t6_pc~0); 3940949#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 3940950#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 3941370#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 3941283#L1073 assume !(0 != activate_threads_~tmp___5~0); 3941284#L1073-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 3941099#L525 assume !(1 == ~t7_pc~0); 3941032#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 3941101#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 3941610#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 3940801#L1081 assume !(0 != activate_threads_~tmp___6~0); 3940802#L1081-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 3940803#L544 assume !(1 == ~t8_pc~0); 3941122#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 3940449#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 3940450#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 3940584#L1089 assume !(0 != activate_threads_~tmp___7~0); 3941413#L1089-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3940966#L921 assume !(1 == ~M_E~0); 3940967#L921-2 assume !(1 == ~T1_E~0); 3940667#L926-1 assume !(1 == ~T2_E~0); 3940668#L931-1 assume !(1 == ~T3_E~0); 3941492#L936-1 assume !(1 == ~T4_E~0); 3941276#L941-1 assume !(1 == ~T5_E~0); 3940962#L946-1 assume !(1 == ~T6_E~0); 3940467#L951-1 assume !(1 == ~T7_E~0); 3940468#L956-1 assume !(1 == ~T8_E~0); 3941375#L961-1 assume !(1 == ~E_1~0); 3941069#L966-1 assume !(1 == ~E_2~0); 3940806#L971-1 assume !(1 == ~E_3~0); 3940807#L976-1 assume !(1 == ~E_4~0); 3941333#L981-1 assume !(1 == ~E_5~0); 3941020#L986-1 assume !(1 == ~E_6~0); 3940926#L991-1 assume !(1 == ~E_7~0); 3940592#L996-1 assume !(1 == ~E_8~0); 3940593#L1001-1 assume { :end_inline_reset_delta_events } true; 3941517#L1262-3 assume true; 4030779#L1262-1 assume !false; 4030748#L1263 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 4030745#L803 [2018-11-18 14:33:19,469 INFO L796 eck$LassoCheckResult]: Loop: 4030745#L803 assume true; 4030743#L681-1 assume !false; 4030740#L682 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 4030738#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 4030736#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 4030735#L672 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 4030734#L686 assume 0 != eval_~tmp~0; 4030733#L686-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 4030731#L694 assume !(0 != eval_~tmp_ndt_1~0); 4030729#L691 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 4030726#L708 assume !(0 != eval_~tmp_ndt_2~0); 4030724#L705 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 4030721#L722 assume !(0 != eval_~tmp_ndt_3~0); 4030719#L719 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 4030490#L736 assume !(0 != eval_~tmp_ndt_4~0); 4030717#L733 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 4031478#L750 assume !(0 != eval_~tmp_ndt_5~0); 4030764#L747 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 4030761#L764 assume !(0 != eval_~tmp_ndt_6~0); 4030759#L761 assume !(0 == ~t6_st~0); 4030752#L775 assume !(0 == ~t7_st~0); 4030751#L789 assume !(0 == ~t8_st~0); 4030745#L803 [2018-11-18 14:33:19,469 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:33:19,469 INFO L82 PathProgramCache]: Analyzing trace with hash 64602117, now seen corresponding path program 6 times [2018-11-18 14:33:19,469 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:33:19,469 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:33:19,470 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:33:19,470 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:33:19,470 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:33:19,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:33:19,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:33:19,487 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:33:19,488 INFO L82 PathProgramCache]: Analyzing trace with hash -644711264, now seen corresponding path program 1 times [2018-11-18 14:33:19,488 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:33:19,488 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:33:19,488 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:33:19,488 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 14:33:19,489 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:33:19,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:33:19,491 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:33:19,492 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:33:19,492 INFO L82 PathProgramCache]: Analyzing trace with hash -530407004, now seen corresponding path program 1 times [2018-11-18 14:33:19,492 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:33:19,492 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:33:19,493 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:33:19,493 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:33:19,493 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:33:19,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:33:19,535 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:33:19,535 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:33:19,535 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:33:19,616 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 14:33:19,616 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 14:33:19,616 INFO L87 Difference]: Start difference. First operand 355572 states and 438100 transitions. cyclomatic complexity: 82592 Second operand 3 states. [2018-11-18 14:33:20,416 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:33:20,416 INFO L93 Difference]: Finished difference Result 501292 states and 617692 transitions. [2018-11-18 14:33:20,416 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 14:33:20,416 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 501292 states and 617692 transitions. [2018-11-18 14:33:21,605 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 445312 [2018-11-18 14:33:22,362 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 501292 states to 501292 states and 617692 transitions. [2018-11-18 14:33:22,362 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 501292 [2018-11-18 14:33:23,201 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 501292 [2018-11-18 14:33:23,201 INFO L73 IsDeterministic]: Start isDeterministic. Operand 501292 states and 617692 transitions. [2018-11-18 14:33:23,297 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:33:23,298 INFO L705 BuchiCegarLoop]: Abstraction has 501292 states and 617692 transitions. [2018-11-18 14:33:23,447 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 501292 states and 617692 transitions. [2018-11-18 14:33:25,478 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 501292 to 489884. [2018-11-18 14:33:25,478 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 489884 states. [2018-11-18 14:33:27,178 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 489884 states to 489884 states and 604052 transitions. [2018-11-18 14:33:27,179 INFO L728 BuchiCegarLoop]: Abstraction has 489884 states and 604052 transitions. [2018-11-18 14:33:27,179 INFO L608 BuchiCegarLoop]: Abstraction has 489884 states and 604052 transitions. [2018-11-18 14:33:27,179 INFO L442 BuchiCegarLoop]: ======== Iteration 44============ [2018-11-18 14:33:27,179 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 489884 states and 604052 transitions. [2018-11-18 14:33:27,916 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 433904 [2018-11-18 14:33:27,917 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:33:27,917 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:33:27,917 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:33:27,918 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:33:27,918 INFO L794 eck$LassoCheckResult]: Stem: 4797827#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 4797705#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 4797706#L1225 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 4798288#L564 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4797743#L571 assume 1 == ~m_i~0;~m_st~0 := 0; 4797723#L571-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4797405#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4797406#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4798293#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4797990#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 4797529#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 4797530#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 4798278#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 4798152#L611-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4798153#L828 assume !(0 == ~M_E~0); 4798305#L828-2 assume !(0 == ~T1_E~0); 4797856#L833-1 assume !(0 == ~T2_E~0); 4797546#L838-1 assume !(0 == ~T3_E~0); 4797547#L843-1 assume !(0 == ~T4_E~0); 4798420#L848-1 assume !(0 == ~T5_E~0); 4798164#L853-1 assume !(0 == ~T6_E~0); 4797840#L858-1 assume !(0 == ~T7_E~0); 4797327#L863-1 assume !(0 == ~T8_E~0); 4797328#L868-1 assume !(0 == ~E_1~0); 4798100#L873-1 assume !(0 == ~E_2~0); 4797948#L878-1 assume !(0 == ~E_3~0); 4797675#L883-1 assume !(0 == ~E_4~0); 4797676#L888-1 assume !(0 == ~E_5~0); 4798244#L893-1 assume !(0 == ~E_6~0); 4797909#L898-1 assume !(0 == ~E_7~0); 4797810#L903-1 assume !(0 == ~E_8~0); 4797476#L908-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 4797477#L392 assume !(1 == ~m_pc~0); 4797882#L392-2 is_master_triggered_~__retres1~0 := 0; 4797890#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 4798482#L404 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 4798250#L1025 assume !(0 != activate_threads_~tmp~1); 4798251#L1025-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 4798086#L411 assume !(1 == ~t1_pc~0); 4798050#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 4797387#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 4797388#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 4797507#L1033 assume !(0 != activate_threads_~tmp___0~0); 4797753#L1033-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 4797754#L430 assume !(1 == ~t2_pc~0); 4798265#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 4797584#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 4797531#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 4797532#L1041 assume !(0 != activate_threads_~tmp___1~0); 4798520#L1041-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 4798521#L449 assume !(1 == ~t3_pc~0); 4798358#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 4798531#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 4798554#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 4798284#L1049 assume !(0 != activate_threads_~tmp___2~0); 4798285#L1049-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 4797426#L468 assume !(1 == ~t4_pc~0); 4797427#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 4797436#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 4797897#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 4797818#L1057 assume !(0 != activate_threads_~tmp___3~0); 4797819#L1057-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 4797659#L487 assume !(1 == ~t5_pc~0); 4797383#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 4797661#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 4798072#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 4798073#L1065 assume !(0 != activate_threads_~tmp___4~0); 4798539#L1065-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 4797839#L506 assume !(1 == ~t6_pc~0); 4797833#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 4797834#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 4798281#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 4798187#L1073 assume !(0 != activate_threads_~tmp___5~0); 4798188#L1073-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 4797993#L525 assume !(1 == ~t7_pc~0); 4797920#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 4797995#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 4798522#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 4797681#L1081 assume !(0 != activate_threads_~tmp___6~0); 4797682#L1081-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 4797683#L544 assume !(1 == ~t8_pc~0); 4798013#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 4797321#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 4797322#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 4797458#L1089 assume !(0 != activate_threads_~tmp___7~0); 4798336#L1089-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4797847#L921 assume !(1 == ~M_E~0); 4797848#L921-2 assume !(1 == ~T1_E~0); 4797542#L926-1 assume !(1 == ~T2_E~0); 4797543#L931-1 assume !(1 == ~T3_E~0); 4798418#L936-1 assume !(1 == ~T4_E~0); 4798177#L941-1 assume !(1 == ~T5_E~0); 4797845#L946-1 assume !(1 == ~T6_E~0); 4797339#L951-1 assume !(1 == ~T7_E~0); 4797340#L956-1 assume !(1 == ~T8_E~0); 4798287#L961-1 assume !(1 == ~E_1~0); 4797956#L966-1 assume !(1 == ~E_2~0); 4797686#L971-1 assume !(1 == ~E_3~0); 4797687#L976-1 assume !(1 == ~E_4~0); 4798239#L981-1 assume !(1 == ~E_5~0); 4797907#L986-1 assume !(1 == ~E_6~0); 4797805#L991-1 assume !(1 == ~E_7~0); 4797464#L996-1 assume !(1 == ~E_8~0); 4797465#L1001-1 assume { :end_inline_reset_delta_events } true; 4798448#L1262-3 assume true; 4863790#L1262-1 assume !false; 4863780#L1263 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 4863773#L803 [2018-11-18 14:33:27,918 INFO L796 eck$LassoCheckResult]: Loop: 4863773#L803 assume true; 4863764#L681-1 assume !false; 4863757#L682 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 4863751#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 4863743#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 4863732#L672 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 4863726#L686 assume 0 != eval_~tmp~0; 4863720#L686-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 4863711#L694 assume !(0 != eval_~tmp_ndt_1~0); 4863705#L691 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 4863698#L708 assume !(0 != eval_~tmp_ndt_2~0); 4863691#L705 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 4863685#L722 assume !(0 != eval_~tmp_ndt_3~0); 4863464#L719 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 4863462#L736 assume !(0 != eval_~tmp_ndt_4~0); 4863461#L733 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 4863460#L750 assume !(0 != eval_~tmp_ndt_5~0); 4863459#L747 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 4863411#L764 assume !(0 != eval_~tmp_ndt_6~0); 4863457#L761 assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0;eval_~tmp_ndt_7~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 4863801#L778 assume !(0 != eval_~tmp_ndt_7~0); 4863791#L775 assume !(0 == ~t7_st~0); 4863783#L789 assume !(0 == ~t8_st~0); 4863773#L803 [2018-11-18 14:33:27,918 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:33:27,918 INFO L82 PathProgramCache]: Analyzing trace with hash 64602117, now seen corresponding path program 7 times [2018-11-18 14:33:27,918 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:33:27,919 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:33:27,919 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:33:27,919 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:33:27,919 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:33:27,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:33:27,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:33:27,943 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:33:27,943 INFO L82 PathProgramCache]: Analyzing trace with hash 1481186053, now seen corresponding path program 1 times [2018-11-18 14:33:27,944 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:33:27,944 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:33:27,944 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:33:27,944 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:33:27,944 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:33:27,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:33:27,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:33:27,949 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:33:27,949 INFO L82 PathProgramCache]: Analyzing trace with hash 729650817, now seen corresponding path program 1 times [2018-11-18 14:33:27,950 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:33:27,950 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:33:27,950 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:33:27,950 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:33:27,950 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:33:27,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:33:27,992 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:33:27,993 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:33:27,993 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-18 14:33:28,079 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 14:33:28,080 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 14:33:28,080 INFO L87 Difference]: Start difference. First operand 489884 states and 604052 transitions. cyclomatic complexity: 114232 Second operand 3 states. [2018-11-18 14:33:29,946 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:33:29,946 INFO L93 Difference]: Finished difference Result 884632 states and 1088772 transitions. [2018-11-18 14:33:29,947 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 14:33:29,947 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 884632 states and 1088772 transitions. [2018-11-18 14:33:37,653 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 772788 [2018-11-18 14:33:39,342 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 884632 states to 884632 states and 1088772 transitions. [2018-11-18 14:33:39,342 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 884632 [2018-11-18 14:33:39,564 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 884632 [2018-11-18 14:33:39,564 INFO L73 IsDeterministic]: Start isDeterministic. Operand 884632 states and 1088772 transitions. [2018-11-18 14:33:39,789 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:33:39,789 INFO L705 BuchiCegarLoop]: Abstraction has 884632 states and 1088772 transitions. [2018-11-18 14:33:40,084 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 884632 states and 1088772 transitions. [2018-11-18 14:33:45,077 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 884632 to 866120. [2018-11-18 14:33:45,077 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 866120 states. [2018-11-18 14:33:46,259 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 866120 states to 866120 states and 1068124 transitions. [2018-11-18 14:33:46,259 INFO L728 BuchiCegarLoop]: Abstraction has 866120 states and 1068124 transitions. [2018-11-18 14:33:46,259 INFO L608 BuchiCegarLoop]: Abstraction has 866120 states and 1068124 transitions. [2018-11-18 14:33:46,259 INFO L442 BuchiCegarLoop]: ======== Iteration 45============ [2018-11-18 14:33:46,259 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 866120 states and 1068124 transitions. [2018-11-18 14:33:52,470 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 754276 [2018-11-18 14:33:52,471 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:33:52,471 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:33:52,471 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:33:52,471 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:33:52,471 INFO L794 eck$LassoCheckResult]: Stem: 6172357#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 6172231#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 6172232#L1225 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 6172810#L564 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6172271#L571 assume 1 == ~m_i~0;~m_st~0 := 0; 6172251#L571-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6171928#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6171929#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6172818#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6172520#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6172053#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 6172054#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 6172800#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 6172674#L611-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6172675#L828 assume !(0 == ~M_E~0); 6172833#L828-2 assume !(0 == ~T1_E~0); 6172385#L833-1 assume !(0 == ~T2_E~0); 6172070#L838-1 assume !(0 == ~T3_E~0); 6172071#L843-1 assume !(0 == ~T4_E~0); 6172952#L848-1 assume !(0 == ~T5_E~0); 6172686#L853-1 assume !(0 == ~T6_E~0); 6172368#L858-1 assume !(0 == ~T7_E~0); 6171851#L863-1 assume !(0 == ~T8_E~0); 6171852#L868-1 assume !(0 == ~E_1~0); 6172625#L873-1 assume !(0 == ~E_2~0); 6172478#L878-1 assume !(0 == ~E_3~0); 6172200#L883-1 assume !(0 == ~E_4~0); 6172201#L888-1 assume !(0 == ~E_5~0); 6172765#L893-1 assume !(0 == ~E_6~0); 6172434#L898-1 assume !(0 == ~E_7~0); 6172340#L903-1 assume !(0 == ~E_8~0); 6171998#L908-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 6171999#L392 assume !(1 == ~m_pc~0); 6172409#L392-2 is_master_triggered_~__retres1~0 := 0; 6172415#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 6173010#L404 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 6172773#L1025 assume !(0 != activate_threads_~tmp~1); 6172774#L1025-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 6172611#L411 assume !(1 == ~t1_pc~0); 6172577#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 6171910#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 6171911#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 6172029#L1033 assume !(0 != activate_threads_~tmp___0~0); 6172278#L1033-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 6172279#L430 assume !(1 == ~t2_pc~0); 6172786#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 6172109#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 6172055#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 6172056#L1041 assume !(0 != activate_threads_~tmp___1~0); 6173049#L1041-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 6173050#L449 assume !(1 == ~t3_pc~0); 6172881#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 6173060#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 6173079#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 6172806#L1049 assume !(0 != activate_threads_~tmp___2~0); 6172807#L1049-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 6171947#L468 assume !(1 == ~t4_pc~0); 6171948#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 6171957#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 6172422#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 6172349#L1057 assume !(0 != activate_threads_~tmp___3~0); 6172350#L1057-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 6172184#L487 assume !(1 == ~t5_pc~0); 6171906#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 6172187#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 6172597#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 6172598#L1065 assume !(0 != activate_threads_~tmp___4~0); 6173069#L1065-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 6172367#L506 assume !(1 == ~t6_pc~0); 6172361#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 6172362#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 6172803#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 6172710#L1073 assume !(0 != activate_threads_~tmp___5~0); 6172711#L1073-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 6172522#L525 assume !(1 == ~t7_pc~0); 6172445#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 6172524#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 6173051#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 6172206#L1081 assume !(0 != activate_threads_~tmp___6~0); 6172207#L1081-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 6172208#L544 assume !(1 == ~t8_pc~0); 6172544#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 6171845#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 6171846#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 6171979#L1089 assume !(0 != activate_threads_~tmp___7~0); 6172859#L1089-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6172376#L921 assume !(1 == ~M_E~0); 6172377#L921-2 assume !(1 == ~T1_E~0); 6172066#L926-1 assume !(1 == ~T2_E~0); 6172067#L931-1 assume !(1 == ~T3_E~0); 6172950#L936-1 assume !(1 == ~T4_E~0); 6172702#L941-1 assume !(1 == ~T5_E~0); 6172374#L946-1 assume !(1 == ~T6_E~0); 6171862#L951-1 assume !(1 == ~T7_E~0); 6171863#L956-1 assume !(1 == ~T8_E~0); 6172809#L961-1 assume !(1 == ~E_1~0); 6172488#L966-1 assume !(1 == ~E_2~0); 6172211#L971-1 assume !(1 == ~E_3~0); 6172212#L976-1 assume !(1 == ~E_4~0); 6172761#L981-1 assume !(1 == ~E_5~0); 6172432#L986-1 assume !(1 == ~E_6~0); 6172334#L991-1 assume !(1 == ~E_7~0); 6171985#L996-1 assume !(1 == ~E_8~0); 6171986#L1001-1 assume { :end_inline_reset_delta_events } true; 6172978#L1262-3 assume true; 6332242#L1262-1 assume !false; 6332217#L1263 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 6332215#L803 [2018-11-18 14:33:52,471 INFO L796 eck$LassoCheckResult]: Loop: 6332215#L803 assume true; 6332213#L681-1 assume !false; 6332211#L682 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 6332209#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 6332206#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 6332205#L672 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 6332202#L686 assume 0 != eval_~tmp~0; 6332200#L686-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 6332197#L694 assume !(0 != eval_~tmp_ndt_1~0); 6332198#L691 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 6333737#L708 assume !(0 != eval_~tmp_ndt_2~0); 6333738#L705 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 6372128#L722 assume !(0 != eval_~tmp_ndt_3~0); 6372126#L719 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 6371862#L736 assume !(0 != eval_~tmp_ndt_4~0); 6372125#L733 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 6376977#L750 assume !(0 != eval_~tmp_ndt_5~0); 6376975#L747 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 6368900#L764 assume !(0 != eval_~tmp_ndt_6~0); 6376971#L761 assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0;eval_~tmp_ndt_7~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 6376969#L778 assume !(0 != eval_~tmp_ndt_7~0); 6332225#L775 assume 0 == ~t7_st~0;havoc eval_~tmp_ndt_8~0;eval_~tmp_ndt_8~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 6332222#L792 assume !(0 != eval_~tmp_ndt_8~0); 6332220#L789 assume !(0 == ~t8_st~0); 6332215#L803 [2018-11-18 14:33:52,471 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:33:52,472 INFO L82 PathProgramCache]: Analyzing trace with hash 64602117, now seen corresponding path program 8 times [2018-11-18 14:33:52,472 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:33:52,472 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:33:52,472 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:33:52,472 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:33:52,472 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:33:52,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:33:52,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:33:52,491 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:33:52,491 INFO L82 PathProgramCache]: Analyzing trace with hash -1328108845, now seen corresponding path program 1 times [2018-11-18 14:33:52,492 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:33:52,492 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:33:52,492 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:33:52,492 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 14:33:52,492 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:33:52,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:33:52,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:33:52,496 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:33:52,496 INFO L82 PathProgramCache]: Analyzing trace with hash 1144102615, now seen corresponding path program 1 times [2018-11-18 14:33:52,496 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:33:52,496 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:33:52,496 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:33:52,497 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:33:52,497 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:33:52,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-18 14:33:52,537 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-18 14:33:52,537 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-18 14:33:52,537 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-18 14:33:52,690 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-18 14:33:52,690 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-18 14:33:52,690 INFO L87 Difference]: Start difference. First operand 866120 states and 1068124 transitions. cyclomatic complexity: 202068 Second operand 3 states. [2018-11-18 14:33:55,426 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-18 14:33:55,426 INFO L93 Difference]: Finished difference Result 1250971 states and 1543575 transitions. [2018-11-18 14:33:55,426 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-18 14:33:55,426 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1250971 states and 1543575 transitions. [2018-11-18 14:33:59,261 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 1081455 [2018-11-18 14:34:01,250 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1250971 states to 1250971 states and 1543575 transitions. [2018-11-18 14:34:01,250 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1250971 [2018-11-18 14:34:02,547 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1250971 [2018-11-18 14:34:02,548 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1250971 states and 1543575 transitions. [2018-11-18 14:34:02,819 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2018-11-18 14:34:02,819 INFO L705 BuchiCegarLoop]: Abstraction has 1250971 states and 1543575 transitions. [2018-11-18 14:34:03,293 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1250971 states and 1543575 transitions. [2018-11-18 14:34:19,467 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1250971 to 1250971. [2018-11-18 14:34:19,468 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1250971 states. [2018-11-18 14:34:21,910 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1250971 states to 1250971 states and 1543575 transitions. [2018-11-18 14:34:21,910 INFO L728 BuchiCegarLoop]: Abstraction has 1250971 states and 1543575 transitions. [2018-11-18 14:34:21,910 INFO L608 BuchiCegarLoop]: Abstraction has 1250971 states and 1543575 transitions. [2018-11-18 14:34:21,910 INFO L442 BuchiCegarLoop]: ======== Iteration 46============ [2018-11-18 14:34:21,910 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1250971 states and 1543575 transitions. [2018-11-18 14:34:25,186 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 1081455 [2018-11-18 14:34:25,186 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2018-11-18 14:34:25,186 INFO L119 BuchiIsEmpty]: Starting construction of run [2018-11-18 14:34:25,187 INFO L866 BuchiCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:34:25,187 INFO L867 BuchiCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-18 14:34:25,187 INFO L794 eck$LassoCheckResult]: Stem: 8289447#ULTIMATE.startENTRY assume { :begin_inline_ULTIMATE.init } true;~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 8289324#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res;havoc main_~__retres1~10;havoc main_~__retres1~10;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 8289325#L1225 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20, start_simulation_#t~ret21, start_simulation_~kernel_st~0, start_simulation_~tmp~3, start_simulation_~tmp___0~1;havoc start_simulation_~kernel_st~0;havoc start_simulation_~tmp~3;havoc start_simulation_~tmp___0~1;start_simulation_~kernel_st~0 := 0;assume { :begin_inline_update_channels } true; 8289896#L564 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8289362#L571 assume 1 == ~m_i~0;~m_st~0 := 0; 8289343#L571-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8289028#L576-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8289029#L581-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8289900#L586-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8289612#L591-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8289152#L596-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 8289153#L601-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 8289886#L606-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 8289768#L611-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8289769#L828 assume !(0 == ~M_E~0); 8289911#L828-2 assume !(0 == ~T1_E~0); 8289476#L833-1 assume !(0 == ~T2_E~0); 8289169#L838-1 assume !(0 == ~T3_E~0); 8289170#L843-1 assume !(0 == ~T4_E~0); 8290017#L848-1 assume !(0 == ~T5_E~0); 8289780#L853-1 assume !(0 == ~T6_E~0); 8289459#L858-1 assume !(0 == ~T7_E~0); 8288950#L863-1 assume !(0 == ~T8_E~0); 8288951#L868-1 assume !(0 == ~E_1~0); 8289717#L873-1 assume !(0 == ~E_2~0); 8289570#L878-1 assume !(0 == ~E_3~0); 8289292#L883-1 assume !(0 == ~E_4~0); 8289293#L888-1 assume !(0 == ~E_5~0); 8289853#L893-1 assume !(0 == ~E_6~0); 8289526#L898-1 assume !(0 == ~E_7~0); 8289431#L903-1 assume !(0 == ~E_8~0); 8289100#L908-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret10, activate_threads_#t~ret11, activate_threads_#t~ret12, activate_threads_#t~ret13, activate_threads_#t~ret14, activate_threads_#t~ret15, activate_threads_#t~ret16, activate_threads_#t~ret17, activate_threads_#t~ret18, activate_threads_~tmp~1, activate_threads_~tmp___0~0, activate_threads_~tmp___1~0, activate_threads_~tmp___2~0, activate_threads_~tmp___3~0, activate_threads_~tmp___4~0, activate_threads_~tmp___5~0, activate_threads_~tmp___6~0, activate_threads_~tmp___7~0;havoc activate_threads_~tmp~1;havoc activate_threads_~tmp___0~0;havoc activate_threads_~tmp___1~0;havoc activate_threads_~tmp___2~0;havoc activate_threads_~tmp___3~0;havoc activate_threads_~tmp___4~0;havoc activate_threads_~tmp___5~0;havoc activate_threads_~tmp___6~0;havoc activate_threads_~tmp___7~0;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res;havoc is_master_triggered_~__retres1~0;havoc is_master_triggered_~__retres1~0; 8289101#L392 assume !(1 == ~m_pc~0); 8289500#L392-2 is_master_triggered_~__retres1~0 := 0; 8289507#L403 is_master_triggered_#res := is_master_triggered_~__retres1~0; 8290073#L404 activate_threads_#t~ret10 := is_master_triggered_#res;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1 := activate_threads_#t~ret10;havoc activate_threads_#t~ret10; 8289860#L1025 assume !(0 != activate_threads_~tmp~1); 8289861#L1025-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res;havoc is_transmit1_triggered_~__retres1~1;havoc is_transmit1_triggered_~__retres1~1; 8289705#L411 assume !(1 == ~t1_pc~0); 8289670#L411-2 is_transmit1_triggered_~__retres1~1 := 0; 8289009#L422 is_transmit1_triggered_#res := is_transmit1_triggered_~__retres1~1; 8289010#L423 activate_threads_#t~ret11 := is_transmit1_triggered_#res;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0 := activate_threads_#t~ret11;havoc activate_threads_#t~ret11; 8289131#L1033 assume !(0 != activate_threads_~tmp___0~0); 8289371#L1033-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res;havoc is_transmit2_triggered_~__retres1~2;havoc is_transmit2_triggered_~__retres1~2; 8289372#L430 assume !(1 == ~t2_pc~0); 8289873#L430-2 is_transmit2_triggered_~__retres1~2 := 0; 8289207#L441 is_transmit2_triggered_#res := is_transmit2_triggered_~__retres1~2; 8289154#L442 activate_threads_#t~ret12 := is_transmit2_triggered_#res;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0 := activate_threads_#t~ret12;havoc activate_threads_#t~ret12; 8289155#L1041 assume !(0 != activate_threads_~tmp___1~0); 8290104#L1041-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res;havoc is_transmit3_triggered_~__retres1~3;havoc is_transmit3_triggered_~__retres1~3; 8290105#L449 assume !(1 == ~t3_pc~0); 8289956#L449-2 is_transmit3_triggered_~__retres1~3 := 0; 8290115#L460 is_transmit3_triggered_#res := is_transmit3_triggered_~__retres1~3; 8290139#L461 activate_threads_#t~ret13 := is_transmit3_triggered_#res;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0 := activate_threads_#t~ret13;havoc activate_threads_#t~ret13; 8289892#L1049 assume !(0 != activate_threads_~tmp___2~0); 8289893#L1049-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res;havoc is_transmit4_triggered_~__retres1~4;havoc is_transmit4_triggered_~__retres1~4; 8289048#L468 assume !(1 == ~t4_pc~0); 8289049#L468-2 is_transmit4_triggered_~__retres1~4 := 0; 8289058#L479 is_transmit4_triggered_#res := is_transmit4_triggered_~__retres1~4; 8289514#L480 activate_threads_#t~ret14 := is_transmit4_triggered_#res;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0 := activate_threads_#t~ret14;havoc activate_threads_#t~ret14; 8289439#L1057 assume !(0 != activate_threads_~tmp___3~0); 8289440#L1057-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res;havoc is_transmit5_triggered_~__retres1~5;havoc is_transmit5_triggered_~__retres1~5; 8289277#L487 assume !(1 == ~t5_pc~0); 8289005#L487-2 is_transmit5_triggered_~__retres1~5 := 0; 8289279#L498 is_transmit5_triggered_#res := is_transmit5_triggered_~__retres1~5; 8289692#L499 activate_threads_#t~ret15 := is_transmit5_triggered_#res;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0 := activate_threads_#t~ret15;havoc activate_threads_#t~ret15; 8289693#L1065 assume !(0 != activate_threads_~tmp___4~0); 8290124#L1065-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res;havoc is_transmit6_triggered_~__retres1~6;havoc is_transmit6_triggered_~__retres1~6; 8289458#L506 assume !(1 == ~t6_pc~0); 8289452#L506-2 is_transmit6_triggered_~__retres1~6 := 0; 8289453#L517 is_transmit6_triggered_#res := is_transmit6_triggered_~__retres1~6; 8289889#L518 activate_threads_#t~ret16 := is_transmit6_triggered_#res;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0 := activate_threads_#t~ret16;havoc activate_threads_#t~ret16; 8289804#L1073 assume !(0 != activate_threads_~tmp___5~0); 8289805#L1073-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res;havoc is_transmit7_triggered_~__retres1~7;havoc is_transmit7_triggered_~__retres1~7; 8289615#L525 assume !(1 == ~t7_pc~0); 8289536#L525-2 is_transmit7_triggered_~__retres1~7 := 0; 8289616#L536 is_transmit7_triggered_#res := is_transmit7_triggered_~__retres1~7; 8290147#L537 activate_threads_#t~ret17 := is_transmit7_triggered_#res;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0 := activate_threads_#t~ret17;havoc activate_threads_#t~ret17; 8289298#L1081 assume !(0 != activate_threads_~tmp___6~0); 8289299#L1081-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res;havoc is_transmit8_triggered_~__retres1~8;havoc is_transmit8_triggered_~__retres1~8; 8289300#L544 assume !(1 == ~t8_pc~0); 8289635#L544-2 is_transmit8_triggered_~__retres1~8 := 0; 8288944#L555 is_transmit8_triggered_#res := is_transmit8_triggered_~__retres1~8; 8288945#L556 activate_threads_#t~ret18 := is_transmit8_triggered_#res;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0 := activate_threads_#t~ret18;havoc activate_threads_#t~ret18; 8289081#L1089 assume !(0 != activate_threads_~tmp___7~0); 8289937#L1089-2 assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8289467#L921 assume !(1 == ~M_E~0); 8289468#L921-2 assume !(1 == ~T1_E~0); 8289165#L926-1 assume !(1 == ~T2_E~0); 8289166#L931-1 assume !(1 == ~T3_E~0); 8290015#L936-1 assume !(1 == ~T4_E~0); 8289790#L941-1 assume !(1 == ~T5_E~0); 8289465#L946-1 assume !(1 == ~T6_E~0); 8288961#L951-1 assume !(1 == ~T7_E~0); 8288962#L956-1 assume !(1 == ~T8_E~0); 8289895#L961-1 assume !(1 == ~E_1~0); 8289578#L966-1 assume !(1 == ~E_2~0); 8289305#L971-1 assume !(1 == ~E_3~0); 8289306#L976-1 assume !(1 == ~E_4~0); 8289849#L981-1 assume !(1 == ~E_5~0); 8289524#L986-1 assume !(1 == ~E_6~0); 8289426#L991-1 assume !(1 == ~E_7~0); 8289087#L996-1 assume !(1 == ~E_8~0); 8289088#L1001-1 assume { :end_inline_reset_delta_events } true; 8290046#L1262-3 assume true; 8520828#L1262-1 assume !false; 8520823#L1263 start_simulation_~kernel_st~0 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret0, eval_#t~nondet1, eval_~tmp_ndt_1~0, eval_#t~nondet2, eval_~tmp_ndt_2~0, eval_#t~nondet3, eval_~tmp_ndt_3~0, eval_#t~nondet4, eval_~tmp_ndt_4~0, eval_#t~nondet5, eval_~tmp_ndt_5~0, eval_#t~nondet6, eval_~tmp_ndt_6~0, eval_#t~nondet7, eval_~tmp_ndt_7~0, eval_#t~nondet8, eval_~tmp_ndt_8~0, eval_#t~nondet9, eval_~tmp_ndt_9~0, eval_~tmp~0;havoc eval_~tmp~0; 8520820#L803 [2018-11-18 14:34:25,187 INFO L796 eck$LassoCheckResult]: Loop: 8520820#L803 assume true; 8520818#L681-1 assume !false; 8520816#L682 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res;havoc exists_runnable_thread_~__retres1~9;havoc exists_runnable_thread_~__retres1~9; 8520815#L624 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9 := 1; 8520814#L671 exists_runnable_thread_#res := exists_runnable_thread_~__retres1~9; 8520813#L672 eval_#t~ret0 := exists_runnable_thread_#res;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0 := eval_#t~ret0;havoc eval_#t~ret0; 8520812#L686 assume 0 != eval_~tmp~0; 8520811#L686-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0;eval_~tmp_ndt_1~0 := eval_#t~nondet1;havoc eval_#t~nondet1; 8520808#L694 assume !(0 != eval_~tmp_ndt_1~0); 8520804#L691 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0;eval_~tmp_ndt_2~0 := eval_#t~nondet2;havoc eval_#t~nondet2; 8520801#L708 assume !(0 != eval_~tmp_ndt_2~0); 8520799#L705 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0;eval_~tmp_ndt_3~0 := eval_#t~nondet3;havoc eval_#t~nondet3; 8520796#L722 assume !(0 != eval_~tmp_ndt_3~0); 8520794#L719 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0;eval_~tmp_ndt_4~0 := eval_#t~nondet4;havoc eval_#t~nondet4; 8520752#L736 assume !(0 != eval_~tmp_ndt_4~0); 8517095#L733 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0;eval_~tmp_ndt_5~0 := eval_#t~nondet5;havoc eval_#t~nondet5; 8517090#L750 assume !(0 != eval_~tmp_ndt_5~0); 8517088#L747 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0;eval_~tmp_ndt_6~0 := eval_#t~nondet6;havoc eval_#t~nondet6; 8517084#L764 assume !(0 != eval_~tmp_ndt_6~0); 8517082#L761 assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0;eval_~tmp_ndt_7~0 := eval_#t~nondet7;havoc eval_#t~nondet7; 8517079#L778 assume !(0 != eval_~tmp_ndt_7~0); 8517077#L775 assume 0 == ~t7_st~0;havoc eval_~tmp_ndt_8~0;eval_~tmp_ndt_8~0 := eval_#t~nondet8;havoc eval_#t~nondet8; 8452191#L792 assume !(0 != eval_~tmp_ndt_8~0); 8517076#L789 assume 0 == ~t8_st~0;havoc eval_~tmp_ndt_9~0;eval_~tmp_ndt_9~0 := eval_#t~nondet9;havoc eval_#t~nondet9; 8520824#L806 assume !(0 != eval_~tmp_ndt_9~0); 8520820#L803 [2018-11-18 14:34:25,187 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:34:25,187 INFO L82 PathProgramCache]: Analyzing trace with hash 64602117, now seen corresponding path program 9 times [2018-11-18 14:34:25,187 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:34:25,187 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:34:25,188 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:34:25,188 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:34:25,188 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:34:25,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:34:25,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:34:25,205 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:34:25,206 INFO L82 PathProgramCache]: Analyzing trace with hash 1778300114, now seen corresponding path program 1 times [2018-11-18 14:34:25,206 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:34:25,206 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:34:25,206 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:34:25,206 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-18 14:34:25,207 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:34:25,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:34:25,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:34:25,211 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-18 14:34:25,211 INFO L82 PathProgramCache]: Analyzing trace with hash 1107444046, now seen corresponding path program 1 times [2018-11-18 14:34:25,211 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-18 14:34:25,211 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-18 14:34:25,211 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:34:25,212 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-18 14:34:25,212 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-18 14:34:25,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:34:25,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-18 14:34:25,917 WARN L180 SmtUtils]: Spent 548.00 ms on a formula simplification. DAG size of input: 281 DAG size of output: 186 [2018-11-18 14:34:26,048 WARN L180 SmtUtils]: Spent 129.00 ms on a formula simplification that was a NOOP. DAG size: 148 [2018-11-18 14:34:26,081 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 18.11 02:34:26 BoogieIcfgContainer [2018-11-18 14:34:26,082 INFO L132 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2018-11-18 14:34:26,082 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-18 14:34:26,082 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-18 14:34:26,082 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-18 14:34:26,083 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 18.11 02:32:29" (3/4) ... [2018-11-18 14:34:26,085 INFO L141 WitnessPrinter]: Generating witness for non-termination counterexample [2018-11-18 14:34:26,145 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_a1d43ee8-d7c4-46fe-b4be-e0cabd484ca0/bin-2019/uautomizer/witness.graphml [2018-11-18 14:34:26,145 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-18 14:34:26,145 INFO L168 Benchmark]: Toolchain (without parser) took 118371.50 ms. Allocated memory was 1.0 GB in the beginning and 9.9 GB in the end (delta: 8.9 GB). Free memory was 958.2 MB in the beginning and 2.7 GB in the end (delta: -1.7 GB). Peak memory consumption was 7.2 GB. Max. memory is 11.5 GB. [2018-11-18 14:34:26,146 INFO L168 Benchmark]: CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 985.6 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-18 14:34:26,146 INFO L168 Benchmark]: CACSL2BoogieTranslator took 286.49 ms. Allocated memory is still 1.0 GB. Free memory was 958.2 MB in the beginning and 934.0 MB in the end (delta: 24.2 MB). Peak memory consumption was 24.2 MB. Max. memory is 11.5 GB. [2018-11-18 14:34:26,146 INFO L168 Benchmark]: Boogie Procedure Inliner took 96.83 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 148.4 MB). Free memory was 934.0 MB in the beginning and 1.1 GB in the end (delta: -202.1 MB). Peak memory consumption was 15.3 MB. Max. memory is 11.5 GB. [2018-11-18 14:34:26,147 INFO L168 Benchmark]: Boogie Preprocessor took 57.15 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 10.0 MB). Peak memory consumption was 10.0 MB. Max. memory is 11.5 GB. [2018-11-18 14:34:26,147 INFO L168 Benchmark]: RCFGBuilder took 1223.83 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 941.8 MB in the end (delta: 184.2 MB). Peak memory consumption was 184.2 MB. Max. memory is 11.5 GB. [2018-11-18 14:34:26,147 INFO L168 Benchmark]: BuchiAutomizer took 116641.19 ms. Allocated memory was 1.2 GB in the beginning and 9.9 GB in the end (delta: 8.8 GB). Free memory was 941.8 MB in the beginning and 2.7 GB in the end (delta: -1.7 GB). Peak memory consumption was 7.0 GB. Max. memory is 11.5 GB. [2018-11-18 14:34:26,147 INFO L168 Benchmark]: Witness Printer took 62.88 ms. Allocated memory is still 9.9 GB. Free memory was 2.7 GB in the beginning and 2.7 GB in the end (delta: 53.0 kB). Peak memory consumption was 53.0 kB. Max. memory is 11.5 GB. [2018-11-18 14:34:26,149 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.16 ms. Allocated memory is still 1.0 GB. Free memory is still 985.6 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 286.49 ms. Allocated memory is still 1.0 GB. Free memory was 958.2 MB in the beginning and 934.0 MB in the end (delta: 24.2 MB). Peak memory consumption was 24.2 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 96.83 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 148.4 MB). Free memory was 934.0 MB in the beginning and 1.1 GB in the end (delta: -202.1 MB). Peak memory consumption was 15.3 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 57.15 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 10.0 MB). Peak memory consumption was 10.0 MB. Max. memory is 11.5 GB. * RCFGBuilder took 1223.83 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 941.8 MB in the end (delta: 184.2 MB). Peak memory consumption was 184.2 MB. Max. memory is 11.5 GB. * BuchiAutomizer took 116641.19 ms. Allocated memory was 1.2 GB in the beginning and 9.9 GB in the end (delta: 8.8 GB). Free memory was 941.8 MB in the beginning and 2.7 GB in the end (delta: -1.7 GB). Peak memory consumption was 7.0 GB. Max. memory is 11.5 GB. * Witness Printer took 62.88 ms. Allocated memory is still 9.9 GB. Free memory was 2.7 GB in the beginning and 2.7 GB in the end (delta: 53.0 kB). Peak memory consumption was 53.0 kB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 46 terminating modules (45 trivial, 1 deterministic, 0 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function -1 * M_E + 1 and consists of 3 locations. 45 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 1250971 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 116.5s and 46 iterations. TraceHistogramMax:2. Analysis of lassos took 8.3s. Construction of modules took 2.2s. Büchi inclusion checks took 10.4s. Highest rank in rank-based complementation 3. Minimization of det autom 43. Minimization of nondet autom 3. Automata minimization 48.6s AutomataMinimizationTime, 46 MinimizatonAttempts, 264379 StatesRemovedByMinimization, 26 NontrivialMinimizations. Non-live state removal took 28.6s Buchi closure took 3.1s. Biggest automaton had 1250971 states and ocurred in iteration 45. Nontrivial modules had stage [1, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 66717 SDtfs, 71465 SDslu, 59365 SDs, 0 SdLazy, 1599 SolverSat, 783 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 2.2s Time LassoAnalysisResults: nont1 unkn0 SFLI13 SFLT0 conc8 concLT1 SILN2 SILU0 SILI21 SILT0 lasso0 LassoPreprocessingBenchmarks: Lassos: inital300 mio100 ax100 hnf100 lsp3 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq209 hnf86 smp100 dnf189 smp63 tf108 neg92 sie116 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 2ms VariablesStem: 0 VariablesLoop: 1 DisjunctsStem: 1 DisjunctsLoop: 2 SupportingInvariants: 0 MotzkinApplications: 4 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 5 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 1 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.1s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - FixpointNonTerminationResult [Line: 681]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite execution State at position 0 is {} State at position 1 is {E_7=2, t3_st=0, __retres1=0, t5_i=1, __retres1=0, kernel_st=1, \result=0, E_3=2, T6_E=2, t7_i=1, tmp_ndt_8=0, tmp_ndt_4=0, \result=0, __retres1=0, m_st=0, t6_pc=0, tmp___2=0, t3_pc=0, \result=0, m_pc=0, tmp___6=0, T8_E=2, t6_st=0, E_6=2, __retres1=0, \result=0, T2_E=2, t8_i=1, t5_st=0, __retres1=1, E_2=2, t7_pc=0, tmp=0, M_E=2, tmp_ndt_3=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3dcf77e9=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7a7e3644=0, T4_E=2, t4_st=0, t3_i=1, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3c487e1b=0, t8_pc=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3f847307=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@321374a3=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@3be165f3=0, t5_pc=0, t7_st=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@30a6a9b5=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4f61aee4=0, \result=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5361e3c4=0, tmp_ndt_7=0, tmp___3=0, t1_i=1, tmp___7=0, __retres1=0, T7_E=2, tmp=1, t2_st=0, t4_i=1, t8_st=0, t4_pc=0, E_5=2, \result=0, E_1=2, tmp_ndt_2=0, \result=0, __retres1=0, tmp_ndt_6=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@310d1ea9=0, tmp___0=0, tmp=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7ec41c2=0, t6_i=1, tmp___4=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@6869625e=0, \result=0, __retres1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@28a028c1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@73c0fa5d=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7fa1edc5=0, \result=0, E_8=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@4da8ebe2=0, tmp___0=0, t1_pc=0, E_4=2, T1_E=2, tmp_ndt_1=0, T5_E=2, t2_i=1, tmp_ndt_9=0, m_i=1, t1_st=0, tmp_ndt_5=0, __retres1=0, t2_pc=0, __retres1=0, tmp___1=0, \result=0, T3_E=2, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@5606f0f1=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@a936b45=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@df6c3c=0, \result=1, tmp___5=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@7cd3aa85=0, org.eclipse.cdt.internal.core.dom.parser.c.CASTFunctionCallExpression@d5dd0a9=0} - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 681]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L15] int m_pc = 0; [L16] int t1_pc = 0; [L17] int t2_pc = 0; [L18] int t3_pc = 0; [L19] int t4_pc = 0; [L20] int t5_pc = 0; [L21] int t6_pc = 0; [L22] int t7_pc = 0; [L23] int t8_pc = 0; [L24] int m_st ; [L25] int t1_st ; [L26] int t2_st ; [L27] int t3_st ; [L28] int t4_st ; [L29] int t5_st ; [L30] int t6_st ; [L31] int t7_st ; [L32] int t8_st ; [L33] int m_i ; [L34] int t1_i ; [L35] int t2_i ; [L36] int t3_i ; [L37] int t4_i ; [L38] int t5_i ; [L39] int t6_i ; [L40] int t7_i ; [L41] int t8_i ; [L42] int M_E = 2; [L43] int T1_E = 2; [L44] int T2_E = 2; [L45] int T3_E = 2; [L46] int T4_E = 2; [L47] int T5_E = 2; [L48] int T6_E = 2; [L49] int T7_E = 2; [L50] int T8_E = 2; [L51] int E_1 = 2; [L52] int E_2 = 2; [L53] int E_3 = 2; [L54] int E_4 = 2; [L55] int E_5 = 2; [L56] int E_6 = 2; [L57] int E_7 = 2; [L58] int E_8 = 2; [L1307] int __retres1 ; [L1311] CALL init_model() [L1215] m_i = 1 [L1216] t1_i = 1 [L1217] t2_i = 1 [L1218] t3_i = 1 [L1219] t4_i = 1 [L1220] t5_i = 1 [L1221] t6_i = 1 [L1222] t7_i = 1 [L1223] RET t8_i = 1 [L1311] init_model() [L1312] CALL start_simulation() [L1248] int kernel_st ; [L1249] int tmp ; [L1250] int tmp___0 ; [L1254] kernel_st = 0 [L1255] FCALL update_channels() [L1256] CALL init_threads() [L571] COND TRUE m_i == 1 [L572] m_st = 0 [L576] COND TRUE t1_i == 1 [L577] t1_st = 0 [L581] COND TRUE t2_i == 1 [L582] t2_st = 0 [L586] COND TRUE t3_i == 1 [L587] t3_st = 0 [L591] COND TRUE t4_i == 1 [L592] t4_st = 0 [L596] COND TRUE t5_i == 1 [L597] t5_st = 0 [L601] COND TRUE t6_i == 1 [L602] t6_st = 0 [L606] COND TRUE t7_i == 1 [L607] t7_st = 0 [L611] COND TRUE t8_i == 1 [L612] RET t8_st = 0 [L1256] init_threads() [L1257] CALL fire_delta_events() [L828] COND FALSE !(M_E == 0) [L833] COND FALSE !(T1_E == 0) [L838] COND FALSE !(T2_E == 0) [L843] COND FALSE !(T3_E == 0) [L848] COND FALSE !(T4_E == 0) [L853] COND FALSE !(T5_E == 0) [L858] COND FALSE !(T6_E == 0) [L863] COND FALSE !(T7_E == 0) [L868] COND FALSE !(T8_E == 0) [L873] COND FALSE !(E_1 == 0) [L878] COND FALSE !(E_2 == 0) [L883] COND FALSE !(E_3 == 0) [L888] COND FALSE !(E_4 == 0) [L893] COND FALSE !(E_5 == 0) [L898] COND FALSE !(E_6 == 0) [L903] COND FALSE !(E_7 == 0) [L908] COND FALSE, RET !(E_8 == 0) [L1257] fire_delta_events() [L1258] CALL activate_threads() [L1011] int tmp ; [L1012] int tmp___0 ; [L1013] int tmp___1 ; [L1014] int tmp___2 ; [L1015] int tmp___3 ; [L1016] int tmp___4 ; [L1017] int tmp___5 ; [L1018] int tmp___6 ; [L1019] int tmp___7 ; [L1023] CALL, EXPR is_master_triggered() [L389] int __retres1 ; [L392] COND FALSE !(m_pc == 1) [L402] __retres1 = 0 [L404] RET return (__retres1); [L1023] EXPR is_master_triggered() [L1023] tmp = is_master_triggered() [L1025] COND FALSE !(\read(tmp)) [L1031] CALL, EXPR is_transmit1_triggered() [L408] int __retres1 ; [L411] COND FALSE !(t1_pc == 1) [L421] __retres1 = 0 [L423] RET return (__retres1); [L1031] EXPR is_transmit1_triggered() [L1031] tmp___0 = is_transmit1_triggered() [L1033] COND FALSE !(\read(tmp___0)) [L1039] CALL, EXPR is_transmit2_triggered() [L427] int __retres1 ; [L430] COND FALSE !(t2_pc == 1) [L440] __retres1 = 0 [L442] RET return (__retres1); [L1039] EXPR is_transmit2_triggered() [L1039] tmp___1 = is_transmit2_triggered() [L1041] COND FALSE !(\read(tmp___1)) [L1047] CALL, EXPR is_transmit3_triggered() [L446] int __retres1 ; [L449] COND FALSE !(t3_pc == 1) [L459] __retres1 = 0 [L461] RET return (__retres1); [L1047] EXPR is_transmit3_triggered() [L1047] tmp___2 = is_transmit3_triggered() [L1049] COND FALSE !(\read(tmp___2)) [L1055] CALL, EXPR is_transmit4_triggered() [L465] int __retres1 ; [L468] COND FALSE !(t4_pc == 1) [L478] __retres1 = 0 [L480] RET return (__retres1); [L1055] EXPR is_transmit4_triggered() [L1055] tmp___3 = is_transmit4_triggered() [L1057] COND FALSE !(\read(tmp___3)) [L1063] CALL, EXPR is_transmit5_triggered() [L484] int __retres1 ; [L487] COND FALSE !(t5_pc == 1) [L497] __retres1 = 0 [L499] RET return (__retres1); [L1063] EXPR is_transmit5_triggered() [L1063] tmp___4 = is_transmit5_triggered() [L1065] COND FALSE !(\read(tmp___4)) [L1071] CALL, EXPR is_transmit6_triggered() [L503] int __retres1 ; [L506] COND FALSE !(t6_pc == 1) [L516] __retres1 = 0 [L518] RET return (__retres1); [L1071] EXPR is_transmit6_triggered() [L1071] tmp___5 = is_transmit6_triggered() [L1073] COND FALSE !(\read(tmp___5)) [L1079] CALL, EXPR is_transmit7_triggered() [L522] int __retres1 ; [L525] COND FALSE !(t7_pc == 1) [L535] __retres1 = 0 [L537] RET return (__retres1); [L1079] EXPR is_transmit7_triggered() [L1079] tmp___6 = is_transmit7_triggered() [L1081] COND FALSE !(\read(tmp___6)) [L1087] CALL, EXPR is_transmit8_triggered() [L541] int __retres1 ; [L544] COND FALSE !(t8_pc == 1) [L554] __retres1 = 0 [L556] RET return (__retres1); [L1087] EXPR is_transmit8_triggered() [L1087] tmp___7 = is_transmit8_triggered() [L1089] COND FALSE, RET !(\read(tmp___7)) [L1258] activate_threads() [L1259] CALL reset_delta_events() [L921] COND FALSE !(M_E == 1) [L926] COND FALSE !(T1_E == 1) [L931] COND FALSE !(T2_E == 1) [L936] COND FALSE !(T3_E == 1) [L941] COND FALSE !(T4_E == 1) [L946] COND FALSE !(T5_E == 1) [L951] COND FALSE !(T6_E == 1) [L956] COND FALSE !(T7_E == 1) [L961] COND FALSE !(T8_E == 1) [L966] COND FALSE !(E_1 == 1) [L971] COND FALSE !(E_2 == 1) [L976] COND FALSE !(E_3 == 1) [L981] COND FALSE !(E_4 == 1) [L986] COND FALSE !(E_5 == 1) [L991] COND FALSE !(E_6 == 1) [L996] COND FALSE !(E_7 == 1) [L1001] COND FALSE, RET !(E_8 == 1) [L1259] reset_delta_events() [L1262] COND TRUE 1 [L1265] kernel_st = 1 [L1266] CALL eval() [L677] int tmp ; Loop: [L681] COND TRUE 1 [L684] CALL, EXPR exists_runnable_thread() [L621] int __retres1 ; [L624] COND TRUE m_st == 0 [L625] __retres1 = 1 [L672] RET return (__retres1); [L684] EXPR exists_runnable_thread() [L684] tmp = exists_runnable_thread() [L686] COND TRUE \read(tmp) [L691] COND TRUE m_st == 0 [L692] int tmp_ndt_1; [L693] tmp_ndt_1 = __VERIFIER_nondet_int() [L694] COND FALSE !(\read(tmp_ndt_1)) [L705] COND TRUE t1_st == 0 [L706] int tmp_ndt_2; [L707] tmp_ndt_2 = __VERIFIER_nondet_int() [L708] COND FALSE !(\read(tmp_ndt_2)) [L719] COND TRUE t2_st == 0 [L720] int tmp_ndt_3; [L721] tmp_ndt_3 = __VERIFIER_nondet_int() [L722] COND FALSE !(\read(tmp_ndt_3)) [L733] COND TRUE t3_st == 0 [L734] int tmp_ndt_4; [L735] tmp_ndt_4 = __VERIFIER_nondet_int() [L736] COND FALSE !(\read(tmp_ndt_4)) [L747] COND TRUE t4_st == 0 [L748] int tmp_ndt_5; [L749] tmp_ndt_5 = __VERIFIER_nondet_int() [L750] COND FALSE !(\read(tmp_ndt_5)) [L761] COND TRUE t5_st == 0 [L762] int tmp_ndt_6; [L763] tmp_ndt_6 = __VERIFIER_nondet_int() [L764] COND FALSE !(\read(tmp_ndt_6)) [L775] COND TRUE t6_st == 0 [L776] int tmp_ndt_7; [L777] tmp_ndt_7 = __VERIFIER_nondet_int() [L778] COND FALSE !(\read(tmp_ndt_7)) [L789] COND TRUE t7_st == 0 [L790] int tmp_ndt_8; [L791] tmp_ndt_8 = __VERIFIER_nondet_int() [L792] COND FALSE !(\read(tmp_ndt_8)) [L803] COND TRUE t8_st == 0 [L804] int tmp_ndt_9; [L805] tmp_ndt_9 = __VERIFIER_nondet_int() [L806] COND FALSE !(\read(tmp_ndt_9)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! Received shutdown request...