./Ultimate.py --spec ../../sv-benchmarks/c/properties/no-overflow.prp --file ../../sv-benchmarks/c/busybox-1.22.0/basename_false-unreach-call_true-no-overflow_true-valid-memsafety.i --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for overflows Using default analysis Version aa418289 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_3aa6edf1-6fa3-40b4-81aa-dcdd6600fcc2/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_3aa6edf1-6fa3-40b4-81aa-dcdd6600fcc2/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_3aa6edf1-6fa3-40b4-81aa-dcdd6600fcc2/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_3aa6edf1-6fa3-40b4-81aa-dcdd6600fcc2/bin-2019/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/busybox-1.22.0/basename_false-unreach-call_true-no-overflow_true-valid-memsafety.i -s /tmp/vcloud-vcloud-master/worker/working_dir_3aa6edf1-6fa3-40b4-81aa-dcdd6600fcc2/bin-2019/uautomizer/config/svcomp-Overflow-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_3aa6edf1-6fa3-40b4-81aa-dcdd6600fcc2/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! overflow) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash c57ebc44b313bf301635c00d4458ecfdd41286b1 ....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Using bit-precise analysis No suitable file found in config dir /tmp/vcloud-vcloud-master/worker/working_dir_3aa6edf1-6fa3-40b4-81aa-dcdd6600fcc2/bin-2019/uautomizer/config using search string *Overflow*64bit*_Bitvector*.epf No suitable settings file found using Overflow*64bit*_Bitvector ERROR: UNSUPPORTED PROPERTY Writing output log to file Ultimate.log Result: ERROR: ExceptionOrErrorResult: SMTLIBException: External (z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000)Received EOF on stdin. stderr output: (error "out of memory") --- Real Ultimate output --- This is Ultimate 0.1.23-aa41828 [2018-11-23 16:16:28,389 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-23 16:16:28,390 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-23 16:16:28,400 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-23 16:16:28,400 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-23 16:16:28,401 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-23 16:16:28,402 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-23 16:16:28,403 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-23 16:16:28,405 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-23 16:16:28,406 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-23 16:16:28,406 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-23 16:16:28,407 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-23 16:16:28,407 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-23 16:16:28,408 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-23 16:16:28,410 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-23 16:16:28,411 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-23 16:16:28,411 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-23 16:16:28,413 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-23 16:16:28,414 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-23 16:16:28,416 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-23 16:16:28,417 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-23 16:16:28,419 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-23 16:16:28,420 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-23 16:16:28,420 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-23 16:16:28,421 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-23 16:16:28,422 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-23 16:16:28,423 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-23 16:16:28,423 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-23 16:16:28,424 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-23 16:16:28,425 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-23 16:16:28,425 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-23 16:16:28,426 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-23 16:16:28,426 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-23 16:16:28,426 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-23 16:16:28,427 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-23 16:16:28,428 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-23 16:16:28,428 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_3aa6edf1-6fa3-40b4-81aa-dcdd6600fcc2/bin-2019/uautomizer/config/svcomp-Overflow-64bit-Automizer_Default.epf [2018-11-23 16:16:28,440 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-23 16:16:28,440 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-23 16:16:28,442 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-23 16:16:28,442 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-11-23 16:16:28,442 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-23 16:16:28,443 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-23 16:16:28,443 INFO L133 SettingsManager]: * Use SBE=true [2018-11-23 16:16:28,443 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-23 16:16:28,443 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-11-23 16:16:28,443 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-23 16:16:28,443 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-23 16:16:28,444 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-23 16:16:28,444 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-23 16:16:28,444 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-23 16:16:28,444 INFO L133 SettingsManager]: * Check absence of signed integer overflows=true [2018-11-23 16:16:28,444 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-23 16:16:28,444 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-23 16:16:28,444 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-23 16:16:28,445 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-23 16:16:28,445 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-23 16:16:28,445 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-23 16:16:28,445 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-23 16:16:28,445 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 16:16:28,445 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-23 16:16:28,446 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-23 16:16:28,446 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-23 16:16:28,446 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-23 16:16:28,446 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-23 16:16:28,446 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-11-23 16:16:28,446 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_3aa6edf1-6fa3-40b4-81aa-dcdd6600fcc2/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! overflow) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> c57ebc44b313bf301635c00d4458ecfdd41286b1 [2018-11-23 16:16:28,478 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-23 16:16:28,488 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-23 16:16:28,491 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-23 16:16:28,493 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-23 16:16:28,493 INFO L276 PluginConnector]: CDTParser initialized [2018-11-23 16:16:28,494 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_3aa6edf1-6fa3-40b4-81aa-dcdd6600fcc2/bin-2019/uautomizer/../../sv-benchmarks/c/busybox-1.22.0/basename_false-unreach-call_true-no-overflow_true-valid-memsafety.i [2018-11-23 16:16:28,549 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_3aa6edf1-6fa3-40b4-81aa-dcdd6600fcc2/bin-2019/uautomizer/data/01fba59ab/3265a0d866f34019a12365046a4fa425/FLAG7d0fe5dcf [2018-11-23 16:16:28,975 INFO L307 CDTParser]: Found 1 translation units. [2018-11-23 16:16:28,976 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_3aa6edf1-6fa3-40b4-81aa-dcdd6600fcc2/sv-benchmarks/c/busybox-1.22.0/basename_false-unreach-call_true-no-overflow_true-valid-memsafety.i [2018-11-23 16:16:28,992 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_3aa6edf1-6fa3-40b4-81aa-dcdd6600fcc2/bin-2019/uautomizer/data/01fba59ab/3265a0d866f34019a12365046a4fa425/FLAG7d0fe5dcf [2018-11-23 16:16:29,285 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_3aa6edf1-6fa3-40b4-81aa-dcdd6600fcc2/bin-2019/uautomizer/data/01fba59ab/3265a0d866f34019a12365046a4fa425 [2018-11-23 16:16:29,287 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-23 16:16:29,289 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-23 16:16:29,289 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-23 16:16:29,290 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-23 16:16:29,293 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-23 16:16:29,293 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 04:16:29" (1/1) ... [2018-11-23 16:16:29,295 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6d887742 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 04:16:29, skipping insertion in model container [2018-11-23 16:16:29,295 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 04:16:29" (1/1) ... [2018-11-23 16:16:29,303 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-23 16:16:29,349 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-23 16:16:29,854 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 16:16:29,937 INFO L191 MainTranslator]: Completed pre-run [2018-11-23 16:16:30,011 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 16:16:30,124 INFO L195 MainTranslator]: Completed translation [2018-11-23 16:16:30,125 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 04:16:30 WrapperNode [2018-11-23 16:16:30,125 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-23 16:16:30,126 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-23 16:16:30,126 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-23 16:16:30,126 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-23 16:16:30,132 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 04:16:30" (1/1) ... [2018-11-23 16:16:30,159 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 04:16:30" (1/1) ... [2018-11-23 16:16:30,172 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-23 16:16:30,173 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-23 16:16:30,173 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-23 16:16:30,173 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-23 16:16:30,180 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 04:16:30" (1/1) ... [2018-11-23 16:16:30,180 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 04:16:30" (1/1) ... [2018-11-23 16:16:30,187 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 04:16:30" (1/1) ... [2018-11-23 16:16:30,188 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 04:16:30" (1/1) ... [2018-11-23 16:16:30,221 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 04:16:30" (1/1) ... [2018-11-23 16:16:30,229 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 04:16:30" (1/1) ... [2018-11-23 16:16:30,235 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 04:16:30" (1/1) ... [2018-11-23 16:16:30,243 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-23 16:16:30,244 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-23 16:16:30,244 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-23 16:16:30,244 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-23 16:16:30,245 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 04:16:30" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3aa6edf1-6fa3-40b4-81aa-dcdd6600fcc2/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 16:16:30,297 INFO L130 BoogieDeclarations]: Found specification of procedure __main [2018-11-23 16:16:30,297 INFO L138 BoogieDeclarations]: Found implementation of procedure __main [2018-11-23 16:16:30,298 INFO L130 BoogieDeclarations]: Found specification of procedure last_char_is [2018-11-23 16:16:30,298 INFO L138 BoogieDeclarations]: Found implementation of procedure last_char_is [2018-11-23 16:16:30,298 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-23 16:16:30,298 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-23 16:16:30,298 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2018-11-23 16:16:30,298 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-11-23 16:16:30,298 INFO L130 BoogieDeclarations]: Found specification of procedure safe_write [2018-11-23 16:16:30,299 INFO L138 BoogieDeclarations]: Found implementation of procedure safe_write [2018-11-23 16:16:30,299 INFO L130 BoogieDeclarations]: Found specification of procedure bb_get_last_path_component_nostrip [2018-11-23 16:16:30,299 INFO L138 BoogieDeclarations]: Found implementation of procedure bb_get_last_path_component_nostrip [2018-11-23 16:16:30,299 INFO L130 BoogieDeclarations]: Found specification of procedure bb_get_last_path_component_strip [2018-11-23 16:16:30,299 INFO L138 BoogieDeclarations]: Found implementation of procedure bb_get_last_path_component_strip [2018-11-23 16:16:30,299 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-11-23 16:16:30,299 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2018-11-23 16:16:30,299 INFO L130 BoogieDeclarations]: Found specification of procedure write [2018-11-23 16:16:30,300 INFO L138 BoogieDeclarations]: Found implementation of procedure write [2018-11-23 16:16:30,300 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2018-11-23 16:16:30,300 INFO L130 BoogieDeclarations]: Found specification of procedure strrchr [2018-11-23 16:16:30,300 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-23 16:16:30,300 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-23 16:16:30,300 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2018-11-23 16:16:30,300 INFO L130 BoogieDeclarations]: Found specification of procedure full_write [2018-11-23 16:16:30,300 INFO L138 BoogieDeclarations]: Found implementation of procedure full_write [2018-11-23 16:16:30,301 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2018-11-23 16:16:30,301 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-23 16:16:30,301 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-23 16:16:31,387 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-23 16:16:31,387 INFO L280 CfgBuilder]: Removed 8 assue(true) statements. [2018-11-23 16:16:31,387 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 04:16:31 BoogieIcfgContainer [2018-11-23 16:16:31,388 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-23 16:16:31,388 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-23 16:16:31,389 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-23 16:16:31,391 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-23 16:16:31,391 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 23.11 04:16:29" (1/3) ... [2018-11-23 16:16:31,392 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@13531642 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 04:16:31, skipping insertion in model container [2018-11-23 16:16:31,392 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 04:16:30" (2/3) ... [2018-11-23 16:16:31,393 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@13531642 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 04:16:31, skipping insertion in model container [2018-11-23 16:16:31,393 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 04:16:31" (3/3) ... [2018-11-23 16:16:31,395 INFO L112 eAbstractionObserver]: Analyzing ICFG basename_false-unreach-call_true-no-overflow_true-valid-memsafety.i [2018-11-23 16:16:31,403 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-23 16:16:31,409 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 28 error locations. [2018-11-23 16:16:31,422 INFO L257 AbstractCegarLoop]: Starting to check reachability of 28 error locations. [2018-11-23 16:16:31,454 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-23 16:16:31,454 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-23 16:16:31,455 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-23 16:16:31,455 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-23 16:16:31,455 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-23 16:16:31,455 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-23 16:16:31,455 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-23 16:16:31,456 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-23 16:16:31,456 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-23 16:16:31,473 INFO L276 IsEmpty]: Start isEmpty. Operand 154 states. [2018-11-23 16:16:31,479 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 9 [2018-11-23 16:16:31,480 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:16:31,481 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:16:31,484 INFO L423 AbstractCegarLoop]: === Iteration 1 === [__mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 16:16:31,489 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:16:31,490 INFO L82 PathProgramCache]: Analyzing trace with hash -51273939, now seen corresponding path program 1 times [2018-11-23 16:16:31,492 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:16:31,493 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:16:31,588 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:16:31,589 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:16:31,589 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:16:31,711 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:16:31,842 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:16:31,844 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:16:31,844 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 16:16:31,847 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 16:16:31,857 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 16:16:31,857 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:16:31,859 INFO L87 Difference]: Start difference. First operand 154 states. Second operand 3 states. [2018-11-23 16:16:31,922 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:16:31,922 INFO L93 Difference]: Finished difference Result 298 states and 388 transitions. [2018-11-23 16:16:31,923 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 16:16:31,924 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 8 [2018-11-23 16:16:31,924 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:16:31,932 INFO L225 Difference]: With dead ends: 298 [2018-11-23 16:16:31,932 INFO L226 Difference]: Without dead ends: 149 [2018-11-23 16:16:31,935 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:16:31,949 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 149 states. [2018-11-23 16:16:31,969 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 149 to 149. [2018-11-23 16:16:31,970 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 149 states. [2018-11-23 16:16:31,972 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 149 states to 149 states and 183 transitions. [2018-11-23 16:16:31,973 INFO L78 Accepts]: Start accepts. Automaton has 149 states and 183 transitions. Word has length 8 [2018-11-23 16:16:31,974 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:16:31,974 INFO L480 AbstractCegarLoop]: Abstraction has 149 states and 183 transitions. [2018-11-23 16:16:31,974 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 16:16:31,974 INFO L276 IsEmpty]: Start isEmpty. Operand 149 states and 183 transitions. [2018-11-23 16:16:31,975 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 10 [2018-11-23 16:16:31,975 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:16:31,975 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:16:31,976 INFO L423 AbstractCegarLoop]: === Iteration 2 === [__mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 16:16:31,976 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:16:31,976 INFO L82 PathProgramCache]: Analyzing trace with hash -1589491972, now seen corresponding path program 1 times [2018-11-23 16:16:31,976 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:16:31,976 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:16:31,988 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:16:31,989 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:16:31,989 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:16:32,018 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:16:32,094 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:16:32,094 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:16:32,094 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 16:16:32,095 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 16:16:32,096 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 16:16:32,096 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:16:32,096 INFO L87 Difference]: Start difference. First operand 149 states and 183 transitions. Second operand 3 states. [2018-11-23 16:16:32,123 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:16:32,124 INFO L93 Difference]: Finished difference Result 152 states and 186 transitions. [2018-11-23 16:16:32,124 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 16:16:32,124 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 9 [2018-11-23 16:16:32,125 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:16:32,126 INFO L225 Difference]: With dead ends: 152 [2018-11-23 16:16:32,126 INFO L226 Difference]: Without dead ends: 151 [2018-11-23 16:16:32,129 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:16:32,130 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 151 states. [2018-11-23 16:16:32,141 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 151 to 151. [2018-11-23 16:16:32,141 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 151 states. [2018-11-23 16:16:32,143 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 151 states to 151 states and 185 transitions. [2018-11-23 16:16:32,143 INFO L78 Accepts]: Start accepts. Automaton has 151 states and 185 transitions. Word has length 9 [2018-11-23 16:16:32,143 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:16:32,144 INFO L480 AbstractCegarLoop]: Abstraction has 151 states and 185 transitions. [2018-11-23 16:16:32,144 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 16:16:32,144 INFO L276 IsEmpty]: Start isEmpty. Operand 151 states and 185 transitions. [2018-11-23 16:16:32,144 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2018-11-23 16:16:32,144 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:16:32,145 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:16:32,146 INFO L423 AbstractCegarLoop]: === Iteration 3 === [__mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 16:16:32,146 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:16:32,146 INFO L82 PathProgramCache]: Analyzing trace with hash -540770008, now seen corresponding path program 1 times [2018-11-23 16:16:32,146 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:16:32,146 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:16:32,158 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:16:32,158 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:16:32,159 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:16:32,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:16:32,273 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-11-23 16:16:32,274 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:16:32,274 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 16:16:32,274 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 16:16:32,274 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 16:16:32,275 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:16:32,275 INFO L87 Difference]: Start difference. First operand 151 states and 185 transitions. Second operand 3 states. [2018-11-23 16:16:32,327 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:16:32,327 INFO L93 Difference]: Finished difference Result 151 states and 185 transitions. [2018-11-23 16:16:32,328 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 16:16:32,328 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 12 [2018-11-23 16:16:32,328 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:16:32,330 INFO L225 Difference]: With dead ends: 151 [2018-11-23 16:16:32,330 INFO L226 Difference]: Without dead ends: 147 [2018-11-23 16:16:32,330 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:16:32,331 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 147 states. [2018-11-23 16:16:32,339 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 147 to 147. [2018-11-23 16:16:32,339 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 147 states. [2018-11-23 16:16:32,340 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 147 states to 147 states and 181 transitions. [2018-11-23 16:16:32,341 INFO L78 Accepts]: Start accepts. Automaton has 147 states and 181 transitions. Word has length 12 [2018-11-23 16:16:32,341 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:16:32,341 INFO L480 AbstractCegarLoop]: Abstraction has 147 states and 181 transitions. [2018-11-23 16:16:32,341 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 16:16:32,341 INFO L276 IsEmpty]: Start isEmpty. Operand 147 states and 181 transitions. [2018-11-23 16:16:32,342 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2018-11-23 16:16:32,342 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:16:32,342 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:16:32,343 INFO L423 AbstractCegarLoop]: === Iteration 4 === [__mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 16:16:32,343 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:16:32,343 INFO L82 PathProgramCache]: Analyzing trace with hash -540768278, now seen corresponding path program 1 times [2018-11-23 16:16:32,343 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:16:32,343 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:16:32,349 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:16:32,349 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:16:32,349 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:16:32,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:16:32,410 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:16:32,410 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:16:32,410 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 16:16:32,411 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 16:16:32,411 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 16:16:32,411 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:16:32,411 INFO L87 Difference]: Start difference. First operand 147 states and 181 transitions. Second operand 3 states. [2018-11-23 16:16:32,428 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:16:32,428 INFO L93 Difference]: Finished difference Result 147 states and 181 transitions. [2018-11-23 16:16:32,428 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 16:16:32,428 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 12 [2018-11-23 16:16:32,429 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:16:32,430 INFO L225 Difference]: With dead ends: 147 [2018-11-23 16:16:32,430 INFO L226 Difference]: Without dead ends: 146 [2018-11-23 16:16:32,430 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:16:32,431 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 146 states. [2018-11-23 16:16:32,438 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 146 to 144. [2018-11-23 16:16:32,439 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 144 states. [2018-11-23 16:16:32,440 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 144 states to 144 states and 178 transitions. [2018-11-23 16:16:32,440 INFO L78 Accepts]: Start accepts. Automaton has 144 states and 178 transitions. Word has length 12 [2018-11-23 16:16:32,440 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:16:32,440 INFO L480 AbstractCegarLoop]: Abstraction has 144 states and 178 transitions. [2018-11-23 16:16:32,440 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 16:16:32,440 INFO L276 IsEmpty]: Start isEmpty. Operand 144 states and 178 transitions. [2018-11-23 16:16:32,441 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2018-11-23 16:16:32,441 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:16:32,441 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:16:32,442 INFO L423 AbstractCegarLoop]: === Iteration 5 === [__mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 16:16:32,442 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:16:32,442 INFO L82 PathProgramCache]: Analyzing trace with hash 415999081, now seen corresponding path program 1 times [2018-11-23 16:16:32,442 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:16:32,442 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:16:32,449 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:16:32,449 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:16:32,449 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:16:32,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:16:32,514 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-11-23 16:16:32,514 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:16:32,514 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 16:16:32,514 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 16:16:32,515 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 16:16:32,515 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:16:32,515 INFO L87 Difference]: Start difference. First operand 144 states and 178 transitions. Second operand 3 states. [2018-11-23 16:16:32,555 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:16:32,555 INFO L93 Difference]: Finished difference Result 144 states and 178 transitions. [2018-11-23 16:16:32,556 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 16:16:32,556 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 13 [2018-11-23 16:16:32,556 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:16:32,557 INFO L225 Difference]: With dead ends: 144 [2018-11-23 16:16:32,557 INFO L226 Difference]: Without dead ends: 142 [2018-11-23 16:16:32,558 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:16:32,558 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 142 states. [2018-11-23 16:16:32,565 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 142 to 142. [2018-11-23 16:16:32,565 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 142 states. [2018-11-23 16:16:32,566 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 142 states to 142 states and 176 transitions. [2018-11-23 16:16:32,566 INFO L78 Accepts]: Start accepts. Automaton has 142 states and 176 transitions. Word has length 13 [2018-11-23 16:16:32,567 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:16:32,567 INFO L480 AbstractCegarLoop]: Abstraction has 142 states and 176 transitions. [2018-11-23 16:16:32,567 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 16:16:32,567 INFO L276 IsEmpty]: Start isEmpty. Operand 142 states and 176 transitions. [2018-11-23 16:16:32,567 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2018-11-23 16:16:32,568 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:16:32,568 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:16:32,568 INFO L423 AbstractCegarLoop]: === Iteration 6 === [__mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 16:16:32,569 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:16:32,569 INFO L82 PathProgramCache]: Analyzing trace with hash 343163019, now seen corresponding path program 1 times [2018-11-23 16:16:32,569 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:16:32,569 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:16:32,577 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:16:32,577 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:16:32,577 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:16:32,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:16:32,638 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-11-23 16:16:32,638 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:16:32,638 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 16:16:32,638 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 16:16:32,639 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 16:16:32,639 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:16:32,639 INFO L87 Difference]: Start difference. First operand 142 states and 176 transitions. Second operand 3 states. [2018-11-23 16:16:32,679 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:16:32,679 INFO L93 Difference]: Finished difference Result 142 states and 176 transitions. [2018-11-23 16:16:32,680 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 16:16:32,680 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 15 [2018-11-23 16:16:32,680 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:16:32,681 INFO L225 Difference]: With dead ends: 142 [2018-11-23 16:16:32,682 INFO L226 Difference]: Without dead ends: 140 [2018-11-23 16:16:32,682 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:16:32,683 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 140 states. [2018-11-23 16:16:32,688 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 140 to 140. [2018-11-23 16:16:32,689 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 140 states. [2018-11-23 16:16:32,689 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 140 states to 140 states and 174 transitions. [2018-11-23 16:16:32,690 INFO L78 Accepts]: Start accepts. Automaton has 140 states and 174 transitions. Word has length 15 [2018-11-23 16:16:32,690 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:16:32,690 INFO L480 AbstractCegarLoop]: Abstraction has 140 states and 174 transitions. [2018-11-23 16:16:32,690 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 16:16:32,690 INFO L276 IsEmpty]: Start isEmpty. Operand 140 states and 174 transitions. [2018-11-23 16:16:32,691 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2018-11-23 16:16:32,691 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:16:32,691 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:16:32,692 INFO L423 AbstractCegarLoop]: === Iteration 7 === [__mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 16:16:32,692 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:16:32,692 INFO L82 PathProgramCache]: Analyzing trace with hash -1254383198, now seen corresponding path program 1 times [2018-11-23 16:16:32,692 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:16:32,693 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:16:32,700 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:16:32,700 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:16:32,700 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:16:32,718 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:16:32,762 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-11-23 16:16:32,762 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:16:32,763 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 16:16:32,763 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 16:16:32,763 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 16:16:32,763 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:16:32,764 INFO L87 Difference]: Start difference. First operand 140 states and 174 transitions. Second operand 3 states. [2018-11-23 16:16:32,791 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:16:32,792 INFO L93 Difference]: Finished difference Result 264 states and 334 transitions. [2018-11-23 16:16:32,792 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 16:16:32,792 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 22 [2018-11-23 16:16:32,792 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:16:32,793 INFO L225 Difference]: With dead ends: 264 [2018-11-23 16:16:32,793 INFO L226 Difference]: Without dead ends: 143 [2018-11-23 16:16:32,794 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:16:32,795 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 143 states. [2018-11-23 16:16:32,799 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 143 to 143. [2018-11-23 16:16:32,799 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 143 states. [2018-11-23 16:16:32,800 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 143 states to 143 states and 177 transitions. [2018-11-23 16:16:32,800 INFO L78 Accepts]: Start accepts. Automaton has 143 states and 177 transitions. Word has length 22 [2018-11-23 16:16:32,800 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:16:32,800 INFO L480 AbstractCegarLoop]: Abstraction has 143 states and 177 transitions. [2018-11-23 16:16:32,801 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 16:16:32,801 INFO L276 IsEmpty]: Start isEmpty. Operand 143 states and 177 transitions. [2018-11-23 16:16:32,801 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-11-23 16:16:32,801 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:16:32,802 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:16:32,802 INFO L423 AbstractCegarLoop]: === Iteration 8 === [__mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 16:16:32,803 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:16:32,803 INFO L82 PathProgramCache]: Analyzing trace with hash 1182405925, now seen corresponding path program 1 times [2018-11-23 16:16:32,803 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:16:32,803 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:16:32,809 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:16:32,809 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:16:32,810 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:16:32,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:16:32,917 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-11-23 16:16:32,917 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:16:32,918 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 16:16:32,918 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 16:16:32,918 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 16:16:32,918 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 16:16:32,918 INFO L87 Difference]: Start difference. First operand 143 states and 177 transitions. Second operand 4 states. [2018-11-23 16:16:32,990 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:16:32,990 INFO L93 Difference]: Finished difference Result 151 states and 187 transitions. [2018-11-23 16:16:32,991 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 16:16:32,991 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 25 [2018-11-23 16:16:32,991 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:16:32,993 INFO L225 Difference]: With dead ends: 151 [2018-11-23 16:16:32,993 INFO L226 Difference]: Without dead ends: 150 [2018-11-23 16:16:32,993 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-23 16:16:32,994 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 150 states. [2018-11-23 16:16:33,002 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 150 to 142. [2018-11-23 16:16:33,002 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 142 states. [2018-11-23 16:16:33,002 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 142 states to 142 states and 176 transitions. [2018-11-23 16:16:33,003 INFO L78 Accepts]: Start accepts. Automaton has 142 states and 176 transitions. Word has length 25 [2018-11-23 16:16:33,003 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:16:33,003 INFO L480 AbstractCegarLoop]: Abstraction has 142 states and 176 transitions. [2018-11-23 16:16:33,003 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 16:16:33,003 INFO L276 IsEmpty]: Start isEmpty. Operand 142 states and 176 transitions. [2018-11-23 16:16:33,004 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-11-23 16:16:33,004 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:16:33,004 INFO L402 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:16:33,004 INFO L423 AbstractCegarLoop]: === Iteration 9 === [__mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 16:16:33,005 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:16:33,005 INFO L82 PathProgramCache]: Analyzing trace with hash 1182405980, now seen corresponding path program 1 times [2018-11-23 16:16:33,005 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:16:33,005 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:16:33,009 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:16:33,010 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:16:33,010 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:16:33,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:16:33,072 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-11-23 16:16:33,072 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:16:33,073 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 16:16:33,073 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 16:16:33,073 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 16:16:33,073 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:16:33,073 INFO L87 Difference]: Start difference. First operand 142 states and 176 transitions. Second operand 3 states. [2018-11-23 16:16:33,101 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:16:33,101 INFO L93 Difference]: Finished difference Result 142 states and 176 transitions. [2018-11-23 16:16:33,102 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 16:16:33,102 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 25 [2018-11-23 16:16:33,102 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:16:33,103 INFO L225 Difference]: With dead ends: 142 [2018-11-23 16:16:33,103 INFO L226 Difference]: Without dead ends: 141 [2018-11-23 16:16:33,103 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:16:33,104 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 141 states. [2018-11-23 16:16:33,108 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 141 to 141. [2018-11-23 16:16:33,108 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 141 states. [2018-11-23 16:16:33,109 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141 states to 141 states and 175 transitions. [2018-11-23 16:16:33,109 INFO L78 Accepts]: Start accepts. Automaton has 141 states and 175 transitions. Word has length 25 [2018-11-23 16:16:33,109 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:16:33,109 INFO L480 AbstractCegarLoop]: Abstraction has 141 states and 175 transitions. [2018-11-23 16:16:33,109 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 16:16:33,109 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 175 transitions. [2018-11-23 16:16:33,110 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-11-23 16:16:33,110 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:16:33,110 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:16:33,111 INFO L423 AbstractCegarLoop]: === Iteration 10 === [__mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 16:16:33,111 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:16:33,111 INFO L82 PathProgramCache]: Analyzing trace with hash -1458323352, now seen corresponding path program 1 times [2018-11-23 16:16:33,112 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:16:33,112 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:16:33,118 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:16:33,118 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:16:33,118 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:16:33,139 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:16:33,201 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:16:33,201 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 16:16:33,202 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3aa6edf1-6fa3-40b4-81aa-dcdd6600fcc2/bin-2019/uautomizer/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 16:16:33,232 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:16:33,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:16:33,363 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 16:16:33,392 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:16:33,414 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 16:16:33,414 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 5 [2018-11-23 16:16:33,414 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 16:16:33,415 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 16:16:33,415 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2018-11-23 16:16:33,416 INFO L87 Difference]: Start difference. First operand 141 states and 175 transitions. Second operand 5 states. [2018-11-23 16:16:33,450 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:16:33,450 INFO L93 Difference]: Finished difference Result 277 states and 345 transitions. [2018-11-23 16:16:33,451 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 16:16:33,451 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 27 [2018-11-23 16:16:33,451 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:16:33,452 INFO L225 Difference]: With dead ends: 277 [2018-11-23 16:16:33,452 INFO L226 Difference]: Without dead ends: 146 [2018-11-23 16:16:33,453 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 30 GetRequests, 27 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2018-11-23 16:16:33,453 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 146 states. [2018-11-23 16:16:33,456 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 146 to 144. [2018-11-23 16:16:33,457 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 144 states. [2018-11-23 16:16:33,462 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 144 states to 144 states and 178 transitions. [2018-11-23 16:16:33,462 INFO L78 Accepts]: Start accepts. Automaton has 144 states and 178 transitions. Word has length 27 [2018-11-23 16:16:33,462 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:16:33,462 INFO L480 AbstractCegarLoop]: Abstraction has 144 states and 178 transitions. [2018-11-23 16:16:33,462 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 16:16:33,462 INFO L276 IsEmpty]: Start isEmpty. Operand 144 states and 178 transitions. [2018-11-23 16:16:33,463 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2018-11-23 16:16:33,463 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:16:33,463 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:16:33,464 INFO L423 AbstractCegarLoop]: === Iteration 11 === [__mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 16:16:33,464 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:16:33,464 INFO L82 PathProgramCache]: Analyzing trace with hash -672341546, now seen corresponding path program 2 times [2018-11-23 16:16:33,464 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:16:33,464 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:16:33,473 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:16:33,473 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:16:33,474 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:16:33,513 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:16:33,569 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 16:16:33,569 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 16:16:33,569 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3aa6edf1-6fa3-40b4-81aa-dcdd6600fcc2/bin-2019/uautomizer/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 16:16:33,596 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-23 16:16:33,703 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-11-23 16:16:33,703 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 16:16:33,708 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 16:16:33,747 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-11-23 16:16:33,768 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-23 16:16:33,768 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [5] total 7 [2018-11-23 16:16:33,768 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-23 16:16:33,769 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-23 16:16:33,769 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-23 16:16:33,769 INFO L87 Difference]: Start difference. First operand 144 states and 178 transitions. Second operand 7 states. [2018-11-23 16:16:33,930 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:16:33,930 INFO L93 Difference]: Finished difference Result 290 states and 361 transitions. [2018-11-23 16:16:33,931 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 16:16:33,931 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 30 [2018-11-23 16:16:33,931 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:16:33,932 INFO L225 Difference]: With dead ends: 290 [2018-11-23 16:16:33,932 INFO L226 Difference]: Without dead ends: 159 [2018-11-23 16:16:33,932 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 34 GetRequests, 29 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-23 16:16:33,933 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 159 states. [2018-11-23 16:16:33,937 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 159 to 148. [2018-11-23 16:16:33,938 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 148 states. [2018-11-23 16:16:33,938 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 148 states to 148 states and 182 transitions. [2018-11-23 16:16:33,939 INFO L78 Accepts]: Start accepts. Automaton has 148 states and 182 transitions. Word has length 30 [2018-11-23 16:16:33,939 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:16:33,939 INFO L480 AbstractCegarLoop]: Abstraction has 148 states and 182 transitions. [2018-11-23 16:16:33,939 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-23 16:16:33,939 INFO L276 IsEmpty]: Start isEmpty. Operand 148 states and 182 transitions. [2018-11-23 16:16:33,940 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-11-23 16:16:33,940 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:16:33,940 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:16:33,941 INFO L423 AbstractCegarLoop]: === Iteration 12 === [__mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 16:16:33,941 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:16:33,941 INFO L82 PathProgramCache]: Analyzing trace with hash -205191436, now seen corresponding path program 1 times [2018-11-23 16:16:33,941 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:16:33,941 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:16:33,949 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:16:33,949 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 16:16:33,949 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:16:33,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:16:34,012 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-11-23 16:16:34,012 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:16:34,012 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 16:16:34,013 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 16:16:34,013 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 16:16:34,013 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:16:34,013 INFO L87 Difference]: Start difference. First operand 148 states and 182 transitions. Second operand 3 states. [2018-11-23 16:16:34,044 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:16:34,044 INFO L93 Difference]: Finished difference Result 158 states and 193 transitions. [2018-11-23 16:16:34,045 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 16:16:34,045 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 32 [2018-11-23 16:16:34,045 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:16:34,046 INFO L225 Difference]: With dead ends: 158 [2018-11-23 16:16:34,046 INFO L226 Difference]: Without dead ends: 157 [2018-11-23 16:16:34,046 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:16:34,047 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 157 states. [2018-11-23 16:16:34,050 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 157 to 156. [2018-11-23 16:16:34,050 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 156 states. [2018-11-23 16:16:34,051 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 156 states to 156 states and 192 transitions. [2018-11-23 16:16:34,051 INFO L78 Accepts]: Start accepts. Automaton has 156 states and 192 transitions. Word has length 32 [2018-11-23 16:16:34,051 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:16:34,051 INFO L480 AbstractCegarLoop]: Abstraction has 156 states and 192 transitions. [2018-11-23 16:16:34,051 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 16:16:34,052 INFO L276 IsEmpty]: Start isEmpty. Operand 156 states and 192 transitions. [2018-11-23 16:16:34,052 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-11-23 16:16:34,052 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:16:34,052 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:16:34,053 INFO L423 AbstractCegarLoop]: === Iteration 13 === [__mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 16:16:34,053 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:16:34,053 INFO L82 PathProgramCache]: Analyzing trace with hash -205189738, now seen corresponding path program 1 times [2018-11-23 16:16:34,053 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:16:34,054 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:16:34,059 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:16:34,059 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:16:34,059 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:16:34,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:16:34,118 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-11-23 16:16:34,118 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:16:34,118 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 16:16:34,119 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 16:16:34,119 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 16:16:34,119 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:16:34,119 INFO L87 Difference]: Start difference. First operand 156 states and 192 transitions. Second operand 3 states. [2018-11-23 16:16:34,136 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:16:34,137 INFO L93 Difference]: Finished difference Result 156 states and 192 transitions. [2018-11-23 16:16:34,137 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 16:16:34,138 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 32 [2018-11-23 16:16:34,138 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:16:34,139 INFO L225 Difference]: With dead ends: 156 [2018-11-23 16:16:34,139 INFO L226 Difference]: Without dead ends: 155 [2018-11-23 16:16:34,139 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:16:34,140 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 155 states. [2018-11-23 16:16:34,145 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 155 to 151. [2018-11-23 16:16:34,145 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 151 states. [2018-11-23 16:16:34,146 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 151 states to 151 states and 186 transitions. [2018-11-23 16:16:34,146 INFO L78 Accepts]: Start accepts. Automaton has 151 states and 186 transitions. Word has length 32 [2018-11-23 16:16:34,147 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:16:34,147 INFO L480 AbstractCegarLoop]: Abstraction has 151 states and 186 transitions. [2018-11-23 16:16:34,147 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 16:16:34,147 INFO L276 IsEmpty]: Start isEmpty. Operand 151 states and 186 transitions. [2018-11-23 16:16:34,147 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2018-11-23 16:16:34,148 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:16:34,148 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:16:34,148 INFO L423 AbstractCegarLoop]: === Iteration 14 === [__mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 16:16:34,149 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:16:34,149 INFO L82 PathProgramCache]: Analyzing trace with hash 1301076365, now seen corresponding path program 1 times [2018-11-23 16:16:34,149 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:16:34,153 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:16:34,158 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:16:34,158 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:16:34,158 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:16:34,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:16:34,226 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-11-23 16:16:34,227 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 16:16:34,227 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3aa6edf1-6fa3-40b4-81aa-dcdd6600fcc2/bin-2019/uautomizer/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 16:16:34,261 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:16:34,387 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:16:34,394 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 16:16:34,456 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-11-23 16:16:34,489 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 16:16:34,490 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 6] total 8 [2018-11-23 16:16:34,490 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-23 16:16:34,490 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-23 16:16:34,490 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=36, Unknown=0, NotChecked=0, Total=56 [2018-11-23 16:16:34,491 INFO L87 Difference]: Start difference. First operand 151 states and 186 transitions. Second operand 8 states. [2018-11-23 16:16:34,608 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:16:34,608 INFO L93 Difference]: Finished difference Result 301 states and 373 transitions. [2018-11-23 16:16:34,609 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-23 16:16:34,609 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 40 [2018-11-23 16:16:34,609 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:16:34,610 INFO L225 Difference]: With dead ends: 301 [2018-11-23 16:16:34,610 INFO L226 Difference]: Without dead ends: 166 [2018-11-23 16:16:34,611 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 43 GetRequests, 37 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=20, Invalid=36, Unknown=0, NotChecked=0, Total=56 [2018-11-23 16:16:34,611 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 166 states. [2018-11-23 16:16:34,617 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 166 to 160. [2018-11-23 16:16:34,617 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 160 states. [2018-11-23 16:16:34,618 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 160 states to 160 states and 195 transitions. [2018-11-23 16:16:34,618 INFO L78 Accepts]: Start accepts. Automaton has 160 states and 195 transitions. Word has length 40 [2018-11-23 16:16:34,618 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:16:34,619 INFO L480 AbstractCegarLoop]: Abstraction has 160 states and 195 transitions. [2018-11-23 16:16:34,619 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-23 16:16:34,619 INFO L276 IsEmpty]: Start isEmpty. Operand 160 states and 195 transitions. [2018-11-23 16:16:34,619 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-11-23 16:16:34,619 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:16:34,620 INFO L402 BasicCegarLoop]: trace histogram [4, 4, 4, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:16:34,620 INFO L423 AbstractCegarLoop]: === Iteration 15 === [__mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 16:16:34,620 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:16:34,621 INFO L82 PathProgramCache]: Analyzing trace with hash 532136062, now seen corresponding path program 2 times [2018-11-23 16:16:34,621 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:16:34,621 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:16:34,627 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:16:34,628 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:16:34,628 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:16:34,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:16:34,728 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 1 proven. 5 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2018-11-23 16:16:34,728 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 16:16:34,728 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3aa6edf1-6fa3-40b4-81aa-dcdd6600fcc2/bin-2019/uautomizer/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 16:16:34,765 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-23 16:16:34,930 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-11-23 16:16:34,930 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 16:16:34,936 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 16:16:34,959 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2018-11-23 16:16:34,991 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-23 16:16:34,991 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [5] total 6 [2018-11-23 16:16:34,991 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 16:16:34,991 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 16:16:34,991 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2018-11-23 16:16:34,992 INFO L87 Difference]: Start difference. First operand 160 states and 195 transitions. Second operand 6 states. [2018-11-23 16:16:35,077 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:16:35,078 INFO L93 Difference]: Finished difference Result 312 states and 391 transitions. [2018-11-23 16:16:35,079 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 16:16:35,079 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 46 [2018-11-23 16:16:35,080 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:16:35,082 INFO L225 Difference]: With dead ends: 312 [2018-11-23 16:16:35,083 INFO L226 Difference]: Without dead ends: 188 [2018-11-23 16:16:35,083 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 50 GetRequests, 46 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2018-11-23 16:16:35,084 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 188 states. [2018-11-23 16:16:35,091 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 188 to 167. [2018-11-23 16:16:35,091 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 167 states. [2018-11-23 16:16:35,092 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 167 states to 167 states and 202 transitions. [2018-11-23 16:16:35,092 INFO L78 Accepts]: Start accepts. Automaton has 167 states and 202 transitions. Word has length 46 [2018-11-23 16:16:35,092 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:16:35,092 INFO L480 AbstractCegarLoop]: Abstraction has 167 states and 202 transitions. [2018-11-23 16:16:35,092 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 16:16:35,093 INFO L276 IsEmpty]: Start isEmpty. Operand 167 states and 202 transitions. [2018-11-23 16:16:35,093 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-11-23 16:16:35,093 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:16:35,093 INFO L402 BasicCegarLoop]: trace histogram [4, 4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:16:35,094 INFO L423 AbstractCegarLoop]: === Iteration 16 === [__mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 16:16:35,094 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:16:35,094 INFO L82 PathProgramCache]: Analyzing trace with hash -1211589613, now seen corresponding path program 1 times [2018-11-23 16:16:35,094 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:16:35,094 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:16:35,102 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:16:35,102 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 16:16:35,102 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:16:35,153 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:16:35,246 INFO L134 CoverageAnalysis]: Checked inductivity of 35 backedges. 1 proven. 12 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2018-11-23 16:16:35,246 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 16:16:35,246 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3aa6edf1-6fa3-40b4-81aa-dcdd6600fcc2/bin-2019/uautomizer/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 16:16:35,283 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:16:35,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:16:35,424 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 16:16:35,496 INFO L134 CoverageAnalysis]: Checked inductivity of 35 backedges. 0 proven. 22 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-11-23 16:16:35,519 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 16:16:35,519 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 7] total 11 [2018-11-23 16:16:35,519 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-11-23 16:16:35,520 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-11-23 16:16:35,520 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=75, Unknown=0, NotChecked=0, Total=110 [2018-11-23 16:16:35,520 INFO L87 Difference]: Start difference. First operand 167 states and 202 transitions. Second operand 11 states. [2018-11-23 16:16:35,634 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:16:35,634 INFO L93 Difference]: Finished difference Result 330 states and 402 transitions. [2018-11-23 16:16:35,636 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-11-23 16:16:35,636 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 50 [2018-11-23 16:16:35,637 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:16:35,637 INFO L225 Difference]: With dead ends: 330 [2018-11-23 16:16:35,638 INFO L226 Difference]: Without dead ends: 182 [2018-11-23 16:16:35,638 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 55 GetRequests, 46 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=35, Invalid=75, Unknown=0, NotChecked=0, Total=110 [2018-11-23 16:16:35,639 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 182 states. [2018-11-23 16:16:35,646 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 182 to 176. [2018-11-23 16:16:35,646 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 176 states. [2018-11-23 16:16:35,647 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 176 states to 176 states and 211 transitions. [2018-11-23 16:16:35,647 INFO L78 Accepts]: Start accepts. Automaton has 176 states and 211 transitions. Word has length 50 [2018-11-23 16:16:35,647 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:16:35,647 INFO L480 AbstractCegarLoop]: Abstraction has 176 states and 211 transitions. [2018-11-23 16:16:35,647 INFO L481 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-11-23 16:16:35,648 INFO L276 IsEmpty]: Start isEmpty. Operand 176 states and 211 transitions. [2018-11-23 16:16:35,648 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-11-23 16:16:35,648 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:16:35,648 INFO L402 BasicCegarLoop]: trace histogram [5, 5, 5, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:16:35,649 INFO L423 AbstractCegarLoop]: === Iteration 17 === [__mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 16:16:35,649 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:16:35,649 INFO L82 PathProgramCache]: Analyzing trace with hash -1484183166, now seen corresponding path program 2 times [2018-11-23 16:16:35,649 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:16:35,649 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:16:35,656 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:16:35,656 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:16:35,657 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:16:35,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:16:35,802 INFO L134 CoverageAnalysis]: Checked inductivity of 58 backedges. 1 proven. 22 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2018-11-23 16:16:35,802 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 16:16:35,802 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3aa6edf1-6fa3-40b4-81aa-dcdd6600fcc2/bin-2019/uautomizer/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 16:16:35,830 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-23 16:16:35,985 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-23 16:16:35,986 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 16:16:35,990 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 16:16:36,071 INFO L134 CoverageAnalysis]: Checked inductivity of 58 backedges. 0 proven. 35 refuted. 0 times theorem prover too weak. 23 trivial. 0 not checked. [2018-11-23 16:16:36,090 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 16:16:36,090 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 8] total 13 [2018-11-23 16:16:36,091 INFO L459 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-11-23 16:16:36,091 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-11-23 16:16:36,091 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=48, Invalid=108, Unknown=0, NotChecked=0, Total=156 [2018-11-23 16:16:36,091 INFO L87 Difference]: Start difference. First operand 176 states and 211 transitions. Second operand 13 states. [2018-11-23 16:16:36,213 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:16:36,214 INFO L93 Difference]: Finished difference Result 345 states and 417 transitions. [2018-11-23 16:16:36,214 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-11-23 16:16:36,214 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 56 [2018-11-23 16:16:36,214 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:16:36,215 INFO L225 Difference]: With dead ends: 345 [2018-11-23 16:16:36,215 INFO L226 Difference]: Without dead ends: 191 [2018-11-23 16:16:36,216 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 62 GetRequests, 51 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=48, Invalid=108, Unknown=0, NotChecked=0, Total=156 [2018-11-23 16:16:36,217 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 191 states. [2018-11-23 16:16:36,224 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 191 to 185. [2018-11-23 16:16:36,224 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 185 states. [2018-11-23 16:16:36,225 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 185 states to 185 states and 220 transitions. [2018-11-23 16:16:36,225 INFO L78 Accepts]: Start accepts. Automaton has 185 states and 220 transitions. Word has length 56 [2018-11-23 16:16:36,225 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:16:36,226 INFO L480 AbstractCegarLoop]: Abstraction has 185 states and 220 transitions. [2018-11-23 16:16:36,226 INFO L481 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-11-23 16:16:36,226 INFO L276 IsEmpty]: Start isEmpty. Operand 185 states and 220 transitions. [2018-11-23 16:16:36,226 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-11-23 16:16:36,226 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:16:36,227 INFO L402 BasicCegarLoop]: trace histogram [6, 6, 6, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:16:36,227 INFO L423 AbstractCegarLoop]: === Iteration 18 === [__mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 16:16:36,227 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:16:36,228 INFO L82 PathProgramCache]: Analyzing trace with hash 1464125235, now seen corresponding path program 3 times [2018-11-23 16:16:36,228 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:16:36,228 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:16:36,234 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:16:36,234 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 16:16:36,235 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:16:36,264 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:16:36,384 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 1 proven. 35 refuted. 0 times theorem prover too weak. 51 trivial. 0 not checked. [2018-11-23 16:16:36,384 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 16:16:36,384 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3aa6edf1-6fa3-40b4-81aa-dcdd6600fcc2/bin-2019/uautomizer/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 16:16:36,416 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-23 16:16:39,472 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 7 check-sat command(s) [2018-11-23 16:16:39,472 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 16:16:39,478 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 16:16:39,502 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 1 proven. 35 refuted. 0 times theorem prover too weak. 51 trivial. 0 not checked. [2018-11-23 16:16:39,524 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 16:16:39,524 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 9 [2018-11-23 16:16:39,525 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-11-23 16:16:39,525 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-11-23 16:16:39,525 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=36, Unknown=0, NotChecked=0, Total=72 [2018-11-23 16:16:39,525 INFO L87 Difference]: Start difference. First operand 185 states and 220 transitions. Second operand 9 states. [2018-11-23 16:16:39,571 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:16:39,572 INFO L93 Difference]: Finished difference Result 329 states and 399 transitions. [2018-11-23 16:16:39,573 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-23 16:16:39,573 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 62 [2018-11-23 16:16:39,574 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:16:39,575 INFO L225 Difference]: With dead ends: 329 [2018-11-23 16:16:39,575 INFO L226 Difference]: Without dead ends: 195 [2018-11-23 16:16:39,575 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 69 GetRequests, 62 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=36, Invalid=36, Unknown=0, NotChecked=0, Total=72 [2018-11-23 16:16:39,576 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 195 states. [2018-11-23 16:16:39,585 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 195 to 191. [2018-11-23 16:16:39,585 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 191 states. [2018-11-23 16:16:39,586 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 191 states to 191 states and 226 transitions. [2018-11-23 16:16:39,587 INFO L78 Accepts]: Start accepts. Automaton has 191 states and 226 transitions. Word has length 62 [2018-11-23 16:16:39,587 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:16:39,587 INFO L480 AbstractCegarLoop]: Abstraction has 191 states and 226 transitions. [2018-11-23 16:16:39,587 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-11-23 16:16:39,587 INFO L276 IsEmpty]: Start isEmpty. Operand 191 states and 226 transitions. [2018-11-23 16:16:39,588 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2018-11-23 16:16:39,588 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:16:39,588 INFO L402 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:16:39,589 INFO L423 AbstractCegarLoop]: === Iteration 19 === [__mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 16:16:39,589 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:16:39,589 INFO L82 PathProgramCache]: Analyzing trace with hash 613455476, now seen corresponding path program 4 times [2018-11-23 16:16:39,593 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:16:39,593 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:16:39,601 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:16:39,601 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 16:16:39,601 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:16:39,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:16:39,807 INFO L134 CoverageAnalysis]: Checked inductivity of 103 backedges. 0 proven. 51 refuted. 0 times theorem prover too weak. 52 trivial. 0 not checked. [2018-11-23 16:16:39,807 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 16:16:39,808 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3aa6edf1-6fa3-40b4-81aa-dcdd6600fcc2/bin-2019/uautomizer/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 16:16:39,841 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-23 16:16:39,976 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-23 16:16:39,976 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 16:16:39,981 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 16:16:40,023 INFO L134 CoverageAnalysis]: Checked inductivity of 103 backedges. 0 proven. 51 refuted. 0 times theorem prover too weak. 52 trivial. 0 not checked. [2018-11-23 16:16:40,043 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 16:16:40,043 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 10 [2018-11-23 16:16:40,044 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-23 16:16:40,044 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-23 16:16:40,044 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-11-23 16:16:40,044 INFO L87 Difference]: Start difference. First operand 191 states and 226 transitions. Second operand 10 states. [2018-11-23 16:16:40,111 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:16:40,111 INFO L93 Difference]: Finished difference Result 362 states and 432 transitions. [2018-11-23 16:16:40,112 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-23 16:16:40,112 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 65 [2018-11-23 16:16:40,112 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:16:40,113 INFO L225 Difference]: With dead ends: 362 [2018-11-23 16:16:40,113 INFO L226 Difference]: Without dead ends: 196 [2018-11-23 16:16:40,114 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 73 GetRequests, 65 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-11-23 16:16:40,114 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 196 states. [2018-11-23 16:16:40,119 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 196 to 194. [2018-11-23 16:16:40,119 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 194 states. [2018-11-23 16:16:40,120 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 194 states to 194 states and 229 transitions. [2018-11-23 16:16:40,121 INFO L78 Accepts]: Start accepts. Automaton has 194 states and 229 transitions. Word has length 65 [2018-11-23 16:16:40,121 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:16:40,121 INFO L480 AbstractCegarLoop]: Abstraction has 194 states and 229 transitions. [2018-11-23 16:16:40,121 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-23 16:16:40,121 INFO L276 IsEmpty]: Start isEmpty. Operand 194 states and 229 transitions. [2018-11-23 16:16:40,121 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2018-11-23 16:16:40,122 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:16:40,122 INFO L402 BasicCegarLoop]: trace histogram [7, 7, 7, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:16:40,122 INFO L423 AbstractCegarLoop]: === Iteration 20 === [__mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 16:16:40,123 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:16:40,123 INFO L82 PathProgramCache]: Analyzing trace with hash -420268702, now seen corresponding path program 5 times [2018-11-23 16:16:40,123 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:16:40,123 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:16:40,129 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:16:40,129 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 16:16:40,129 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:16:40,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:16:40,260 INFO L134 CoverageAnalysis]: Checked inductivity of 122 backedges. 0 proven. 70 refuted. 0 times theorem prover too weak. 52 trivial. 0 not checked. [2018-11-23 16:16:40,260 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 16:16:40,261 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3aa6edf1-6fa3-40b4-81aa-dcdd6600fcc2/bin-2019/uautomizer/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 16:16:40,294 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-11-23 16:16:41,980 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2018-11-23 16:16:41,980 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 16:16:41,983 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 16:16:42,095 INFO L134 CoverageAnalysis]: Checked inductivity of 122 backedges. 1 proven. 51 refuted. 0 times theorem prover too weak. 70 trivial. 0 not checked. [2018-11-23 16:16:42,115 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 16:16:42,116 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 9] total 17 [2018-11-23 16:16:42,116 INFO L459 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-11-23 16:16:42,116 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-11-23 16:16:42,116 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=80, Invalid=192, Unknown=0, NotChecked=0, Total=272 [2018-11-23 16:16:42,116 INFO L87 Difference]: Start difference. First operand 194 states and 229 transitions. Second operand 17 states. [2018-11-23 16:16:42,248 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:16:42,249 INFO L93 Difference]: Finished difference Result 375 states and 447 transitions. [2018-11-23 16:16:42,250 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-11-23 16:16:42,250 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 68 [2018-11-23 16:16:42,250 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:16:42,251 INFO L225 Difference]: With dead ends: 375 [2018-11-23 16:16:42,251 INFO L226 Difference]: Without dead ends: 209 [2018-11-23 16:16:42,252 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 77 GetRequests, 62 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 49 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=80, Invalid=192, Unknown=0, NotChecked=0, Total=272 [2018-11-23 16:16:42,252 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 209 states. [2018-11-23 16:16:42,258 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 209 to 203. [2018-11-23 16:16:42,258 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 203 states. [2018-11-23 16:16:42,259 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 203 states to 203 states and 238 transitions. [2018-11-23 16:16:42,259 INFO L78 Accepts]: Start accepts. Automaton has 203 states and 238 transitions. Word has length 68 [2018-11-23 16:16:42,260 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:16:42,260 INFO L480 AbstractCegarLoop]: Abstraction has 203 states and 238 transitions. [2018-11-23 16:16:42,260 INFO L481 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-11-23 16:16:42,260 INFO L276 IsEmpty]: Start isEmpty. Operand 203 states and 238 transitions. [2018-11-23 16:16:42,260 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2018-11-23 16:16:42,260 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:16:42,261 INFO L402 BasicCegarLoop]: trace histogram [8, 8, 8, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:16:42,261 INFO L423 AbstractCegarLoop]: === Iteration 21 === [__mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 16:16:42,261 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:16:42,261 INFO L82 PathProgramCache]: Analyzing trace with hash -1212679597, now seen corresponding path program 6 times [2018-11-23 16:16:42,262 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:16:42,262 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:16:42,268 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:16:42,268 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 16:16:42,268 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:16:42,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:16:42,403 INFO L134 CoverageAnalysis]: Checked inductivity of 163 backedges. 1 proven. 70 refuted. 0 times theorem prover too weak. 92 trivial. 0 not checked. [2018-11-23 16:16:42,403 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 16:16:42,403 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3aa6edf1-6fa3-40b4-81aa-dcdd6600fcc2/bin-2019/uautomizer/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 16:16:42,430 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-11-23 16:16:49,475 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 9 check-sat command(s) [2018-11-23 16:16:49,475 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 16:16:49,481 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 16:16:49,652 INFO L134 CoverageAnalysis]: Checked inductivity of 163 backedges. 0 proven. 92 refuted. 0 times theorem prover too weak. 71 trivial. 0 not checked. [2018-11-23 16:16:49,675 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 16:16:49,675 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 11] total 19 [2018-11-23 16:16:49,675 INFO L459 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-11-23 16:16:49,676 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-11-23 16:16:49,676 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=99, Invalid=243, Unknown=0, NotChecked=0, Total=342 [2018-11-23 16:16:49,676 INFO L87 Difference]: Start difference. First operand 203 states and 238 transitions. Second operand 19 states. [2018-11-23 16:16:49,844 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:16:49,844 INFO L93 Difference]: Finished difference Result 390 states and 462 transitions. [2018-11-23 16:16:49,845 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-11-23 16:16:49,845 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 74 [2018-11-23 16:16:49,845 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:16:49,846 INFO L225 Difference]: With dead ends: 390 [2018-11-23 16:16:49,847 INFO L226 Difference]: Without dead ends: 218 [2018-11-23 16:16:49,847 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 83 GetRequests, 66 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 63 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=99, Invalid=243, Unknown=0, NotChecked=0, Total=342 [2018-11-23 16:16:49,848 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 218 states. [2018-11-23 16:16:49,858 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 218 to 212. [2018-11-23 16:16:49,858 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 212 states. [2018-11-23 16:16:49,859 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 212 states to 212 states and 247 transitions. [2018-11-23 16:16:49,859 INFO L78 Accepts]: Start accepts. Automaton has 212 states and 247 transitions. Word has length 74 [2018-11-23 16:16:49,859 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:16:49,860 INFO L480 AbstractCegarLoop]: Abstraction has 212 states and 247 transitions. [2018-11-23 16:16:49,860 INFO L481 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-11-23 16:16:49,860 INFO L276 IsEmpty]: Start isEmpty. Operand 212 states and 247 transitions. [2018-11-23 16:16:49,860 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 81 [2018-11-23 16:16:49,861 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:16:49,861 INFO L402 BasicCegarLoop]: trace histogram [9, 9, 9, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:16:49,861 INFO L423 AbstractCegarLoop]: === Iteration 22 === [__mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 16:16:49,862 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:16:49,862 INFO L82 PathProgramCache]: Analyzing trace with hash -38749886, now seen corresponding path program 7 times [2018-11-23 16:16:49,862 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:16:49,862 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:16:49,869 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:16:49,870 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 16:16:49,870 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:16:49,907 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:16:50,104 INFO L134 CoverageAnalysis]: Checked inductivity of 210 backedges. 1 proven. 92 refuted. 0 times theorem prover too weak. 117 trivial. 0 not checked. [2018-11-23 16:16:50,104 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 16:16:50,104 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3aa6edf1-6fa3-40b4-81aa-dcdd6600fcc2/bin-2019/uautomizer/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 16:16:50,156 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:16:50,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:16:50,298 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 16:16:50,476 INFO L134 CoverageAnalysis]: Checked inductivity of 210 backedges. 0 proven. 117 refuted. 0 times theorem prover too weak. 93 trivial. 0 not checked. [2018-11-23 16:16:50,495 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 16:16:50,496 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 12] total 21 [2018-11-23 16:16:50,496 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 16:16:50,496 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 16:16:50,496 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=120, Invalid=300, Unknown=0, NotChecked=0, Total=420 [2018-11-23 16:16:50,497 INFO L87 Difference]: Start difference. First operand 212 states and 247 transitions. Second operand 21 states. [2018-11-23 16:16:50,650 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:16:50,650 INFO L93 Difference]: Finished difference Result 403 states and 475 transitions. [2018-11-23 16:16:50,650 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-11-23 16:16:50,650 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 80 [2018-11-23 16:16:50,651 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:16:50,652 INFO L225 Difference]: With dead ends: 403 [2018-11-23 16:16:50,652 INFO L226 Difference]: Without dead ends: 225 [2018-11-23 16:16:50,653 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 90 GetRequests, 71 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 80 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=120, Invalid=300, Unknown=0, NotChecked=0, Total=420 [2018-11-23 16:16:50,653 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 225 states. [2018-11-23 16:16:50,661 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 225 to 221. [2018-11-23 16:16:50,661 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 221 states. [2018-11-23 16:16:50,662 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 221 states to 221 states and 256 transitions. [2018-11-23 16:16:50,662 INFO L78 Accepts]: Start accepts. Automaton has 221 states and 256 transitions. Word has length 80 [2018-11-23 16:16:50,662 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:16:50,662 INFO L480 AbstractCegarLoop]: Abstraction has 221 states and 256 transitions. [2018-11-23 16:16:50,662 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 16:16:50,662 INFO L276 IsEmpty]: Start isEmpty. Operand 221 states and 256 transitions. [2018-11-23 16:16:50,663 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2018-11-23 16:16:50,663 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:16:50,663 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:16:50,664 INFO L423 AbstractCegarLoop]: === Iteration 23 === [__mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 16:16:50,664 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:16:50,664 INFO L82 PathProgramCache]: Analyzing trace with hash -622054029, now seen corresponding path program 8 times [2018-11-23 16:16:50,664 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:16:50,664 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:16:50,670 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:16:50,670 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:16:50,670 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:16:50,698 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:16:50,845 INFO L134 CoverageAnalysis]: Checked inductivity of 263 backedges. 1 proven. 117 refuted. 0 times theorem prover too weak. 145 trivial. 0 not checked. [2018-11-23 16:16:50,845 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 16:16:50,845 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3aa6edf1-6fa3-40b4-81aa-dcdd6600fcc2/bin-2019/uautomizer/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 16:16:50,868 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-23 16:16:51,004 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-23 16:16:51,004 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 16:16:51,010 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 16:16:51,028 INFO L134 CoverageAnalysis]: Checked inductivity of 263 backedges. 1 proven. 117 refuted. 0 times theorem prover too weak. 145 trivial. 0 not checked. [2018-11-23 16:16:51,050 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 16:16:51,050 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12] total 13 [2018-11-23 16:16:51,050 INFO L459 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-11-23 16:16:51,050 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-11-23 16:16:51,051 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2018-11-23 16:16:51,051 INFO L87 Difference]: Start difference. First operand 221 states and 256 transitions. Second operand 13 states. [2018-11-23 16:16:51,121 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:16:51,121 INFO L93 Difference]: Finished difference Result 373 states and 443 transitions. [2018-11-23 16:16:51,121 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-11-23 16:16:51,122 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 86 [2018-11-23 16:16:51,122 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:16:51,123 INFO L225 Difference]: With dead ends: 373 [2018-11-23 16:16:51,123 INFO L226 Difference]: Without dead ends: 227 [2018-11-23 16:16:51,123 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 97 GetRequests, 86 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2018-11-23 16:16:51,124 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 227 states. [2018-11-23 16:16:51,129 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 227 to 227. [2018-11-23 16:16:51,129 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 227 states. [2018-11-23 16:16:51,130 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 227 states to 227 states and 262 transitions. [2018-11-23 16:16:51,130 INFO L78 Accepts]: Start accepts. Automaton has 227 states and 262 transitions. Word has length 86 [2018-11-23 16:16:51,130 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:16:51,130 INFO L480 AbstractCegarLoop]: Abstraction has 227 states and 262 transitions. [2018-11-23 16:16:51,130 INFO L481 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-11-23 16:16:51,130 INFO L276 IsEmpty]: Start isEmpty. Operand 227 states and 262 transitions. [2018-11-23 16:16:51,131 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-11-23 16:16:51,131 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:16:51,131 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:16:51,131 INFO L423 AbstractCegarLoop]: === Iteration 24 === [__mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 16:16:51,131 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:16:51,132 INFO L82 PathProgramCache]: Analyzing trace with hash -576225228, now seen corresponding path program 9 times [2018-11-23 16:16:51,132 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:16:51,132 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:16:51,138 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:16:51,138 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 16:16:51,138 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:16:51,518 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:16:51,984 WARN L180 SmtUtils]: Spent 107.00 ms on a formula simplification. DAG size of input: 42 DAG size of output: 30 [2018-11-23 16:16:52,401 INFO L134 CoverageAnalysis]: Checked inductivity of 291 backedges. 0 proven. 29 refuted. 0 times theorem prover too weak. 262 trivial. 0 not checked. [2018-11-23 16:16:52,401 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 16:16:52,401 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3aa6edf1-6fa3-40b4-81aa-dcdd6600fcc2/bin-2019/uautomizer/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 16:16:52,424 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-23 16:17:29,497 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2018-11-23 16:17:29,497 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 16:17:29,510 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 16:17:29,925 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-11-23 16:17:29,927 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-23 16:17:29,938 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:17:29,939 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:16, output treesize:15 [2018-11-23 16:17:30,003 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:30,005 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:30,006 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-11-23 16:17:30,007 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-23 16:17:30,044 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 12 [2018-11-23 16:17:30,047 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 11 [2018-11-23 16:17:30,048 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-11-23 16:17:30,051 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:17:30,084 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 12 [2018-11-23 16:17:30,087 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 11 [2018-11-23 16:17:30,087 INFO L267 ElimStorePlain]: Start of recursive call 6: End of recursive call: and 1 xjuncts. [2018-11-23 16:17:30,090 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:17:30,116 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, 2 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:17:30,116 INFO L202 ElimStorePlain]: Needed 6 recursive calls to eliminate 3 variables, input treesize:59, output treesize:49 [2018-11-23 16:17:30,210 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:30,213 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:30,216 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:30,217 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 13 [2018-11-23 16:17:30,218 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-23 16:17:30,322 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 634 treesize of output 452 [2018-11-23 16:17:30,454 WARN L180 SmtUtils]: Spent 129.00 ms on a formula simplification. DAG size of input: 74 DAG size of output: 51 [2018-11-23 16:17:30,463 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:30,467 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 3 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 35 [2018-11-23 16:17:30,467 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-11-23 16:17:30,510 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 154 treesize of output 146 [2018-11-23 16:17:30,515 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 11 [2018-11-23 16:17:30,515 INFO L267 ElimStorePlain]: Start of recursive call 6: End of recursive call: and 1 xjuncts. [2018-11-23 16:17:30,573 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 141 treesize of output 150 [2018-11-23 16:17:30,577 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 104 treesize of output 1 [2018-11-23 16:17:30,578 INFO L267 ElimStorePlain]: Start of recursive call 8: End of recursive call: and 1 xjuncts. [2018-11-23 16:17:30,598 INFO L267 ElimStorePlain]: Start of recursive call 7: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:17:30,616 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-1 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:17:30,634 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:17:30,687 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 191 treesize of output 105 [2018-11-23 16:17:30,736 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:30,739 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 35 [2018-11-23 16:17:30,739 INFO L267 ElimStorePlain]: Start of recursive call 10: End of recursive call: and 1 xjuncts. [2018-11-23 16:17:30,764 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 66 treesize of output 58 [2018-11-23 16:17:30,767 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 11 [2018-11-23 16:17:30,768 INFO L267 ElimStorePlain]: Start of recursive call 12: End of recursive call: and 1 xjuncts. [2018-11-23 16:17:30,807 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 53 treesize of output 70 [2018-11-23 16:17:30,812 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 23 [2018-11-23 16:17:30,812 INFO L267 ElimStorePlain]: Start of recursive call 14: End of recursive call: and 1 xjuncts. [2018-11-23 16:17:30,828 INFO L267 ElimStorePlain]: Start of recursive call 13: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:17:30,838 INFO L267 ElimStorePlain]: Start of recursive call 11: 1 dim-1 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:17:30,848 INFO L267 ElimStorePlain]: Start of recursive call 9: 1 dim-1 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:17:30,884 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 1 dim-1 vars, 2 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-11-23 16:17:30,885 INFO L202 ElimStorePlain]: Needed 14 recursive calls to eliminate 7 variables, input treesize:676, output treesize:101 [2018-11-23 16:17:31,017 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 173 treesize of output 169 [2018-11-23 16:17:31,022 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 47 [2018-11-23 16:17:31,022 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 16:17:31,049 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:17:31,113 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 90 treesize of output 107 [2018-11-23 16:17:31,116 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 1 [2018-11-23 16:17:31,117 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-23 16:17:31,128 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:17:31,157 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-11-23 16:17:31,157 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 5 variables, input treesize:219, output treesize:101 [2018-11-23 16:17:31,187 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 173 treesize of output 169 [2018-11-23 16:17:31,193 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 47 [2018-11-23 16:17:31,193 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 16:17:31,223 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:17:31,298 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 90 treesize of output 107 [2018-11-23 16:17:31,302 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 1 [2018-11-23 16:17:31,302 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-23 16:17:31,317 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:17:31,357 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-11-23 16:17:31,357 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 5 variables, input treesize:219, output treesize:101 [2018-11-23 16:17:31,395 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 173 treesize of output 169 [2018-11-23 16:17:31,400 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 47 [2018-11-23 16:17:31,400 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 16:17:31,418 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:17:31,473 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 90 treesize of output 107 [2018-11-23 16:17:31,476 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 1 [2018-11-23 16:17:31,476 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-23 16:17:31,492 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:17:31,523 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-11-23 16:17:31,524 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 5 variables, input treesize:219, output treesize:101 [2018-11-23 16:17:31,553 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 173 treesize of output 169 [2018-11-23 16:17:31,557 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 47 [2018-11-23 16:17:31,557 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 16:17:31,577 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:17:31,632 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 90 treesize of output 107 [2018-11-23 16:17:31,636 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 1 [2018-11-23 16:17:31,636 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-23 16:17:31,653 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:17:31,685 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-11-23 16:17:31,685 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 5 variables, input treesize:219, output treesize:101 [2018-11-23 16:17:31,719 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 173 treesize of output 169 [2018-11-23 16:17:31,723 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 47 [2018-11-23 16:17:31,724 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 16:17:31,748 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:17:31,803 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 90 treesize of output 107 [2018-11-23 16:17:31,807 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 1 [2018-11-23 16:17:31,807 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-23 16:17:31,820 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:17:31,850 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-11-23 16:17:31,850 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 5 variables, input treesize:219, output treesize:101 [2018-11-23 16:17:31,876 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 173 treesize of output 169 [2018-11-23 16:17:31,880 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 47 [2018-11-23 16:17:31,881 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 16:17:31,900 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:17:31,954 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 90 treesize of output 107 [2018-11-23 16:17:31,957 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 1 [2018-11-23 16:17:31,957 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-23 16:17:31,969 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:17:31,999 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-11-23 16:17:32,000 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 5 variables, input treesize:219, output treesize:101 [2018-11-23 16:17:32,025 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 173 treesize of output 169 [2018-11-23 16:17:32,029 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 47 [2018-11-23 16:17:32,029 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 16:17:32,049 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:17:32,104 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 90 treesize of output 107 [2018-11-23 16:17:32,108 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 1 [2018-11-23 16:17:32,108 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-23 16:17:32,120 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:17:32,152 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-11-23 16:17:32,152 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 5 variables, input treesize:219, output treesize:101 [2018-11-23 16:17:32,177 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 173 treesize of output 169 [2018-11-23 16:17:32,182 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 47 [2018-11-23 16:17:32,182 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 16:17:32,214 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:17:32,282 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 90 treesize of output 107 [2018-11-23 16:17:32,286 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 1 [2018-11-23 16:17:32,286 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-23 16:17:32,300 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:17:32,332 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-11-23 16:17:32,332 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 5 variables, input treesize:219, output treesize:101 [2018-11-23 16:17:32,366 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 149 treesize of output 166 [2018-11-23 16:17:32,370 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 47 [2018-11-23 16:17:32,370 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 16:17:32,390 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:17:32,446 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 114 treesize of output 110 [2018-11-23 16:17:32,450 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 47 [2018-11-23 16:17:32,450 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-23 16:17:32,465 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:17:32,498 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-11-23 16:17:32,498 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 5 variables, input treesize:219, output treesize:101 [2018-11-23 16:17:32,524 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 149 treesize of output 166 [2018-11-23 16:17:32,528 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 1 [2018-11-23 16:17:32,528 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 16:17:32,546 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:17:32,604 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 114 treesize of output 110 [2018-11-23 16:17:32,608 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 47 [2018-11-23 16:17:32,608 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-23 16:17:32,624 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:17:32,657 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-11-23 16:17:32,657 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 5 variables, input treesize:219, output treesize:101 [2018-11-23 16:17:32,949 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 56 treesize of output 48 [2018-11-23 16:17:32,954 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:32,955 INFO L683 Elim1Store]: detected equality via solver [2018-11-23 16:17:32,963 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 44 treesize of output 39 [2018-11-23 16:17:32,963 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 16:17:32,992 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 9 [2018-11-23 16:17:32,993 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-11-23 16:17:32,996 INFO L267 ElimStorePlain]: Start of recursive call 2: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:17:33,024 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 1 dim-2 vars, End of recursive call: 4 dim-0 vars, and 1 xjuncts. [2018-11-23 16:17:33,024 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 5 variables, input treesize:112, output treesize:57 [2018-11-23 16:17:33,146 INFO L134 CoverageAnalysis]: Checked inductivity of 291 backedges. 0 proven. 146 refuted. 0 times theorem prover too weak. 145 trivial. 0 not checked. [2018-11-23 16:17:33,172 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 16:17:33,172 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 21] total 29 [2018-11-23 16:17:33,172 INFO L459 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-11-23 16:17:33,173 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-11-23 16:17:33,173 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=84, Invalid=728, Unknown=0, NotChecked=0, Total=812 [2018-11-23 16:17:33,173 INFO L87 Difference]: Start difference. First operand 227 states and 262 transitions. Second operand 29 states. [2018-11-23 16:17:36,592 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:17:36,592 INFO L93 Difference]: Finished difference Result 450 states and 529 transitions. [2018-11-23 16:17:36,592 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-11-23 16:17:36,592 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 89 [2018-11-23 16:17:36,592 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:17:36,594 INFO L225 Difference]: With dead ends: 450 [2018-11-23 16:17:36,594 INFO L226 Difference]: Without dead ends: 341 [2018-11-23 16:17:36,595 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 126 GetRequests, 75 SyntacticMatches, 9 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 279 ImplicationChecksByTransitivity, 2.9s TimeCoverageRelationStatistics Valid=249, Invalid=1643, Unknown=0, NotChecked=0, Total=1892 [2018-11-23 16:17:36,596 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 341 states. [2018-11-23 16:17:36,609 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 341 to 234. [2018-11-23 16:17:36,609 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 234 states. [2018-11-23 16:17:36,610 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 234 states to 234 states and 272 transitions. [2018-11-23 16:17:36,610 INFO L78 Accepts]: Start accepts. Automaton has 234 states and 272 transitions. Word has length 89 [2018-11-23 16:17:36,611 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:17:36,611 INFO L480 AbstractCegarLoop]: Abstraction has 234 states and 272 transitions. [2018-11-23 16:17:36,611 INFO L481 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-11-23 16:17:36,611 INFO L276 IsEmpty]: Start isEmpty. Operand 234 states and 272 transitions. [2018-11-23 16:17:36,611 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-11-23 16:17:36,611 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:17:36,612 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:17:36,612 INFO L423 AbstractCegarLoop]: === Iteration 25 === [__mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 16:17:36,612 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:17:36,612 INFO L82 PathProgramCache]: Analyzing trace with hash 1101225913, now seen corresponding path program 1 times [2018-11-23 16:17:36,612 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:17:36,612 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:17:36,622 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:17:36,622 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 16:17:36,622 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:17:36,643 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:17:36,724 INFO L134 CoverageAnalysis]: Checked inductivity of 291 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 291 trivial. 0 not checked. [2018-11-23 16:17:36,725 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:17:36,725 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 16:17:36,725 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 16:17:36,725 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 16:17:36,725 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 16:17:36,725 INFO L87 Difference]: Start difference. First operand 234 states and 272 transitions. Second operand 4 states. [2018-11-23 16:17:36,781 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:17:36,781 INFO L93 Difference]: Finished difference Result 235 states and 273 transitions. [2018-11-23 16:17:36,782 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 16:17:36,782 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 90 [2018-11-23 16:17:36,783 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:17:36,784 INFO L225 Difference]: With dead ends: 235 [2018-11-23 16:17:36,784 INFO L226 Difference]: Without dead ends: 234 [2018-11-23 16:17:36,784 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-23 16:17:36,784 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 234 states. [2018-11-23 16:17:36,793 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 234 to 233. [2018-11-23 16:17:36,794 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 233 states. [2018-11-23 16:17:36,795 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 233 states to 233 states and 271 transitions. [2018-11-23 16:17:36,795 INFO L78 Accepts]: Start accepts. Automaton has 233 states and 271 transitions. Word has length 90 [2018-11-23 16:17:36,795 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:17:36,795 INFO L480 AbstractCegarLoop]: Abstraction has 233 states and 271 transitions. [2018-11-23 16:17:36,795 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 16:17:36,795 INFO L276 IsEmpty]: Start isEmpty. Operand 233 states and 271 transitions. [2018-11-23 16:17:36,796 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 92 [2018-11-23 16:17:36,796 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:17:36,796 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:17:36,796 INFO L423 AbstractCegarLoop]: === Iteration 26 === [__mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 16:17:36,797 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:17:36,797 INFO L82 PathProgramCache]: Analyzing trace with hash -221734862, now seen corresponding path program 1 times [2018-11-23 16:17:36,797 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:17:36,797 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:17:36,803 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:17:36,803 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:17:36,803 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:17:36,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:17:36,871 INFO L134 CoverageAnalysis]: Checked inductivity of 291 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 291 trivial. 0 not checked. [2018-11-23 16:17:36,872 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:17:36,872 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 16:17:36,872 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 16:17:36,872 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 16:17:36,872 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:17:36,873 INFO L87 Difference]: Start difference. First operand 233 states and 271 transitions. Second operand 3 states. [2018-11-23 16:17:36,891 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:17:36,891 INFO L93 Difference]: Finished difference Result 237 states and 275 transitions. [2018-11-23 16:17:36,892 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 16:17:36,892 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 91 [2018-11-23 16:17:36,892 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:17:36,893 INFO L225 Difference]: With dead ends: 237 [2018-11-23 16:17:36,893 INFO L226 Difference]: Without dead ends: 236 [2018-11-23 16:17:36,893 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:17:36,894 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 236 states. [2018-11-23 16:17:36,903 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 236 to 236. [2018-11-23 16:17:36,903 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 236 states. [2018-11-23 16:17:36,904 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 236 states to 236 states and 274 transitions. [2018-11-23 16:17:36,904 INFO L78 Accepts]: Start accepts. Automaton has 236 states and 274 transitions. Word has length 91 [2018-11-23 16:17:36,904 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:17:36,904 INFO L480 AbstractCegarLoop]: Abstraction has 236 states and 274 transitions. [2018-11-23 16:17:36,904 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 16:17:36,904 INFO L276 IsEmpty]: Start isEmpty. Operand 236 states and 274 transitions. [2018-11-23 16:17:36,905 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-11-23 16:17:36,905 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:17:36,905 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 10, 10, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:17:36,906 INFO L423 AbstractCegarLoop]: === Iteration 27 === [__mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 16:17:36,906 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:17:36,906 INFO L82 PathProgramCache]: Analyzing trace with hash -43375882, now seen corresponding path program 1 times [2018-11-23 16:17:36,906 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:17:36,906 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:17:36,933 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:17:36,933 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:17:36,933 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:17:36,956 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:17:37,008 INFO L134 CoverageAnalysis]: Checked inductivity of 294 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 291 trivial. 0 not checked. [2018-11-23 16:17:37,008 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:17:37,008 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 16:17:37,008 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 16:17:37,009 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 16:17:37,009 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:17:37,009 INFO L87 Difference]: Start difference. First operand 236 states and 274 transitions. Second operand 3 states. [2018-11-23 16:17:37,023 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:17:37,023 INFO L93 Difference]: Finished difference Result 236 states and 274 transitions. [2018-11-23 16:17:37,024 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 16:17:37,024 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 94 [2018-11-23 16:17:37,025 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:17:37,026 INFO L225 Difference]: With dead ends: 236 [2018-11-23 16:17:37,026 INFO L226 Difference]: Without dead ends: 219 [2018-11-23 16:17:37,026 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:17:37,026 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 219 states. [2018-11-23 16:17:37,034 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 219 to 218. [2018-11-23 16:17:37,035 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 218 states. [2018-11-23 16:17:37,035 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 218 states to 218 states and 250 transitions. [2018-11-23 16:17:37,035 INFO L78 Accepts]: Start accepts. Automaton has 218 states and 250 transitions. Word has length 94 [2018-11-23 16:17:37,036 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:17:37,036 INFO L480 AbstractCegarLoop]: Abstraction has 218 states and 250 transitions. [2018-11-23 16:17:37,036 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 16:17:37,036 INFO L276 IsEmpty]: Start isEmpty. Operand 218 states and 250 transitions. [2018-11-23 16:17:37,037 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 115 [2018-11-23 16:17:37,037 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:17:37,037 INFO L402 BasicCegarLoop]: trace histogram [20, 20, 20, 10, 10, 10, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:17:37,038 INFO L423 AbstractCegarLoop]: === Iteration 28 === [__mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 16:17:37,038 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:17:37,038 INFO L82 PathProgramCache]: Analyzing trace with hash 1510247437, now seen corresponding path program 1 times [2018-11-23 16:17:37,038 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:17:37,038 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:17:37,044 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:17:37,044 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:17:37,045 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:17:37,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:17:37,136 INFO L134 CoverageAnalysis]: Checked inductivity of 759 backedges. 324 proven. 0 refuted. 0 times theorem prover too weak. 435 trivial. 0 not checked. [2018-11-23 16:17:37,136 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:17:37,136 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 16:17:37,136 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 16:17:37,136 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 16:17:37,137 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:17:37,137 INFO L87 Difference]: Start difference. First operand 218 states and 250 transitions. Second operand 3 states. [2018-11-23 16:17:37,159 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:17:37,159 INFO L93 Difference]: Finished difference Result 218 states and 250 transitions. [2018-11-23 16:17:37,161 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 16:17:37,161 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 114 [2018-11-23 16:17:37,161 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:17:37,162 INFO L225 Difference]: With dead ends: 218 [2018-11-23 16:17:37,162 INFO L226 Difference]: Without dead ends: 217 [2018-11-23 16:17:37,162 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 16:17:37,163 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 217 states. [2018-11-23 16:17:37,171 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 217 to 217. [2018-11-23 16:17:37,171 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 217 states. [2018-11-23 16:17:37,172 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 217 states to 217 states and 249 transitions. [2018-11-23 16:17:37,172 INFO L78 Accepts]: Start accepts. Automaton has 217 states and 249 transitions. Word has length 114 [2018-11-23 16:17:37,173 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:17:37,173 INFO L480 AbstractCegarLoop]: Abstraction has 217 states and 249 transitions. [2018-11-23 16:17:37,173 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 16:17:37,173 INFO L276 IsEmpty]: Start isEmpty. Operand 217 states and 249 transitions. [2018-11-23 16:17:37,174 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 127 [2018-11-23 16:17:37,174 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:17:37,174 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:17:37,175 INFO L423 AbstractCegarLoop]: === Iteration 29 === [__mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 16:17:37,175 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:17:37,175 INFO L82 PathProgramCache]: Analyzing trace with hash 1035682170, now seen corresponding path program 1 times [2018-11-23 16:17:37,175 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:17:37,175 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:17:37,181 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:17:37,182 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:17:37,182 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:17:37,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:17:37,275 INFO L134 CoverageAnalysis]: Checked inductivity of 291 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 291 trivial. 0 not checked. [2018-11-23 16:17:37,275 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:17:37,275 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 16:17:37,276 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 16:17:37,276 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 16:17:37,276 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-23 16:17:37,276 INFO L87 Difference]: Start difference. First operand 217 states and 249 transitions. Second operand 4 states. [2018-11-23 16:17:37,302 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:17:37,302 INFO L93 Difference]: Finished difference Result 225 states and 258 transitions. [2018-11-23 16:17:37,303 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 16:17:37,303 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 126 [2018-11-23 16:17:37,303 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:17:37,304 INFO L225 Difference]: With dead ends: 225 [2018-11-23 16:17:37,304 INFO L226 Difference]: Without dead ends: 224 [2018-11-23 16:17:37,304 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-23 16:17:37,305 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 224 states. [2018-11-23 16:17:37,314 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 224 to 222. [2018-11-23 16:17:37,314 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 222 states. [2018-11-23 16:17:37,315 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 222 states to 222 states and 255 transitions. [2018-11-23 16:17:37,315 INFO L78 Accepts]: Start accepts. Automaton has 222 states and 255 transitions. Word has length 126 [2018-11-23 16:17:37,315 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:17:37,315 INFO L480 AbstractCegarLoop]: Abstraction has 222 states and 255 transitions. [2018-11-23 16:17:37,315 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 16:17:37,315 INFO L276 IsEmpty]: Start isEmpty. Operand 222 states and 255 transitions. [2018-11-23 16:17:37,316 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 128 [2018-11-23 16:17:37,316 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:17:37,317 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:17:37,317 INFO L423 AbstractCegarLoop]: === Iteration 30 === [__mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 16:17:37,317 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:17:37,317 INFO L82 PathProgramCache]: Analyzing trace with hash 2041376282, now seen corresponding path program 1 times [2018-11-23 16:17:37,317 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:17:37,317 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:17:37,323 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:17:37,324 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:17:37,324 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:17:37,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:17:37,405 INFO L134 CoverageAnalysis]: Checked inductivity of 291 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 291 trivial. 0 not checked. [2018-11-23 16:17:37,405 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 16:17:37,406 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 16:17:37,406 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 16:17:37,406 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 16:17:37,407 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-23 16:17:37,407 INFO L87 Difference]: Start difference. First operand 222 states and 255 transitions. Second operand 4 states. [2018-11-23 16:17:37,430 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 16:17:37,430 INFO L93 Difference]: Finished difference Result 224 states and 257 transitions. [2018-11-23 16:17:37,431 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 16:17:37,431 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 127 [2018-11-23 16:17:37,431 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 16:17:37,432 INFO L225 Difference]: With dead ends: 224 [2018-11-23 16:17:37,432 INFO L226 Difference]: Without dead ends: 223 [2018-11-23 16:17:37,433 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-11-23 16:17:37,433 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 223 states. [2018-11-23 16:17:37,442 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 223 to 223. [2018-11-23 16:17:37,442 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 223 states. [2018-11-23 16:17:37,443 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 223 states to 223 states and 256 transitions. [2018-11-23 16:17:37,443 INFO L78 Accepts]: Start accepts. Automaton has 223 states and 256 transitions. Word has length 127 [2018-11-23 16:17:37,443 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 16:17:37,443 INFO L480 AbstractCegarLoop]: Abstraction has 223 states and 256 transitions. [2018-11-23 16:17:37,443 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 16:17:37,443 INFO L276 IsEmpty]: Start isEmpty. Operand 223 states and 256 transitions. [2018-11-23 16:17:37,444 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 124 [2018-11-23 16:17:37,445 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 16:17:37,445 INFO L402 BasicCegarLoop]: trace histogram [20, 20, 20, 10, 10, 10, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 16:17:37,445 INFO L423 AbstractCegarLoop]: === Iteration 31 === [__mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, __mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, full_writeErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 16:17:37,445 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 16:17:37,445 INFO L82 PathProgramCache]: Analyzing trace with hash -1749488180, now seen corresponding path program 10 times [2018-11-23 16:17:37,445 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 16:17:37,446 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 16:17:37,453 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:17:37,453 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 16:17:37,453 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 16:17:38,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 16:17:39,452 WARN L180 SmtUtils]: Spent 196.00 ms on a formula simplification. DAG size of input: 81 DAG size of output: 52 [2018-11-23 16:17:39,591 WARN L180 SmtUtils]: Spent 121.00 ms on a formula simplification. DAG size of input: 61 DAG size of output: 45 [2018-11-23 16:17:39,733 WARN L180 SmtUtils]: Spent 120.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 46 [2018-11-23 16:17:39,901 WARN L180 SmtUtils]: Spent 121.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 46 [2018-11-23 16:17:40,084 WARN L180 SmtUtils]: Spent 125.00 ms on a formula simplification. DAG size of input: 63 DAG size of output: 46 [2018-11-23 16:17:41,176 WARN L180 SmtUtils]: Spent 106.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 40 [2018-11-23 16:17:41,334 WARN L180 SmtUtils]: Spent 112.00 ms on a formula simplification. DAG size of input: 63 DAG size of output: 46 [2018-11-23 16:17:41,504 WARN L180 SmtUtils]: Spent 120.00 ms on a formula simplification. DAG size of input: 75 DAG size of output: 46 [2018-11-23 16:17:41,709 WARN L180 SmtUtils]: Spent 110.00 ms on a formula simplification. DAG size of input: 68 DAG size of output: 46 [2018-11-23 16:17:41,936 WARN L180 SmtUtils]: Spent 123.00 ms on a formula simplification. DAG size of input: 71 DAG size of output: 46 [2018-11-23 16:17:42,105 WARN L180 SmtUtils]: Spent 115.00 ms on a formula simplification. DAG size of input: 64 DAG size of output: 46 [2018-11-23 16:17:42,284 WARN L180 SmtUtils]: Spent 118.00 ms on a formula simplification. DAG size of input: 67 DAG size of output: 47 [2018-11-23 16:17:42,522 WARN L180 SmtUtils]: Spent 116.00 ms on a formula simplification. DAG size of input: 66 DAG size of output: 47 [2018-11-23 16:17:42,774 WARN L180 SmtUtils]: Spent 124.00 ms on a formula simplification. DAG size of input: 72 DAG size of output: 47 [2018-11-23 16:17:42,992 WARN L180 SmtUtils]: Spent 143.00 ms on a formula simplification. DAG size of input: 72 DAG size of output: 47 [2018-11-23 16:17:43,247 WARN L180 SmtUtils]: Spent 170.00 ms on a formula simplification. DAG size of input: 76 DAG size of output: 46 [2018-11-23 16:17:43,564 WARN L180 SmtUtils]: Spent 131.00 ms on a formula simplification. DAG size of input: 70 DAG size of output: 47 [2018-11-23 16:17:43,839 WARN L180 SmtUtils]: Spent 119.00 ms on a formula simplification. DAG size of input: 66 DAG size of output: 46 [2018-11-23 16:17:44,895 INFO L134 CoverageAnalysis]: Checked inductivity of 761 backedges. 0 proven. 613 refuted. 0 times theorem prover too weak. 148 trivial. 0 not checked. [2018-11-23 16:17:44,896 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 16:17:44,896 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_3aa6edf1-6fa3-40b4-81aa-dcdd6600fcc2/bin-2019/uautomizer/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 16:17:44,916 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-23 16:17:45,096 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-23 16:17:45,097 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 16:17:45,107 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 16:17:45,117 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 164 treesize of output 151 [2018-11-23 16:17:45,132 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:45,167 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 151 treesize of output 142 [2018-11-23 16:17:45,177 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:45,196 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:45,253 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 138 treesize of output 133 [2018-11-23 16:17:45,275 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 127 treesize of output 118 [2018-11-23 16:17:45,358 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:45,362 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:45,366 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:45,369 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:45,370 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 6 disjoint index pairs (out of 6 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 104 treesize of output 120 [2018-11-23 16:17:45,613 WARN L180 SmtUtils]: Spent 241.00 ms on a formula simplification. DAG size of input: 52 DAG size of output: 42 [2018-11-23 16:17:45,655 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:45,661 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:45,685 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:45,691 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:45,696 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:45,700 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:45,703 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:45,708 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:45,709 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 11 disjoint index pairs (out of 15 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 91 treesize of output 130 [2018-11-23 16:17:45,818 WARN L180 SmtUtils]: Spent 107.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 50 [2018-11-23 16:17:45,833 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:45,835 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:45,840 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:45,842 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:45,843 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:45,845 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:45,846 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:45,848 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:45,849 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:45,850 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:45,852 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 17 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 76 treesize of output 140 [2018-11-23 16:17:46,106 WARN L180 SmtUtils]: Spent 253.00 ms on a formula simplification. DAG size of input: 73 DAG size of output: 59 [2018-11-23 16:17:46,125 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:46,135 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:46,144 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:46,153 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:46,157 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:46,161 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:46,164 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:46,168 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:46,171 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:46,173 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:46,175 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:46,178 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:46,179 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 8 select indices, 8 select index equivalence classes, 24 disjoint index pairs (out of 28 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 64 treesize of output 161 [2018-11-23 16:17:46,402 WARN L180 SmtUtils]: Spent 220.00 ms on a formula simplification. DAG size of input: 86 DAG size of output: 70 [2018-11-23 16:17:46,414 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:46,418 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:46,423 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:46,428 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:46,430 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:46,433 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:46,435 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:46,437 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:46,439 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:46,441 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:46,443 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:46,445 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:46,447 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:46,449 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:46,450 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 32 disjoint index pairs (out of 36 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 55 treesize of output 185 [2018-11-23 16:17:46,468 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 32 disjoint index pairs (out of 36 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 58 treesize of output 179 [2018-11-23 16:17:46,469 INFO L267 ElimStorePlain]: Start of recursive call 11: End of recursive call: and 1 xjuncts. [2018-11-23 16:17:46,568 INFO L267 ElimStorePlain]: Start of recursive call 10: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:17:46,668 INFO L267 ElimStorePlain]: Start of recursive call 9: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:17:46,775 INFO L267 ElimStorePlain]: Start of recursive call 8: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:17:46,899 INFO L267 ElimStorePlain]: Start of recursive call 7: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:17:47,012 INFO L267 ElimStorePlain]: Start of recursive call 6: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:17:47,132 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:17:47,357 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:47,373 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:47,398 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:47,455 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 125 treesize of output 124 [2018-11-23 16:17:48,108 WARN L180 SmtUtils]: Spent 651.00 ms on a formula simplification. DAG size of input: 72 DAG size of output: 72 [2018-11-23 16:17:48,139 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:48,144 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:48,165 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:48,172 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:48,188 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:48,194 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:48,235 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:48,236 INFO L303 Elim1Store]: Index analysis took 126 ms [2018-11-23 16:17:48,292 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 8 disjoint index pairs (out of 10 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 113 treesize of output 137 [2018-11-23 16:17:49,104 WARN L180 SmtUtils]: Spent 810.00 ms on a formula simplification. DAG size of input: 88 DAG size of output: 76 [2018-11-23 16:17:49,134 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:49,139 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:49,145 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:49,151 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:49,167 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:49,172 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:49,176 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:49,179 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:49,184 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:49,185 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 13 disjoint index pairs (out of 15 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 110 treesize of output 150 [2018-11-23 16:17:49,476 WARN L180 SmtUtils]: Spent 290.00 ms on a formula simplification. DAG size of input: 72 DAG size of output: 54 [2018-11-23 16:17:49,501 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:49,506 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:49,511 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:49,516 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:49,528 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:49,531 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:49,535 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:49,538 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:49,542 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:49,545 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:49,549 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:49,550 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 19 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 76 treesize of output 148 [2018-11-23 16:17:49,815 WARN L180 SmtUtils]: Spent 264.00 ms on a formula simplification. DAG size of input: 77 DAG size of output: 63 [2018-11-23 16:17:49,828 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:49,839 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:49,842 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:49,846 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:49,850 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:49,859 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:49,863 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:49,866 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:49,870 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:49,874 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:49,877 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:49,880 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:49,881 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 8 select indices, 8 select index equivalence classes, 26 disjoint index pairs (out of 28 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 64 treesize of output 169 [2018-11-23 16:17:50,128 WARN L180 SmtUtils]: Spent 245.00 ms on a formula simplification. DAG size of input: 90 DAG size of output: 74 [2018-11-23 16:17:50,137 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:50,142 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:50,144 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:50,146 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:50,148 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:50,155 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:50,158 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:50,160 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:50,163 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:50,165 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:50,167 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:50,169 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:50,171 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:50,173 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:50,174 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 34 disjoint index pairs (out of 36 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 55 treesize of output 193 [2018-11-23 16:17:50,186 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 34 disjoint index pairs (out of 36 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 58 treesize of output 187 [2018-11-23 16:17:50,187 INFO L267 ElimStorePlain]: Start of recursive call 18: End of recursive call: and 1 xjuncts. [2018-11-23 16:17:50,294 INFO L267 ElimStorePlain]: Start of recursive call 17: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:17:50,401 INFO L267 ElimStorePlain]: Start of recursive call 16: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:17:50,511 INFO L267 ElimStorePlain]: Start of recursive call 15: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:17:50,637 INFO L267 ElimStorePlain]: Start of recursive call 14: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:17:50,873 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:50,878 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:50,884 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:50,910 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:50,916 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:50,922 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:50,936 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:50,943 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:50,949 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:50,952 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:50,956 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:50,960 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:50,996 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:50,996 INFO L303 Elim1Store]: Index analysis took 163 ms [2018-11-23 16:17:51,038 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 14 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 100 treesize of output 148 [2018-11-23 16:17:51,814 WARN L180 SmtUtils]: Spent 774.00 ms on a formula simplification. DAG size of input: 98 DAG size of output: 84 [2018-11-23 16:17:51,847 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:51,851 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:51,864 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:51,868 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:51,882 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:51,887 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:51,892 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:51,897 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:51,902 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:51,907 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:51,912 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:51,913 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 16 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 99 treesize of output 154 [2018-11-23 16:17:52,193 WARN L180 SmtUtils]: Spent 278.00 ms on a formula simplification. DAG size of input: 79 DAG size of output: 57 [2018-11-23 16:17:52,213 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:52,220 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:52,227 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:52,237 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:52,241 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:52,250 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:52,254 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:52,258 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:52,262 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:52,265 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:52,269 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:52,273 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:52,277 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:52,278 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 8 select indices, 8 select index equivalence classes, 23 disjoint index pairs (out of 28 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 64 treesize of output 157 [2018-11-23 16:17:52,495 WARN L180 SmtUtils]: Spent 214.00 ms on a formula simplification. DAG size of input: 84 DAG size of output: 68 [2018-11-23 16:17:52,507 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:52,511 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:52,516 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:52,521 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:52,523 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:52,528 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:52,530 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:52,532 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:52,534 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:52,536 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:52,538 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:52,541 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:52,543 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:52,545 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:52,546 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 31 disjoint index pairs (out of 36 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 55 treesize of output 181 [2018-11-23 16:17:52,564 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 31 disjoint index pairs (out of 36 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 58 treesize of output 175 [2018-11-23 16:17:52,565 INFO L267 ElimStorePlain]: Start of recursive call 23: End of recursive call: and 1 xjuncts. [2018-11-23 16:17:52,665 INFO L267 ElimStorePlain]: Start of recursive call 22: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:17:52,766 INFO L267 ElimStorePlain]: Start of recursive call 21: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:17:52,878 INFO L267 ElimStorePlain]: Start of recursive call 20: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:17:53,099 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:53,103 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:53,106 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:53,128 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:53,133 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:53,138 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:53,152 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:53,156 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:53,161 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:53,166 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:53,171 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:53,176 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:53,181 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:53,196 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:53,209 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:53,223 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:53,223 INFO L303 Elim1Store]: Index analysis took 153 ms [2018-11-23 16:17:53,251 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 8 select indices, 8 select index equivalence classes, 21 disjoint index pairs (out of 28 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 101 treesize of output 162 [2018-11-23 16:17:54,030 WARN L180 SmtUtils]: Spent 776.00 ms on a formula simplification. DAG size of input: 110 DAG size of output: 90 [2018-11-23 16:17:54,051 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:54,058 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:54,063 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:54,073 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:54,083 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:54,086 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:54,090 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:54,097 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:54,100 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:54,103 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:54,105 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:54,108 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:54,116 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:54,120 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:54,122 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:54,126 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:54,136 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:54,140 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:54,150 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:54,151 INFO L303 Elim1Store]: Index analysis took 119 ms [2018-11-23 16:17:54,172 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 29 disjoint index pairs (out of 36 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 109 treesize of output 187 [2018-11-23 16:17:54,946 WARN L180 SmtUtils]: Spent 771.00 ms on a formula simplification. DAG size of input: 124 DAG size of output: 100 [2018-11-23 16:17:54,959 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:54,964 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:54,966 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:54,971 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:54,975 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:54,978 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:54,980 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:54,985 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:54,987 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:54,989 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:54,991 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:54,994 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:54,996 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:55,001 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:55,003 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:55,006 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:55,008 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:55,010 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:55,012 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:55,014 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:55,016 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:55,024 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:55,039 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 10 select indices, 10 select index equivalence classes, 38 disjoint index pairs (out of 45 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 124 treesize of output 215 [2018-11-23 16:17:55,060 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 31 disjoint index pairs (out of 36 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 209 treesize of output 203 [2018-11-23 16:17:55,061 INFO L267 ElimStorePlain]: Start of recursive call 27: End of recursive call: and 1 xjuncts. [2018-11-23 16:17:55,544 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:55,546 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:55,555 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:55,557 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:55,562 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:55,565 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:55,567 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:55,569 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:55,571 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:55,574 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:55,576 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:55,578 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:55,580 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:55,582 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:55,585 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:55,587 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:55,596 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:55,610 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 10 select indices, 10 select index equivalence classes, 39 disjoint index pairs (out of 45 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 145 treesize of output 213 [2018-11-23 16:17:55,612 INFO L267 ElimStorePlain]: Start of recursive call 28: End of recursive call: and 2 xjuncts. [2018-11-23 16:17:56,148 INFO L267 ElimStorePlain]: Start of recursive call 26: 2 dim-1 vars, End of recursive call: and 3 xjuncts. [2018-11-23 16:17:56,698 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:56,703 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:56,708 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:56,713 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:56,715 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:56,720 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:56,721 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:56,723 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:56,725 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:56,727 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:56,729 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:56,731 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:56,732 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:56,734 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:56,736 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:56,737 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 31 disjoint index pairs (out of 36 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 122 treesize of output 193 [2018-11-23 16:17:56,756 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 31 disjoint index pairs (out of 36 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 58 treesize of output 175 [2018-11-23 16:17:56,756 INFO L267 ElimStorePlain]: Start of recursive call 30: End of recursive call: and 1 xjuncts. [2018-11-23 16:17:56,888 INFO L267 ElimStorePlain]: Start of recursive call 29: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:17:57,461 INFO L267 ElimStorePlain]: Start of recursive call 25: 2 dim-1 vars, End of recursive call: and 4 xjuncts. [2018-11-23 16:17:58,157 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:58,165 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:58,172 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:58,181 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:58,185 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:58,194 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:58,198 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:58,202 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:58,205 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:58,209 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:58,212 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:58,216 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:58,219 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:58,220 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 8 select indices, 8 select index equivalence classes, 23 disjoint index pairs (out of 28 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 107 treesize of output 169 [2018-11-23 16:17:58,450 WARN L180 SmtUtils]: Spent 228.00 ms on a formula simplification. DAG size of input: 90 DAG size of output: 68 [2018-11-23 16:17:58,462 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:58,466 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:58,471 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:58,479 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:58,481 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:58,486 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:58,488 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:58,490 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:58,492 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:58,494 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:58,496 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:58,498 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:58,499 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:58,501 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:58,503 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:17:58,504 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 31 disjoint index pairs (out of 36 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 55 treesize of output 181 [2018-11-23 16:17:58,525 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 31 disjoint index pairs (out of 36 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 58 treesize of output 175 [2018-11-23 16:17:58,525 INFO L267 ElimStorePlain]: Start of recursive call 33: End of recursive call: and 1 xjuncts. [2018-11-23 16:17:58,625 INFO L267 ElimStorePlain]: Start of recursive call 32: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:17:58,740 INFO L267 ElimStorePlain]: Start of recursive call 31: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:17:59,506 INFO L267 ElimStorePlain]: Start of recursive call 24: 2 dim-1 vars, End of recursive call: and 5 xjuncts. [2018-11-23 16:18:00,336 INFO L267 ElimStorePlain]: Start of recursive call 19: 2 dim-1 vars, End of recursive call: and 6 xjuncts. [2018-11-23 16:18:01,267 INFO L267 ElimStorePlain]: Start of recursive call 13: 2 dim-1 vars, End of recursive call: and 7 xjuncts. [2018-11-23 16:18:02,348 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:02,372 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:02,387 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:02,399 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:02,400 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 7 disjoint index pairs (out of 6 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 119 treesize of output 135 [2018-11-23 16:18:02,657 WARN L180 SmtUtils]: Spent 256.00 ms on a formula simplification. DAG size of input: 59 DAG size of output: 45 [2018-11-23 16:18:02,676 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:02,683 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:02,706 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:02,712 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:02,728 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:02,734 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:02,741 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:02,746 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:02,752 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:02,752 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 12 disjoint index pairs (out of 15 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 91 treesize of output 134 [2018-11-23 16:18:02,865 WARN L180 SmtUtils]: Spent 111.00 ms on a formula simplification. DAG size of input: 64 DAG size of output: 52 [2018-11-23 16:18:02,872 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:02,873 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:02,879 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:02,880 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:02,884 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:02,885 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:02,887 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:02,888 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:02,889 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:02,891 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:02,892 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 18 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 76 treesize of output 146 [2018-11-23 16:18:03,177 WARN L180 SmtUtils]: Spent 284.00 ms on a formula simplification. DAG size of input: 75 DAG size of output: 61 [2018-11-23 16:18:03,191 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:03,195 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:03,204 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:03,215 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:03,218 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:03,227 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:03,230 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:03,234 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:03,238 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:03,242 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:03,246 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:03,252 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:03,254 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 8 select indices, 8 select index equivalence classes, 25 disjoint index pairs (out of 28 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 64 treesize of output 165 [2018-11-23 16:18:03,515 WARN L180 SmtUtils]: Spent 259.00 ms on a formula simplification. DAG size of input: 88 DAG size of output: 72 [2018-11-23 16:18:03,524 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:03,526 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:03,531 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:03,536 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:03,538 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:03,543 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:03,546 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:03,548 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:03,550 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:03,551 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:03,554 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:03,556 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:03,558 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:03,560 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:03,561 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 33 disjoint index pairs (out of 36 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 55 treesize of output 189 [2018-11-23 16:18:03,574 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 33 disjoint index pairs (out of 36 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 58 treesize of output 183 [2018-11-23 16:18:03,575 INFO L267 ElimStorePlain]: Start of recursive call 39: End of recursive call: and 1 xjuncts. [2018-11-23 16:18:03,677 INFO L267 ElimStorePlain]: Start of recursive call 38: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:18:03,789 INFO L267 ElimStorePlain]: Start of recursive call 37: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:18:03,911 INFO L267 ElimStorePlain]: Start of recursive call 36: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:18:04,038 INFO L267 ElimStorePlain]: Start of recursive call 35: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:18:04,187 INFO L267 ElimStorePlain]: Start of recursive call 34: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:18:05,267 INFO L267 ElimStorePlain]: Start of recursive call 12: 2 dim-1 vars, End of recursive call: and 8 xjuncts. [2018-11-23 16:18:06,480 INFO L267 ElimStorePlain]: Start of recursive call 4: 2 dim-1 vars, End of recursive call: and 9 xjuncts. [2018-11-23 16:18:07,831 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 136 treesize of output 123 [2018-11-23 16:18:07,858 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 120 treesize of output 107 [2018-11-23 16:18:07,983 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:08,008 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:08,023 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:08,039 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:08,039 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 5 disjoint index pairs (out of 6 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 104 treesize of output 116 [2018-11-23 16:18:08,245 WARN L180 SmtUtils]: Spent 205.00 ms on a formula simplification. DAG size of input: 50 DAG size of output: 40 [2018-11-23 16:18:08,279 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:08,286 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:08,309 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:08,324 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:08,329 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:08,335 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:08,338 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:08,343 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:08,344 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 10 disjoint index pairs (out of 15 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 91 treesize of output 126 [2018-11-23 16:18:08,613 WARN L180 SmtUtils]: Spent 267.00 ms on a formula simplification. DAG size of input: 60 DAG size of output: 48 [2018-11-23 16:18:08,639 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:08,642 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:08,662 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:08,666 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:08,680 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:08,685 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:08,690 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:08,695 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:08,699 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:08,704 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:08,705 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 16 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 76 treesize of output 138 [2018-11-23 16:18:08,833 WARN L180 SmtUtils]: Spent 127.00 ms on a formula simplification. DAG size of input: 71 DAG size of output: 57 [2018-11-23 16:18:08,841 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:08,844 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:08,848 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:08,851 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:08,853 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:08,856 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:08,858 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:08,860 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:08,861 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:08,863 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:08,865 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:08,866 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:08,867 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 8 select indices, 8 select index equivalence classes, 23 disjoint index pairs (out of 28 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 64 treesize of output 157 [2018-11-23 16:18:09,092 WARN L180 SmtUtils]: Spent 223.00 ms on a formula simplification. DAG size of input: 84 DAG size of output: 68 [2018-11-23 16:18:09,104 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:09,109 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:09,115 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:09,120 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:09,122 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:09,127 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:09,129 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:09,131 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:09,133 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:09,135 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:09,137 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:09,139 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:09,141 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:09,143 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 16:18:09,144 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 31 disjoint index pairs (out of 36 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 55 treesize of output 181 [2018-11-23 16:18:09,162 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 31 disjoint index pairs (out of 36 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 58 treesize of output 175 [2018-11-23 16:18:09,163 INFO L267 ElimStorePlain]: Start of recursive call 47: End of recursive call: and 1 xjuncts. [2018-11-23 16:18:09,279 INFO L267 ElimStorePlain]: Start of recursive call 46: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:18:09,379 INFO L267 ElimStorePlain]: Start of recursive call 45: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:18:09,485 INFO L267 ElimStorePlain]: Start of recursive call 44: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:18:09,596 INFO L267 ElimStorePlain]: Start of recursive call 43: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:18:09,706 INFO L267 ElimStorePlain]: Start of recursive call 42: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:18:09,821 INFO L267 ElimStorePlain]: Start of recursive call 41: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:18:09,938 INFO L267 ElimStorePlain]: Start of recursive call 40: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 16:18:11,261 INFO L267 ElimStorePlain]: Start of recursive call 3: 2 dim-1 vars, End of recursive call: and 10 xjuncts. [2018-11-23 16:18:12,570 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 10 xjuncts. [2018-11-23 16:18:13,944 INFO L267 ElimStorePlain]: Start of recursive call 1: 7 dim-0 vars, 1 dim-1 vars, End of recursive call: 63 dim-0 vars, and 10 xjuncts. [2018-11-23 16:18:13,945 INFO L202 ElimStorePlain]: Needed 47 recursive calls to eliminate 8 variables, input treesize:174, output treesize:1772 [2018-11-23 16:18:42,923 WARN L194 Executor]: External (z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000) stderr output: (error "out of memory") [2018-11-23 16:18:43,123 WARN L521 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 15 z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 16:18:43,124 FATAL L265 ToolchainWalker]: An unrecoverable error occured during an interaction with an SMT solver: de.uni_freiburg.informatik.ultimate.logic.SMTLIBException: External (z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000)Received EOF on stdin. stderr output: (error "out of memory") at de.uni_freiburg.informatik.ultimate.smtsolver.external.Executor.parse(Executor.java:208) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Executor.parseCheckSatResult(Executor.java:225) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Scriptor.checkSat(Scriptor.java:155) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.WrapperScript.checkSat(WrapperScript.java:116) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.WrapperScript.checkSat(WrapperScript.java:116) at de.uni_freiburg.informatik.ultimate.logic.Util.checkSat(Util.java:61) at de.uni_freiburg.informatik.ultimate.logic.simplification.SimplifyDDA.getRedundancy(SimplifyDDA.java:626) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.SimplifyDDAWithTimeout.getRedundancy(SimplifyDDAWithTimeout.java:122) at de.uni_freiburg.informatik.ultimate.logic.simplification.SimplifyDDA$Simplifier.walk(SimplifyDDA.java:371) at de.uni_freiburg.informatik.ultimate.logic.NonRecursive.run(NonRecursive.java:122) at de.uni_freiburg.informatik.ultimate.logic.NonRecursive.run(NonRecursive.java:113) at de.uni_freiburg.informatik.ultimate.logic.simplification.SimplifyDDA.simplifyOnce(SimplifyDDA.java:650) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.SimplifyDDAWithTimeout.getSimplifiedTerm(SimplifyDDAWithTimeout.java:187) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.SmtUtils.simplify(SmtUtils.java:151) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate(PredicateUnifier.java:354) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate(PredicateUnifier.java:299) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.TraceCheckSpWp$UnifyPostprocessor.postprocess(TraceCheckSpWp.java:575) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.predicates.IterativePredicateTransformer.applyPostprocessors(IterativePredicateTransformer.java:439) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.predicates.IterativePredicateTransformer.computeStrongestPostconditionSequence(IterativePredicateTransformer.java:200) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.TraceCheckSpWp.computeInterpolantsUsingUnsatCore(TraceCheckSpWp.java:286) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.TraceCheckSpWp.computeInterpolants(TraceCheckSpWp.java:175) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.TraceCheckSpWp.(TraceCheckSpWp.java:162) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.TraceCheckConstructor.constructForwardBackward(TraceCheckConstructor.java:224) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.TraceCheckConstructor.constructTraceCheck(TraceCheckConstructor.java:188) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.TraceCheckConstructor.get(TraceCheckConstructor.java:165) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.MultiTrackRefinementStrategy.getTraceCheck(MultiTrackRefinementStrategy.java:232) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.BaseRefinementStrategy.checkFeasibility(BaseRefinementStrategy.java:223) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.BaseRefinementStrategy.executeStrategy(BaseRefinementStrategy.java:197) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.TraceAbstractionRefinementEngine.(TraceAbstractionRefinementEngine.java:70) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.BasicCegarLoop.isCounterexampleFeasible(BasicCegarLoop.java:456) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.AbstractCegarLoop.iterateInternal(AbstractCegarLoop.java:434) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.AbstractCegarLoop.iterate(AbstractCegarLoop.java:376) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.iterate(TraceAbstractionStarter.java:334) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.runCegarLoops(TraceAbstractionStarter.java:174) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.(TraceAbstractionStarter.java:126) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver.finish(TraceAbstractionObserver.java:123) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runObserver(PluginConnector.java:168) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runTool(PluginConnector.java:151) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.run(PluginConnector.java:128) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.executePluginConnector(ToolchainWalker.java:232) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.processPlugin(ToolchainWalker.java:226) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walkUnprotected(ToolchainWalker.java:142) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walk(ToolchainWalker.java:104) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainManager$Toolchain.processToolchain(ToolchainManager.java:316) at de.uni_freiburg.informatik.ultimate.core.coreplugin.toolchain.DefaultToolchainJob.run(DefaultToolchainJob.java:145) at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) Caused by: de.uni_freiburg.informatik.ultimate.logic.SMTLIBException: EOF at de.uni_freiburg.informatik.ultimate.smtsolver.external.Parser$Action$.CUP$do_action(Parser.java:1427) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Parser.do_action(Parser.java:630) at com.github.jhoenicke.javacup.runtime.LRParser.parse(LRParser.java:419) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Executor.parse(Executor.java:205) ... 45 more [2018-11-23 16:18:43,128 INFO L168 Benchmark]: Toolchain (without parser) took 133839.98 ms. Allocated memory was 1.0 GB in the beginning and 1.8 GB in the end (delta: 769.7 MB). Free memory was 956.4 MB in the beginning and 1.6 GB in the end (delta: -659.5 MB). Peak memory consumption was 110.2 MB. Max. memory is 11.5 GB. [2018-11-23 16:18:43,128 INFO L168 Benchmark]: CDTParser took 0.18 ms. Allocated memory is still 1.0 GB. Free memory is still 985.4 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-23 16:18:43,128 INFO L168 Benchmark]: CACSL2BoogieTranslator took 835.89 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 134.2 MB). Free memory was 956.4 MB in the beginning and 1.1 GB in the end (delta: -101.1 MB). Peak memory consumption was 50.4 MB. Max. memory is 11.5 GB. [2018-11-23 16:18:43,129 INFO L168 Benchmark]: Boogie Procedure Inliner took 46.90 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. [2018-11-23 16:18:43,129 INFO L168 Benchmark]: Boogie Preprocessor took 71.02 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 8.1 MB). Peak memory consumption was 8.1 MB. Max. memory is 11.5 GB. [2018-11-23 16:18:43,129 INFO L168 Benchmark]: RCFGBuilder took 1143.66 ms. Allocated memory is still 1.2 GB. Free memory was 1.0 GB in the beginning and 954.5 MB in the end (delta: 92.4 MB). Peak memory consumption was 92.4 MB. Max. memory is 11.5 GB. [2018-11-23 16:18:43,129 INFO L168 Benchmark]: TraceAbstraction took 131738.61 ms. Allocated memory was 1.2 GB in the beginning and 1.8 GB in the end (delta: 635.4 MB). Free memory was 954.5 MB in the beginning and 1.6 GB in the end (delta: -661.4 MB). There was no memory consumed. Max. memory is 11.5 GB. [2018-11-23 16:18:43,131 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.18 ms. Allocated memory is still 1.0 GB. Free memory is still 985.4 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 835.89 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 134.2 MB). Free memory was 956.4 MB in the beginning and 1.1 GB in the end (delta: -101.1 MB). Peak memory consumption was 50.4 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 46.90 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 71.02 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 8.1 MB). Peak memory consumption was 8.1 MB. Max. memory is 11.5 GB. * RCFGBuilder took 1143.66 ms. Allocated memory is still 1.2 GB. Free memory was 1.0 GB in the beginning and 954.5 MB in the end (delta: 92.4 MB). Peak memory consumption was 92.4 MB. Max. memory is 11.5 GB. * TraceAbstraction took 131738.61 ms. Allocated memory was 1.2 GB in the beginning and 1.8 GB in the end (delta: 635.4 MB). Free memory was 954.5 MB in the beginning and 1.6 GB in the end (delta: -661.4 MB). There was no memory consumed. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - ExceptionOrErrorResult: SMTLIBException: External (z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000)Received EOF on stdin. stderr output: (error "out of memory") de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: SMTLIBException: External (z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000)Received EOF on stdin. stderr output: (error "out of memory") : de.uni_freiburg.informatik.ultimate.smtsolver.external.Executor.parse(Executor.java:208) RESULT: Ultimate could not prove your program: Toolchain returned no result. Received shutdown request...