./Ultimate.py --spec ../../sv-benchmarks/c/properties/no-overflow.prp --file ../../sv-benchmarks/c/busybox-1.22.0/dirname_true-no-overflow_true-valid-memsafety.i --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for overflows Using default analysis Version aa418289 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_bb12028c-b1da-4712-8a45-3e9c572ad540/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_bb12028c-b1da-4712-8a45-3e9c572ad540/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_bb12028c-b1da-4712-8a45-3e9c572ad540/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_bb12028c-b1da-4712-8a45-3e9c572ad540/bin-2019/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/busybox-1.22.0/dirname_true-no-overflow_true-valid-memsafety.i -s /tmp/vcloud-vcloud-master/worker/working_dir_bb12028c-b1da-4712-8a45-3e9c572ad540/bin-2019/uautomizer/config/svcomp-Overflow-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_bb12028c-b1da-4712-8a45-3e9c572ad540/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! overflow) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash eb1520ccd16a6dcbfeb7912e1d04b4742bbea576 ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Using bit-precise analysis No suitable file found in config dir /tmp/vcloud-vcloud-master/worker/working_dir_bb12028c-b1da-4712-8a45-3e9c572ad540/bin-2019/uautomizer/config using search string *Overflow*64bit*_Bitvector*.epf No suitable settings file found using Overflow*64bit*_Bitvector ERROR: UNSUPPORTED PROPERTY Writing output log to file Ultimate.log Result: ERROR: ExceptionOrErrorResult: SMTLIBException: External (z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000)Received EOF on stdin. stderr output: (error "out of memory") --- Real Ultimate output --- This is Ultimate 0.1.23-aa41828 [2018-11-23 14:42:17,136 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-23 14:42:17,137 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-23 14:42:17,145 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-23 14:42:17,145 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-23 14:42:17,146 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-23 14:42:17,146 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-23 14:42:17,148 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-23 14:42:17,149 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-23 14:42:17,149 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-23 14:42:17,150 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-23 14:42:17,150 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-23 14:42:17,151 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-23 14:42:17,151 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-23 14:42:17,152 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-23 14:42:17,153 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-23 14:42:17,153 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-23 14:42:17,154 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-23 14:42:17,156 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-23 14:42:17,157 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-23 14:42:17,158 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-23 14:42:17,158 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-23 14:42:17,160 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-23 14:42:17,160 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-23 14:42:17,160 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-23 14:42:17,161 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-23 14:42:17,162 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-23 14:42:17,162 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-23 14:42:17,163 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-23 14:42:17,163 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-23 14:42:17,164 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-23 14:42:17,164 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-23 14:42:17,164 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-23 14:42:17,164 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-23 14:42:17,165 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-23 14:42:17,166 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-23 14:42:17,166 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_bb12028c-b1da-4712-8a45-3e9c572ad540/bin-2019/uautomizer/config/svcomp-Overflow-64bit-Automizer_Default.epf [2018-11-23 14:42:17,176 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-23 14:42:17,176 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-23 14:42:17,177 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-23 14:42:17,177 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-11-23 14:42:17,177 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-23 14:42:17,178 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-23 14:42:17,178 INFO L133 SettingsManager]: * Use SBE=true [2018-11-23 14:42:17,178 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-23 14:42:17,178 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-11-23 14:42:17,178 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-23 14:42:17,178 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-23 14:42:17,178 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-23 14:42:17,179 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-23 14:42:17,179 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-23 14:42:17,179 INFO L133 SettingsManager]: * Check absence of signed integer overflows=true [2018-11-23 14:42:17,179 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-23 14:42:17,179 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-23 14:42:17,179 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-23 14:42:17,179 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-23 14:42:17,180 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-23 14:42:17,180 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-23 14:42:17,180 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-23 14:42:17,180 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 14:42:17,180 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-23 14:42:17,180 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-23 14:42:17,181 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-23 14:42:17,181 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-23 14:42:17,181 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-23 14:42:17,181 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-11-23 14:42:17,181 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_bb12028c-b1da-4712-8a45-3e9c572ad540/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! overflow) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> eb1520ccd16a6dcbfeb7912e1d04b4742bbea576 [2018-11-23 14:42:17,204 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-23 14:42:17,211 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-23 14:42:17,213 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-23 14:42:17,214 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-23 14:42:17,214 INFO L276 PluginConnector]: CDTParser initialized [2018-11-23 14:42:17,215 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_bb12028c-b1da-4712-8a45-3e9c572ad540/bin-2019/uautomizer/../../sv-benchmarks/c/busybox-1.22.0/dirname_true-no-overflow_true-valid-memsafety.i [2018-11-23 14:42:17,247 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_bb12028c-b1da-4712-8a45-3e9c572ad540/bin-2019/uautomizer/data/262c83ba8/483127ed468e4f32b8f54cdb29c1c0f0/FLAGbd3a33a6b [2018-11-23 14:42:17,616 INFO L307 CDTParser]: Found 1 translation units. [2018-11-23 14:42:17,617 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_bb12028c-b1da-4712-8a45-3e9c572ad540/sv-benchmarks/c/busybox-1.22.0/dirname_true-no-overflow_true-valid-memsafety.i [2018-11-23 14:42:17,630 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_bb12028c-b1da-4712-8a45-3e9c572ad540/bin-2019/uautomizer/data/262c83ba8/483127ed468e4f32b8f54cdb29c1c0f0/FLAGbd3a33a6b [2018-11-23 14:42:17,641 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_bb12028c-b1da-4712-8a45-3e9c572ad540/bin-2019/uautomizer/data/262c83ba8/483127ed468e4f32b8f54cdb29c1c0f0 [2018-11-23 14:42:17,644 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-23 14:42:17,645 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-23 14:42:17,646 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-23 14:42:17,646 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-23 14:42:17,649 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-23 14:42:17,649 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 02:42:17" (1/1) ... [2018-11-23 14:42:17,651 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@74858241 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:42:17, skipping insertion in model container [2018-11-23 14:42:17,652 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 02:42:17" (1/1) ... [2018-11-23 14:42:17,658 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-23 14:42:17,695 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-23 14:42:18,120 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 14:42:18,138 INFO L191 MainTranslator]: Completed pre-run [2018-11-23 14:42:18,194 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 14:42:18,339 INFO L195 MainTranslator]: Completed translation [2018-11-23 14:42:18,340 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:42:18 WrapperNode [2018-11-23 14:42:18,340 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-23 14:42:18,340 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-23 14:42:18,340 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-23 14:42:18,341 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-23 14:42:18,347 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:42:18" (1/1) ... [2018-11-23 14:42:18,370 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:42:18" (1/1) ... [2018-11-23 14:42:18,380 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-23 14:42:18,380 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-23 14:42:18,381 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-23 14:42:18,381 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-23 14:42:18,389 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:42:18" (1/1) ... [2018-11-23 14:42:18,389 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:42:18" (1/1) ... [2018-11-23 14:42:18,395 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:42:18" (1/1) ... [2018-11-23 14:42:18,395 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:42:18" (1/1) ... [2018-11-23 14:42:18,421 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:42:18" (1/1) ... [2018-11-23 14:42:18,427 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:42:18" (1/1) ... [2018-11-23 14:42:18,430 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:42:18" (1/1) ... [2018-11-23 14:42:18,433 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-23 14:42:18,434 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-23 14:42:18,434 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-23 14:42:18,434 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-23 14:42:18,435 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:42:18" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_bb12028c-b1da-4712-8a45-3e9c572ad540/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 14:42:18,480 INFO L130 BoogieDeclarations]: Found specification of procedure __main [2018-11-23 14:42:18,480 INFO L138 BoogieDeclarations]: Found implementation of procedure __main [2018-11-23 14:42:18,480 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-23 14:42:18,481 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-23 14:42:18,481 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2018-11-23 14:42:18,481 INFO L130 BoogieDeclarations]: Found specification of procedure fflush_all [2018-11-23 14:42:18,481 INFO L138 BoogieDeclarations]: Found implementation of procedure fflush_all [2018-11-23 14:42:18,482 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-11-23 14:42:18,482 INFO L130 BoogieDeclarations]: Found specification of procedure single_argv [2018-11-23 14:42:18,482 INFO L138 BoogieDeclarations]: Found implementation of procedure single_argv [2018-11-23 14:42:18,482 INFO L130 BoogieDeclarations]: Found specification of procedure bb_show_usage [2018-11-23 14:42:18,482 INFO L138 BoogieDeclarations]: Found implementation of procedure bb_show_usage [2018-11-23 14:42:18,482 INFO L130 BoogieDeclarations]: Found specification of procedure dirname [2018-11-23 14:42:18,482 INFO L138 BoogieDeclarations]: Found implementation of procedure dirname [2018-11-23 14:42:18,482 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-11-23 14:42:18,483 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2018-11-23 14:42:18,483 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2018-11-23 14:42:18,483 INFO L130 BoogieDeclarations]: Found specification of procedure puts [2018-11-23 14:42:18,483 INFO L130 BoogieDeclarations]: Found specification of procedure fflush [2018-11-23 14:42:18,483 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-23 14:42:18,483 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-23 14:42:18,483 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2018-11-23 14:42:18,483 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2018-11-23 14:42:18,483 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-23 14:42:18,483 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-23 14:42:19,127 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-23 14:42:19,127 INFO L280 CfgBuilder]: Removed 6 assue(true) statements. [2018-11-23 14:42:19,128 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 02:42:19 BoogieIcfgContainer [2018-11-23 14:42:19,128 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-23 14:42:19,129 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-23 14:42:19,129 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-23 14:42:19,131 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-23 14:42:19,131 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 23.11 02:42:17" (1/3) ... [2018-11-23 14:42:19,131 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1394bbe8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 02:42:19, skipping insertion in model container [2018-11-23 14:42:19,131 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 02:42:18" (2/3) ... [2018-11-23 14:42:19,132 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1394bbe8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 02:42:19, skipping insertion in model container [2018-11-23 14:42:19,132 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 02:42:19" (3/3) ... [2018-11-23 14:42:19,133 INFO L112 eAbstractionObserver]: Analyzing ICFG dirname_true-no-overflow_true-valid-memsafety.i [2018-11-23 14:42:19,140 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-23 14:42:19,146 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 28 error locations. [2018-11-23 14:42:19,156 INFO L257 AbstractCegarLoop]: Starting to check reachability of 28 error locations. [2018-11-23 14:42:19,178 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-23 14:42:19,178 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-23 14:42:19,178 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-23 14:42:19,179 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-23 14:42:19,179 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-23 14:42:19,179 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-23 14:42:19,179 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-23 14:42:19,179 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-23 14:42:19,179 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-23 14:42:19,194 INFO L276 IsEmpty]: Start isEmpty. Operand 118 states. [2018-11-23 14:42:19,199 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 9 [2018-11-23 14:42:19,199 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:42:19,200 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:42:19,201 INFO L423 AbstractCegarLoop]: === Iteration 1 === [single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 14:42:19,205 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:42:19,205 INFO L82 PathProgramCache]: Analyzing trace with hash -484679774, now seen corresponding path program 1 times [2018-11-23 14:42:19,206 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:42:19,207 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:42:19,243 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:42:19,243 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:42:19,243 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:42:19,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:42:19,427 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:42:19,429 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:42:19,429 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 14:42:19,431 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 14:42:19,439 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 14:42:19,440 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:42:19,442 INFO L87 Difference]: Start difference. First operand 118 states. Second operand 3 states. [2018-11-23 14:42:19,492 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:42:19,493 INFO L93 Difference]: Finished difference Result 226 states and 277 transitions. [2018-11-23 14:42:19,493 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 14:42:19,494 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 8 [2018-11-23 14:42:19,495 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:42:19,501 INFO L225 Difference]: With dead ends: 226 [2018-11-23 14:42:19,502 INFO L226 Difference]: Without dead ends: 113 [2018-11-23 14:42:19,504 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:42:19,515 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 113 states. [2018-11-23 14:42:19,532 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 113 to 113. [2018-11-23 14:42:19,533 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 113 states. [2018-11-23 14:42:19,535 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 113 states to 113 states and 131 transitions. [2018-11-23 14:42:19,536 INFO L78 Accepts]: Start accepts. Automaton has 113 states and 131 transitions. Word has length 8 [2018-11-23 14:42:19,536 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:42:19,536 INFO L480 AbstractCegarLoop]: Abstraction has 113 states and 131 transitions. [2018-11-23 14:42:19,536 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 14:42:19,537 INFO L276 IsEmpty]: Start isEmpty. Operand 113 states and 131 transitions. [2018-11-23 14:42:19,537 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 10 [2018-11-23 14:42:19,537 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:42:19,537 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:42:19,538 INFO L423 AbstractCegarLoop]: === Iteration 2 === [single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 14:42:19,538 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:42:19,538 INFO L82 PathProgramCache]: Analyzing trace with hash -2140170941, now seen corresponding path program 1 times [2018-11-23 14:42:19,538 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:42:19,539 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:42:19,540 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:42:19,541 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:42:19,541 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:42:19,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:42:19,598 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:42:19,598 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:42:19,599 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 14:42:19,600 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 14:42:19,600 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 14:42:19,600 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:42:19,601 INFO L87 Difference]: Start difference. First operand 113 states and 131 transitions. Second operand 3 states. [2018-11-23 14:42:19,627 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:42:19,627 INFO L93 Difference]: Finished difference Result 116 states and 134 transitions. [2018-11-23 14:42:19,628 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 14:42:19,628 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 9 [2018-11-23 14:42:19,629 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:42:19,630 INFO L225 Difference]: With dead ends: 116 [2018-11-23 14:42:19,630 INFO L226 Difference]: Without dead ends: 115 [2018-11-23 14:42:19,631 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:42:19,631 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 115 states. [2018-11-23 14:42:19,638 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 115 to 115. [2018-11-23 14:42:19,639 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 115 states. [2018-11-23 14:42:19,640 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 133 transitions. [2018-11-23 14:42:19,640 INFO L78 Accepts]: Start accepts. Automaton has 115 states and 133 transitions. Word has length 9 [2018-11-23 14:42:19,641 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:42:19,641 INFO L480 AbstractCegarLoop]: Abstraction has 115 states and 133 transitions. [2018-11-23 14:42:19,641 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 14:42:19,641 INFO L276 IsEmpty]: Start isEmpty. Operand 115 states and 133 transitions. [2018-11-23 14:42:19,641 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2018-11-23 14:42:19,642 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:42:19,642 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:42:19,642 INFO L423 AbstractCegarLoop]: === Iteration 3 === [single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 14:42:19,643 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:42:19,643 INFO L82 PathProgramCache]: Analyzing trace with hash 957163037, now seen corresponding path program 1 times [2018-11-23 14:42:19,643 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:42:19,643 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:42:19,645 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:42:19,645 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:42:19,645 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:42:19,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:42:19,710 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-11-23 14:42:19,710 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:42:19,711 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 14:42:19,711 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 14:42:19,712 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 14:42:19,712 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:42:19,712 INFO L87 Difference]: Start difference. First operand 115 states and 133 transitions. Second operand 3 states. [2018-11-23 14:42:19,753 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:42:19,753 INFO L93 Difference]: Finished difference Result 115 states and 133 transitions. [2018-11-23 14:42:19,753 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 14:42:19,754 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 12 [2018-11-23 14:42:19,754 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:42:19,755 INFO L225 Difference]: With dead ends: 115 [2018-11-23 14:42:19,755 INFO L226 Difference]: Without dead ends: 111 [2018-11-23 14:42:19,755 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:42:19,755 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 111 states. [2018-11-23 14:42:19,761 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 111 to 111. [2018-11-23 14:42:19,761 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 111 states. [2018-11-23 14:42:19,762 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 111 states to 111 states and 129 transitions. [2018-11-23 14:42:19,762 INFO L78 Accepts]: Start accepts. Automaton has 111 states and 129 transitions. Word has length 12 [2018-11-23 14:42:19,762 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:42:19,762 INFO L480 AbstractCegarLoop]: Abstraction has 111 states and 129 transitions. [2018-11-23 14:42:19,763 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 14:42:19,763 INFO L276 IsEmpty]: Start isEmpty. Operand 111 states and 129 transitions. [2018-11-23 14:42:19,763 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2018-11-23 14:42:19,763 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:42:19,763 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:42:19,764 INFO L423 AbstractCegarLoop]: === Iteration 4 === [single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 14:42:19,764 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:42:19,764 INFO L82 PathProgramCache]: Analyzing trace with hash 957164767, now seen corresponding path program 1 times [2018-11-23 14:42:19,764 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:42:19,765 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:42:19,766 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:42:19,766 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:42:19,767 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:42:19,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:42:19,822 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:42:19,822 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:42:19,823 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 14:42:19,823 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 14:42:19,823 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 14:42:19,823 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:42:19,823 INFO L87 Difference]: Start difference. First operand 111 states and 129 transitions. Second operand 3 states. [2018-11-23 14:42:19,846 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:42:19,846 INFO L93 Difference]: Finished difference Result 111 states and 129 transitions. [2018-11-23 14:42:19,847 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 14:42:19,847 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 12 [2018-11-23 14:42:19,847 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:42:19,848 INFO L225 Difference]: With dead ends: 111 [2018-11-23 14:42:19,848 INFO L226 Difference]: Without dead ends: 110 [2018-11-23 14:42:19,848 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:42:19,849 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 110 states. [2018-11-23 14:42:19,854 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 110 to 108. [2018-11-23 14:42:19,854 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 108 states. [2018-11-23 14:42:19,870 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108 states to 108 states and 126 transitions. [2018-11-23 14:42:19,871 INFO L78 Accepts]: Start accepts. Automaton has 108 states and 126 transitions. Word has length 12 [2018-11-23 14:42:19,871 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:42:19,871 INFO L480 AbstractCegarLoop]: Abstraction has 108 states and 126 transitions. [2018-11-23 14:42:19,871 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 14:42:19,871 INFO L276 IsEmpty]: Start isEmpty. Operand 108 states and 126 transitions. [2018-11-23 14:42:19,871 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2018-11-23 14:42:19,871 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:42:19,872 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:42:19,872 INFO L423 AbstractCegarLoop]: === Iteration 5 === [single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 14:42:19,873 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:42:19,873 INFO L82 PathProgramCache]: Analyzing trace with hash -392716752, now seen corresponding path program 1 times [2018-11-23 14:42:19,873 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:42:19,873 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:42:19,875 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:42:19,875 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:42:19,875 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:42:19,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:42:19,950 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-11-23 14:42:19,950 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:42:19,950 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 14:42:19,950 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 14:42:19,950 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 14:42:19,951 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:42:19,951 INFO L87 Difference]: Start difference. First operand 108 states and 126 transitions. Second operand 3 states. [2018-11-23 14:42:19,979 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:42:19,979 INFO L93 Difference]: Finished difference Result 108 states and 126 transitions. [2018-11-23 14:42:19,980 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 14:42:19,980 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 13 [2018-11-23 14:42:19,980 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:42:19,981 INFO L225 Difference]: With dead ends: 108 [2018-11-23 14:42:19,981 INFO L226 Difference]: Without dead ends: 106 [2018-11-23 14:42:19,981 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:42:19,981 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 106 states. [2018-11-23 14:42:19,987 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 106 to 106. [2018-11-23 14:42:19,987 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 106 states. [2018-11-23 14:42:19,987 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 106 states to 106 states and 124 transitions. [2018-11-23 14:42:19,988 INFO L78 Accepts]: Start accepts. Automaton has 106 states and 124 transitions. Word has length 13 [2018-11-23 14:42:19,988 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:42:19,988 INFO L480 AbstractCegarLoop]: Abstraction has 106 states and 124 transitions. [2018-11-23 14:42:19,988 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 14:42:19,988 INFO L276 IsEmpty]: Start isEmpty. Operand 106 states and 124 transitions. [2018-11-23 14:42:19,988 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2018-11-23 14:42:19,989 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:42:19,989 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:42:19,989 INFO L423 AbstractCegarLoop]: === Iteration 6 === [single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 14:42:19,989 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:42:19,990 INFO L82 PathProgramCache]: Analyzing trace with hash 556328978, now seen corresponding path program 1 times [2018-11-23 14:42:19,990 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:42:19,990 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:42:19,991 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:42:19,991 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:42:19,991 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:42:20,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:42:20,045 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-11-23 14:42:20,046 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:42:20,046 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 14:42:20,046 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 14:42:20,046 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 14:42:20,046 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:42:20,046 INFO L87 Difference]: Start difference. First operand 106 states and 124 transitions. Second operand 3 states. [2018-11-23 14:42:20,077 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:42:20,077 INFO L93 Difference]: Finished difference Result 106 states and 124 transitions. [2018-11-23 14:42:20,078 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 14:42:20,078 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 15 [2018-11-23 14:42:20,078 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:42:20,079 INFO L225 Difference]: With dead ends: 106 [2018-11-23 14:42:20,079 INFO L226 Difference]: Without dead ends: 104 [2018-11-23 14:42:20,079 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:42:20,079 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 104 states. [2018-11-23 14:42:20,084 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 104 to 104. [2018-11-23 14:42:20,084 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 104 states. [2018-11-23 14:42:20,085 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 104 states to 104 states and 122 transitions. [2018-11-23 14:42:20,085 INFO L78 Accepts]: Start accepts. Automaton has 104 states and 122 transitions. Word has length 15 [2018-11-23 14:42:20,085 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:42:20,085 INFO L480 AbstractCegarLoop]: Abstraction has 104 states and 122 transitions. [2018-11-23 14:42:20,085 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 14:42:20,086 INFO L276 IsEmpty]: Start isEmpty. Operand 104 states and 122 transitions. [2018-11-23 14:42:20,086 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2018-11-23 14:42:20,086 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:42:20,086 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:42:20,087 INFO L423 AbstractCegarLoop]: === Iteration 7 === [single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 14:42:20,087 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:42:20,087 INFO L82 PathProgramCache]: Analyzing trace with hash 1553574359, now seen corresponding path program 1 times [2018-11-23 14:42:20,087 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:42:20,087 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:42:20,088 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:42:20,088 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:42:20,088 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:42:20,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:42:20,130 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-11-23 14:42:20,130 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:42:20,130 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 14:42:20,130 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 14:42:20,130 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 14:42:20,130 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:42:20,131 INFO L87 Difference]: Start difference. First operand 104 states and 122 transitions. Second operand 3 states. [2018-11-23 14:42:20,158 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:42:20,158 INFO L93 Difference]: Finished difference Result 192 states and 230 transitions. [2018-11-23 14:42:20,159 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 14:42:20,159 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 22 [2018-11-23 14:42:20,159 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:42:20,160 INFO L225 Difference]: With dead ends: 192 [2018-11-23 14:42:20,160 INFO L226 Difference]: Without dead ends: 107 [2018-11-23 14:42:20,160 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:42:20,160 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 107 states. [2018-11-23 14:42:20,167 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 107 to 107. [2018-11-23 14:42:20,167 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 107 states. [2018-11-23 14:42:20,167 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 107 states to 107 states and 125 transitions. [2018-11-23 14:42:20,168 INFO L78 Accepts]: Start accepts. Automaton has 107 states and 125 transitions. Word has length 22 [2018-11-23 14:42:20,168 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:42:20,168 INFO L480 AbstractCegarLoop]: Abstraction has 107 states and 125 transitions. [2018-11-23 14:42:20,168 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 14:42:20,168 INFO L276 IsEmpty]: Start isEmpty. Operand 107 states and 125 transitions. [2018-11-23 14:42:20,168 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-11-23 14:42:20,169 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:42:20,169 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:42:20,169 INFO L423 AbstractCegarLoop]: === Iteration 8 === [single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 14:42:20,169 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:42:20,169 INFO L82 PathProgramCache]: Analyzing trace with hash -32009876, now seen corresponding path program 1 times [2018-11-23 14:42:20,169 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:42:20,170 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:42:20,171 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:42:20,171 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:42:20,171 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:42:20,188 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:42:20,232 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-11-23 14:42:20,232 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:42:20,232 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 14:42:20,232 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 14:42:20,232 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 14:42:20,233 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 14:42:20,233 INFO L87 Difference]: Start difference. First operand 107 states and 125 transitions. Second operand 4 states. [2018-11-23 14:42:20,270 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:42:20,270 INFO L93 Difference]: Finished difference Result 115 states and 135 transitions. [2018-11-23 14:42:20,271 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 14:42:20,271 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 25 [2018-11-23 14:42:20,271 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:42:20,272 INFO L225 Difference]: With dead ends: 115 [2018-11-23 14:42:20,272 INFO L226 Difference]: Without dead ends: 114 [2018-11-23 14:42:20,273 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-23 14:42:20,273 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 114 states. [2018-11-23 14:42:20,280 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 114 to 106. [2018-11-23 14:42:20,281 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 106 states. [2018-11-23 14:42:20,281 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 106 states to 106 states and 124 transitions. [2018-11-23 14:42:20,281 INFO L78 Accepts]: Start accepts. Automaton has 106 states and 124 transitions. Word has length 25 [2018-11-23 14:42:20,282 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:42:20,282 INFO L480 AbstractCegarLoop]: Abstraction has 106 states and 124 transitions. [2018-11-23 14:42:20,282 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 14:42:20,282 INFO L276 IsEmpty]: Start isEmpty. Operand 106 states and 124 transitions. [2018-11-23 14:42:20,282 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-11-23 14:42:20,282 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:42:20,283 INFO L402 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:42:20,283 INFO L423 AbstractCegarLoop]: === Iteration 9 === [single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 14:42:20,283 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:42:20,283 INFO L82 PathProgramCache]: Analyzing trace with hash -32009821, now seen corresponding path program 1 times [2018-11-23 14:42:20,283 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:42:20,284 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:42:20,284 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:42:20,285 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:42:20,285 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:42:20,299 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:42:20,338 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 1 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-11-23 14:42:20,338 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:42:20,338 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 14:42:20,339 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 14:42:20,339 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 14:42:20,339 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:42:20,339 INFO L87 Difference]: Start difference. First operand 106 states and 124 transitions. Second operand 3 states. [2018-11-23 14:42:20,349 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:42:20,349 INFO L93 Difference]: Finished difference Result 106 states and 124 transitions. [2018-11-23 14:42:20,349 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 14:42:20,349 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 25 [2018-11-23 14:42:20,350 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:42:20,350 INFO L225 Difference]: With dead ends: 106 [2018-11-23 14:42:20,350 INFO L226 Difference]: Without dead ends: 105 [2018-11-23 14:42:20,351 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:42:20,351 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 105 states. [2018-11-23 14:42:20,354 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 105 to 105. [2018-11-23 14:42:20,354 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 105 states. [2018-11-23 14:42:20,355 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 105 states to 105 states and 123 transitions. [2018-11-23 14:42:20,355 INFO L78 Accepts]: Start accepts. Automaton has 105 states and 123 transitions. Word has length 25 [2018-11-23 14:42:20,355 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:42:20,355 INFO L480 AbstractCegarLoop]: Abstraction has 105 states and 123 transitions. [2018-11-23 14:42:20,355 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 14:42:20,356 INFO L276 IsEmpty]: Start isEmpty. Operand 105 states and 123 transitions. [2018-11-23 14:42:20,356 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-11-23 14:42:20,356 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:42:20,356 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:42:20,357 INFO L423 AbstractCegarLoop]: === Iteration 10 === [single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 14:42:20,357 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:42:20,357 INFO L82 PathProgramCache]: Analyzing trace with hash -992305943, now seen corresponding path program 1 times [2018-11-23 14:42:20,357 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:42:20,357 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:42:20,358 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:42:20,358 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:42:20,358 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:42:20,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:42:20,406 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-11-23 14:42:20,406 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:42:20,406 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 14:42:20,406 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 14:42:20,407 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 14:42:20,407 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:42:20,407 INFO L87 Difference]: Start difference. First operand 105 states and 123 transitions. Second operand 3 states. [2018-11-23 14:42:20,428 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:42:20,428 INFO L93 Difference]: Finished difference Result 123 states and 144 transitions. [2018-11-23 14:42:20,428 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 14:42:20,428 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 26 [2018-11-23 14:42:20,429 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:42:20,429 INFO L225 Difference]: With dead ends: 123 [2018-11-23 14:42:20,429 INFO L226 Difference]: Without dead ends: 122 [2018-11-23 14:42:20,430 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:42:20,430 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 122 states. [2018-11-23 14:42:20,434 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 122 to 114. [2018-11-23 14:42:20,434 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 114 states. [2018-11-23 14:42:20,434 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 135 transitions. [2018-11-23 14:42:20,435 INFO L78 Accepts]: Start accepts. Automaton has 114 states and 135 transitions. Word has length 26 [2018-11-23 14:42:20,435 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:42:20,435 INFO L480 AbstractCegarLoop]: Abstraction has 114 states and 135 transitions. [2018-11-23 14:42:20,435 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 14:42:20,435 INFO L276 IsEmpty]: Start isEmpty. Operand 114 states and 135 transitions. [2018-11-23 14:42:20,435 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-11-23 14:42:20,435 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:42:20,436 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:42:20,436 INFO L423 AbstractCegarLoop]: === Iteration 11 === [single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 14:42:20,436 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:42:20,436 INFO L82 PathProgramCache]: Analyzing trace with hash -992304245, now seen corresponding path program 1 times [2018-11-23 14:42:20,436 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:42:20,437 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:42:20,437 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:42:20,438 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:42:20,438 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:42:20,452 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:42:20,474 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-11-23 14:42:20,474 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:42:20,474 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 14:42:20,474 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 14:42:20,474 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 14:42:20,474 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:42:20,475 INFO L87 Difference]: Start difference. First operand 114 states and 135 transitions. Second operand 3 states. [2018-11-23 14:42:20,492 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:42:20,492 INFO L93 Difference]: Finished difference Result 121 states and 143 transitions. [2018-11-23 14:42:20,493 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 14:42:20,493 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 26 [2018-11-23 14:42:20,493 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:42:20,493 INFO L225 Difference]: With dead ends: 121 [2018-11-23 14:42:20,494 INFO L226 Difference]: Without dead ends: 120 [2018-11-23 14:42:20,494 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:42:20,494 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 120 states. [2018-11-23 14:42:20,498 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 120 to 109. [2018-11-23 14:42:20,498 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 109 states. [2018-11-23 14:42:20,498 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 109 states to 109 states and 129 transitions. [2018-11-23 14:42:20,498 INFO L78 Accepts]: Start accepts. Automaton has 109 states and 129 transitions. Word has length 26 [2018-11-23 14:42:20,498 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:42:20,499 INFO L480 AbstractCegarLoop]: Abstraction has 109 states and 129 transitions. [2018-11-23 14:42:20,499 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 14:42:20,499 INFO L276 IsEmpty]: Start isEmpty. Operand 109 states and 129 transitions. [2018-11-23 14:42:20,499 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-11-23 14:42:20,499 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:42:20,499 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:42:20,500 INFO L423 AbstractCegarLoop]: === Iteration 12 === [single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 14:42:20,500 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:42:20,500 INFO L82 PathProgramCache]: Analyzing trace with hash 1525307751, now seen corresponding path program 1 times [2018-11-23 14:42:20,500 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:42:20,500 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:42:20,501 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:42:20,501 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:42:20,502 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:42:20,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:42:20,559 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:42:20,559 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 14:42:20,559 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_bb12028c-b1da-4712-8a45-3e9c572ad540/bin-2019/uautomizer/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 14:42:20,579 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:42:20,685 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:42:20,692 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 14:42:20,709 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:42:20,725 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 14:42:20,725 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 5 [2018-11-23 14:42:20,726 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 14:42:20,726 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 14:42:20,726 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2018-11-23 14:42:20,726 INFO L87 Difference]: Start difference. First operand 109 states and 129 transitions. Second operand 5 states. [2018-11-23 14:42:20,743 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:42:20,743 INFO L93 Difference]: Finished difference Result 213 states and 253 transitions. [2018-11-23 14:42:20,743 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 14:42:20,743 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 29 [2018-11-23 14:42:20,743 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:42:20,744 INFO L225 Difference]: With dead ends: 213 [2018-11-23 14:42:20,744 INFO L226 Difference]: Without dead ends: 114 [2018-11-23 14:42:20,744 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 32 GetRequests, 29 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2018-11-23 14:42:20,745 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 114 states. [2018-11-23 14:42:20,748 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 114 to 112. [2018-11-23 14:42:20,749 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 112 states. [2018-11-23 14:42:20,749 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 112 states to 112 states and 132 transitions. [2018-11-23 14:42:20,749 INFO L78 Accepts]: Start accepts. Automaton has 112 states and 132 transitions. Word has length 29 [2018-11-23 14:42:20,750 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:42:20,750 INFO L480 AbstractCegarLoop]: Abstraction has 112 states and 132 transitions. [2018-11-23 14:42:20,750 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 14:42:20,750 INFO L276 IsEmpty]: Start isEmpty. Operand 112 states and 132 transitions. [2018-11-23 14:42:20,750 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-11-23 14:42:20,750 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:42:20,751 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:42:20,751 INFO L423 AbstractCegarLoop]: === Iteration 13 === [single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 14:42:20,751 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:42:20,751 INFO L82 PathProgramCache]: Analyzing trace with hash -1995699453, now seen corresponding path program 2 times [2018-11-23 14:42:20,751 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:42:20,752 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:42:20,753 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:42:20,753 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:42:20,753 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:42:20,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:42:20,814 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 14:42:20,814 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 14:42:20,814 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_bb12028c-b1da-4712-8a45-3e9c572ad540/bin-2019/uautomizer/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 14:42:20,822 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-23 14:42:20,938 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-11-23 14:42:20,938 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 14:42:20,942 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 14:42:20,967 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-11-23 14:42:20,983 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-23 14:42:20,983 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [5] total 7 [2018-11-23 14:42:20,983 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-23 14:42:20,984 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-23 14:42:20,984 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-23 14:42:20,984 INFO L87 Difference]: Start difference. First operand 112 states and 132 transitions. Second operand 7 states. [2018-11-23 14:42:21,058 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:42:21,059 INFO L93 Difference]: Finished difference Result 216 states and 256 transitions. [2018-11-23 14:42:21,059 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 14:42:21,059 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 32 [2018-11-23 14:42:21,059 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:42:21,060 INFO L225 Difference]: With dead ends: 216 [2018-11-23 14:42:21,060 INFO L226 Difference]: Without dead ends: 117 [2018-11-23 14:42:21,061 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 36 GetRequests, 31 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-23 14:42:21,061 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states. [2018-11-23 14:42:21,064 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 115. [2018-11-23 14:42:21,064 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 115 states. [2018-11-23 14:42:21,065 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 134 transitions. [2018-11-23 14:42:21,065 INFO L78 Accepts]: Start accepts. Automaton has 115 states and 134 transitions. Word has length 32 [2018-11-23 14:42:21,065 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:42:21,065 INFO L480 AbstractCegarLoop]: Abstraction has 115 states and 134 transitions. [2018-11-23 14:42:21,065 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-23 14:42:21,065 INFO L276 IsEmpty]: Start isEmpty. Operand 115 states and 134 transitions. [2018-11-23 14:42:21,066 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-11-23 14:42:21,066 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:42:21,066 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:42:21,067 INFO L423 AbstractCegarLoop]: === Iteration 14 === [single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 14:42:21,067 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:42:21,067 INFO L82 PathProgramCache]: Analyzing trace with hash -842011914, now seen corresponding path program 1 times [2018-11-23 14:42:21,067 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:42:21,067 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:42:21,068 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:42:21,068 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 14:42:21,069 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:42:21,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:42:21,114 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-11-23 14:42:21,114 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:42:21,114 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 14:42:21,115 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 14:42:21,115 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 14:42:21,115 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:42:21,115 INFO L87 Difference]: Start difference. First operand 115 states and 134 transitions. Second operand 3 states. [2018-11-23 14:42:21,130 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:42:21,130 INFO L93 Difference]: Finished difference Result 115 states and 134 transitions. [2018-11-23 14:42:21,131 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 14:42:21,131 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 39 [2018-11-23 14:42:21,131 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:42:21,132 INFO L225 Difference]: With dead ends: 115 [2018-11-23 14:42:21,132 INFO L226 Difference]: Without dead ends: 114 [2018-11-23 14:42:21,132 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:42:21,133 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 114 states. [2018-11-23 14:42:21,136 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 114 to 108. [2018-11-23 14:42:21,136 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 108 states. [2018-11-23 14:42:21,136 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108 states to 108 states and 126 transitions. [2018-11-23 14:42:21,136 INFO L78 Accepts]: Start accepts. Automaton has 108 states and 126 transitions. Word has length 39 [2018-11-23 14:42:21,137 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:42:21,137 INFO L480 AbstractCegarLoop]: Abstraction has 108 states and 126 transitions. [2018-11-23 14:42:21,137 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 14:42:21,137 INFO L276 IsEmpty]: Start isEmpty. Operand 108 states and 126 transitions. [2018-11-23 14:42:21,137 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-11-23 14:42:21,138 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:42:21,138 INFO L402 BasicCegarLoop]: trace histogram [3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:42:21,138 INFO L423 AbstractCegarLoop]: === Iteration 15 === [single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 14:42:21,138 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:42:21,139 INFO L82 PathProgramCache]: Analyzing trace with hash -716164038, now seen corresponding path program 1 times [2018-11-23 14:42:21,139 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:42:21,139 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:42:21,140 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:42:21,140 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:42:21,140 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:42:21,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:42:21,190 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-11-23 14:42:21,190 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 14:42:21,190 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_bb12028c-b1da-4712-8a45-3e9c572ad540/bin-2019/uautomizer/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 14:42:21,200 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:42:21,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:42:21,310 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 14:42:21,343 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-11-23 14:42:21,359 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 14:42:21,359 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 6] total 8 [2018-11-23 14:42:21,359 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-23 14:42:21,359 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-23 14:42:21,359 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=36, Unknown=0, NotChecked=0, Total=56 [2018-11-23 14:42:21,359 INFO L87 Difference]: Start difference. First operand 108 states and 126 transitions. Second operand 8 states. [2018-11-23 14:42:21,399 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:42:21,399 INFO L93 Difference]: Finished difference Result 210 states and 247 transitions. [2018-11-23 14:42:21,400 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-23 14:42:21,400 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 42 [2018-11-23 14:42:21,400 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:42:21,401 INFO L225 Difference]: With dead ends: 210 [2018-11-23 14:42:21,401 INFO L226 Difference]: Without dead ends: 118 [2018-11-23 14:42:21,401 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 45 GetRequests, 39 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=20, Invalid=36, Unknown=0, NotChecked=0, Total=56 [2018-11-23 14:42:21,402 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 118 states. [2018-11-23 14:42:21,405 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 118 to 114. [2018-11-23 14:42:21,406 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 114 states. [2018-11-23 14:42:21,406 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 132 transitions. [2018-11-23 14:42:21,406 INFO L78 Accepts]: Start accepts. Automaton has 114 states and 132 transitions. Word has length 42 [2018-11-23 14:42:21,406 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:42:21,406 INFO L480 AbstractCegarLoop]: Abstraction has 114 states and 132 transitions. [2018-11-23 14:42:21,406 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-23 14:42:21,407 INFO L276 IsEmpty]: Start isEmpty. Operand 114 states and 132 transitions. [2018-11-23 14:42:21,407 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-11-23 14:42:21,407 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:42:21,407 INFO L402 BasicCegarLoop]: trace histogram [4, 4, 4, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:42:21,408 INFO L423 AbstractCegarLoop]: === Iteration 16 === [single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 14:42:21,408 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:42:21,408 INFO L82 PathProgramCache]: Analyzing trace with hash -86642261, now seen corresponding path program 2 times [2018-11-23 14:42:21,408 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:42:21,408 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:42:21,409 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:42:21,409 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:42:21,409 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:42:21,428 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:42:21,473 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 1 proven. 5 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2018-11-23 14:42:21,473 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 14:42:21,473 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_bb12028c-b1da-4712-8a45-3e9c572ad540/bin-2019/uautomizer/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 14:42:21,483 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-23 14:42:21,580 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-11-23 14:42:21,581 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 14:42:21,585 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 14:42:21,599 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2018-11-23 14:42:21,616 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-23 14:42:21,616 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [5] total 6 [2018-11-23 14:42:21,617 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 14:42:21,617 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 14:42:21,617 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2018-11-23 14:42:21,617 INFO L87 Difference]: Start difference. First operand 114 states and 132 transitions. Second operand 6 states. [2018-11-23 14:42:21,670 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:42:21,670 INFO L93 Difference]: Finished difference Result 216 states and 260 transitions. [2018-11-23 14:42:21,670 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 14:42:21,671 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 48 [2018-11-23 14:42:21,671 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:42:21,673 INFO L225 Difference]: With dead ends: 216 [2018-11-23 14:42:21,673 INFO L226 Difference]: Without dead ends: 131 [2018-11-23 14:42:21,673 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 48 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2018-11-23 14:42:21,674 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 131 states. [2018-11-23 14:42:21,678 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 131 to 118. [2018-11-23 14:42:21,678 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 118 states. [2018-11-23 14:42:21,679 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118 states to 118 states and 136 transitions. [2018-11-23 14:42:21,679 INFO L78 Accepts]: Start accepts. Automaton has 118 states and 136 transitions. Word has length 48 [2018-11-23 14:42:21,679 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:42:21,680 INFO L480 AbstractCegarLoop]: Abstraction has 118 states and 136 transitions. [2018-11-23 14:42:21,680 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 14:42:21,680 INFO L276 IsEmpty]: Start isEmpty. Operand 118 states and 136 transitions. [2018-11-23 14:42:21,680 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-11-23 14:42:21,680 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:42:21,680 INFO L402 BasicCegarLoop]: trace histogram [4, 4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:42:21,681 INFO L423 AbstractCegarLoop]: === Iteration 17 === [single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 14:42:21,681 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:42:21,681 INFO L82 PathProgramCache]: Analyzing trace with hash 1247548610, now seen corresponding path program 1 times [2018-11-23 14:42:21,681 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:42:21,681 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:42:21,683 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:42:21,683 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 14:42:21,683 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:42:21,706 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:42:21,754 INFO L134 CoverageAnalysis]: Checked inductivity of 35 backedges. 1 proven. 12 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2018-11-23 14:42:21,755 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 14:42:21,755 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_bb12028c-b1da-4712-8a45-3e9c572ad540/bin-2019/uautomizer/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 14:42:21,770 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:42:21,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:42:21,928 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 14:42:21,984 INFO L134 CoverageAnalysis]: Checked inductivity of 35 backedges. 0 proven. 22 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-11-23 14:42:22,011 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 14:42:22,011 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 7] total 11 [2018-11-23 14:42:22,012 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-11-23 14:42:22,012 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-11-23 14:42:22,012 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=75, Unknown=0, NotChecked=0, Total=110 [2018-11-23 14:42:22,012 INFO L87 Difference]: Start difference. First operand 118 states and 136 transitions. Second operand 11 states. [2018-11-23 14:42:22,088 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:42:22,088 INFO L93 Difference]: Finished difference Result 227 states and 264 transitions. [2018-11-23 14:42:22,089 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-11-23 14:42:22,089 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 52 [2018-11-23 14:42:22,089 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:42:22,090 INFO L225 Difference]: With dead ends: 227 [2018-11-23 14:42:22,090 INFO L226 Difference]: Without dead ends: 128 [2018-11-23 14:42:22,090 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 57 GetRequests, 48 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=35, Invalid=75, Unknown=0, NotChecked=0, Total=110 [2018-11-23 14:42:22,091 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 128 states. [2018-11-23 14:42:22,094 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 128 to 124. [2018-11-23 14:42:22,094 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 124 states. [2018-11-23 14:42:22,095 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 124 states to 124 states and 142 transitions. [2018-11-23 14:42:22,095 INFO L78 Accepts]: Start accepts. Automaton has 124 states and 142 transitions. Word has length 52 [2018-11-23 14:42:22,095 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:42:22,095 INFO L480 AbstractCegarLoop]: Abstraction has 124 states and 142 transitions. [2018-11-23 14:42:22,095 INFO L481 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-11-23 14:42:22,095 INFO L276 IsEmpty]: Start isEmpty. Operand 124 states and 142 transitions. [2018-11-23 14:42:22,096 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2018-11-23 14:42:22,096 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:42:22,096 INFO L402 BasicCegarLoop]: trace histogram [5, 5, 5, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:42:22,096 INFO L423 AbstractCegarLoop]: === Iteration 18 === [single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 14:42:22,097 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:42:22,097 INFO L82 PathProgramCache]: Analyzing trace with hash 2080661809, now seen corresponding path program 2 times [2018-11-23 14:42:22,097 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:42:22,097 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:42:22,098 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:42:22,098 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:42:22,098 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:42:22,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:42:22,200 INFO L134 CoverageAnalysis]: Checked inductivity of 58 backedges. 1 proven. 22 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2018-11-23 14:42:22,200 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 14:42:22,200 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_bb12028c-b1da-4712-8a45-3e9c572ad540/bin-2019/uautomizer/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 14:42:22,213 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-23 14:42:22,374 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-23 14:42:22,374 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 14:42:22,380 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 14:42:22,456 INFO L134 CoverageAnalysis]: Checked inductivity of 58 backedges. 0 proven. 35 refuted. 0 times theorem prover too weak. 23 trivial. 0 not checked. [2018-11-23 14:42:22,471 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 14:42:22,472 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 8] total 13 [2018-11-23 14:42:22,472 INFO L459 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-11-23 14:42:22,472 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-11-23 14:42:22,472 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=48, Invalid=108, Unknown=0, NotChecked=0, Total=156 [2018-11-23 14:42:22,472 INFO L87 Difference]: Start difference. First operand 124 states and 142 transitions. Second operand 13 states. [2018-11-23 14:42:22,561 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:42:22,561 INFO L93 Difference]: Finished difference Result 236 states and 273 transitions. [2018-11-23 14:42:22,562 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-11-23 14:42:22,562 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 58 [2018-11-23 14:42:22,562 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:42:22,563 INFO L225 Difference]: With dead ends: 236 [2018-11-23 14:42:22,563 INFO L226 Difference]: Without dead ends: 134 [2018-11-23 14:42:22,564 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 64 GetRequests, 53 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 24 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=48, Invalid=108, Unknown=0, NotChecked=0, Total=156 [2018-11-23 14:42:22,564 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 134 states. [2018-11-23 14:42:22,568 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 134 to 130. [2018-11-23 14:42:22,569 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 130 states. [2018-11-23 14:42:22,569 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 130 states to 130 states and 148 transitions. [2018-11-23 14:42:22,569 INFO L78 Accepts]: Start accepts. Automaton has 130 states and 148 transitions. Word has length 58 [2018-11-23 14:42:22,570 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:42:22,570 INFO L480 AbstractCegarLoop]: Abstraction has 130 states and 148 transitions. [2018-11-23 14:42:22,570 INFO L481 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-11-23 14:42:22,570 INFO L276 IsEmpty]: Start isEmpty. Operand 130 states and 148 transitions. [2018-11-23 14:42:22,570 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2018-11-23 14:42:22,570 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:42:22,570 INFO L402 BasicCegarLoop]: trace histogram [6, 6, 6, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:42:22,571 INFO L423 AbstractCegarLoop]: === Iteration 19 === [single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 14:42:22,571 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:42:22,571 INFO L82 PathProgramCache]: Analyzing trace with hash -1647139486, now seen corresponding path program 3 times [2018-11-23 14:42:22,571 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:42:22,571 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:42:22,572 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:42:22,572 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 14:42:22,573 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:42:22,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:42:22,667 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 1 proven. 35 refuted. 0 times theorem prover too weak. 51 trivial. 0 not checked. [2018-11-23 14:42:22,667 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 14:42:22,667 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_bb12028c-b1da-4712-8a45-3e9c572ad540/bin-2019/uautomizer/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 14:42:22,682 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-23 14:42:24,584 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 7 check-sat command(s) [2018-11-23 14:42:24,584 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 14:42:24,588 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 14:42:24,601 INFO L134 CoverageAnalysis]: Checked inductivity of 87 backedges. 1 proven. 35 refuted. 0 times theorem prover too weak. 51 trivial. 0 not checked. [2018-11-23 14:42:24,620 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 14:42:24,620 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 9 [2018-11-23 14:42:24,620 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-11-23 14:42:24,620 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-11-23 14:42:24,620 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=36, Unknown=0, NotChecked=0, Total=72 [2018-11-23 14:42:24,620 INFO L87 Difference]: Start difference. First operand 130 states and 148 transitions. Second operand 9 states. [2018-11-23 14:42:24,645 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:42:24,646 INFO L93 Difference]: Finished difference Result 230 states and 266 transitions. [2018-11-23 14:42:24,647 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-23 14:42:24,647 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 64 [2018-11-23 14:42:24,648 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:42:24,648 INFO L225 Difference]: With dead ends: 230 [2018-11-23 14:42:24,648 INFO L226 Difference]: Without dead ends: 135 [2018-11-23 14:42:24,649 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 71 GetRequests, 64 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=36, Invalid=36, Unknown=0, NotChecked=0, Total=72 [2018-11-23 14:42:24,649 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 135 states. [2018-11-23 14:42:24,654 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 135 to 133. [2018-11-23 14:42:24,654 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 133 states. [2018-11-23 14:42:24,654 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 133 states to 133 states and 151 transitions. [2018-11-23 14:42:24,655 INFO L78 Accepts]: Start accepts. Automaton has 133 states and 151 transitions. Word has length 64 [2018-11-23 14:42:24,655 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:42:24,655 INFO L480 AbstractCegarLoop]: Abstraction has 133 states and 151 transitions. [2018-11-23 14:42:24,655 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-11-23 14:42:24,655 INFO L276 IsEmpty]: Start isEmpty. Operand 133 states and 151 transitions. [2018-11-23 14:42:24,655 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2018-11-23 14:42:24,655 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:42:24,655 INFO L402 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:42:24,656 INFO L423 AbstractCegarLoop]: === Iteration 20 === [single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 14:42:24,656 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:42:24,656 INFO L82 PathProgramCache]: Analyzing trace with hash 1571808757, now seen corresponding path program 4 times [2018-11-23 14:42:24,656 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:42:24,656 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:42:24,661 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:42:24,662 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 14:42:24,662 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:42:24,683 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:42:24,758 INFO L134 CoverageAnalysis]: Checked inductivity of 103 backedges. 0 proven. 51 refuted. 0 times theorem prover too weak. 52 trivial. 0 not checked. [2018-11-23 14:42:24,759 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 14:42:24,759 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_bb12028c-b1da-4712-8a45-3e9c572ad540/bin-2019/uautomizer/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 14:42:24,779 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-23 14:42:24,879 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-23 14:42:24,879 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 14:42:24,883 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 14:42:24,897 INFO L134 CoverageAnalysis]: Checked inductivity of 103 backedges. 0 proven. 51 refuted. 0 times theorem prover too weak. 52 trivial. 0 not checked. [2018-11-23 14:42:24,913 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 14:42:24,914 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 10 [2018-11-23 14:42:24,914 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-23 14:42:24,914 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-23 14:42:24,914 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-11-23 14:42:24,915 INFO L87 Difference]: Start difference. First operand 133 states and 151 transitions. Second operand 10 states. [2018-11-23 14:42:24,968 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:42:24,968 INFO L93 Difference]: Finished difference Result 246 states and 282 transitions. [2018-11-23 14:42:24,969 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-23 14:42:24,969 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 67 [2018-11-23 14:42:24,969 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:42:24,970 INFO L225 Difference]: With dead ends: 246 [2018-11-23 14:42:24,970 INFO L226 Difference]: Without dead ends: 138 [2018-11-23 14:42:24,971 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 75 GetRequests, 67 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-11-23 14:42:24,971 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 138 states. [2018-11-23 14:42:24,975 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 138 to 136. [2018-11-23 14:42:24,975 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 136 states. [2018-11-23 14:42:24,976 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 136 states to 136 states and 154 transitions. [2018-11-23 14:42:24,976 INFO L78 Accepts]: Start accepts. Automaton has 136 states and 154 transitions. Word has length 67 [2018-11-23 14:42:24,976 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:42:24,976 INFO L480 AbstractCegarLoop]: Abstraction has 136 states and 154 transitions. [2018-11-23 14:42:24,976 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-23 14:42:24,976 INFO L276 IsEmpty]: Start isEmpty. Operand 136 states and 154 transitions. [2018-11-23 14:42:24,977 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-11-23 14:42:24,977 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:42:24,977 INFO L402 BasicCegarLoop]: trace histogram [7, 7, 7, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:42:24,977 INFO L423 AbstractCegarLoop]: === Iteration 21 === [single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 14:42:24,977 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:42:24,977 INFO L82 PathProgramCache]: Analyzing trace with hash 312181393, now seen corresponding path program 5 times [2018-11-23 14:42:24,978 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:42:24,978 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:42:24,979 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:42:24,979 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 14:42:24,979 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:42:25,002 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:42:25,069 INFO L134 CoverageAnalysis]: Checked inductivity of 122 backedges. 0 proven. 70 refuted. 0 times theorem prover too weak. 52 trivial. 0 not checked. [2018-11-23 14:42:25,069 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 14:42:25,069 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_bb12028c-b1da-4712-8a45-3e9c572ad540/bin-2019/uautomizer/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 14:42:25,079 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-11-23 14:42:28,735 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2018-11-23 14:42:28,736 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 14:42:28,739 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 14:42:28,798 INFO L134 CoverageAnalysis]: Checked inductivity of 122 backedges. 1 proven. 51 refuted. 0 times theorem prover too weak. 70 trivial. 0 not checked. [2018-11-23 14:42:28,814 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 14:42:28,814 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 9] total 17 [2018-11-23 14:42:28,814 INFO L459 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-11-23 14:42:28,814 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-11-23 14:42:28,815 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=80, Invalid=192, Unknown=0, NotChecked=0, Total=272 [2018-11-23 14:42:28,815 INFO L87 Difference]: Start difference. First operand 136 states and 154 transitions. Second operand 17 states. [2018-11-23 14:42:28,887 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:42:28,887 INFO L93 Difference]: Finished difference Result 254 states and 291 transitions. [2018-11-23 14:42:28,893 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-11-23 14:42:28,893 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 70 [2018-11-23 14:42:28,894 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:42:28,894 INFO L225 Difference]: With dead ends: 254 [2018-11-23 14:42:28,894 INFO L226 Difference]: Without dead ends: 146 [2018-11-23 14:42:28,895 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 79 GetRequests, 64 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 49 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=80, Invalid=192, Unknown=0, NotChecked=0, Total=272 [2018-11-23 14:42:28,895 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 146 states. [2018-11-23 14:42:28,900 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 146 to 142. [2018-11-23 14:42:28,900 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 142 states. [2018-11-23 14:42:28,901 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 142 states to 142 states and 160 transitions. [2018-11-23 14:42:28,901 INFO L78 Accepts]: Start accepts. Automaton has 142 states and 160 transitions. Word has length 70 [2018-11-23 14:42:28,901 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:42:28,901 INFO L480 AbstractCegarLoop]: Abstraction has 142 states and 160 transitions. [2018-11-23 14:42:28,901 INFO L481 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-11-23 14:42:28,901 INFO L276 IsEmpty]: Start isEmpty. Operand 142 states and 160 transitions. [2018-11-23 14:42:28,904 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2018-11-23 14:42:28,904 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:42:28,904 INFO L402 BasicCegarLoop]: trace histogram [8, 8, 8, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:42:28,905 INFO L423 AbstractCegarLoop]: === Iteration 22 === [single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 14:42:28,905 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:42:28,905 INFO L82 PathProgramCache]: Analyzing trace with hash 1501953538, now seen corresponding path program 6 times [2018-11-23 14:42:28,905 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:42:28,905 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:42:28,906 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:42:28,906 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 14:42:28,906 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:42:28,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:42:29,040 INFO L134 CoverageAnalysis]: Checked inductivity of 163 backedges. 1 proven. 70 refuted. 0 times theorem prover too weak. 92 trivial. 0 not checked. [2018-11-23 14:42:29,040 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 14:42:29,040 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_bb12028c-b1da-4712-8a45-3e9c572ad540/bin-2019/uautomizer/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 14:42:29,053 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-11-23 14:42:34,174 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 9 check-sat command(s) [2018-11-23 14:42:34,174 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 14:42:34,180 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 14:42:34,276 INFO L134 CoverageAnalysis]: Checked inductivity of 163 backedges. 0 proven. 92 refuted. 0 times theorem prover too weak. 71 trivial. 0 not checked. [2018-11-23 14:42:34,295 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 14:42:34,295 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 11] total 19 [2018-11-23 14:42:34,295 INFO L459 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-11-23 14:42:34,295 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-11-23 14:42:34,295 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=99, Invalid=243, Unknown=0, NotChecked=0, Total=342 [2018-11-23 14:42:34,296 INFO L87 Difference]: Start difference. First operand 142 states and 160 transitions. Second operand 19 states. [2018-11-23 14:42:34,395 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:42:34,395 INFO L93 Difference]: Finished difference Result 263 states and 300 transitions. [2018-11-23 14:42:34,396 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-11-23 14:42:34,396 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 76 [2018-11-23 14:42:34,396 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:42:34,397 INFO L225 Difference]: With dead ends: 263 [2018-11-23 14:42:34,397 INFO L226 Difference]: Without dead ends: 152 [2018-11-23 14:42:34,397 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 85 GetRequests, 67 SyntacticMatches, 1 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 70 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=99, Invalid=243, Unknown=0, NotChecked=0, Total=342 [2018-11-23 14:42:34,398 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 152 states. [2018-11-23 14:42:34,403 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 152 to 148. [2018-11-23 14:42:34,403 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 148 states. [2018-11-23 14:42:34,403 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 148 states to 148 states and 166 transitions. [2018-11-23 14:42:34,404 INFO L78 Accepts]: Start accepts. Automaton has 148 states and 166 transitions. Word has length 76 [2018-11-23 14:42:34,404 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:42:34,404 INFO L480 AbstractCegarLoop]: Abstraction has 148 states and 166 transitions. [2018-11-23 14:42:34,404 INFO L481 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-11-23 14:42:34,404 INFO L276 IsEmpty]: Start isEmpty. Operand 148 states and 166 transitions. [2018-11-23 14:42:34,405 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 83 [2018-11-23 14:42:34,406 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:42:34,406 INFO L402 BasicCegarLoop]: trace histogram [9, 9, 9, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:42:34,406 INFO L423 AbstractCegarLoop]: === Iteration 23 === [single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 14:42:34,406 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:42:34,406 INFO L82 PathProgramCache]: Analyzing trace with hash 631233521, now seen corresponding path program 7 times [2018-11-23 14:42:34,407 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:42:34,407 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:42:34,408 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:42:34,408 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 14:42:34,408 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:42:34,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:42:34,540 INFO L134 CoverageAnalysis]: Checked inductivity of 210 backedges. 1 proven. 92 refuted. 0 times theorem prover too weak. 117 trivial. 0 not checked. [2018-11-23 14:42:34,540 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 14:42:34,540 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_bb12028c-b1da-4712-8a45-3e9c572ad540/bin-2019/uautomizer/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 14:42:34,553 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:42:34,666 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:42:34,670 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 14:42:34,756 INFO L134 CoverageAnalysis]: Checked inductivity of 210 backedges. 0 proven. 117 refuted. 0 times theorem prover too weak. 93 trivial. 0 not checked. [2018-11-23 14:42:34,772 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 14:42:34,772 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 12] total 21 [2018-11-23 14:42:34,773 INFO L459 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-11-23 14:42:34,773 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-11-23 14:42:34,773 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=120, Invalid=300, Unknown=0, NotChecked=0, Total=420 [2018-11-23 14:42:34,773 INFO L87 Difference]: Start difference. First operand 148 states and 166 transitions. Second operand 21 states. [2018-11-23 14:42:34,840 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:42:34,840 INFO L93 Difference]: Finished difference Result 270 states and 307 transitions. [2018-11-23 14:42:34,841 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-11-23 14:42:34,841 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 82 [2018-11-23 14:42:34,841 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:42:34,842 INFO L225 Difference]: With dead ends: 270 [2018-11-23 14:42:34,842 INFO L226 Difference]: Without dead ends: 156 [2018-11-23 14:42:34,842 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 92 GetRequests, 73 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 80 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=120, Invalid=300, Unknown=0, NotChecked=0, Total=420 [2018-11-23 14:42:34,843 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 156 states. [2018-11-23 14:42:34,849 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 156 to 154. [2018-11-23 14:42:34,849 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 154 states. [2018-11-23 14:42:34,850 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 154 states to 154 states and 172 transitions. [2018-11-23 14:42:34,850 INFO L78 Accepts]: Start accepts. Automaton has 154 states and 172 transitions. Word has length 82 [2018-11-23 14:42:34,850 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:42:34,850 INFO L480 AbstractCegarLoop]: Abstraction has 154 states and 172 transitions. [2018-11-23 14:42:34,850 INFO L481 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-11-23 14:42:34,851 INFO L276 IsEmpty]: Start isEmpty. Operand 154 states and 172 transitions. [2018-11-23 14:42:34,851 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 89 [2018-11-23 14:42:34,851 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:42:34,851 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:42:34,851 INFO L423 AbstractCegarLoop]: === Iteration 24 === [single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 14:42:34,852 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:42:34,852 INFO L82 PathProgramCache]: Analyzing trace with hash 1461722786, now seen corresponding path program 8 times [2018-11-23 14:42:34,852 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:42:34,852 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:42:34,853 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:42:34,853 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:42:34,854 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:42:34,881 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:42:34,975 INFO L134 CoverageAnalysis]: Checked inductivity of 263 backedges. 1 proven. 117 refuted. 0 times theorem prover too weak. 145 trivial. 0 not checked. [2018-11-23 14:42:34,975 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 14:42:34,975 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_bb12028c-b1da-4712-8a45-3e9c572ad540/bin-2019/uautomizer/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 14:42:34,987 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-23 14:42:35,110 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-23 14:42:35,110 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 14:42:35,114 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 14:42:35,130 INFO L134 CoverageAnalysis]: Checked inductivity of 263 backedges. 1 proven. 117 refuted. 0 times theorem prover too weak. 145 trivial. 0 not checked. [2018-11-23 14:42:35,146 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 14:42:35,147 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12] total 13 [2018-11-23 14:42:35,147 INFO L459 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-11-23 14:42:35,147 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-11-23 14:42:35,147 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2018-11-23 14:42:35,148 INFO L87 Difference]: Start difference. First operand 154 states and 172 transitions. Second operand 13 states. [2018-11-23 14:42:35,206 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:42:35,207 INFO L93 Difference]: Finished difference Result 264 states and 300 transitions. [2018-11-23 14:42:35,209 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-11-23 14:42:35,209 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 88 [2018-11-23 14:42:35,210 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:42:35,210 INFO L225 Difference]: With dead ends: 264 [2018-11-23 14:42:35,210 INFO L226 Difference]: Without dead ends: 157 [2018-11-23 14:42:35,211 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 99 GetRequests, 88 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=78, Invalid=78, Unknown=0, NotChecked=0, Total=156 [2018-11-23 14:42:35,211 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 157 states. [2018-11-23 14:42:35,220 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 157 to 157. [2018-11-23 14:42:35,220 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 157 states. [2018-11-23 14:42:35,221 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 157 states to 157 states and 175 transitions. [2018-11-23 14:42:35,221 INFO L78 Accepts]: Start accepts. Automaton has 157 states and 175 transitions. Word has length 88 [2018-11-23 14:42:35,221 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:42:35,221 INFO L480 AbstractCegarLoop]: Abstraction has 157 states and 175 transitions. [2018-11-23 14:42:35,221 INFO L481 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-11-23 14:42:35,221 INFO L276 IsEmpty]: Start isEmpty. Operand 157 states and 175 transitions. [2018-11-23 14:42:35,222 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 92 [2018-11-23 14:42:35,222 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:42:35,222 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:42:35,222 INFO L423 AbstractCegarLoop]: === Iteration 25 === [single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 14:42:35,222 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:42:35,222 INFO L82 PathProgramCache]: Analyzing trace with hash 1012982965, now seen corresponding path program 9 times [2018-11-23 14:42:35,223 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:42:35,223 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:42:35,224 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:42:35,224 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 14:42:35,224 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:42:35,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:42:36,886 INFO L134 CoverageAnalysis]: Checked inductivity of 291 backedges. 0 proven. 146 refuted. 0 times theorem prover too weak. 145 trivial. 0 not checked. [2018-11-23 14:42:36,886 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 14:42:36,886 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_bb12028c-b1da-4712-8a45-3e9c572ad540/bin-2019/uautomizer/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 14:42:36,895 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-23 14:43:07,356 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2018-11-23 14:43:07,356 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 14:43:07,367 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 14:43:07,454 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-11-23 14:43:07,455 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-23 14:43:07,462 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:07,463 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:16, output treesize:15 [2018-11-23 14:43:07,487 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:07,489 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:07,490 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-11-23 14:43:07,490 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-23 14:43:07,509 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 12 [2018-11-23 14:43:07,511 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 11 [2018-11-23 14:43:07,511 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-11-23 14:43:07,513 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:07,528 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 12 [2018-11-23 14:43:07,530 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 11 [2018-11-23 14:43:07,530 INFO L267 ElimStorePlain]: Start of recursive call 6: End of recursive call: and 1 xjuncts. [2018-11-23 14:43:07,532 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:07,543 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, 2 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:07,544 INFO L202 ElimStorePlain]: Needed 6 recursive calls to eliminate 3 variables, input treesize:62, output treesize:52 [2018-11-23 14:43:07,589 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:07,592 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:07,593 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:07,594 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 13 [2018-11-23 14:43:07,595 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-11-23 14:43:07,661 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 606 treesize of output 424 [2018-11-23 14:43:07,751 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:07,754 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 3 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 35 [2018-11-23 14:43:07,755 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-11-23 14:43:07,782 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 341 treesize of output 335 [2018-11-23 14:43:07,785 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-11-23 14:43:07,785 INFO L267 ElimStorePlain]: Start of recursive call 6: End of recursive call: and 1 xjuncts. [2018-11-23 14:43:07,814 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 330 treesize of output 339 [2018-11-23 14:43:07,817 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 100 treesize of output 1 [2018-11-23 14:43:07,818 INFO L267 ElimStorePlain]: Start of recursive call 8: End of recursive call: and 1 xjuncts. [2018-11-23 14:43:07,830 INFO L267 ElimStorePlain]: Start of recursive call 7: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:07,839 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-1 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:07,848 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:07,881 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 207 treesize of output 121 [2018-11-23 14:43:07,903 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:07,904 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 35 [2018-11-23 14:43:07,904 INFO L267 ElimStorePlain]: Start of recursive call 10: End of recursive call: and 1 xjuncts. [2018-11-23 14:43:07,914 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 102 treesize of output 96 [2018-11-23 14:43:07,917 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-11-23 14:43:07,917 INFO L267 ElimStorePlain]: Start of recursive call 12: End of recursive call: and 1 xjuncts. [2018-11-23 14:43:07,931 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 91 treesize of output 108 [2018-11-23 14:43:07,934 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 1 [2018-11-23 14:43:07,934 INFO L267 ElimStorePlain]: Start of recursive call 14: End of recursive call: and 1 xjuncts. [2018-11-23 14:43:07,950 INFO L267 ElimStorePlain]: Start of recursive call 13: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:07,954 INFO L267 ElimStorePlain]: Start of recursive call 11: 1 dim-1 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:07,958 INFO L267 ElimStorePlain]: Start of recursive call 9: 1 dim-1 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:07,975 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, 2 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-23 14:43:07,975 INFO L202 ElimStorePlain]: Needed 14 recursive calls to eliminate 5 variables, input treesize:654, output treesize:103 [2018-11-23 14:43:08,033 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 142 treesize of output 159 [2018-11-23 14:43:08,035 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 44 treesize of output 1 [2018-11-23 14:43:08,035 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 14:43:08,053 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:08,094 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 108 treesize of output 102 [2018-11-23 14:43:08,099 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 42 treesize of output 41 [2018-11-23 14:43:08,099 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-23 14:43:08,107 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:08,121 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-23 14:43:08,122 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 3 variables, input treesize:210, output treesize:100 [2018-11-23 14:43:08,172 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 150 treesize of output 167 [2018-11-23 14:43:08,174 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 1 [2018-11-23 14:43:08,174 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 14:43:08,182 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:08,207 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 112 treesize of output 106 [2018-11-23 14:43:08,209 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 46 treesize of output 45 [2018-11-23 14:43:08,209 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-23 14:43:08,216 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:08,229 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-23 14:43:08,230 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 4 variables, input treesize:218, output treesize:100 [2018-11-23 14:43:08,252 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 171 treesize of output 165 [2018-11-23 14:43:08,257 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 46 treesize of output 45 [2018-11-23 14:43:08,257 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 14:43:08,272 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:08,303 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 91 treesize of output 108 [2018-11-23 14:43:08,305 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 1 [2018-11-23 14:43:08,306 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-23 14:43:08,312 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:08,328 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-23 14:43:08,328 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 4 variables, input treesize:218, output treesize:100 [2018-11-23 14:43:08,343 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 171 treesize of output 165 [2018-11-23 14:43:08,346 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 46 treesize of output 45 [2018-11-23 14:43:08,346 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 14:43:08,354 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:08,380 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 91 treesize of output 108 [2018-11-23 14:43:08,382 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 1 [2018-11-23 14:43:08,382 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-23 14:43:08,388 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:08,402 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-23 14:43:08,402 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 4 variables, input treesize:218, output treesize:100 [2018-11-23 14:43:08,413 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 171 treesize of output 165 [2018-11-23 14:43:08,415 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 46 treesize of output 45 [2018-11-23 14:43:08,415 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 14:43:08,424 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:08,446 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 91 treesize of output 108 [2018-11-23 14:43:08,448 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 1 [2018-11-23 14:43:08,449 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-23 14:43:08,459 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:08,473 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-23 14:43:08,473 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 4 variables, input treesize:218, output treesize:100 [2018-11-23 14:43:08,486 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 171 treesize of output 165 [2018-11-23 14:43:08,489 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 46 treesize of output 45 [2018-11-23 14:43:08,489 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 14:43:08,499 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:08,524 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 91 treesize of output 108 [2018-11-23 14:43:08,527 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 1 [2018-11-23 14:43:08,527 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-23 14:43:08,534 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:08,549 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-23 14:43:08,549 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 4 variables, input treesize:218, output treesize:100 [2018-11-23 14:43:08,568 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 171 treesize of output 165 [2018-11-23 14:43:08,576 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 46 treesize of output 45 [2018-11-23 14:43:08,576 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 14:43:08,592 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:08,622 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 91 treesize of output 108 [2018-11-23 14:43:08,624 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 1 [2018-11-23 14:43:08,624 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-23 14:43:08,631 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:08,650 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-23 14:43:08,650 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 3 variables, input treesize:218, output treesize:100 [2018-11-23 14:43:08,666 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 171 treesize of output 165 [2018-11-23 14:43:08,669 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 46 treesize of output 45 [2018-11-23 14:43:08,669 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 14:43:08,682 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:08,715 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 91 treesize of output 108 [2018-11-23 14:43:08,720 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 1 [2018-11-23 14:43:08,720 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-23 14:43:08,728 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:08,764 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-23 14:43:08,764 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 3 variables, input treesize:218, output treesize:100 [2018-11-23 14:43:08,783 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 171 treesize of output 165 [2018-11-23 14:43:08,786 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 46 treesize of output 45 [2018-11-23 14:43:08,786 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 14:43:08,796 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:08,822 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 91 treesize of output 108 [2018-11-23 14:43:08,824 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 1 [2018-11-23 14:43:08,825 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-23 14:43:08,832 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:08,847 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-23 14:43:08,847 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 3 variables, input treesize:218, output treesize:100 [2018-11-23 14:43:08,871 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 171 treesize of output 165 [2018-11-23 14:43:08,873 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 46 treesize of output 45 [2018-11-23 14:43:08,873 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-11-23 14:43:08,881 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:08,904 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 91 treesize of output 108 [2018-11-23 14:43:08,906 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 1 [2018-11-23 14:43:08,906 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-11-23 14:43:08,913 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:08,929 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-11-23 14:43:08,929 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 3 variables, input treesize:221, output treesize:103 [2018-11-23 14:43:09,276 INFO L134 CoverageAnalysis]: Checked inductivity of 291 backedges. 55 proven. 11 refuted. 0 times theorem prover too weak. 225 trivial. 0 not checked. [2018-11-23 14:43:09,297 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 14:43:09,297 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 17] total 40 [2018-11-23 14:43:09,298 INFO L459 AbstractCegarLoop]: Interpolant automaton has 40 states [2018-11-23 14:43:09,298 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2018-11-23 14:43:09,298 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=271, Invalid=1289, Unknown=0, NotChecked=0, Total=1560 [2018-11-23 14:43:09,298 INFO L87 Difference]: Start difference. First operand 157 states and 175 transitions. Second operand 40 states. [2018-11-23 14:43:10,484 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:43:10,485 INFO L93 Difference]: Finished difference Result 279 states and 320 transitions. [2018-11-23 14:43:10,485 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-11-23 14:43:10,485 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 91 [2018-11-23 14:43:10,485 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:43:10,486 INFO L225 Difference]: With dead ends: 279 [2018-11-23 14:43:10,486 INFO L226 Difference]: Without dead ends: 208 [2018-11-23 14:43:10,487 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 136 GetRequests, 81 SyntacticMatches, 6 SemanticMatches, 49 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 738 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=451, Invalid=2099, Unknown=0, NotChecked=0, Total=2550 [2018-11-23 14:43:10,487 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 208 states. [2018-11-23 14:43:10,498 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 208 to 205. [2018-11-23 14:43:10,499 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 205 states. [2018-11-23 14:43:10,499 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 205 states to 205 states and 230 transitions. [2018-11-23 14:43:10,500 INFO L78 Accepts]: Start accepts. Automaton has 205 states and 230 transitions. Word has length 91 [2018-11-23 14:43:10,500 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:43:10,500 INFO L480 AbstractCegarLoop]: Abstraction has 205 states and 230 transitions. [2018-11-23 14:43:10,500 INFO L481 AbstractCegarLoop]: Interpolant automaton has 40 states. [2018-11-23 14:43:10,500 INFO L276 IsEmpty]: Start isEmpty. Operand 205 states and 230 transitions. [2018-11-23 14:43:10,501 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 98 [2018-11-23 14:43:10,501 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:43:10,501 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:43:10,502 INFO L423 AbstractCegarLoop]: === Iteration 26 === [single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 14:43:10,502 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:43:10,502 INFO L82 PathProgramCache]: Analyzing trace with hash -2132172502, now seen corresponding path program 1 times [2018-11-23 14:43:10,502 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:43:10,502 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:43:10,503 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:43:10,503 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 14:43:10,503 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:43:10,530 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:43:10,589 INFO L134 CoverageAnalysis]: Checked inductivity of 291 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 291 trivial. 0 not checked. [2018-11-23 14:43:10,589 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:43:10,589 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 14:43:10,590 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 14:43:10,590 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 14:43:10,590 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:43:10,590 INFO L87 Difference]: Start difference. First operand 205 states and 230 transitions. Second operand 3 states. [2018-11-23 14:43:10,620 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:43:10,620 INFO L93 Difference]: Finished difference Result 223 states and 250 transitions. [2018-11-23 14:43:10,620 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 14:43:10,620 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 97 [2018-11-23 14:43:10,620 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:43:10,621 INFO L225 Difference]: With dead ends: 223 [2018-11-23 14:43:10,621 INFO L226 Difference]: Without dead ends: 205 [2018-11-23 14:43:10,622 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:43:10,622 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 205 states. [2018-11-23 14:43:10,632 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 205 to 205. [2018-11-23 14:43:10,632 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 205 states. [2018-11-23 14:43:10,633 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 205 states to 205 states and 230 transitions. [2018-11-23 14:43:10,633 INFO L78 Accepts]: Start accepts. Automaton has 205 states and 230 transitions. Word has length 97 [2018-11-23 14:43:10,633 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:43:10,633 INFO L480 AbstractCegarLoop]: Abstraction has 205 states and 230 transitions. [2018-11-23 14:43:10,634 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 14:43:10,634 INFO L276 IsEmpty]: Start isEmpty. Operand 205 states and 230 transitions. [2018-11-23 14:43:10,634 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 99 [2018-11-23 14:43:10,634 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:43:10,634 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:43:10,635 INFO L423 AbstractCegarLoop]: === Iteration 27 === [single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 14:43:10,635 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:43:10,635 INFO L82 PathProgramCache]: Analyzing trace with hash -1672837872, now seen corresponding path program 1 times [2018-11-23 14:43:10,635 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:43:10,635 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:43:10,636 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:43:10,636 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:43:10,636 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:43:10,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:43:10,726 INFO L134 CoverageAnalysis]: Checked inductivity of 291 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 291 trivial. 0 not checked. [2018-11-23 14:43:10,726 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:43:10,726 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 14:43:10,726 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 14:43:10,727 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 14:43:10,727 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:43:10,727 INFO L87 Difference]: Start difference. First operand 205 states and 230 transitions. Second operand 3 states. [2018-11-23 14:43:10,750 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:43:10,750 INFO L93 Difference]: Finished difference Result 208 states and 233 transitions. [2018-11-23 14:43:10,750 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 14:43:10,750 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 98 [2018-11-23 14:43:10,750 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:43:10,751 INFO L225 Difference]: With dead ends: 208 [2018-11-23 14:43:10,751 INFO L226 Difference]: Without dead ends: 207 [2018-11-23 14:43:10,751 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:43:10,752 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 207 states. [2018-11-23 14:43:10,763 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 207 to 207. [2018-11-23 14:43:10,763 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 207 states. [2018-11-23 14:43:10,764 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 207 states to 207 states and 232 transitions. [2018-11-23 14:43:10,764 INFO L78 Accepts]: Start accepts. Automaton has 207 states and 232 transitions. Word has length 98 [2018-11-23 14:43:10,764 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:43:10,764 INFO L480 AbstractCegarLoop]: Abstraction has 207 states and 232 transitions. [2018-11-23 14:43:10,764 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 14:43:10,764 INFO L276 IsEmpty]: Start isEmpty. Operand 207 states and 232 transitions. [2018-11-23 14:43:10,765 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 102 [2018-11-23 14:43:10,765 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:43:10,765 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 10, 10, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:43:10,765 INFO L423 AbstractCegarLoop]: === Iteration 28 === [single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 14:43:10,765 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:43:10,766 INFO L82 PathProgramCache]: Analyzing trace with hash -1007265881, now seen corresponding path program 1 times [2018-11-23 14:43:10,766 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:43:10,766 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:43:10,767 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:43:10,767 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:43:10,767 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:43:10,792 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:43:10,833 INFO L134 CoverageAnalysis]: Checked inductivity of 294 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 291 trivial. 0 not checked. [2018-11-23 14:43:10,834 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:43:10,834 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 14:43:10,834 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 14:43:10,834 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 14:43:10,834 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:43:10,834 INFO L87 Difference]: Start difference. First operand 207 states and 232 transitions. Second operand 3 states. [2018-11-23 14:43:10,861 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:43:10,861 INFO L93 Difference]: Finished difference Result 207 states and 232 transitions. [2018-11-23 14:43:10,862 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 14:43:10,862 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 101 [2018-11-23 14:43:10,862 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:43:10,863 INFO L225 Difference]: With dead ends: 207 [2018-11-23 14:43:10,863 INFO L226 Difference]: Without dead ends: 206 [2018-11-23 14:43:10,863 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:43:10,863 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 206 states. [2018-11-23 14:43:10,874 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 206 to 204. [2018-11-23 14:43:10,874 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 204 states. [2018-11-23 14:43:10,875 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 204 states to 204 states and 229 transitions. [2018-11-23 14:43:10,875 INFO L78 Accepts]: Start accepts. Automaton has 204 states and 229 transitions. Word has length 101 [2018-11-23 14:43:10,875 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:43:10,875 INFO L480 AbstractCegarLoop]: Abstraction has 204 states and 229 transitions. [2018-11-23 14:43:10,875 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 14:43:10,875 INFO L276 IsEmpty]: Start isEmpty. Operand 204 states and 229 transitions. [2018-11-23 14:43:10,876 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-11-23 14:43:10,876 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:43:10,876 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:43:10,877 INFO L423 AbstractCegarLoop]: === Iteration 29 === [single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 14:43:10,877 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:43:10,877 INFO L82 PathProgramCache]: Analyzing trace with hash 446640932, now seen corresponding path program 1 times [2018-11-23 14:43:10,877 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:43:10,877 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:43:10,878 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:43:10,878 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:43:10,878 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:43:10,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:43:10,965 INFO L134 CoverageAnalysis]: Checked inductivity of 292 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 292 trivial. 0 not checked. [2018-11-23 14:43:10,965 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:43:10,965 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 14:43:10,966 INFO L459 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-11-23 14:43:10,966 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-11-23 14:43:10,966 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-11-23 14:43:10,966 INFO L87 Difference]: Start difference. First operand 204 states and 229 transitions. Second operand 4 states. [2018-11-23 14:43:11,046 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:43:11,046 INFO L93 Difference]: Finished difference Result 205 states and 230 transitions. [2018-11-23 14:43:11,049 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 14:43:11,049 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 113 [2018-11-23 14:43:11,050 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:43:11,050 INFO L225 Difference]: With dead ends: 205 [2018-11-23 14:43:11,050 INFO L226 Difference]: Without dead ends: 204 [2018-11-23 14:43:11,051 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-23 14:43:11,051 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 204 states. [2018-11-23 14:43:11,058 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 204 to 203. [2018-11-23 14:43:11,058 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 203 states. [2018-11-23 14:43:11,059 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 203 states to 203 states and 228 transitions. [2018-11-23 14:43:11,059 INFO L78 Accepts]: Start accepts. Automaton has 203 states and 228 transitions. Word has length 113 [2018-11-23 14:43:11,060 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:43:11,060 INFO L480 AbstractCegarLoop]: Abstraction has 203 states and 228 transitions. [2018-11-23 14:43:11,060 INFO L481 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-11-23 14:43:11,060 INFO L276 IsEmpty]: Start isEmpty. Operand 203 states and 228 transitions. [2018-11-23 14:43:11,061 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 115 [2018-11-23 14:43:11,061 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:43:11,061 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:43:11,061 INFO L423 AbstractCegarLoop]: === Iteration 30 === [single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 14:43:11,061 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:43:11,061 INFO L82 PathProgramCache]: Analyzing trace with hash 960967235, now seen corresponding path program 1 times [2018-11-23 14:43:11,061 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:43:11,061 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:43:11,062 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:43:11,062 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:43:11,063 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:43:11,080 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:43:11,112 INFO L134 CoverageAnalysis]: Checked inductivity of 292 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 292 trivial. 0 not checked. [2018-11-23 14:43:11,112 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:43:11,113 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 14:43:11,113 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 14:43:11,113 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 14:43:11,113 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:43:11,113 INFO L87 Difference]: Start difference. First operand 203 states and 228 transitions. Second operand 3 states. [2018-11-23 14:43:11,129 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:43:11,129 INFO L93 Difference]: Finished difference Result 207 states and 232 transitions. [2018-11-23 14:43:11,130 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 14:43:11,130 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 114 [2018-11-23 14:43:11,130 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:43:11,131 INFO L225 Difference]: With dead ends: 207 [2018-11-23 14:43:11,131 INFO L226 Difference]: Without dead ends: 206 [2018-11-23 14:43:11,131 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:43:11,132 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 206 states. [2018-11-23 14:43:11,139 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 206 to 206. [2018-11-23 14:43:11,139 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 206 states. [2018-11-23 14:43:11,140 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 206 states to 206 states and 231 transitions. [2018-11-23 14:43:11,140 INFO L78 Accepts]: Start accepts. Automaton has 206 states and 231 transitions. Word has length 114 [2018-11-23 14:43:11,140 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:43:11,140 INFO L480 AbstractCegarLoop]: Abstraction has 206 states and 231 transitions. [2018-11-23 14:43:11,140 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 14:43:11,140 INFO L276 IsEmpty]: Start isEmpty. Operand 206 states and 231 transitions. [2018-11-23 14:43:11,141 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 118 [2018-11-23 14:43:11,141 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:43:11,141 INFO L402 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 10, 10, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:43:11,142 INFO L423 AbstractCegarLoop]: === Iteration 31 === [single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 14:43:11,142 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:43:11,142 INFO L82 PathProgramCache]: Analyzing trace with hash -2076872735, now seen corresponding path program 1 times [2018-11-23 14:43:11,142 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:43:11,142 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:43:11,143 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:43:11,143 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:43:11,143 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:43:11,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:43:11,192 INFO L134 CoverageAnalysis]: Checked inductivity of 295 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 292 trivial. 0 not checked. [2018-11-23 14:43:11,192 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 14:43:11,192 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-11-23 14:43:11,193 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 14:43:11,193 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 14:43:11,193 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:43:11,193 INFO L87 Difference]: Start difference. First operand 206 states and 231 transitions. Second operand 3 states. [2018-11-23 14:43:11,206 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 14:43:11,206 INFO L93 Difference]: Finished difference Result 206 states and 231 transitions. [2018-11-23 14:43:11,207 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 14:43:11,207 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 117 [2018-11-23 14:43:11,207 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 14:43:11,208 INFO L225 Difference]: With dead ends: 206 [2018-11-23 14:43:11,208 INFO L226 Difference]: Without dead ends: 151 [2018-11-23 14:43:11,208 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 14:43:11,208 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 151 states. [2018-11-23 14:43:11,214 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 151 to 151. [2018-11-23 14:43:11,214 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 151 states. [2018-11-23 14:43:11,214 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 151 states to 151 states and 161 transitions. [2018-11-23 14:43:11,215 INFO L78 Accepts]: Start accepts. Automaton has 151 states and 161 transitions. Word has length 117 [2018-11-23 14:43:11,215 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 14:43:11,215 INFO L480 AbstractCegarLoop]: Abstraction has 151 states and 161 transitions. [2018-11-23 14:43:11,215 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 14:43:11,215 INFO L276 IsEmpty]: Start isEmpty. Operand 151 states and 161 transitions. [2018-11-23 14:43:11,216 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 126 [2018-11-23 14:43:11,216 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 14:43:11,216 INFO L402 BasicCegarLoop]: trace histogram [20, 20, 20, 10, 10, 10, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 14:43:11,216 INFO L423 AbstractCegarLoop]: === Iteration 32 === [single_argvErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, single_argvErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr10ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr2ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr15ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr3ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr9ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr5ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr4ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr7ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr8ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr14ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr13ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr12ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr0ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr6ASSERT_VIOLATIONINTEGER_OVERFLOW, mainErr11ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr1ASSERT_VIOLATIONINTEGER_OVERFLOW, dirnameErr0ASSERT_VIOLATIONINTEGER_OVERFLOW]=== [2018-11-23 14:43:11,216 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 14:43:11,216 INFO L82 PathProgramCache]: Analyzing trace with hash 576931341, now seen corresponding path program 10 times [2018-11-23 14:43:11,216 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 14:43:11,217 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 14:43:11,218 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:43:11,218 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 14:43:11,218 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 14:43:12,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 14:43:12,962 WARN L180 SmtUtils]: Spent 118.00 ms on a formula simplification. DAG size of input: 100 DAG size of output: 41 [2018-11-23 14:43:13,094 WARN L180 SmtUtils]: Spent 109.00 ms on a formula simplification. DAG size of input: 99 DAG size of output: 52 [2018-11-23 14:43:13,253 WARN L180 SmtUtils]: Spent 138.00 ms on a formula simplification. DAG size of input: 101 DAG size of output: 50 [2018-11-23 14:43:13,448 WARN L180 SmtUtils]: Spent 150.00 ms on a formula simplification. DAG size of input: 116 DAG size of output: 50 [2018-11-23 14:43:13,626 WARN L180 SmtUtils]: Spent 154.00 ms on a formula simplification. DAG size of input: 100 DAG size of output: 54 [2018-11-23 14:43:13,844 WARN L180 SmtUtils]: Spent 180.00 ms on a formula simplification. DAG size of input: 107 DAG size of output: 54 [2018-11-23 14:43:14,083 WARN L180 SmtUtils]: Spent 165.00 ms on a formula simplification. DAG size of input: 109 DAG size of output: 55 [2018-11-23 14:43:14,241 WARN L180 SmtUtils]: Spent 130.00 ms on a formula simplification. DAG size of input: 96 DAG size of output: 50 [2018-11-23 14:43:14,409 WARN L180 SmtUtils]: Spent 137.00 ms on a formula simplification. DAG size of input: 104 DAG size of output: 50 [2018-11-23 14:43:14,626 WARN L180 SmtUtils]: Spent 146.00 ms on a formula simplification. DAG size of input: 102 DAG size of output: 49 [2018-11-23 14:43:14,851 WARN L180 SmtUtils]: Spent 143.00 ms on a formula simplification. DAG size of input: 108 DAG size of output: 51 [2018-11-23 14:43:15,063 WARN L180 SmtUtils]: Spent 140.00 ms on a formula simplification. DAG size of input: 105 DAG size of output: 50 [2018-11-23 14:43:15,271 WARN L180 SmtUtils]: Spent 136.00 ms on a formula simplification. DAG size of input: 95 DAG size of output: 48 [2018-11-23 14:43:15,987 INFO L134 CoverageAnalysis]: Checked inductivity of 761 backedges. 0 proven. 524 refuted. 0 times theorem prover too weak. 237 trivial. 0 not checked. [2018-11-23 14:43:15,987 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 14:43:15,987 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_bb12028c-b1da-4712-8a45-3e9c572ad540/bin-2019/uautomizer/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 14:43:15,995 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-23 14:43:16,136 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-23 14:43:16,137 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 14:43:16,145 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 14:43:16,153 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 141 treesize of output 131 [2018-11-23 14:43:16,164 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:16,187 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 131 treesize of output 125 [2018-11-23 14:43:16,195 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:16,207 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:16,213 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 121 treesize of output 119 [2018-11-23 14:43:16,217 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 113 treesize of output 107 [2018-11-23 14:43:16,339 WARN L180 SmtUtils]: Spent 120.00 ms on a formula simplification. DAG size of input: 44 DAG size of output: 42 [2018-11-23 14:43:16,345 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:16,348 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:16,351 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:16,377 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:16,378 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 6 disjoint index pairs (out of 6 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 93 treesize of output 112 [2018-11-23 14:43:16,487 WARN L180 SmtUtils]: Spent 107.00 ms on a formula simplification. DAG size of input: 52 DAG size of output: 42 [2018-11-23 14:43:16,493 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:16,496 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:16,499 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:16,501 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:16,511 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:16,523 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:16,526 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:16,532 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:16,533 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 11 disjoint index pairs (out of 15 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 83 treesize of output 123 [2018-11-23 14:43:16,584 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:16,584 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:16,586 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:16,587 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:16,589 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:16,590 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:16,590 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:16,591 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:16,592 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:16,593 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:16,594 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 17 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 71 treesize of output 138 [2018-11-23 14:43:16,619 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 17 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 71 treesize of output 132 [2018-11-23 14:43:16,655 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 17 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 65 treesize of output 126 [2018-11-23 14:43:16,704 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 26 disjoint index pairs (out of 36 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 55 treesize of output 157 [2018-11-23 14:43:16,722 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 10 select indices, 10 select index equivalence classes, 26 disjoint index pairs (out of 45 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 57 treesize of output 154 [2018-11-23 14:43:16,722 INFO L267 ElimStorePlain]: Start of recursive call 12: End of recursive call: and 1 xjuncts. [2018-11-23 14:43:16,765 INFO L267 ElimStorePlain]: Start of recursive call 11: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:16,806 INFO L267 ElimStorePlain]: Start of recursive call 10: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:16,848 INFO L267 ElimStorePlain]: Start of recursive call 9: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:16,892 INFO L267 ElimStorePlain]: Start of recursive call 8: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:16,936 INFO L267 ElimStorePlain]: Start of recursive call 7: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:16,980 INFO L267 ElimStorePlain]: Start of recursive call 6: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:17,026 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:17,104 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:17,106 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:17,109 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:17,141 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 111 treesize of output 113 [2018-11-23 14:43:17,484 WARN L180 SmtUtils]: Spent 341.00 ms on a formula simplification. DAG size of input: 71 DAG size of output: 71 [2018-11-23 14:43:17,491 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:17,494 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:17,498 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:17,517 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:17,531 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:17,539 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:17,551 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:17,577 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 8 disjoint index pairs (out of 10 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 102 treesize of output 129 [2018-11-23 14:43:17,972 WARN L180 SmtUtils]: Spent 394.00 ms on a formula simplification. DAG size of input: 87 DAG size of output: 75 [2018-11-23 14:43:17,978 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:17,980 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:17,988 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:17,991 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:17,998 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:18,000 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:18,012 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:18,016 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:18,035 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:18,038 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:18,042 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:18,046 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:18,061 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:18,083 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 14 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 92 treesize of output 141 [2018-11-23 14:43:18,548 WARN L180 SmtUtils]: Spent 464.00 ms on a formula simplification. DAG size of input: 97 DAG size of output: 81 [2018-11-23 14:43:18,557 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:18,560 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:18,562 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:18,570 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:18,572 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:18,582 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:18,584 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:18,587 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:18,598 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:18,600 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:18,603 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:18,610 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:18,613 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:18,623 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:18,626 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:18,633 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:18,653 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 8 select indices, 8 select index equivalence classes, 21 disjoint index pairs (out of 28 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 96 treesize of output 160 [2018-11-23 14:43:18,677 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 16 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 154 treesize of output 148 [2018-11-23 14:43:18,716 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 16 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 65 treesize of output 118 [2018-11-23 14:43:18,772 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:18,778 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:18,786 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:18,790 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:18,796 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:18,798 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:18,799 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:18,800 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:18,807 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:18,808 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 25 disjoint index pairs (out of 36 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 55 treesize of output 159 [2018-11-23 14:43:18,835 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 10 select indices, 10 select index equivalence classes, 25 disjoint index pairs (out of 45 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 63 treesize of output 154 [2018-11-23 14:43:18,836 INFO L267 ElimStorePlain]: Start of recursive call 20: End of recursive call: and 1 xjuncts. [2018-11-23 14:43:18,886 INFO L267 ElimStorePlain]: Start of recursive call 19: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:18,931 INFO L267 ElimStorePlain]: Start of recursive call 18: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:19,001 INFO L267 ElimStorePlain]: Start of recursive call 17: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:19,125 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:19,128 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:19,134 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:19,139 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:19,145 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:19,149 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:19,157 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:19,159 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:19,162 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:19,167 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:19,174 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:19,179 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:19,181 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:19,198 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 8 select indices, 8 select index equivalence classes, 22 disjoint index pairs (out of 28 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 106 treesize of output 158 [2018-11-23 14:43:19,235 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 16 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 152 treesize of output 145 [2018-11-23 14:43:19,351 WARN L180 SmtUtils]: Spent 114.00 ms on a formula simplification. DAG size of input: 81 DAG size of output: 69 [2018-11-23 14:43:19,356 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:19,361 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:19,369 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:19,373 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:19,378 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:19,380 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:19,381 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:19,382 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:19,388 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:19,388 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 25 disjoint index pairs (out of 36 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 55 treesize of output 159 [2018-11-23 14:43:19,406 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 10 select indices, 10 select index equivalence classes, 25 disjoint index pairs (out of 45 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 63 treesize of output 154 [2018-11-23 14:43:19,407 INFO L267 ElimStorePlain]: Start of recursive call 24: End of recursive call: and 1 xjuncts. [2018-11-23 14:43:19,448 INFO L267 ElimStorePlain]: Start of recursive call 23: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:19,492 INFO L267 ElimStorePlain]: Start of recursive call 22: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:19,614 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:19,621 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:19,630 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:19,641 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:19,646 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:19,648 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:19,650 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:19,665 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:19,677 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 8 select indices, 8 select index equivalence classes, 23 disjoint index pairs (out of 28 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 124 treesize of output 155 [2018-11-23 14:43:19,993 WARN L180 SmtUtils]: Spent 314.00 ms on a formula simplification. DAG size of input: 109 DAG size of output: 109 [2018-11-23 14:43:19,996 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:19,998 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:20,000 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:20,002 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:20,004 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:20,006 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:20,006 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:20,007 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:20,010 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:20,011 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 32 disjoint index pairs (out of 36 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 150 treesize of output 218 [2018-11-23 14:43:20,025 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 10 select indices, 10 select index equivalence classes, 32 disjoint index pairs (out of 45 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 63 treesize of output 182 [2018-11-23 14:43:20,025 INFO L267 ElimStorePlain]: Start of recursive call 27: End of recursive call: and 1 xjuncts. [2018-11-23 14:43:20,104 INFO L267 ElimStorePlain]: Start of recursive call 26: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:20,225 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:20,226 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:20,233 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:20,236 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:20,240 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:20,244 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:20,246 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:20,249 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:20,251 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:20,252 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:20,255 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:20,256 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:20,258 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:20,261 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:20,263 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:20,265 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:20,268 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:20,275 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 10 select indices, 10 select index equivalence classes, 33 disjoint index pairs (out of 45 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 124 treesize of output 200 [2018-11-23 14:43:20,300 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 11 select indices, 11 select index equivalence classes, 34 disjoint index pairs (out of 55 index pairs), introduced 0 new quantified variables, introduced 2 case distinctions, treesize of input 196 treesize of output 192 [2018-11-23 14:43:20,301 INFO L267 ElimStorePlain]: Start of recursive call 29: End of recursive call: and 2 xjuncts. [2018-11-23 14:43:20,554 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:20,555 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:20,558 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:20,562 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:20,564 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:20,566 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:20,567 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:20,568 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:20,569 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:20,570 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:20,571 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 10 select indices, 10 select index equivalence classes, 33 disjoint index pairs (out of 45 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 152 treesize of output 220 [2018-11-23 14:43:20,572 INFO L267 ElimStorePlain]: Start of recursive call 30: End of recursive call: and 1 xjuncts. [2018-11-23 14:43:20,778 INFO L267 ElimStorePlain]: Start of recursive call 28: 2 dim-1 vars, End of recursive call: and 3 xjuncts. [2018-11-23 14:43:21,060 INFO L267 ElimStorePlain]: Start of recursive call 25: 2 dim-1 vars, End of recursive call: and 4 xjuncts. [2018-11-23 14:43:21,363 INFO L267 ElimStorePlain]: Start of recursive call 21: 2 dim-1 vars, End of recursive call: and 5 xjuncts. [2018-11-23 14:43:21,706 INFO L267 ElimStorePlain]: Start of recursive call 16: 2 dim-1 vars, End of recursive call: and 6 xjuncts. [2018-11-23 14:43:22,106 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:22,109 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:22,116 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:22,128 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:22,131 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:22,140 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:22,143 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:22,146 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:22,153 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:22,155 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:22,158 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:22,159 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 16 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 94 treesize of output 146 [2018-11-23 14:43:22,180 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 16 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 71 treesize of output 128 [2018-11-23 14:43:22,208 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 16 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 65 treesize of output 122 [2018-11-23 14:43:22,287 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 25 disjoint index pairs (out of 36 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 55 treesize of output 153 [2018-11-23 14:43:22,304 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 10 select indices, 10 select index equivalence classes, 25 disjoint index pairs (out of 45 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 57 treesize of output 150 [2018-11-23 14:43:22,304 INFO L267 ElimStorePlain]: Start of recursive call 35: End of recursive call: and 1 xjuncts. [2018-11-23 14:43:22,344 INFO L267 ElimStorePlain]: Start of recursive call 34: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:22,384 INFO L267 ElimStorePlain]: Start of recursive call 33: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:22,423 INFO L267 ElimStorePlain]: Start of recursive call 32: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:22,473 INFO L267 ElimStorePlain]: Start of recursive call 31: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:22,895 INFO L267 ElimStorePlain]: Start of recursive call 15: 2 dim-1 vars, End of recursive call: and 7 xjuncts. [2018-11-23 14:43:23,344 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:23,347 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:23,349 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:23,351 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:23,358 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:23,365 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:23,373 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:23,376 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:23,378 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:23,379 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 13 disjoint index pairs (out of 15 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 102 treesize of output 143 [2018-11-23 14:43:23,549 WARN L180 SmtUtils]: Spent 168.00 ms on a formula simplification. DAG size of input: 72 DAG size of output: 54 [2018-11-23 14:43:23,554 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:23,557 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:23,564 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:23,570 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:23,572 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:23,579 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:23,582 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:23,584 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:23,587 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:23,589 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:23,591 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:23,592 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 19 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 71 treesize of output 146 [2018-11-23 14:43:23,606 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 19 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 71 treesize of output 140 [2018-11-23 14:43:23,637 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 19 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 65 treesize of output 134 [2018-11-23 14:43:23,727 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 28 disjoint index pairs (out of 36 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 55 treesize of output 165 [2018-11-23 14:43:23,741 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 10 select indices, 10 select index equivalence classes, 28 disjoint index pairs (out of 45 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 57 treesize of output 162 [2018-11-23 14:43:23,742 INFO L267 ElimStorePlain]: Start of recursive call 41: End of recursive call: and 1 xjuncts. [2018-11-23 14:43:23,786 INFO L267 ElimStorePlain]: Start of recursive call 40: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:23,830 INFO L267 ElimStorePlain]: Start of recursive call 39: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:23,875 INFO L267 ElimStorePlain]: Start of recursive call 38: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:23,922 INFO L267 ElimStorePlain]: Start of recursive call 37: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:23,973 INFO L267 ElimStorePlain]: Start of recursive call 36: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:24,409 INFO L267 ElimStorePlain]: Start of recursive call 14: 2 dim-1 vars, End of recursive call: and 8 xjuncts. [2018-11-23 14:43:24,928 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:24,931 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:24,934 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:24,955 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:24,955 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 7 disjoint index pairs (out of 6 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 108 treesize of output 127 [2018-11-23 14:43:25,097 WARN L180 SmtUtils]: Spent 140.00 ms on a formula simplification. DAG size of input: 59 DAG size of output: 45 [2018-11-23 14:43:25,103 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:25,106 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:25,109 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:25,112 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:25,135 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:25,142 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:25,149 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:25,151 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:25,158 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:25,159 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 12 disjoint index pairs (out of 15 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 83 treesize of output 127 [2018-11-23 14:43:25,304 WARN L180 SmtUtils]: Spent 144.00 ms on a formula simplification. DAG size of input: 64 DAG size of output: 52 [2018-11-23 14:43:25,309 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:25,316 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:25,322 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:25,324 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:25,330 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:25,333 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:25,335 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:25,342 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:25,344 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:25,346 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:25,347 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 18 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 71 treesize of output 142 [2018-11-23 14:43:25,364 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 18 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 71 treesize of output 136 [2018-11-23 14:43:25,397 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 18 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 65 treesize of output 130 [2018-11-23 14:43:25,479 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 27 disjoint index pairs (out of 36 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 55 treesize of output 161 [2018-11-23 14:43:25,496 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 10 select indices, 10 select index equivalence classes, 27 disjoint index pairs (out of 45 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 57 treesize of output 158 [2018-11-23 14:43:25,497 INFO L267 ElimStorePlain]: Start of recursive call 48: End of recursive call: and 1 xjuncts. [2018-11-23 14:43:25,540 INFO L267 ElimStorePlain]: Start of recursive call 47: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:25,583 INFO L267 ElimStorePlain]: Start of recursive call 46: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:25,626 INFO L267 ElimStorePlain]: Start of recursive call 45: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:25,671 INFO L267 ElimStorePlain]: Start of recursive call 44: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:25,718 INFO L267 ElimStorePlain]: Start of recursive call 43: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:25,767 INFO L267 ElimStorePlain]: Start of recursive call 42: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:26,251 INFO L267 ElimStorePlain]: Start of recursive call 13: 2 dim-1 vars, End of recursive call: and 9 xjuncts. [2018-11-23 14:43:26,780 INFO L267 ElimStorePlain]: Start of recursive call 4: 2 dim-1 vars, End of recursive call: and 10 xjuncts. [2018-11-23 14:43:27,408 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 119 treesize of output 109 [2018-11-23 14:43:27,425 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 106 treesize of output 96 [2018-11-23 14:43:27,439 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:27,440 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:27,441 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:27,445 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:27,446 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 5 disjoint index pairs (out of 6 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 93 treesize of output 108 [2018-11-23 14:43:27,550 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:27,553 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:27,556 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:27,564 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:27,574 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:27,586 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:27,589 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:27,596 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:27,597 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 10 disjoint index pairs (out of 15 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 83 treesize of output 119 [2018-11-23 14:43:27,738 WARN L180 SmtUtils]: Spent 140.00 ms on a formula simplification. DAG size of input: 60 DAG size of output: 48 [2018-11-23 14:43:27,744 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:27,750 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:27,760 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:27,763 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:27,774 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:27,777 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:27,779 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:27,786 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:27,788 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:27,790 INFO L701 Elim1Store]: detected not equals via solver [2018-11-23 14:43:27,790 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 16 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 71 treesize of output 134 [2018-11-23 14:43:27,813 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 16 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 71 treesize of output 128 [2018-11-23 14:43:27,854 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 16 disjoint index pairs (out of 21 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 65 treesize of output 122 [2018-11-23 14:43:27,933 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 25 disjoint index pairs (out of 36 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 55 treesize of output 153 [2018-11-23 14:43:27,950 INFO L478 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 10 select indices, 10 select index equivalence classes, 25 disjoint index pairs (out of 45 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 57 treesize of output 150 [2018-11-23 14:43:27,951 INFO L267 ElimStorePlain]: Start of recursive call 57: End of recursive call: and 1 xjuncts. [2018-11-23 14:43:27,990 INFO L267 ElimStorePlain]: Start of recursive call 56: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:28,030 INFO L267 ElimStorePlain]: Start of recursive call 55: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:28,071 INFO L267 ElimStorePlain]: Start of recursive call 54: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:28,113 INFO L267 ElimStorePlain]: Start of recursive call 53: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:28,156 INFO L267 ElimStorePlain]: Start of recursive call 52: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:28,202 INFO L267 ElimStorePlain]: Start of recursive call 51: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:28,252 INFO L267 ElimStorePlain]: Start of recursive call 50: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:28,303 INFO L267 ElimStorePlain]: Start of recursive call 49: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-11-23 14:43:28,903 INFO L267 ElimStorePlain]: Start of recursive call 3: 2 dim-1 vars, End of recursive call: and 11 xjuncts. [2018-11-23 14:43:29,476 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 11 xjuncts. [2018-11-23 14:43:30,077 INFO L267 ElimStorePlain]: Start of recursive call 1: 9 dim-0 vars, 1 dim-1 vars, End of recursive call: 90 dim-0 vars, and 11 xjuncts. [2018-11-23 14:43:30,078 INFO L202 ElimStorePlain]: Needed 57 recursive calls to eliminate 10 variables, input treesize:151, output treesize:1736 [2018-11-23 14:43:51,658 WARN L194 Executor]: External (z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000) stderr output: (error "out of memory") [2018-11-23 14:43:51,859 WARN L521 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 15 z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 14:43:51,859 FATAL L265 ToolchainWalker]: An unrecoverable error occured during an interaction with an SMT solver: de.uni_freiburg.informatik.ultimate.logic.SMTLIBException: External (z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000)Received EOF on stdin. stderr output: (error "out of memory") at de.uni_freiburg.informatik.ultimate.smtsolver.external.Executor.parse(Executor.java:208) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Executor.parseCheckSatResult(Executor.java:225) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Scriptor.checkSat(Scriptor.java:155) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.WrapperScript.checkSat(WrapperScript.java:116) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.WrapperScript.checkSat(WrapperScript.java:116) at de.uni_freiburg.informatik.ultimate.logic.Util.checkSat(Util.java:61) at de.uni_freiburg.informatik.ultimate.logic.simplification.SimplifyDDA.getRedundancy(SimplifyDDA.java:626) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.SimplifyDDAWithTimeout.getRedundancy(SimplifyDDAWithTimeout.java:122) at de.uni_freiburg.informatik.ultimate.logic.simplification.SimplifyDDA$Simplifier.walk(SimplifyDDA.java:371) at de.uni_freiburg.informatik.ultimate.logic.NonRecursive.run(NonRecursive.java:122) at de.uni_freiburg.informatik.ultimate.logic.NonRecursive.run(NonRecursive.java:113) at de.uni_freiburg.informatik.ultimate.logic.simplification.SimplifyDDA.simplifyOnce(SimplifyDDA.java:650) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.SimplifyDDAWithTimeout.getSimplifiedTerm(SimplifyDDAWithTimeout.java:187) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.SmtUtils.simplify(SmtUtils.java:151) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate(PredicateUnifier.java:354) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate(PredicateUnifier.java:299) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.TraceCheckSpWp$UnifyPostprocessor.postprocess(TraceCheckSpWp.java:575) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.predicates.IterativePredicateTransformer.applyPostprocessors(IterativePredicateTransformer.java:439) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.predicates.IterativePredicateTransformer.computeStrongestPostconditionSequence(IterativePredicateTransformer.java:200) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.TraceCheckSpWp.computeInterpolantsUsingUnsatCore(TraceCheckSpWp.java:286) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.TraceCheckSpWp.computeInterpolants(TraceCheckSpWp.java:175) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.TraceCheckSpWp.(TraceCheckSpWp.java:162) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.TraceCheckConstructor.constructForwardBackward(TraceCheckConstructor.java:224) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.TraceCheckConstructor.constructTraceCheck(TraceCheckConstructor.java:188) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.TraceCheckConstructor.get(TraceCheckConstructor.java:165) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.MultiTrackRefinementStrategy.getTraceCheck(MultiTrackRefinementStrategy.java:232) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.BaseRefinementStrategy.checkFeasibility(BaseRefinementStrategy.java:223) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.BaseRefinementStrategy.executeStrategy(BaseRefinementStrategy.java:197) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.TraceAbstractionRefinementEngine.(TraceAbstractionRefinementEngine.java:70) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.BasicCegarLoop.isCounterexampleFeasible(BasicCegarLoop.java:456) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.AbstractCegarLoop.iterateInternal(AbstractCegarLoop.java:434) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.AbstractCegarLoop.iterate(AbstractCegarLoop.java:376) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.iterate(TraceAbstractionStarter.java:334) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.runCegarLoops(TraceAbstractionStarter.java:174) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.(TraceAbstractionStarter.java:126) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver.finish(TraceAbstractionObserver.java:123) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runObserver(PluginConnector.java:168) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runTool(PluginConnector.java:151) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.run(PluginConnector.java:128) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.executePluginConnector(ToolchainWalker.java:232) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.processPlugin(ToolchainWalker.java:226) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walkUnprotected(ToolchainWalker.java:142) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walk(ToolchainWalker.java:104) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainManager$Toolchain.processToolchain(ToolchainManager.java:316) at de.uni_freiburg.informatik.ultimate.core.coreplugin.toolchain.DefaultToolchainJob.run(DefaultToolchainJob.java:145) at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) Caused by: de.uni_freiburg.informatik.ultimate.logic.SMTLIBException: EOF at de.uni_freiburg.informatik.ultimate.smtsolver.external.Parser$Action$.CUP$do_action(Parser.java:1427) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Parser.do_action(Parser.java:630) at com.github.jhoenicke.javacup.runtime.LRParser.parse(LRParser.java:419) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Executor.parse(Executor.java:205) ... 45 more [2018-11-23 14:43:51,862 INFO L168 Benchmark]: Toolchain (without parser) took 94217.98 ms. Allocated memory was 1.0 GB in the beginning and 1.8 GB in the end (delta: 744.5 MB). Free memory was 957.6 MB in the beginning and 1.5 GB in the end (delta: -529.5 MB). Peak memory consumption was 214.9 MB. Max. memory is 11.5 GB. [2018-11-23 14:43:51,863 INFO L168 Benchmark]: CDTParser took 0.10 ms. Allocated memory is still 1.0 GB. Free memory is still 985.6 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-23 14:43:51,863 INFO L168 Benchmark]: CACSL2BoogieTranslator took 694.24 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 139.5 MB). Free memory was 957.6 MB in the beginning and 1.1 GB in the end (delta: -104.7 MB). Peak memory consumption was 48.7 MB. Max. memory is 11.5 GB. [2018-11-23 14:43:51,863 INFO L168 Benchmark]: Boogie Procedure Inliner took 39.96 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. [2018-11-23 14:43:51,863 INFO L168 Benchmark]: Boogie Preprocessor took 53.17 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. [2018-11-23 14:43:51,863 INFO L168 Benchmark]: RCFGBuilder took 694.15 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 970.1 MB in the end (delta: 84.2 MB). Peak memory consumption was 84.2 MB. Max. memory is 11.5 GB. [2018-11-23 14:43:51,863 INFO L168 Benchmark]: TraceAbstraction took 92733.27 ms. Allocated memory was 1.2 GB in the beginning and 1.8 GB in the end (delta: 605.0 MB). Free memory was 970.1 MB in the beginning and 1.5 GB in the end (delta: -517.0 MB). Peak memory consumption was 88.0 MB. Max. memory is 11.5 GB. [2018-11-23 14:43:51,864 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.10 ms. Allocated memory is still 1.0 GB. Free memory is still 985.6 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 694.24 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 139.5 MB). Free memory was 957.6 MB in the beginning and 1.1 GB in the end (delta: -104.7 MB). Peak memory consumption was 48.7 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 39.96 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 53.17 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 5.4 MB). Peak memory consumption was 5.4 MB. Max. memory is 11.5 GB. * RCFGBuilder took 694.15 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 970.1 MB in the end (delta: 84.2 MB). Peak memory consumption was 84.2 MB. Max. memory is 11.5 GB. * TraceAbstraction took 92733.27 ms. Allocated memory was 1.2 GB in the beginning and 1.8 GB in the end (delta: 605.0 MB). Free memory was 970.1 MB in the beginning and 1.5 GB in the end (delta: -517.0 MB). Peak memory consumption was 88.0 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - ExceptionOrErrorResult: SMTLIBException: External (z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000)Received EOF on stdin. stderr output: (error "out of memory") de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: SMTLIBException: External (z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000)Received EOF on stdin. stderr output: (error "out of memory") : de.uni_freiburg.informatik.ultimate.smtsolver.external.Executor.parse(Executor.java:208) RESULT: Ultimate could not prove your program: Toolchain returned no result. Received shutdown request...