./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/bitvector/interleave_bits_true-unreach-call_true-no-overflow.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version aa418289 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_0bcc5560-9368-4d8a-9bff-77d43d0a8e71/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_0bcc5560-9368-4d8a-9bff-77d43d0a8e71/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_0bcc5560-9368-4d8a-9bff-77d43d0a8e71/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_0bcc5560-9368-4d8a-9bff-77d43d0a8e71/bin-2019/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/bitvector/interleave_bits_true-unreach-call_true-no-overflow.i -s /tmp/vcloud-vcloud-master/worker/working_dir_0bcc5560-9368-4d8a-9bff-77d43d0a8e71/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_0bcc5560-9368-4d8a-9bff-77d43d0a8e71/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash a69112b8d023c6203418abb04301ebe890b3a5f5 ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................. Execution finished normally Using bit-precise analysis Retrying with bit-precise analysis Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_0bcc5560-9368-4d8a-9bff-77d43d0a8e71/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_0bcc5560-9368-4d8a-9bff-77d43d0a8e71/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_0bcc5560-9368-4d8a-9bff-77d43d0a8e71/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_0bcc5560-9368-4d8a-9bff-77d43d0a8e71/bin-2019/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/bitvector/interleave_bits_true-unreach-call_true-no-overflow.i -s /tmp/vcloud-vcloud-master/worker/working_dir_0bcc5560-9368-4d8a-9bff-77d43d0a8e71/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Bitvector.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_0bcc5560-9368-4d8a-9bff-77d43d0a8e71/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash a69112b8d023c6203418abb04301ebe890b3a5f5 ........................................................................................................................................................................................................................................................................................................................................................................................................................................................ Execution finished normally Writing output log to file Ultimate.log Result: TRUE --- Real Ultimate output --- This is Ultimate 0.1.23-aa41828 [2018-11-23 05:32:31,135 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-23 05:32:31,136 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-23 05:32:31,142 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-23 05:32:31,143 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-23 05:32:31,143 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-23 05:32:31,144 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-23 05:32:31,145 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-23 05:32:31,146 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-23 05:32:31,147 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-23 05:32:31,148 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-23 05:32:31,148 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-23 05:32:31,148 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-23 05:32:31,149 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-23 05:32:31,149 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-23 05:32:31,150 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-23 05:32:31,150 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-23 05:32:31,151 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-23 05:32:31,152 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-23 05:32:31,153 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-23 05:32:31,154 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-23 05:32:31,155 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-23 05:32:31,156 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-23 05:32:31,157 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-23 05:32:31,157 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-23 05:32:31,157 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-23 05:32:31,158 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-23 05:32:31,158 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-23 05:32:31,159 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-23 05:32:31,160 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-23 05:32:31,160 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-23 05:32:31,160 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-23 05:32:31,160 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-23 05:32:31,161 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-23 05:32:31,161 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-23 05:32:31,162 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-23 05:32:31,162 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_0bcc5560-9368-4d8a-9bff-77d43d0a8e71/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Default.epf [2018-11-23 05:32:31,169 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-23 05:32:31,169 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-23 05:32:31,169 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-23 05:32:31,170 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-11-23 05:32:31,170 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-23 05:32:31,170 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-23 05:32:31,170 INFO L133 SettingsManager]: * Use SBE=true [2018-11-23 05:32:31,170 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-23 05:32:31,171 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-23 05:32:31,171 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-23 05:32:31,171 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-23 05:32:31,171 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-23 05:32:31,171 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-23 05:32:31,171 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-23 05:32:31,171 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-23 05:32:31,172 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-23 05:32:31,172 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-23 05:32:31,172 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-23 05:32:31,172 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-23 05:32:31,172 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-23 05:32:31,172 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-23 05:32:31,172 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-23 05:32:31,172 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-23 05:32:31,173 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 05:32:31,173 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-23 05:32:31,173 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-23 05:32:31,173 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-23 05:32:31,173 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-23 05:32:31,173 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-23 05:32:31,173 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-11-23 05:32:31,174 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_0bcc5560-9368-4d8a-9bff-77d43d0a8e71/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> a69112b8d023c6203418abb04301ebe890b3a5f5 [2018-11-23 05:32:31,196 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-23 05:32:31,204 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-23 05:32:31,207 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-23 05:32:31,208 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-23 05:32:31,208 INFO L276 PluginConnector]: CDTParser initialized [2018-11-23 05:32:31,209 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_0bcc5560-9368-4d8a-9bff-77d43d0a8e71/bin-2019/uautomizer/../../sv-benchmarks/c/bitvector/interleave_bits_true-unreach-call_true-no-overflow.i [2018-11-23 05:32:31,248 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_0bcc5560-9368-4d8a-9bff-77d43d0a8e71/bin-2019/uautomizer/data/6bd0e010a/342d6c516fc847d0bf4f21c39a69f884/FLAGcbb318fc1 [2018-11-23 05:32:31,585 INFO L307 CDTParser]: Found 1 translation units. [2018-11-23 05:32:31,585 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_0bcc5560-9368-4d8a-9bff-77d43d0a8e71/sv-benchmarks/c/bitvector/interleave_bits_true-unreach-call_true-no-overflow.i [2018-11-23 05:32:31,589 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_0bcc5560-9368-4d8a-9bff-77d43d0a8e71/bin-2019/uautomizer/data/6bd0e010a/342d6c516fc847d0bf4f21c39a69f884/FLAGcbb318fc1 [2018-11-23 05:32:32,009 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_0bcc5560-9368-4d8a-9bff-77d43d0a8e71/bin-2019/uautomizer/data/6bd0e010a/342d6c516fc847d0bf4f21c39a69f884 [2018-11-23 05:32:32,012 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-23 05:32:32,013 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-23 05:32:32,014 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-23 05:32:32,014 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-23 05:32:32,017 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-23 05:32:32,018 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 05:32:32" (1/1) ... [2018-11-23 05:32:32,021 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@32768438 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:32:32, skipping insertion in model container [2018-11-23 05:32:32,021 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 05:32:32" (1/1) ... [2018-11-23 05:32:32,029 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-23 05:32:32,042 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-23 05:32:32,146 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 05:32:32,148 INFO L191 MainTranslator]: Completed pre-run [2018-11-23 05:32:32,162 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 05:32:32,171 INFO L195 MainTranslator]: Completed translation [2018-11-23 05:32:32,171 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:32:32 WrapperNode [2018-11-23 05:32:32,171 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-23 05:32:32,171 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-23 05:32:32,172 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-23 05:32:32,172 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-23 05:32:32,176 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:32:32" (1/1) ... [2018-11-23 05:32:32,181 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:32:32" (1/1) ... [2018-11-23 05:32:32,184 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-23 05:32:32,185 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-23 05:32:32,185 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-23 05:32:32,185 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-23 05:32:32,190 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:32:32" (1/1) ... [2018-11-23 05:32:32,190 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:32:32" (1/1) ... [2018-11-23 05:32:32,191 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:32:32" (1/1) ... [2018-11-23 05:32:32,191 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:32:32" (1/1) ... [2018-11-23 05:32:32,194 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:32:32" (1/1) ... [2018-11-23 05:32:32,231 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:32:32" (1/1) ... [2018-11-23 05:32:32,231 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:32:32" (1/1) ... [2018-11-23 05:32:32,232 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-23 05:32:32,233 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-23 05:32:32,233 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-23 05:32:32,233 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-23 05:32:32,233 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:32:32" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0bcc5560-9368-4d8a-9bff-77d43d0a8e71/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 05:32:32,269 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-23 05:32:32,269 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-23 05:32:32,269 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-23 05:32:32,269 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-23 05:32:32,269 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-23 05:32:32,270 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-23 05:32:32,270 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2018-11-23 05:32:32,270 INFO L138 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2018-11-23 05:32:32,361 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-23 05:32:32,361 INFO L280 CfgBuilder]: Removed 1 assue(true) statements. [2018-11-23 05:32:32,361 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 05:32:32 BoogieIcfgContainer [2018-11-23 05:32:32,362 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-23 05:32:32,362 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-23 05:32:32,362 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-23 05:32:32,364 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-23 05:32:32,364 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 23.11 05:32:32" (1/3) ... [2018-11-23 05:32:32,365 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@239fa148 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 05:32:32, skipping insertion in model container [2018-11-23 05:32:32,365 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:32:32" (2/3) ... [2018-11-23 05:32:32,365 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@239fa148 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 05:32:32, skipping insertion in model container [2018-11-23 05:32:32,365 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 05:32:32" (3/3) ... [2018-11-23 05:32:32,366 INFO L112 eAbstractionObserver]: Analyzing ICFG interleave_bits_true-unreach-call_true-no-overflow.i [2018-11-23 05:32:32,372 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-23 05:32:32,376 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-11-23 05:32:32,389 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-11-23 05:32:32,413 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-23 05:32:32,414 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-23 05:32:32,414 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-23 05:32:32,414 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-23 05:32:32,414 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-23 05:32:32,414 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-23 05:32:32,414 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-23 05:32:32,415 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-23 05:32:32,415 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-23 05:32:32,427 INFO L276 IsEmpty]: Start isEmpty. Operand 18 states. [2018-11-23 05:32:32,431 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2018-11-23 05:32:32,431 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:32:32,431 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:32:32,432 INFO L423 AbstractCegarLoop]: === Iteration 1 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:32:32,436 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:32:32,436 INFO L82 PathProgramCache]: Analyzing trace with hash -480905734, now seen corresponding path program 1 times [2018-11-23 05:32:32,437 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 05:32:32,437 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 05:32:32,473 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:32:32,473 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:32:32,473 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:32:32,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:32:32,566 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:32:32,568 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 05:32:32,568 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 05:32:32,572 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 05:32:32,583 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 05:32:32,584 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 05:32:32,585 INFO L87 Difference]: Start difference. First operand 18 states. Second operand 3 states. [2018-11-23 05:32:32,602 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:32:32,602 INFO L93 Difference]: Finished difference Result 31 states and 36 transitions. [2018-11-23 05:32:32,603 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 05:32:32,603 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 11 [2018-11-23 05:32:32,604 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:32:32,608 INFO L225 Difference]: With dead ends: 31 [2018-11-23 05:32:32,608 INFO L226 Difference]: Without dead ends: 13 [2018-11-23 05:32:32,610 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 05:32:32,621 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13 states. [2018-11-23 05:32:32,630 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13 to 13. [2018-11-23 05:32:32,631 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13 states. [2018-11-23 05:32:32,631 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 13 transitions. [2018-11-23 05:32:32,633 INFO L78 Accepts]: Start accepts. Automaton has 13 states and 13 transitions. Word has length 11 [2018-11-23 05:32:32,633 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:32:32,633 INFO L480 AbstractCegarLoop]: Abstraction has 13 states and 13 transitions. [2018-11-23 05:32:32,633 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 05:32:32,633 INFO L276 IsEmpty]: Start isEmpty. Operand 13 states and 13 transitions. [2018-11-23 05:32:32,634 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2018-11-23 05:32:32,634 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:32:32,634 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:32:32,634 INFO L423 AbstractCegarLoop]: === Iteration 2 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:32:32,634 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:32:32,635 INFO L82 PathProgramCache]: Analyzing trace with hash -436122843, now seen corresponding path program 1 times [2018-11-23 05:32:32,635 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 05:32:32,635 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 05:32:32,636 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:32:32,636 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:32:32,636 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:32:32,644 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:32:32,704 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:32:32,706 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 05:32:32,706 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0bcc5560-9368-4d8a-9bff-77d43d0a8e71/bin-2019/uautomizer/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 05:32:32,721 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:32:32,733 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:32:32,738 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:32:32,772 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:32:32,786 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:32:32,787 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 5 [2018-11-23 05:32:32,787 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-23 05:32:32,787 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-23 05:32:32,787 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-23 05:32:32,788 INFO L87 Difference]: Start difference. First operand 13 states and 13 transitions. Second operand 5 states. [2018-11-23 05:32:32,798 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:32:32,798 INFO L93 Difference]: Finished difference Result 20 states and 20 transitions. [2018-11-23 05:32:32,798 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-11-23 05:32:32,799 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 12 [2018-11-23 05:32:32,799 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:32:32,799 INFO L225 Difference]: With dead ends: 20 [2018-11-23 05:32:32,799 INFO L226 Difference]: Without dead ends: 14 [2018-11-23 05:32:32,800 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 11 SyntacticMatches, 1 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-11-23 05:32:32,800 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14 states. [2018-11-23 05:32:32,802 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14 to 14. [2018-11-23 05:32:32,802 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14 states. [2018-11-23 05:32:32,803 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14 states to 14 states and 14 transitions. [2018-11-23 05:32:32,803 INFO L78 Accepts]: Start accepts. Automaton has 14 states and 14 transitions. Word has length 12 [2018-11-23 05:32:32,803 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:32:32,803 INFO L480 AbstractCegarLoop]: Abstraction has 14 states and 14 transitions. [2018-11-23 05:32:32,803 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-23 05:32:32,803 INFO L276 IsEmpty]: Start isEmpty. Operand 14 states and 14 transitions. [2018-11-23 05:32:32,803 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2018-11-23 05:32:32,803 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:32:32,804 INFO L402 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:32:32,804 INFO L423 AbstractCegarLoop]: === Iteration 3 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:32:32,804 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:32:32,804 INFO L82 PathProgramCache]: Analyzing trace with hash 952146778, now seen corresponding path program 2 times [2018-11-23 05:32:32,804 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 05:32:32,804 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 05:32:32,805 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:32:32,805 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:32:32,805 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:32:32,811 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:32:32,882 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:32:32,882 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 05:32:32,882 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0bcc5560-9368-4d8a-9bff-77d43d0a8e71/bin-2019/uautomizer/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 05:32:32,891 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-23 05:32:32,899 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-23 05:32:32,899 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 05:32:32,901 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:32:32,926 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:32:32,941 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:32:32,941 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5] total 6 [2018-11-23 05:32:32,942 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 05:32:32,942 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 05:32:32,942 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2018-11-23 05:32:32,942 INFO L87 Difference]: Start difference. First operand 14 states and 14 transitions. Second operand 6 states. [2018-11-23 05:32:32,974 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:32:32,975 INFO L93 Difference]: Finished difference Result 21 states and 21 transitions. [2018-11-23 05:32:32,975 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-11-23 05:32:32,975 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 13 [2018-11-23 05:32:32,975 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:32:32,976 INFO L225 Difference]: With dead ends: 21 [2018-11-23 05:32:32,976 INFO L226 Difference]: Without dead ends: 15 [2018-11-23 05:32:32,976 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 12 SyntacticMatches, 1 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2018-11-23 05:32:32,976 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15 states. [2018-11-23 05:32:32,978 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15 to 15. [2018-11-23 05:32:32,978 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15 states. [2018-11-23 05:32:32,979 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 15 transitions. [2018-11-23 05:32:32,979 INFO L78 Accepts]: Start accepts. Automaton has 15 states and 15 transitions. Word has length 13 [2018-11-23 05:32:32,979 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:32:32,979 INFO L480 AbstractCegarLoop]: Abstraction has 15 states and 15 transitions. [2018-11-23 05:32:32,979 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 05:32:32,979 INFO L276 IsEmpty]: Start isEmpty. Operand 15 states and 15 transitions. [2018-11-23 05:32:32,980 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2018-11-23 05:32:32,980 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:32:32,980 INFO L402 BasicCegarLoop]: trace histogram [3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:32:32,980 INFO L423 AbstractCegarLoop]: === Iteration 4 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:32:32,980 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:32:32,981 INFO L82 PathProgramCache]: Analyzing trace with hash 1038832069, now seen corresponding path program 3 times [2018-11-23 05:32:32,981 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 05:32:32,981 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 05:32:32,982 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:32:32,982 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 05:32:32,982 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:32:32,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:32:33,051 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:32:33,051 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 05:32:33,052 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0bcc5560-9368-4d8a-9bff-77d43d0a8e71/bin-2019/uautomizer/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 05:32:33,058 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-23 05:32:33,065 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2018-11-23 05:32:33,065 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 05:32:33,066 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:32:33,078 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:32:33,093 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:32:33,093 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 7 [2018-11-23 05:32:33,093 INFO L459 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-11-23 05:32:33,093 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-11-23 05:32:33,093 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-23 05:32:33,094 INFO L87 Difference]: Start difference. First operand 15 states and 15 transitions. Second operand 7 states. [2018-11-23 05:32:33,116 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:32:33,116 INFO L93 Difference]: Finished difference Result 22 states and 22 transitions. [2018-11-23 05:32:33,116 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 05:32:33,116 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 14 [2018-11-23 05:32:33,116 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:32:33,117 INFO L225 Difference]: With dead ends: 22 [2018-11-23 05:32:33,117 INFO L226 Difference]: Without dead ends: 16 [2018-11-23 05:32:33,117 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 13 SyntacticMatches, 1 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-11-23 05:32:33,117 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16 states. [2018-11-23 05:32:33,119 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16 to 16. [2018-11-23 05:32:33,120 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16 states. [2018-11-23 05:32:33,120 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16 states to 16 states and 16 transitions. [2018-11-23 05:32:33,120 INFO L78 Accepts]: Start accepts. Automaton has 16 states and 16 transitions. Word has length 14 [2018-11-23 05:32:33,120 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:32:33,120 INFO L480 AbstractCegarLoop]: Abstraction has 16 states and 16 transitions. [2018-11-23 05:32:33,121 INFO L481 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-11-23 05:32:33,121 INFO L276 IsEmpty]: Start isEmpty. Operand 16 states and 16 transitions. [2018-11-23 05:32:33,121 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2018-11-23 05:32:33,121 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:32:33,121 INFO L402 BasicCegarLoop]: trace histogram [4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:32:33,121 INFO L423 AbstractCegarLoop]: === Iteration 5 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:32:33,122 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:32:33,122 INFO L82 PathProgramCache]: Analyzing trace with hash -568891206, now seen corresponding path program 4 times [2018-11-23 05:32:33,122 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 05:32:33,122 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 05:32:33,123 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:32:33,123 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 05:32:33,123 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:32:33,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:32:33,216 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:32:33,216 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 05:32:33,216 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0bcc5560-9368-4d8a-9bff-77d43d0a8e71/bin-2019/uautomizer/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 05:32:33,227 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-23 05:32:33,233 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-23 05:32:33,233 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 05:32:33,234 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:32:33,253 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:32:33,269 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:32:33,269 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 8 [2018-11-23 05:32:33,269 INFO L459 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-11-23 05:32:33,269 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-11-23 05:32:33,269 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2018-11-23 05:32:33,270 INFO L87 Difference]: Start difference. First operand 16 states and 16 transitions. Second operand 8 states. [2018-11-23 05:32:33,291 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:32:33,291 INFO L93 Difference]: Finished difference Result 23 states and 23 transitions. [2018-11-23 05:32:33,291 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-23 05:32:33,291 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 15 [2018-11-23 05:32:33,291 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:32:33,291 INFO L225 Difference]: With dead ends: 23 [2018-11-23 05:32:33,292 INFO L226 Difference]: Without dead ends: 17 [2018-11-23 05:32:33,292 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 14 SyntacticMatches, 1 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2018-11-23 05:32:33,292 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17 states. [2018-11-23 05:32:33,293 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17 to 17. [2018-11-23 05:32:33,293 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 17 states. [2018-11-23 05:32:33,294 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17 states to 17 states and 17 transitions. [2018-11-23 05:32:33,294 INFO L78 Accepts]: Start accepts. Automaton has 17 states and 17 transitions. Word has length 15 [2018-11-23 05:32:33,294 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:32:33,294 INFO L480 AbstractCegarLoop]: Abstraction has 17 states and 17 transitions. [2018-11-23 05:32:33,294 INFO L481 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-11-23 05:32:33,294 INFO L276 IsEmpty]: Start isEmpty. Operand 17 states and 17 transitions. [2018-11-23 05:32:33,295 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-11-23 05:32:33,295 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:32:33,295 INFO L402 BasicCegarLoop]: trace histogram [5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:32:33,295 INFO L423 AbstractCegarLoop]: === Iteration 6 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:32:33,295 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:32:33,295 INFO L82 PathProgramCache]: Analyzing trace with hash 1131294821, now seen corresponding path program 5 times [2018-11-23 05:32:33,295 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 05:32:33,295 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 05:32:33,296 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:32:33,296 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 05:32:33,296 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:32:33,301 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:32:33,369 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:32:33,369 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 05:32:33,369 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0bcc5560-9368-4d8a-9bff-77d43d0a8e71/bin-2019/uautomizer/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 05:32:33,391 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-11-23 05:32:33,400 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) [2018-11-23 05:32:33,401 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 05:32:33,402 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:32:33,435 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:32:33,449 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:32:33,450 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 9 [2018-11-23 05:32:33,450 INFO L459 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-11-23 05:32:33,450 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-11-23 05:32:33,450 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2018-11-23 05:32:33,450 INFO L87 Difference]: Start difference. First operand 17 states and 17 transitions. Second operand 9 states. [2018-11-23 05:32:33,480 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:32:33,480 INFO L93 Difference]: Finished difference Result 24 states and 24 transitions. [2018-11-23 05:32:33,480 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-11-23 05:32:33,480 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 16 [2018-11-23 05:32:33,481 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:32:33,481 INFO L225 Difference]: With dead ends: 24 [2018-11-23 05:32:33,481 INFO L226 Difference]: Without dead ends: 18 [2018-11-23 05:32:33,481 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 23 GetRequests, 15 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2018-11-23 05:32:33,481 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18 states. [2018-11-23 05:32:33,483 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18 to 18. [2018-11-23 05:32:33,483 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18 states. [2018-11-23 05:32:33,484 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 18 transitions. [2018-11-23 05:32:33,484 INFO L78 Accepts]: Start accepts. Automaton has 18 states and 18 transitions. Word has length 16 [2018-11-23 05:32:33,484 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:32:33,484 INFO L480 AbstractCegarLoop]: Abstraction has 18 states and 18 transitions. [2018-11-23 05:32:33,484 INFO L481 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-11-23 05:32:33,484 INFO L276 IsEmpty]: Start isEmpty. Operand 18 states and 18 transitions. [2018-11-23 05:32:33,485 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-11-23 05:32:33,485 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:32:33,485 INFO L402 BasicCegarLoop]: trace histogram [6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:32:33,485 INFO L423 AbstractCegarLoop]: === Iteration 7 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:32:33,485 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:32:33,485 INFO L82 PathProgramCache]: Analyzing trace with hash -1997513190, now seen corresponding path program 6 times [2018-11-23 05:32:33,486 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 05:32:33,486 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 05:32:33,486 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:32:33,486 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 05:32:33,486 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:32:33,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:32:33,593 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:32:33,593 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 05:32:33,594 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0bcc5560-9368-4d8a-9bff-77d43d0a8e71/bin-2019/uautomizer/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 05:32:33,602 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-11-23 05:32:33,613 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 4 check-sat command(s) [2018-11-23 05:32:33,613 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 05:32:33,614 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:32:33,633 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:32:33,647 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:32:33,647 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 10 [2018-11-23 05:32:33,648 INFO L459 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-11-23 05:32:33,648 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-11-23 05:32:33,648 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=66, Unknown=0, NotChecked=0, Total=90 [2018-11-23 05:32:33,648 INFO L87 Difference]: Start difference. First operand 18 states and 18 transitions. Second operand 10 states. [2018-11-23 05:32:33,699 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:32:33,700 INFO L93 Difference]: Finished difference Result 25 states and 25 transitions. [2018-11-23 05:32:33,700 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-11-23 05:32:33,700 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 17 [2018-11-23 05:32:33,700 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:32:33,701 INFO L225 Difference]: With dead ends: 25 [2018-11-23 05:32:33,701 INFO L226 Difference]: Without dead ends: 19 [2018-11-23 05:32:33,701 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 25 GetRequests, 16 SyntacticMatches, 1 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=24, Invalid=66, Unknown=0, NotChecked=0, Total=90 [2018-11-23 05:32:33,701 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19 states. [2018-11-23 05:32:33,703 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19 to 19. [2018-11-23 05:32:33,703 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19 states. [2018-11-23 05:32:33,704 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19 states to 19 states and 19 transitions. [2018-11-23 05:32:33,704 INFO L78 Accepts]: Start accepts. Automaton has 19 states and 19 transitions. Word has length 17 [2018-11-23 05:32:33,704 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:32:33,704 INFO L480 AbstractCegarLoop]: Abstraction has 19 states and 19 transitions. [2018-11-23 05:32:33,704 INFO L481 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-11-23 05:32:33,704 INFO L276 IsEmpty]: Start isEmpty. Operand 19 states and 19 transitions. [2018-11-23 05:32:33,705 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2018-11-23 05:32:33,705 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:32:33,705 INFO L402 BasicCegarLoop]: trace histogram [7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:32:33,705 INFO L423 AbstractCegarLoop]: === Iteration 8 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:32:33,705 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:32:33,705 INFO L82 PathProgramCache]: Analyzing trace with hash -206313723, now seen corresponding path program 7 times [2018-11-23 05:32:33,705 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 05:32:33,706 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 05:32:33,706 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:32:33,706 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 05:32:33,706 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:32:33,714 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:32:33,814 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:32:33,815 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 05:32:33,815 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0bcc5560-9368-4d8a-9bff-77d43d0a8e71/bin-2019/uautomizer/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 05:32:33,823 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:32:33,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:32:33,842 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:32:33,874 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:32:33,889 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:32:33,889 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10] total 11 [2018-11-23 05:32:33,889 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-11-23 05:32:33,889 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-11-23 05:32:33,889 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=83, Unknown=0, NotChecked=0, Total=110 [2018-11-23 05:32:33,889 INFO L87 Difference]: Start difference. First operand 19 states and 19 transitions. Second operand 11 states. [2018-11-23 05:32:33,925 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:32:33,925 INFO L93 Difference]: Finished difference Result 26 states and 26 transitions. [2018-11-23 05:32:33,925 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-11-23 05:32:33,926 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 18 [2018-11-23 05:32:33,926 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:32:33,926 INFO L225 Difference]: With dead ends: 26 [2018-11-23 05:32:33,926 INFO L226 Difference]: Without dead ends: 20 [2018-11-23 05:32:33,927 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 27 GetRequests, 17 SyntacticMatches, 1 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=27, Invalid=83, Unknown=0, NotChecked=0, Total=110 [2018-11-23 05:32:33,927 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20 states. [2018-11-23 05:32:33,929 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20 to 20. [2018-11-23 05:32:33,929 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20 states. [2018-11-23 05:32:33,929 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 20 transitions. [2018-11-23 05:32:33,929 INFO L78 Accepts]: Start accepts. Automaton has 20 states and 20 transitions. Word has length 18 [2018-11-23 05:32:33,930 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:32:33,930 INFO L480 AbstractCegarLoop]: Abstraction has 20 states and 20 transitions. [2018-11-23 05:32:33,930 INFO L481 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-11-23 05:32:33,930 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states and 20 transitions. [2018-11-23 05:32:33,930 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2018-11-23 05:32:33,930 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:32:33,930 INFO L402 BasicCegarLoop]: trace histogram [8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:32:33,930 INFO L423 AbstractCegarLoop]: === Iteration 9 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:32:33,931 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:32:33,931 INFO L82 PathProgramCache]: Analyzing trace with hash -513705094, now seen corresponding path program 8 times [2018-11-23 05:32:33,931 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 05:32:33,931 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 05:32:33,931 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:32:33,932 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:32:33,932 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:32:33,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:32:34,039 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:32:34,039 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 05:32:34,039 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0bcc5560-9368-4d8a-9bff-77d43d0a8e71/bin-2019/uautomizer/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 05:32:34,045 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-23 05:32:34,052 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-23 05:32:34,052 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 05:32:34,053 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:32:34,080 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:32:34,095 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:32:34,095 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11] total 12 [2018-11-23 05:32:34,096 INFO L459 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-11-23 05:32:34,096 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-11-23 05:32:34,096 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=102, Unknown=0, NotChecked=0, Total=132 [2018-11-23 05:32:34,096 INFO L87 Difference]: Start difference. First operand 20 states and 20 transitions. Second operand 12 states. [2018-11-23 05:32:34,148 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:32:34,148 INFO L93 Difference]: Finished difference Result 27 states and 27 transitions. [2018-11-23 05:32:34,148 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-11-23 05:32:34,149 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 19 [2018-11-23 05:32:34,149 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:32:34,149 INFO L225 Difference]: With dead ends: 27 [2018-11-23 05:32:34,149 INFO L226 Difference]: Without dead ends: 21 [2018-11-23 05:32:34,150 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 29 GetRequests, 18 SyntacticMatches, 1 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=30, Invalid=102, Unknown=0, NotChecked=0, Total=132 [2018-11-23 05:32:34,150 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21 states. [2018-11-23 05:32:34,151 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21 to 21. [2018-11-23 05:32:34,151 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21 states. [2018-11-23 05:32:34,152 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 21 transitions. [2018-11-23 05:32:34,152 INFO L78 Accepts]: Start accepts. Automaton has 21 states and 21 transitions. Word has length 19 [2018-11-23 05:32:34,152 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:32:34,152 INFO L480 AbstractCegarLoop]: Abstraction has 21 states and 21 transitions. [2018-11-23 05:32:34,152 INFO L481 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-11-23 05:32:34,153 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 21 transitions. [2018-11-23 05:32:34,153 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2018-11-23 05:32:34,153 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:32:34,153 INFO L402 BasicCegarLoop]: trace histogram [9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:32:34,153 INFO L423 AbstractCegarLoop]: === Iteration 10 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:32:34,154 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:32:34,154 INFO L82 PathProgramCache]: Analyzing trace with hash -1452903003, now seen corresponding path program 9 times [2018-11-23 05:32:34,154 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 05:32:34,154 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 05:32:34,154 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:32:34,155 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 05:32:34,155 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:32:34,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:32:34,259 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:32:34,259 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 05:32:34,259 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0bcc5560-9368-4d8a-9bff-77d43d0a8e71/bin-2019/uautomizer/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 05:32:34,265 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-23 05:32:34,281 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2018-11-23 05:32:34,281 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 05:32:34,282 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:32:34,304 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:32:34,318 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:32:34,318 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12] total 13 [2018-11-23 05:32:34,318 INFO L459 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-11-23 05:32:34,319 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-11-23 05:32:34,319 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=123, Unknown=0, NotChecked=0, Total=156 [2018-11-23 05:32:34,319 INFO L87 Difference]: Start difference. First operand 21 states and 21 transitions. Second operand 13 states. [2018-11-23 05:32:34,365 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:32:34,365 INFO L93 Difference]: Finished difference Result 28 states and 28 transitions. [2018-11-23 05:32:34,366 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-11-23 05:32:34,366 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 20 [2018-11-23 05:32:34,367 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:32:34,367 INFO L225 Difference]: With dead ends: 28 [2018-11-23 05:32:34,367 INFO L226 Difference]: Without dead ends: 22 [2018-11-23 05:32:34,367 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 31 GetRequests, 19 SyntacticMatches, 1 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=33, Invalid=123, Unknown=0, NotChecked=0, Total=156 [2018-11-23 05:32:34,367 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states. [2018-11-23 05:32:34,369 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 22. [2018-11-23 05:32:34,369 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22 states. [2018-11-23 05:32:34,370 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 22 transitions. [2018-11-23 05:32:34,370 INFO L78 Accepts]: Start accepts. Automaton has 22 states and 22 transitions. Word has length 20 [2018-11-23 05:32:34,370 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:32:34,370 INFO L480 AbstractCegarLoop]: Abstraction has 22 states and 22 transitions. [2018-11-23 05:32:34,370 INFO L481 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-11-23 05:32:34,370 INFO L276 IsEmpty]: Start isEmpty. Operand 22 states and 22 transitions. [2018-11-23 05:32:34,371 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2018-11-23 05:32:34,371 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:32:34,371 INFO L402 BasicCegarLoop]: trace histogram [10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:32:34,371 INFO L423 AbstractCegarLoop]: === Iteration 11 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:32:34,371 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:32:34,371 INFO L82 PathProgramCache]: Analyzing trace with hash -503267110, now seen corresponding path program 10 times [2018-11-23 05:32:34,371 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 05:32:34,371 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 05:32:34,372 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:32:34,372 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 05:32:34,372 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:32:34,380 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:32:34,497 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:32:34,497 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 05:32:34,497 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0bcc5560-9368-4d8a-9bff-77d43d0a8e71/bin-2019/uautomizer/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 05:32:34,503 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-23 05:32:34,514 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-23 05:32:34,514 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 05:32:34,515 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:32:34,542 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:32:34,560 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:32:34,560 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13] total 14 [2018-11-23 05:32:34,560 INFO L459 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-11-23 05:32:34,560 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-11-23 05:32:34,560 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=146, Unknown=0, NotChecked=0, Total=182 [2018-11-23 05:32:34,561 INFO L87 Difference]: Start difference. First operand 22 states and 22 transitions. Second operand 14 states. [2018-11-23 05:32:34,624 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:32:34,624 INFO L93 Difference]: Finished difference Result 29 states and 29 transitions. [2018-11-23 05:32:34,625 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-11-23 05:32:34,625 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 21 [2018-11-23 05:32:34,625 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:32:34,625 INFO L225 Difference]: With dead ends: 29 [2018-11-23 05:32:34,625 INFO L226 Difference]: Without dead ends: 23 [2018-11-23 05:32:34,625 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 33 GetRequests, 20 SyntacticMatches, 1 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=36, Invalid=146, Unknown=0, NotChecked=0, Total=182 [2018-11-23 05:32:34,626 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23 states. [2018-11-23 05:32:34,627 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23 to 23. [2018-11-23 05:32:34,627 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 23 states. [2018-11-23 05:32:34,628 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23 states to 23 states and 23 transitions. [2018-11-23 05:32:34,628 INFO L78 Accepts]: Start accepts. Automaton has 23 states and 23 transitions. Word has length 21 [2018-11-23 05:32:34,628 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:32:34,628 INFO L480 AbstractCegarLoop]: Abstraction has 23 states and 23 transitions. [2018-11-23 05:32:34,628 INFO L481 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-11-23 05:32:34,628 INFO L276 IsEmpty]: Start isEmpty. Operand 23 states and 23 transitions. [2018-11-23 05:32:34,629 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2018-11-23 05:32:34,629 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:32:34,629 INFO L402 BasicCegarLoop]: trace histogram [11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:32:34,629 INFO L423 AbstractCegarLoop]: === Iteration 12 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:32:34,629 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:32:34,629 INFO L82 PathProgramCache]: Analyzing trace with hash -1129325499, now seen corresponding path program 11 times [2018-11-23 05:32:34,629 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 05:32:34,629 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 05:32:34,630 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:32:34,630 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 05:32:34,631 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:32:34,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:32:34,734 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:32:34,734 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 05:32:34,734 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0bcc5560-9368-4d8a-9bff-77d43d0a8e71/bin-2019/uautomizer/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 05:32:34,740 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-11-23 05:32:35,361 INFO L249 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2018-11-23 05:32:35,362 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 05:32:35,373 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:32:35,387 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:32:35,402 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:32:35,402 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14] total 15 [2018-11-23 05:32:35,402 INFO L459 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-11-23 05:32:35,402 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-11-23 05:32:35,403 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=171, Unknown=0, NotChecked=0, Total=210 [2018-11-23 05:32:35,403 INFO L87 Difference]: Start difference. First operand 23 states and 23 transitions. Second operand 15 states. [2018-11-23 05:32:35,496 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:32:35,497 INFO L93 Difference]: Finished difference Result 30 states and 30 transitions. [2018-11-23 05:32:35,497 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-11-23 05:32:35,498 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 22 [2018-11-23 05:32:35,498 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:32:35,498 INFO L225 Difference]: With dead ends: 30 [2018-11-23 05:32:35,498 INFO L226 Difference]: Without dead ends: 24 [2018-11-23 05:32:35,498 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 35 GetRequests, 21 SyntacticMatches, 1 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=39, Invalid=171, Unknown=0, NotChecked=0, Total=210 [2018-11-23 05:32:35,499 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24 states. [2018-11-23 05:32:35,501 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24 to 24. [2018-11-23 05:32:35,501 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24 states. [2018-11-23 05:32:35,501 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 24 transitions. [2018-11-23 05:32:35,501 INFO L78 Accepts]: Start accepts. Automaton has 24 states and 24 transitions. Word has length 22 [2018-11-23 05:32:35,501 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:32:35,504 INFO L480 AbstractCegarLoop]: Abstraction has 24 states and 24 transitions. [2018-11-23 05:32:35,504 INFO L481 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-11-23 05:32:35,504 INFO L276 IsEmpty]: Start isEmpty. Operand 24 states and 24 transitions. [2018-11-23 05:32:35,504 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2018-11-23 05:32:35,504 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:32:35,505 INFO L402 BasicCegarLoop]: trace histogram [12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:32:35,505 INFO L423 AbstractCegarLoop]: === Iteration 13 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:32:35,505 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:32:35,505 INFO L82 PathProgramCache]: Analyzing trace with hash 937700922, now seen corresponding path program 12 times [2018-11-23 05:32:35,505 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 05:32:35,505 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 05:32:35,506 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:32:35,506 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 05:32:35,506 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:32:35,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:32:35,637 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:32:35,637 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 05:32:35,638 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0bcc5560-9368-4d8a-9bff-77d43d0a8e71/bin-2019/uautomizer/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 05:32:35,643 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-11-23 05:32:35,664 INFO L249 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2018-11-23 05:32:35,664 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 05:32:35,666 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:32:35,686 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:32:35,700 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:32:35,700 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15] total 16 [2018-11-23 05:32:35,701 INFO L459 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-11-23 05:32:35,701 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-11-23 05:32:35,701 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=42, Invalid=198, Unknown=0, NotChecked=0, Total=240 [2018-11-23 05:32:35,701 INFO L87 Difference]: Start difference. First operand 24 states and 24 transitions. Second operand 16 states. [2018-11-23 05:32:35,767 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:32:35,767 INFO L93 Difference]: Finished difference Result 31 states and 31 transitions. [2018-11-23 05:32:35,767 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-11-23 05:32:35,767 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 23 [2018-11-23 05:32:35,767 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:32:35,768 INFO L225 Difference]: With dead ends: 31 [2018-11-23 05:32:35,768 INFO L226 Difference]: Without dead ends: 25 [2018-11-23 05:32:35,768 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 37 GetRequests, 22 SyntacticMatches, 1 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=42, Invalid=198, Unknown=0, NotChecked=0, Total=240 [2018-11-23 05:32:35,768 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states. [2018-11-23 05:32:35,770 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 25. [2018-11-23 05:32:35,770 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 25 states. [2018-11-23 05:32:35,770 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 25 transitions. [2018-11-23 05:32:35,770 INFO L78 Accepts]: Start accepts. Automaton has 25 states and 25 transitions. Word has length 23 [2018-11-23 05:32:35,770 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:32:35,771 INFO L480 AbstractCegarLoop]: Abstraction has 25 states and 25 transitions. [2018-11-23 05:32:35,771 INFO L481 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-11-23 05:32:35,771 INFO L276 IsEmpty]: Start isEmpty. Operand 25 states and 25 transitions. [2018-11-23 05:32:35,771 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2018-11-23 05:32:35,771 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:32:35,771 INFO L402 BasicCegarLoop]: trace histogram [13, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:32:35,772 INFO L423 AbstractCegarLoop]: === Iteration 14 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:32:35,772 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:32:35,772 INFO L82 PathProgramCache]: Analyzing trace with hash 591010533, now seen corresponding path program 13 times [2018-11-23 05:32:35,772 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 05:32:35,772 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 05:32:35,773 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:32:35,773 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 05:32:35,773 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:32:35,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:32:35,918 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 0 proven. 91 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:32:35,918 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 05:32:35,919 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0bcc5560-9368-4d8a-9bff-77d43d0a8e71/bin-2019/uautomizer/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 05:32:35,925 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:32:35,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:32:35,932 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:32:35,947 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 0 proven. 91 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:32:35,962 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:32:35,962 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16] total 17 [2018-11-23 05:32:35,962 INFO L459 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-11-23 05:32:35,963 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-11-23 05:32:35,963 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=227, Unknown=0, NotChecked=0, Total=272 [2018-11-23 05:32:35,963 INFO L87 Difference]: Start difference. First operand 25 states and 25 transitions. Second operand 17 states. [2018-11-23 05:32:36,079 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:32:36,080 INFO L93 Difference]: Finished difference Result 32 states and 32 transitions. [2018-11-23 05:32:36,080 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-11-23 05:32:36,080 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 24 [2018-11-23 05:32:36,081 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:32:36,081 INFO L225 Difference]: With dead ends: 32 [2018-11-23 05:32:36,081 INFO L226 Difference]: Without dead ends: 26 [2018-11-23 05:32:36,081 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 39 GetRequests, 23 SyntacticMatches, 1 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=45, Invalid=227, Unknown=0, NotChecked=0, Total=272 [2018-11-23 05:32:36,081 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26 states. [2018-11-23 05:32:36,083 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26 to 26. [2018-11-23 05:32:36,083 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 26 states. [2018-11-23 05:32:36,083 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26 states to 26 states and 26 transitions. [2018-11-23 05:32:36,083 INFO L78 Accepts]: Start accepts. Automaton has 26 states and 26 transitions. Word has length 24 [2018-11-23 05:32:36,084 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:32:36,084 INFO L480 AbstractCegarLoop]: Abstraction has 26 states and 26 transitions. [2018-11-23 05:32:36,084 INFO L481 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-11-23 05:32:36,084 INFO L276 IsEmpty]: Start isEmpty. Operand 26 states and 26 transitions. [2018-11-23 05:32:36,084 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-11-23 05:32:36,084 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:32:36,084 INFO L402 BasicCegarLoop]: trace histogram [14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:32:36,085 INFO L423 AbstractCegarLoop]: === Iteration 15 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:32:36,085 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:32:36,085 INFO L82 PathProgramCache]: Analyzing trace with hash -1566456934, now seen corresponding path program 14 times [2018-11-23 05:32:36,085 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 05:32:36,085 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 05:32:36,086 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:32:36,086 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:32:36,086 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:32:36,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:32:36,247 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 0 proven. 105 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:32:36,247 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 05:32:36,247 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0bcc5560-9368-4d8a-9bff-77d43d0a8e71/bin-2019/uautomizer/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 05:32:36,267 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-11-23 05:32:36,277 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-23 05:32:36,278 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 05:32:36,279 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:32:36,297 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 0 proven. 105 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:32:36,312 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:32:36,312 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17] total 18 [2018-11-23 05:32:36,313 INFO L459 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-11-23 05:32:36,313 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-11-23 05:32:36,313 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=48, Invalid=258, Unknown=0, NotChecked=0, Total=306 [2018-11-23 05:32:36,313 INFO L87 Difference]: Start difference. First operand 26 states and 26 transitions. Second operand 18 states. [2018-11-23 05:32:36,397 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:32:36,397 INFO L93 Difference]: Finished difference Result 33 states and 33 transitions. [2018-11-23 05:32:36,398 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-11-23 05:32:36,398 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 25 [2018-11-23 05:32:36,398 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:32:36,398 INFO L225 Difference]: With dead ends: 33 [2018-11-23 05:32:36,398 INFO L226 Difference]: Without dead ends: 27 [2018-11-23 05:32:36,399 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 41 GetRequests, 24 SyntacticMatches, 1 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=48, Invalid=258, Unknown=0, NotChecked=0, Total=306 [2018-11-23 05:32:36,399 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27 states. [2018-11-23 05:32:36,401 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27 to 27. [2018-11-23 05:32:36,401 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 27 states. [2018-11-23 05:32:36,401 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 27 transitions. [2018-11-23 05:32:36,401 INFO L78 Accepts]: Start accepts. Automaton has 27 states and 27 transitions. Word has length 25 [2018-11-23 05:32:36,402 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:32:36,402 INFO L480 AbstractCegarLoop]: Abstraction has 27 states and 27 transitions. [2018-11-23 05:32:36,402 INFO L481 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-11-23 05:32:36,402 INFO L276 IsEmpty]: Start isEmpty. Operand 27 states and 27 transitions. [2018-11-23 05:32:36,402 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-11-23 05:32:36,402 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:32:36,402 INFO L402 BasicCegarLoop]: trace histogram [15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:32:36,402 INFO L423 AbstractCegarLoop]: === Iteration 16 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:32:36,403 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:32:36,403 INFO L82 PathProgramCache]: Analyzing trace with hash 271528325, now seen corresponding path program 15 times [2018-11-23 05:32:36,403 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 05:32:36,403 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 05:32:36,403 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:32:36,404 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 05:32:36,404 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:32:36,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:32:36,543 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 0 proven. 120 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:32:36,544 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-23 05:32:36,544 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0bcc5560-9368-4d8a-9bff-77d43d0a8e71/bin-2019/uautomizer/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-23 05:32:36,550 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-11-23 05:32:36,636 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2018-11-23 05:32:36,636 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 05:32:36,638 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:32:36,665 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 0 proven. 120 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:32:36,680 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:32:36,680 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18] total 19 [2018-11-23 05:32:36,680 INFO L459 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-11-23 05:32:36,680 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-11-23 05:32:36,680 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=291, Unknown=0, NotChecked=0, Total=342 [2018-11-23 05:32:36,681 INFO L87 Difference]: Start difference. First operand 27 states and 27 transitions. Second operand 19 states. [2018-11-23 05:32:36,763 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:32:36,763 INFO L93 Difference]: Finished difference Result 34 states and 34 transitions. [2018-11-23 05:32:36,763 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-11-23 05:32:36,763 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 26 [2018-11-23 05:32:36,764 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:32:36,764 INFO L225 Difference]: With dead ends: 34 [2018-11-23 05:32:36,764 INFO L226 Difference]: Without dead ends: 28 [2018-11-23 05:32:36,764 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 43 GetRequests, 25 SyntacticMatches, 1 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=51, Invalid=291, Unknown=0, NotChecked=0, Total=342 [2018-11-23 05:32:36,765 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states. [2018-11-23 05:32:36,771 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 28. [2018-11-23 05:32:36,771 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 28 states. [2018-11-23 05:32:36,771 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 28 transitions. [2018-11-23 05:32:36,771 INFO L78 Accepts]: Start accepts. Automaton has 28 states and 28 transitions. Word has length 26 [2018-11-23 05:32:36,771 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:32:36,772 INFO L480 AbstractCegarLoop]: Abstraction has 28 states and 28 transitions. [2018-11-23 05:32:36,772 INFO L481 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-11-23 05:32:36,772 INFO L276 IsEmpty]: Start isEmpty. Operand 28 states and 28 transitions. [2018-11-23 05:32:36,772 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-11-23 05:32:36,772 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:32:36,772 INFO L402 BasicCegarLoop]: trace histogram [16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:32:36,772 INFO L423 AbstractCegarLoop]: === Iteration 17 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:32:36,773 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:32:36,773 INFO L82 PathProgramCache]: Analyzing trace with hash 1414496506, now seen corresponding path program 16 times [2018-11-23 05:32:36,773 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-23 05:32:36,773 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-23 05:32:36,773 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:32:36,773 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-11-23 05:32:36,774 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-23 05:32:36,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 05:32:36,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-23 05:32:36,796 INFO L469 BasicCegarLoop]: Counterexample might be feasible ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] CALL call ULTIMATE.init(); [?] assume true; [?] RET #32#return; [?] CALL call #t~ret2 := main(); [?] ~x~0 := #t~nondet0;havoc #t~nondet0;~y~0 := #t~nondet1;havoc #t~nondet1;havoc ~xx~0;havoc ~yy~0;havoc ~zz~0;~z~0 := 0;~i~0 := 0; VAL [main_~i~0=0, main_~x~0=3, main_~y~0=2, main_~z~0=0] [?] assume !!(~i~0 % 4294967296 < 16);~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0)));~i~0 := 1 + ~i~0; VAL [main_~i~0=1, main_~x~0=3, main_~y~0=2] [?] assume !!(~i~0 % 4294967296 < 16);~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0)));~i~0 := 1 + ~i~0; VAL [main_~i~0=2, main_~x~0=3, main_~y~0=2] [?] assume !!(~i~0 % 4294967296 < 16);~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0)));~i~0 := 1 + ~i~0; VAL [main_~i~0=3, main_~x~0=3, main_~y~0=2] [?] assume !!(~i~0 % 4294967296 < 16);~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0)));~i~0 := 1 + ~i~0; VAL [main_~i~0=4, main_~x~0=3, main_~y~0=2] [?] assume !!(~i~0 % 4294967296 < 16);~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0)));~i~0 := 1 + ~i~0; VAL [main_~i~0=5, main_~x~0=3, main_~y~0=2] [?] assume !!(~i~0 % 4294967296 < 16);~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0)));~i~0 := 1 + ~i~0; VAL [main_~i~0=6, main_~x~0=3, main_~y~0=2] [?] assume !!(~i~0 % 4294967296 < 16);~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0)));~i~0 := 1 + ~i~0; VAL [main_~i~0=7, main_~x~0=3, main_~y~0=2] [?] assume !!(~i~0 % 4294967296 < 16);~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0)));~i~0 := 1 + ~i~0; VAL [main_~i~0=8, main_~x~0=3, main_~y~0=2] [?] assume !!(~i~0 % 4294967296 < 16);~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0)));~i~0 := 1 + ~i~0; VAL [main_~i~0=9, main_~x~0=3, main_~y~0=2] [?] assume !!(~i~0 % 4294967296 < 16);~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0)));~i~0 := 1 + ~i~0; VAL [main_~i~0=10, main_~x~0=3, main_~y~0=2] [?] assume !!(~i~0 % 4294967296 < 16);~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0)));~i~0 := 1 + ~i~0; VAL [main_~i~0=11, main_~x~0=3, main_~y~0=2] [?] assume !!(~i~0 % 4294967296 < 16);~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0)));~i~0 := 1 + ~i~0; VAL [main_~i~0=12, main_~x~0=3, main_~y~0=2] [?] assume !!(~i~0 % 4294967296 < 16);~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0)));~i~0 := 1 + ~i~0; VAL [main_~i~0=13, main_~x~0=3, main_~y~0=2] [?] assume !!(~i~0 % 4294967296 < 16);~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0)));~i~0 := 1 + ~i~0; VAL [main_~i~0=14, main_~x~0=3, main_~y~0=2] [?] assume !!(~i~0 % 4294967296 < 16);~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0)));~i~0 := 1 + ~i~0; VAL [main_~i~0=15, main_~x~0=3, main_~y~0=2] [?] assume !!(~i~0 % 4294967296 < 16);~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0)));~i~0 := 1 + ~i~0; VAL [main_~i~0=16, main_~x~0=3, main_~y~0=2] [?] assume !(~i~0 % 4294967296 < 16); VAL [main_~i~0=16, main_~x~0=3, main_~y~0=2] [?] ~xx~0 := ~x~0 % 65536;~yy~0 := ~y~0 % 65536;~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 256 * ~xx~0), 16711935);~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 16 * ~xx~0), 252645135);~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 4 * ~xx~0), 858993459);~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 2 * ~xx~0), 1431655765);~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 256 * ~yy~0), 16711935);~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 16 * ~yy~0), 252645135);~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 4 * ~yy~0), 858993459);~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 2 * ~yy~0), 1431655765);~zz~0 := ~bitwiseOr(~xx~0, 2 * ~yy~0); VAL [main_~i~0=16, main_~x~0=3, main_~y~0=2] [?] CALL call __VERIFIER_assert((if ~z~0 % 4294967296 == ~zz~0 % 4294967296 then 1 else 0)); VAL [|__VERIFIER_assert_#in~cond|=0] [?] ~cond := #in~cond; VAL [__VERIFIER_assert_~cond=0, |__VERIFIER_assert_#in~cond|=0] [?] assume 0 == ~cond; VAL [__VERIFIER_assert_~cond=0, |__VERIFIER_assert_#in~cond|=0] [?] assume !false; VAL [__VERIFIER_assert_~cond=0, |__VERIFIER_assert_#in~cond|=0] [?] CALL call ULTIMATE.init(); [?] ensures true; [?] RET call ULTIMATE.init(); [?] CALL call #t~ret2 := main(); [L23] ~x~0 := #t~nondet0; [L23] havoc #t~nondet0; [L24] ~y~0 := #t~nondet1; [L24] havoc #t~nondet1; [L25] havoc ~xx~0; [L26] havoc ~yy~0; [L27] havoc ~zz~0; [L28] ~z~0 := 0; [L29] ~i~0 := 0; VAL [~i~0=0, ~x~0=3, ~y~0=2, ~z~0=0] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=1, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=2, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=3, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=4, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=5, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=6, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=7, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=8, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=9, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=10, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=11, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=12, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=13, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=14, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=15, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=16, ~x~0=3, ~y~0=2] [L30-L33] assume !(~i~0 % 4294967296 < 16); VAL [~i~0=16, ~x~0=3, ~y~0=2] [L34] ~xx~0 := ~x~0 % 65536; [L35] ~yy~0 := ~y~0 % 65536; [L36] ~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 256 * ~xx~0), 16711935); [L37] ~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 16 * ~xx~0), 252645135); [L38] ~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 4 * ~xx~0), 858993459); [L39] ~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 2 * ~xx~0), 1431655765); [L40] ~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 256 * ~yy~0), 16711935); [L41] ~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 16 * ~yy~0), 252645135); [L42] ~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 4 * ~yy~0), 858993459); [L43] ~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 2 * ~yy~0), 1431655765); [L45] ~zz~0 := ~bitwiseOr(~xx~0, 2 * ~yy~0); VAL [~i~0=16, ~x~0=3, ~y~0=2] [L47] CALL call __VERIFIER_assert((if ~z~0 % 4294967296 == ~zz~0 % 4294967296 then 1 else 0)); VAL [#in~cond=0] [L4-L9] ~cond := #in~cond; VAL [#in~cond=0, ~cond=0] [L5-L7] assume 0 == ~cond; VAL [#in~cond=0, ~cond=0] [L6] assert false; VAL [#in~cond=0, ~cond=0] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [?] CALL call ULTIMATE.init(); [?] ensures true; [?] RET call ULTIMATE.init(); [?] CALL call #t~ret2 := main(); [L23] ~x~0 := #t~nondet0; [L23] havoc #t~nondet0; [L24] ~y~0 := #t~nondet1; [L24] havoc #t~nondet1; [L25] havoc ~xx~0; [L26] havoc ~yy~0; [L27] havoc ~zz~0; [L28] ~z~0 := 0; [L29] ~i~0 := 0; VAL [~i~0=0, ~x~0=3, ~y~0=2, ~z~0=0] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=1, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=2, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=3, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=4, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=5, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=6, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=7, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=8, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=9, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=10, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=11, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=12, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=13, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=14, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=15, ~x~0=3, ~y~0=2] [L30-L33] assume !!(~i~0 % 4294967296 < 16); [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=16, ~x~0=3, ~y~0=2] [L30-L33] assume !(~i~0 % 4294967296 < 16); VAL [~i~0=16, ~x~0=3, ~y~0=2] [L34] ~xx~0 := ~x~0 % 65536; [L35] ~yy~0 := ~y~0 % 65536; [L36] ~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 256 * ~xx~0), 16711935); [L37] ~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 16 * ~xx~0), 252645135); [L38] ~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 4 * ~xx~0), 858993459); [L39] ~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 2 * ~xx~0), 1431655765); [L40] ~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 256 * ~yy~0), 16711935); [L41] ~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 16 * ~yy~0), 252645135); [L42] ~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 4 * ~yy~0), 858993459); [L43] ~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 2 * ~yy~0), 1431655765); [L45] ~zz~0 := ~bitwiseOr(~xx~0, 2 * ~yy~0); VAL [~i~0=16, ~x~0=3, ~y~0=2] [L47] CALL call __VERIFIER_assert((if ~z~0 % 4294967296 == ~zz~0 % 4294967296 then 1 else 0)); VAL [#in~cond=0] [L4-L9] ~cond := #in~cond; VAL [#in~cond=0, ~cond=0] [L5-L7] assume 0 == ~cond; VAL [#in~cond=0, ~cond=0] [L6] assert false; VAL [#in~cond=0, ~cond=0] [?] CALL call ULTIMATE.init(); [?] RET call ULTIMATE.init(); [?] CALL call #t~ret2 := main(); [L23] ~x~0 := #t~nondet0; [L23] havoc #t~nondet0; [L24] ~y~0 := #t~nondet1; [L24] havoc #t~nondet1; [L25] havoc ~xx~0; [L26] havoc ~yy~0; [L27] havoc ~zz~0; [L28] ~z~0 := 0; [L29] ~i~0 := 0; VAL [~i~0=0, ~x~0=3, ~y~0=2, ~z~0=0] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=1, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=2, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=3, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=4, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=5, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=6, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=7, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=8, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=9, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=10, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=11, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=12, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=13, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=14, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=15, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=16, ~x~0=3, ~y~0=2] [L30-L33] COND TRUE !(~i~0 % 4294967296 < 16) VAL [~i~0=16, ~x~0=3, ~y~0=2] [L34] ~xx~0 := ~x~0 % 65536; [L35] ~yy~0 := ~y~0 % 65536; [L36] ~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 256 * ~xx~0), 16711935); [L37] ~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 16 * ~xx~0), 252645135); [L38] ~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 4 * ~xx~0), 858993459); [L39] ~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 2 * ~xx~0), 1431655765); [L40] ~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 256 * ~yy~0), 16711935); [L41] ~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 16 * ~yy~0), 252645135); [L42] ~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 4 * ~yy~0), 858993459); [L43] ~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 2 * ~yy~0), 1431655765); [L45] ~zz~0 := ~bitwiseOr(~xx~0, 2 * ~yy~0); VAL [~i~0=16, ~x~0=3, ~y~0=2] [L47] CALL call __VERIFIER_assert((if ~z~0 % 4294967296 == ~zz~0 % 4294967296 then 1 else 0)); VAL [#in~cond=0] [L4-L9] ~cond := #in~cond; VAL [#in~cond=0, ~cond=0] [L5] COND TRUE 0 == ~cond VAL [#in~cond=0, ~cond=0] [L6] assert false; VAL [#in~cond=0, ~cond=0] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [?] CALL call ULTIMATE.init(); [?] RET call ULTIMATE.init(); [?] CALL call #t~ret2 := main(); [L23] ~x~0 := #t~nondet0; [L23] havoc #t~nondet0; [L24] ~y~0 := #t~nondet1; [L24] havoc #t~nondet1; [L25] havoc ~xx~0; [L26] havoc ~yy~0; [L27] havoc ~zz~0; [L28] ~z~0 := 0; [L29] ~i~0 := 0; VAL [~i~0=0, ~x~0=3, ~y~0=2, ~z~0=0] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=1, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=2, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=3, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=4, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=5, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=6, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=7, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=8, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=9, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=10, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=11, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=12, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=13, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=14, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=15, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=16, ~x~0=3, ~y~0=2] [L30-L33] COND TRUE !(~i~0 % 4294967296 < 16) VAL [~i~0=16, ~x~0=3, ~y~0=2] [L34] ~xx~0 := ~x~0 % 65536; [L35] ~yy~0 := ~y~0 % 65536; [L36] ~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 256 * ~xx~0), 16711935); [L37] ~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 16 * ~xx~0), 252645135); [L38] ~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 4 * ~xx~0), 858993459); [L39] ~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 2 * ~xx~0), 1431655765); [L40] ~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 256 * ~yy~0), 16711935); [L41] ~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 16 * ~yy~0), 252645135); [L42] ~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 4 * ~yy~0), 858993459); [L43] ~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 2 * ~yy~0), 1431655765); [L45] ~zz~0 := ~bitwiseOr(~xx~0, 2 * ~yy~0); VAL [~i~0=16, ~x~0=3, ~y~0=2] [L47] CALL call __VERIFIER_assert((if ~z~0 % 4294967296 == ~zz~0 % 4294967296 then 1 else 0)); VAL [#in~cond=0] [L4-L9] ~cond := #in~cond; VAL [#in~cond=0, ~cond=0] [L5] COND TRUE 0 == ~cond VAL [#in~cond=0, ~cond=0] [L6] assert false; VAL [#in~cond=0, ~cond=0] [?] CALL call ULTIMATE.init(); [?] RET call ULTIMATE.init(); [?] CALL call #t~ret2 := main(); [L23] ~x~0 := #t~nondet0; [L23] havoc #t~nondet0; [L24] ~y~0 := #t~nondet1; [L24] havoc #t~nondet1; [L25] havoc ~xx~0; [L26] havoc ~yy~0; [L27] havoc ~zz~0; [L28] ~z~0 := 0; [L29] ~i~0 := 0; VAL [~i~0=0, ~x~0=3, ~y~0=2, ~z~0=0] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=1, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=2, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=3, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=4, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=5, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=6, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=7, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=8, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=9, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=10, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=11, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=12, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=13, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=14, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=15, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=16, ~x~0=3, ~y~0=2] [L30-L33] COND TRUE !(~i~0 % 4294967296 < 16) VAL [~i~0=16, ~x~0=3, ~y~0=2] [L34] ~xx~0 := ~x~0 % 65536; [L35] ~yy~0 := ~y~0 % 65536; [L36] ~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 256 * ~xx~0), 16711935); [L37] ~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 16 * ~xx~0), 252645135); [L38] ~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 4 * ~xx~0), 858993459); [L39] ~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 2 * ~xx~0), 1431655765); [L40] ~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 256 * ~yy~0), 16711935); [L41] ~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 16 * ~yy~0), 252645135); [L42] ~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 4 * ~yy~0), 858993459); [L43] ~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 2 * ~yy~0), 1431655765); [L45] ~zz~0 := ~bitwiseOr(~xx~0, 2 * ~yy~0); VAL [~i~0=16, ~x~0=3, ~y~0=2] [L47] CALL call __VERIFIER_assert((if ~z~0 % 4294967296 == ~zz~0 % 4294967296 then 1 else 0)); VAL [#in~cond=0] [L4-L9] ~cond := #in~cond; VAL [#in~cond=0, ~cond=0] [L5] COND TRUE 0 == ~cond VAL [#in~cond=0, ~cond=0] [L6] assert false; VAL [#in~cond=0, ~cond=0] ----- ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [?] CALL call ULTIMATE.init(); [?] RET call ULTIMATE.init(); [?] CALL call #t~ret2 := main(); [L23] ~x~0 := #t~nondet0; [L23] havoc #t~nondet0; [L24] ~y~0 := #t~nondet1; [L24] havoc #t~nondet1; [L25] havoc ~xx~0; [L26] havoc ~yy~0; [L27] havoc ~zz~0; [L28] ~z~0 := 0; [L29] ~i~0 := 0; VAL [~i~0=0, ~x~0=3, ~y~0=2, ~z~0=0] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=1, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=2, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=3, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=4, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=5, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=6, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=7, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=8, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=9, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=10, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=11, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=12, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=13, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=14, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=15, ~x~0=3, ~y~0=2] [L30-L33] COND FALSE !(!(~i~0 % 4294967296 < 16)) [L31] ~z~0 := ~bitwiseOr(~z~0, ~bitwiseOr(~shiftLeft(~bitwiseAnd(~x~0 % 65536, ~shiftLeft(1, ~i~0)), ~i~0), ~shiftLeft(~bitwiseAnd(~y~0 % 65536, ~shiftLeft(1, ~i~0)), 1 + ~i~0))); [L32] ~i~0 := 1 + ~i~0; VAL [~i~0=16, ~x~0=3, ~y~0=2] [L30-L33] COND TRUE !(~i~0 % 4294967296 < 16) VAL [~i~0=16, ~x~0=3, ~y~0=2] [L34] ~xx~0 := ~x~0 % 65536; [L35] ~yy~0 := ~y~0 % 65536; [L36] ~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 256 * ~xx~0), 16711935); [L37] ~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 16 * ~xx~0), 252645135); [L38] ~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 4 * ~xx~0), 858993459); [L39] ~xx~0 := ~bitwiseAnd(~bitwiseOr(~xx~0, 2 * ~xx~0), 1431655765); [L40] ~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 256 * ~yy~0), 16711935); [L41] ~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 16 * ~yy~0), 252645135); [L42] ~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 4 * ~yy~0), 858993459); [L43] ~yy~0 := ~bitwiseAnd(~bitwiseOr(~yy~0, 2 * ~yy~0), 1431655765); [L45] ~zz~0 := ~bitwiseOr(~xx~0, 2 * ~yy~0); VAL [~i~0=16, ~x~0=3, ~y~0=2] [L47] CALL call __VERIFIER_assert((if ~z~0 % 4294967296 == ~zz~0 % 4294967296 then 1 else 0)); VAL [#in~cond=0] [L4-L9] ~cond := #in~cond; VAL [#in~cond=0, ~cond=0] [L5] COND TRUE 0 == ~cond VAL [#in~cond=0, ~cond=0] [L6] assert false; VAL [#in~cond=0, ~cond=0] [L23] unsigned short x = __VERIFIER_nondet_ushort(); [L24] unsigned short y = __VERIFIER_nondet_ushort(); [L25] unsigned int xx; [L26] unsigned int yy; [L27] unsigned int zz; [L28] unsigned int z = 0; [L29] unsigned int i = 0; VAL [i=0, x=3, y=2, z=0] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=1, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=2, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=3, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=4, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=5, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=6, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=7, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=8, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=9, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=10, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=11, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=12, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=13, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=14, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=15, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=16, x=3, y=2] [L30] COND FALSE !(i < sizeof(x) * 8) VAL [i=16, x=3, y=2] [L34] xx = x [L35] yy = y [L36] xx = (xx | (xx << 8u)) & 16711935U [L37] xx = (xx | (xx << 4u)) & 252645135U [L38] xx = (xx | (xx << 2u)) & 858993459U [L39] xx = (xx | (xx << 1u)) & 1431655765U [L40] yy = (yy | (yy << 8u)) & 16711935U [L41] yy = (yy | (yy << 4u)) & 252645135U [L42] yy = (yy | (yy << 2u)) & 858993459U [L43] yy = (yy | (yy << 1u)) & 1431655765U [L45] zz = xx | (yy << 1U) VAL [i=16, x=3, y=2] [L47] CALL __VERIFIER_assert(z == zz) VAL [\old(cond)=0] [L5] COND TRUE !(cond) VAL [\old(cond)=0, cond=0] [L6] __VERIFIER_error() VAL [\old(cond)=0, cond=0] ----- [2018-11-23 05:32:36,832 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 23.11 05:32:36 BoogieIcfgContainer [2018-11-23 05:32:36,832 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-11-23 05:32:36,833 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-23 05:32:36,833 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-23 05:32:36,833 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-23 05:32:36,833 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 05:32:32" (3/4) ... [2018-11-23 05:32:36,836 INFO L147 WitnessPrinter]: No result that supports witness generation found [2018-11-23 05:32:36,836 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-23 05:32:36,837 INFO L168 Benchmark]: Toolchain (without parser) took 4824.70 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 167.8 MB). Free memory was 958.2 MB in the beginning and 1.0 GB in the end (delta: -42.6 MB). Peak memory consumption was 125.2 MB. Max. memory is 11.5 GB. [2018-11-23 05:32:36,838 INFO L168 Benchmark]: CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 985.6 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-23 05:32:36,839 INFO L168 Benchmark]: CACSL2BoogieTranslator took 157.64 ms. Allocated memory is still 1.0 GB. Free memory was 958.2 MB in the beginning and 947.2 MB in the end (delta: 10.9 MB). Peak memory consumption was 10.9 MB. Max. memory is 11.5 GB. [2018-11-23 05:32:36,839 INFO L168 Benchmark]: Boogie Procedure Inliner took 13.10 ms. Allocated memory is still 1.0 GB. Free memory was 947.2 MB in the beginning and 944.6 MB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. [2018-11-23 05:32:36,839 INFO L168 Benchmark]: Boogie Preprocessor took 47.62 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 131.6 MB). Free memory was 944.6 MB in the beginning and 1.1 GB in the end (delta: -191.7 MB). Peak memory consumption was 14.0 MB. Max. memory is 11.5 GB. [2018-11-23 05:32:36,840 INFO L168 Benchmark]: RCFGBuilder took 129.05 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 19.7 MB). Peak memory consumption was 19.7 MB. Max. memory is 11.5 GB. [2018-11-23 05:32:36,840 INFO L168 Benchmark]: TraceAbstraction took 4470.27 ms. Allocated memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 36.2 MB). Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 115.8 MB). Peak memory consumption was 152.0 MB. Max. memory is 11.5 GB. [2018-11-23 05:32:36,840 INFO L168 Benchmark]: Witness Printer took 3.92 ms. Allocated memory is still 1.2 GB. Free memory is still 1.0 GB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-23 05:32:36,843 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 985.6 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 157.64 ms. Allocated memory is still 1.0 GB. Free memory was 958.2 MB in the beginning and 947.2 MB in the end (delta: 10.9 MB). Peak memory consumption was 10.9 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 13.10 ms. Allocated memory is still 1.0 GB. Free memory was 947.2 MB in the beginning and 944.6 MB in the end (delta: 2.7 MB). Peak memory consumption was 2.7 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 47.62 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 131.6 MB). Free memory was 944.6 MB in the beginning and 1.1 GB in the end (delta: -191.7 MB). Peak memory consumption was 14.0 MB. Max. memory is 11.5 GB. * RCFGBuilder took 129.05 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 19.7 MB). Peak memory consumption was 19.7 MB. Max. memory is 11.5 GB. * TraceAbstraction took 4470.27 ms. Allocated memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 36.2 MB). Free memory was 1.1 GB in the beginning and 1.0 GB in the end (delta: 115.8 MB). Peak memory consumption was 152.0 MB. Max. memory is 11.5 GB. * Witness Printer took 3.92 ms. Allocated memory is still 1.2 GB. Free memory is still 1.0 GB. There was no memory consumed. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - UnprovableResult [Line: 6]: Unable to prove that call of __VERIFIER_error() unreachable Unable to prove that call of __VERIFIER_error() unreachable Reason: overapproximation of bitwiseOr at line 45, overapproximation of bitwiseAnd at line 36. Possible FailurePath: [L23] unsigned short x = __VERIFIER_nondet_ushort(); [L24] unsigned short y = __VERIFIER_nondet_ushort(); [L25] unsigned int xx; [L26] unsigned int yy; [L27] unsigned int zz; [L28] unsigned int z = 0; [L29] unsigned int i = 0; VAL [i=0, x=3, y=2, z=0] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=1, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=2, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=3, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=4, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=5, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=6, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=7, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=8, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=9, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=10, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=11, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=12, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=13, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=14, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=15, x=3, y=2] [L30] COND TRUE i < sizeof(x) * 8 [L31] z |= ((x & (1U << i)) << i) | ((y & (1U << i)) << (i + 1)) [L32] i += 1U VAL [i=16, x=3, y=2] [L30] COND FALSE !(i < sizeof(x) * 8) VAL [i=16, x=3, y=2] [L34] xx = x [L35] yy = y [L36] xx = (xx | (xx << 8u)) & 16711935U [L37] xx = (xx | (xx << 4u)) & 252645135U [L38] xx = (xx | (xx << 2u)) & 858993459U [L39] xx = (xx | (xx << 1u)) & 1431655765U [L40] yy = (yy | (yy << 8u)) & 16711935U [L41] yy = (yy | (yy << 4u)) & 252645135U [L42] yy = (yy | (yy << 2u)) & 858993459U [L43] yy = (yy | (yy << 1u)) & 1431655765U [L45] zz = xx | (yy << 1U) VAL [i=16, x=3, y=2] [L47] CALL __VERIFIER_assert(z == zz) VAL [\old(cond)=0] [L5] COND TRUE !(cond) VAL [\old(cond)=0, cond=0] [L6] __VERIFIER_error() VAL [\old(cond)=0, cond=0] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 18 locations, 1 error locations. UNSAFE Result, 4.4s OverallTime, 17 OverallIterations, 16 TraceHistogramMax, 0.8s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 182 SDtfs, 0 SDslu, 906 SDs, 0 SdLazy, 1696 SolverSat, 120 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 0.6s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 438 GetRequests, 272 SyntacticMatches, 15 SemanticMatches, 151 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 30 ImplicationChecksByTransitivity, 1.5s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=28occurred in iteration=16, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.0s AutomataMinimizationTime, 16 MinimizatonAttempts, 0 StatesRemovedByMinimization, 0 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.0s SsaConstructionTime, 0.9s SatisfiabilityAnalysisTime, 1.9s InterpolantComputationTime, 608 NumberOfCodeBlocks, 608 NumberOfCodeBlocksAsserted, 70 NumberOfCheckSat, 550 ConstructedInterpolants, 0 QuantifiedInterpolants, 44080 SizeOfPredicates, 15 NumberOfNonLiveVariables, 795 ConjunctsInSsa, 285 ConjunctsInUnsatCore, 31 InterpolantComputations, 1 PerfectInterpolantSequences, 0/1360 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: unable to determine feasibility of some traces Received shutdown request... ### Bit-precise run ### This is Ultimate 0.1.23-aa41828 [2018-11-23 05:32:38,303 INFO L170 SettingsManager]: Resetting all preferences to default values... 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[2018-11-23 05:32:38,330 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-23 05:32:38,331 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-23 05:32:38,331 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-23 05:32:38,332 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-23 05:32:38,332 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-23 05:32:38,333 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-23 05:32:38,334 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-23 05:32:38,334 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-23 05:32:38,334 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-23 05:32:38,334 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-23 05:32:38,335 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-23 05:32:38,335 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-23 05:32:38,336 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-23 05:32:38,336 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_0bcc5560-9368-4d8a-9bff-77d43d0a8e71/bin-2019/uautomizer/config/svcomp-Reach-32bit-Automizer_Bitvector.epf [2018-11-23 05:32:38,347 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-23 05:32:38,348 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-23 05:32:38,348 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-23 05:32:38,348 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-11-23 05:32:38,349 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-23 05:32:38,349 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-23 05:32:38,349 INFO L133 SettingsManager]: * Use SBE=true [2018-11-23 05:32:38,349 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-23 05:32:38,349 INFO L133 SettingsManager]: * sizeof long=4 [2018-11-23 05:32:38,349 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-11-23 05:32:38,350 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-23 05:32:38,350 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-23 05:32:38,350 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-23 05:32:38,350 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-23 05:32:38,350 INFO L133 SettingsManager]: * Use bitvectors instead of ints=true [2018-11-23 05:32:38,350 INFO L133 SettingsManager]: * Memory model=HoenickeLindenmann_4ByteResolution [2018-11-23 05:32:38,350 INFO L133 SettingsManager]: * sizeof long double=12 [2018-11-23 05:32:38,350 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-23 05:32:38,351 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-23 05:32:38,351 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-23 05:32:38,351 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-23 05:32:38,351 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-23 05:32:38,351 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-23 05:32:38,351 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-23 05:32:38,351 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 05:32:38,352 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-23 05:32:38,352 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-23 05:32:38,352 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-23 05:32:38,352 INFO L133 SettingsManager]: * Trace refinement strategy=WOLF [2018-11-23 05:32:38,352 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-23 05:32:38,352 INFO L133 SettingsManager]: * Command for external solver=cvc4nyu --tear-down-incremental --rewrite-divk --print-success --lang smt [2018-11-23 05:32:38,352 INFO L133 SettingsManager]: * Logic for external solver=AUFBV [2018-11-23 05:32:38,352 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_0bcc5560-9368-4d8a-9bff-77d43d0a8e71/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> a69112b8d023c6203418abb04301ebe890b3a5f5 [2018-11-23 05:32:38,385 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-23 05:32:38,394 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-23 05:32:38,396 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-23 05:32:38,397 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-23 05:32:38,398 INFO L276 PluginConnector]: CDTParser initialized [2018-11-23 05:32:38,398 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_0bcc5560-9368-4d8a-9bff-77d43d0a8e71/bin-2019/uautomizer/../../sv-benchmarks/c/bitvector/interleave_bits_true-unreach-call_true-no-overflow.i [2018-11-23 05:32:38,436 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_0bcc5560-9368-4d8a-9bff-77d43d0a8e71/bin-2019/uautomizer/data/32af351e2/cfea6247ef364ed093513e0540828f03/FLAGc96248730 [2018-11-23 05:32:38,841 INFO L307 CDTParser]: Found 1 translation units. [2018-11-23 05:32:38,842 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_0bcc5560-9368-4d8a-9bff-77d43d0a8e71/sv-benchmarks/c/bitvector/interleave_bits_true-unreach-call_true-no-overflow.i [2018-11-23 05:32:38,845 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_0bcc5560-9368-4d8a-9bff-77d43d0a8e71/bin-2019/uautomizer/data/32af351e2/cfea6247ef364ed093513e0540828f03/FLAGc96248730 [2018-11-23 05:32:38,855 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_0bcc5560-9368-4d8a-9bff-77d43d0a8e71/bin-2019/uautomizer/data/32af351e2/cfea6247ef364ed093513e0540828f03 [2018-11-23 05:32:38,858 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-23 05:32:38,859 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-23 05:32:38,860 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-23 05:32:38,860 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-23 05:32:38,863 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-23 05:32:38,863 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 05:32:38" (1/1) ... [2018-11-23 05:32:38,866 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6c58243f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:32:38, skipping insertion in model container [2018-11-23 05:32:38,866 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 23.11 05:32:38" (1/1) ... [2018-11-23 05:32:38,874 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-23 05:32:38,891 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-23 05:32:39,014 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 05:32:39,017 INFO L191 MainTranslator]: Completed pre-run [2018-11-23 05:32:39,032 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-23 05:32:39,041 INFO L195 MainTranslator]: Completed translation [2018-11-23 05:32:39,041 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:32:39 WrapperNode [2018-11-23 05:32:39,041 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-23 05:32:39,042 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-23 05:32:39,042 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-23 05:32:39,042 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-23 05:32:39,050 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:32:39" (1/1) ... [2018-11-23 05:32:39,056 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:32:39" (1/1) ... [2018-11-23 05:32:39,062 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-23 05:32:39,062 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-23 05:32:39,062 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-23 05:32:39,062 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-23 05:32:39,069 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:32:39" (1/1) ... [2018-11-23 05:32:39,069 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:32:39" (1/1) ... [2018-11-23 05:32:39,070 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:32:39" (1/1) ... [2018-11-23 05:32:39,070 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:32:39" (1/1) ... [2018-11-23 05:32:39,075 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:32:39" (1/1) ... [2018-11-23 05:32:39,079 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:32:39" (1/1) ... [2018-11-23 05:32:39,079 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:32:39" (1/1) ... [2018-11-23 05:32:39,081 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-23 05:32:39,081 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-23 05:32:39,081 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-23 05:32:39,081 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-23 05:32:39,082 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:32:39" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0bcc5560-9368-4d8a-9bff-77d43d0a8e71/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-23 05:32:39,159 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-23 05:32:39,159 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-23 05:32:39,159 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-23 05:32:39,159 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-23 05:32:39,159 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-23 05:32:39,159 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-23 05:32:39,159 INFO L130 BoogieDeclarations]: Found specification of procedure __VERIFIER_assert [2018-11-23 05:32:39,159 INFO L138 BoogieDeclarations]: Found implementation of procedure __VERIFIER_assert [2018-11-23 05:32:39,277 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-23 05:32:39,277 INFO L280 CfgBuilder]: Removed 1 assue(true) statements. [2018-11-23 05:32:39,277 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 05:32:39 BoogieIcfgContainer [2018-11-23 05:32:39,278 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-23 05:32:39,278 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-23 05:32:39,278 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-23 05:32:39,281 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-23 05:32:39,281 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 23.11 05:32:38" (1/3) ... [2018-11-23 05:32:39,282 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@32356207 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 05:32:39, skipping insertion in model container [2018-11-23 05:32:39,282 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 23.11 05:32:39" (2/3) ... [2018-11-23 05:32:39,282 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@32356207 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 23.11 05:32:39, skipping insertion in model container [2018-11-23 05:32:39,283 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 05:32:39" (3/3) ... [2018-11-23 05:32:39,284 INFO L112 eAbstractionObserver]: Analyzing ICFG interleave_bits_true-unreach-call_true-no-overflow.i [2018-11-23 05:32:39,292 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-23 05:32:39,298 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-11-23 05:32:39,308 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-11-23 05:32:39,325 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-23 05:32:39,326 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-23 05:32:39,326 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-23 05:32:39,326 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-23 05:32:39,326 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-23 05:32:39,326 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-23 05:32:39,327 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-23 05:32:39,327 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-23 05:32:39,327 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-23 05:32:39,341 INFO L276 IsEmpty]: Start isEmpty. Operand 18 states. [2018-11-23 05:32:39,345 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2018-11-23 05:32:39,345 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:32:39,346 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:32:39,347 INFO L423 AbstractCegarLoop]: === Iteration 1 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:32:39,350 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:32:39,350 INFO L82 PathProgramCache]: Analyzing trace with hash -480905734, now seen corresponding path program 1 times [2018-11-23 05:32:39,353 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:32:39,353 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0bcc5560-9368-4d8a-9bff-77d43d0a8e71/bin-2019/uautomizer/cvc4nyu Starting monitored process 2 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:32:39,367 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:32:39,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:32:39,397 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:32:39,428 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:32:39,429 INFO L312 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2018-11-23 05:32:39,432 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-23 05:32:39,432 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-23 05:32:39,435 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-23 05:32:39,442 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-23 05:32:39,443 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 05:32:39,444 INFO L87 Difference]: Start difference. First operand 18 states. Second operand 3 states. [2018-11-23 05:32:39,465 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:32:39,466 INFO L93 Difference]: Finished difference Result 31 states and 36 transitions. [2018-11-23 05:32:39,466 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-23 05:32:39,467 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 11 [2018-11-23 05:32:39,467 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:32:39,472 INFO L225 Difference]: With dead ends: 31 [2018-11-23 05:32:39,472 INFO L226 Difference]: Without dead ends: 13 [2018-11-23 05:32:39,474 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 9 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-23 05:32:39,484 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13 states. [2018-11-23 05:32:39,494 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13 to 13. [2018-11-23 05:32:39,495 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13 states. [2018-11-23 05:32:39,495 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 13 transitions. [2018-11-23 05:32:39,496 INFO L78 Accepts]: Start accepts. Automaton has 13 states and 13 transitions. Word has length 11 [2018-11-23 05:32:39,496 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:32:39,497 INFO L480 AbstractCegarLoop]: Abstraction has 13 states and 13 transitions. [2018-11-23 05:32:39,497 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-23 05:32:39,497 INFO L276 IsEmpty]: Start isEmpty. Operand 13 states and 13 transitions. [2018-11-23 05:32:39,497 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2018-11-23 05:32:39,497 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:32:39,497 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:32:39,498 INFO L423 AbstractCegarLoop]: === Iteration 2 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:32:39,498 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:32:39,498 INFO L82 PathProgramCache]: Analyzing trace with hash -436122843, now seen corresponding path program 1 times [2018-11-23 05:32:39,499 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:32:39,499 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0bcc5560-9368-4d8a-9bff-77d43d0a8e71/bin-2019/uautomizer/cvc4nyu Starting monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:32:39,521 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-23 05:32:39,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-23 05:32:39,542 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:32:39,556 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:32:39,556 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 05:32:39,587 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:32:39,588 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:32:39,588 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 6 [2018-11-23 05:32:39,589 INFO L459 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-11-23 05:32:39,589 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-11-23 05:32:39,589 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-11-23 05:32:39,590 INFO L87 Difference]: Start difference. First operand 13 states and 13 transitions. Second operand 6 states. [2018-11-23 05:32:39,630 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:32:39,630 INFO L93 Difference]: Finished difference Result 22 states and 24 transitions. [2018-11-23 05:32:39,631 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-23 05:32:39,631 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 12 [2018-11-23 05:32:39,631 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:32:39,632 INFO L225 Difference]: With dead ends: 22 [2018-11-23 05:32:39,632 INFO L226 Difference]: Without dead ends: 16 [2018-11-23 05:32:39,633 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 19 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=23, Unknown=0, NotChecked=0, Total=42 [2018-11-23 05:32:39,633 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16 states. [2018-11-23 05:32:39,636 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16 to 16. [2018-11-23 05:32:39,636 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16 states. [2018-11-23 05:32:39,636 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16 states to 16 states and 16 transitions. [2018-11-23 05:32:39,636 INFO L78 Accepts]: Start accepts. Automaton has 16 states and 16 transitions. Word has length 12 [2018-11-23 05:32:39,637 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:32:39,637 INFO L480 AbstractCegarLoop]: Abstraction has 16 states and 16 transitions. [2018-11-23 05:32:39,637 INFO L481 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-11-23 05:32:39,637 INFO L276 IsEmpty]: Start isEmpty. Operand 16 states and 16 transitions. [2018-11-23 05:32:39,637 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2018-11-23 05:32:39,637 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:32:39,638 INFO L402 BasicCegarLoop]: trace histogram [4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:32:39,638 INFO L423 AbstractCegarLoop]: === Iteration 3 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:32:39,639 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:32:39,639 INFO L82 PathProgramCache]: Analyzing trace with hash -568891206, now seen corresponding path program 2 times [2018-11-23 05:32:39,640 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:32:39,640 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0bcc5560-9368-4d8a-9bff-77d43d0a8e71/bin-2019/uautomizer/cvc4nyu Starting monitored process 4 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:32:39,655 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2018-11-23 05:32:39,699 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-11-23 05:32:39,699 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 05:32:39,703 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:32:39,736 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:32:39,736 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 05:32:39,823 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:32:39,824 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:32:39,824 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 12 [2018-11-23 05:32:39,824 INFO L459 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-11-23 05:32:39,825 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-11-23 05:32:39,825 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=86, Unknown=0, NotChecked=0, Total=132 [2018-11-23 05:32:39,825 INFO L87 Difference]: Start difference. First operand 16 states and 16 transitions. Second operand 12 states. [2018-11-23 05:32:40,063 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:32:40,063 INFO L93 Difference]: Finished difference Result 28 states and 33 transitions. [2018-11-23 05:32:40,064 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-11-23 05:32:40,064 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 15 [2018-11-23 05:32:40,064 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:32:40,065 INFO L225 Difference]: With dead ends: 28 [2018-11-23 05:32:40,065 INFO L226 Difference]: Without dead ends: 22 [2018-11-23 05:32:40,065 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 33 GetRequests, 19 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=94, Invalid=146, Unknown=0, NotChecked=0, Total=240 [2018-11-23 05:32:40,066 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states. [2018-11-23 05:32:40,069 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 22. [2018-11-23 05:32:40,070 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22 states. [2018-11-23 05:32:40,070 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 22 transitions. [2018-11-23 05:32:40,070 INFO L78 Accepts]: Start accepts. Automaton has 22 states and 22 transitions. Word has length 15 [2018-11-23 05:32:40,071 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:32:40,071 INFO L480 AbstractCegarLoop]: Abstraction has 22 states and 22 transitions. [2018-11-23 05:32:40,071 INFO L481 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-11-23 05:32:40,071 INFO L276 IsEmpty]: Start isEmpty. Operand 22 states and 22 transitions. [2018-11-23 05:32:40,071 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2018-11-23 05:32:40,071 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:32:40,072 INFO L402 BasicCegarLoop]: trace histogram [10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:32:40,072 INFO L423 AbstractCegarLoop]: === Iteration 4 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:32:40,072 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:32:40,072 INFO L82 PathProgramCache]: Analyzing trace with hash -503267110, now seen corresponding path program 3 times [2018-11-23 05:32:40,072 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:32:40,072 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0bcc5560-9368-4d8a-9bff-77d43d0a8e71/bin-2019/uautomizer/cvc4nyu Starting monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:32:40,096 INFO L101 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2018-11-23 05:32:40,327 INFO L249 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2018-11-23 05:32:40,327 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 05:32:40,345 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:32:40,462 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:32:40,462 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 05:32:40,890 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:32:40,892 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:32:40,892 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13] total 24 [2018-11-23 05:32:40,892 INFO L459 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-11-23 05:32:40,892 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-11-23 05:32:40,893 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=161, Invalid=391, Unknown=0, NotChecked=0, Total=552 [2018-11-23 05:32:40,893 INFO L87 Difference]: Start difference. First operand 22 states and 22 transitions. Second operand 24 states. [2018-11-23 05:32:41,372 WARN L180 SmtUtils]: Spent 221.00 ms on a formula simplification. DAG size of input: 52 DAG size of output: 35 [2018-11-23 05:32:41,661 WARN L180 SmtUtils]: Spent 204.00 ms on a formula simplification. DAG size of input: 47 DAG size of output: 35 [2018-11-23 05:32:41,874 WARN L180 SmtUtils]: Spent 126.00 ms on a formula simplification. DAG size of input: 42 DAG size of output: 35 [2018-11-23 05:32:42,062 WARN L180 SmtUtils]: Spent 110.00 ms on a formula simplification. DAG size of input: 37 DAG size of output: 35 [2018-11-23 05:32:42,526 WARN L180 SmtUtils]: Spent 139.00 ms on a formula simplification that was a NOOP. DAG size: 54 [2018-11-23 05:32:42,855 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:32:42,855 INFO L93 Difference]: Finished difference Result 40 states and 51 transitions. [2018-11-23 05:32:42,855 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-11-23 05:32:42,855 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 21 [2018-11-23 05:32:42,856 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:32:42,856 INFO L225 Difference]: With dead ends: 40 [2018-11-23 05:32:42,856 INFO L226 Difference]: Without dead ends: 34 [2018-11-23 05:32:42,857 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 19 SyntacticMatches, 0 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 94 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=370, Invalid=820, Unknown=0, NotChecked=0, Total=1190 [2018-11-23 05:32:42,857 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34 states. [2018-11-23 05:32:42,864 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34 to 34. [2018-11-23 05:32:42,864 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 34 states. [2018-11-23 05:32:42,864 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34 states to 34 states and 35 transitions. [2018-11-23 05:32:42,865 INFO L78 Accepts]: Start accepts. Automaton has 34 states and 35 transitions. Word has length 21 [2018-11-23 05:32:42,865 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:32:42,865 INFO L480 AbstractCegarLoop]: Abstraction has 34 states and 35 transitions. [2018-11-23 05:32:42,865 INFO L481 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-11-23 05:32:42,865 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states and 35 transitions. [2018-11-23 05:32:42,866 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-11-23 05:32:42,866 INFO L394 BasicCegarLoop]: Found error trace [2018-11-23 05:32:42,866 INFO L402 BasicCegarLoop]: trace histogram [16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-23 05:32:42,866 INFO L423 AbstractCegarLoop]: === Iteration 5 === [__VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-23 05:32:42,866 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-23 05:32:42,866 INFO L82 PathProgramCache]: Analyzing trace with hash 1414496506, now seen corresponding path program 4 times [2018-11-23 05:32:42,867 INFO L223 ckRefinementStrategy]: Switched to mode CVC4_FPBP [2018-11-23 05:32:42,867 INFO L69 tionRefinementEngine]: Using refinement strategy WolfRefinementStrategy No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_0bcc5560-9368-4d8a-9bff-77d43d0a8e71/bin-2019/uautomizer/cvc4nyu Starting monitored process 6 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk [2018-11-23 05:32:42,879 INFO L101 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-11-23 05:32:43,023 INFO L249 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-11-23 05:32:43,023 INFO L250 tOrderPrioritization]: Conjunction of SSA is unsat [2018-11-23 05:32:43,052 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-23 05:32:44,140 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 0 proven. 136 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:32:44,141 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-11-23 05:34:20,440 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 120 proven. 16 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-23 05:34:20,442 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-23 05:34:20,442 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22] total 40 [2018-11-23 05:34:20,442 INFO L459 AbstractCegarLoop]: Interpolant automaton has 40 states [2018-11-23 05:34:20,443 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2018-11-23 05:34:20,443 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=320, Invalid=1239, Unknown=1, NotChecked=0, Total=1560 [2018-11-23 05:34:20,443 INFO L87 Difference]: Start difference. First operand 34 states and 35 transitions. Second operand 40 states. [2018-11-23 05:34:27,699 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-23 05:34:27,700 INFO L93 Difference]: Finished difference Result 34 states and 35 transitions. [2018-11-23 05:34:27,700 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-11-23 05:34:27,700 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 27 [2018-11-23 05:34:27,700 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-23 05:34:27,700 INFO L225 Difference]: With dead ends: 34 [2018-11-23 05:34:27,701 INFO L226 Difference]: Without dead ends: 0 [2018-11-23 05:34:27,701 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 55 GetRequests, 13 SyntacticMatches, 2 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 49 ImplicationChecksByTransitivity, 97.9s TimeCoverageRelationStatistics Valid=346, Invalid=1375, Unknown=1, NotChecked=0, Total=1722 [2018-11-23 05:34:27,701 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 0 states. [2018-11-23 05:34:27,702 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 0 to 0. [2018-11-23 05:34:27,702 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 0 states. [2018-11-23 05:34:27,702 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 0 states to 0 states and 0 transitions. [2018-11-23 05:34:27,702 INFO L78 Accepts]: Start accepts. Automaton has 0 states and 0 transitions. Word has length 27 [2018-11-23 05:34:27,703 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-23 05:34:27,703 INFO L480 AbstractCegarLoop]: Abstraction has 0 states and 0 transitions. [2018-11-23 05:34:27,703 INFO L481 AbstractCegarLoop]: Interpolant automaton has 40 states. [2018-11-23 05:34:27,703 INFO L276 IsEmpty]: Start isEmpty. Operand 0 states and 0 transitions. [2018-11-23 05:34:27,704 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-11-23 05:34:27,707 INFO L343 DoubleDeckerVisitor]: Before removal of dead ends 0 states and 0 transitions. [2018-11-23 05:34:29,356 WARN L180 SmtUtils]: Spent 1.53 s on a formula simplification. DAG size of input: 257 DAG size of output: 208 [2018-11-23 05:34:29,629 WARN L180 SmtUtils]: Spent 270.00 ms on a formula simplification that was a NOOP. DAG size: 207 [2018-11-23 05:34:29,631 INFO L451 ceAbstractionStarter]: At program point ULTIMATE.initFINAL(line -1) the Hoare annotation is: true [2018-11-23 05:34:29,631 INFO L448 ceAbstractionStarter]: For program point ULTIMATE.initEXIT(line -1) no Hoare annotation was computed. [2018-11-23 05:34:29,631 INFO L448 ceAbstractionStarter]: For program point ULTIMATE.startEXIT(line -1) no Hoare annotation was computed. [2018-11-23 05:34:29,631 INFO L451 ceAbstractionStarter]: At program point L-1(line -1) the Hoare annotation is: true [2018-11-23 05:34:29,631 INFO L451 ceAbstractionStarter]: At program point ULTIMATE.startENTRY(line -1) the Hoare annotation is: true [2018-11-23 05:34:29,632 INFO L448 ceAbstractionStarter]: For program point ULTIMATE.startFINAL(line -1) no Hoare annotation was computed. [2018-11-23 05:34:29,632 INFO L451 ceAbstractionStarter]: At program point mainENTRY(lines 21 48) the Hoare annotation is: true [2018-11-23 05:34:29,632 INFO L444 ceAbstractionStarter]: At program point L30-2(lines 30 33) the Hoare annotation is: (let ((.cse7 ((_ zero_extend 16) main_~x~0)) (.cse8 ((_ zero_extend 16) main_~y~0))) (let ((.cse12 (bvor (_ bv0 32) (bvor (bvshl (bvand .cse7 (_ bv1 32)) (_ bv0 32)) (bvshl (bvand .cse8 (_ bv1 32)) (_ bv1 32)))))) (let ((.cse14 (bvor .cse12 (bvor (bvshl (bvand .cse7 (_ bv2 32)) (_ bv1 32)) (bvshl (bvand .cse8 (_ bv2 32)) (_ bv2 32)))))) (let ((.cse10 (bvor .cse14 (bvor (bvshl (bvand .cse7 (_ bv4 32)) (_ bv2 32)) (bvshl (bvand .cse8 (_ bv4 32)) (_ bv3 32)))))) (let ((.cse6 (bvor .cse10 (bvor (bvshl (bvand .cse7 (_ bv8 32)) (_ bv3 32)) (bvshl (bvand .cse8 (_ bv8 32)) (_ bv4 32)))))) (let ((.cse0 (bvor .cse6 (bvor (bvshl (bvand .cse7 (_ bv16 32)) (_ bv4 32)) (bvshl (bvand .cse8 (_ bv16 32)) (_ bv5 32)))))) (let ((.cse2 (bvor (bvor .cse0 (bvor (bvshl (bvand .cse7 (_ bv32 32)) (_ bv5 32)) (bvshl (bvand .cse8 (_ bv32 32)) (_ bv6 32)))) (bvor (bvshl (bvand .cse7 (_ bv64 32)) (_ bv6 32)) (bvshl (bvand .cse8 (_ bv64 32)) (_ bv7 32)))))) (let ((.cse9 (bvor (bvor .cse2 (bvor (bvshl (bvand .cse7 (_ bv128 32)) (_ bv7 32)) (bvshl (bvand .cse8 (_ bv128 32)) (_ bv8 32)))) (bvor (bvshl (bvand .cse7 (_ bv256 32)) (_ bv8 32)) (bvshl (bvand .cse8 (_ bv256 32)) (_ bv9 32)))))) (let ((.cse11 (bvor .cse9 (bvor (bvshl (bvand .cse7 (_ bv512 32)) (_ bv9 32)) (bvshl (bvand .cse8 (_ bv512 32)) (_ bv10 32)))))) (let ((.cse3 (bvor (bvor .cse11 (bvor (bvshl (bvand .cse7 (_ bv1024 32)) (_ bv10 32)) (bvshl (bvand .cse8 (_ bv1024 32)) (_ bv11 32)))) (bvor (bvshl (bvand .cse7 (_ bv2048 32)) (_ bv11 32)) (bvshl (bvand .cse8 (_ bv2048 32)) (_ bv12 32)))))) (let ((.cse13 (bvadd main_~i~0 (_ bv4294967295 32))) (.cse4 (bvor .cse3 (bvor (bvshl (bvand .cse7 (_ bv4096 32)) (_ bv12 32)) (bvshl (bvand .cse8 (_ bv4096 32)) (_ bv13 32)))))) (let ((.cse5 (bvor .cse4 (bvor (bvshl (bvand .cse7 (_ bv8192 32)) (_ bv13 32)) (bvshl (bvand .cse8 (_ bv8192 32)) (_ bv14 32))))) (.cse1 (let ((.cse15 (bvshl (_ bv1 32) .cse13))) (bvor (bvshl (bvand .cse7 .cse15) .cse13) (bvshl (bvand .cse8 .cse15) main_~i~0))))) (or (and (= (_ bv6 32) main_~i~0) (= main_~z~0 (bvor .cse0 .cse1))) (and (= main_~z~0 .cse2) (= (bvadd main_~i~0 (_ bv4294967289 32)) (_ bv0 32))) (and (= main_~z~0 .cse3) (= (bvadd main_~i~0 (_ bv4294967284 32)) (_ bv0 32))) (and (= .cse4 main_~z~0) (= (bvadd main_~i~0 (_ bv4294967283 32)) (_ bv0 32))) (and (= main_~z~0 .cse5) (= (bvadd main_~i~0 (_ bv4294967282 32)) (_ bv0 32))) (and (= .cse0 main_~z~0) (= (bvadd main_~i~0 (_ bv4294967291 32)) (_ bv0 32))) (and (= main_~z~0 .cse6) (= (bvadd main_~i~0 (_ bv4294967292 32)) (_ bv0 32))) (= (bvor (bvor .cse5 (bvor (bvshl (bvand .cse7 (_ bv16384 32)) (_ bv14 32)) (bvshl (bvand .cse8 (_ bv16384 32)) (_ bv15 32)))) (bvor (bvshl (bvand .cse7 (_ bv32768 32)) (_ bv15 32)) (bvshl (bvand .cse8 (_ bv32768 32)) (_ bv16 32)))) main_~z~0) (and (= main_~z~0 (_ bv0 32)) (= main_~i~0 (_ bv0 32))) (and (= (bvadd main_~i~0 (_ bv4294967287 32)) (_ bv0 32)) (= main_~z~0 .cse9)) (and (= main_~z~0 .cse10) (= (bvadd main_~i~0 (_ bv4294967293 32)) (_ bv0 32))) (and (= main_~z~0 .cse11) (= (_ bv10 32) main_~i~0)) (and (= main_~z~0 .cse12) (= .cse13 (_ bv0 32))) (and (= (_ bv11 32) main_~i~0) (= main_~z~0 (bvor .cse11 .cse1))) (and (= (bvor .cse5 .cse1) main_~z~0) (= (_ bv15 32) main_~i~0)) (and (= (bvor .cse2 .cse1) main_~z~0) (= (_ bv8 32) main_~i~0)) (and (= main_~z~0 .cse14) (= (_ bv2 32) main_~i~0))))))))))))))) [2018-11-23 05:34:29,632 INFO L448 ceAbstractionStarter]: For program point L30-3(lines 30 33) no Hoare annotation was computed. [2018-11-23 05:34:29,632 INFO L448 ceAbstractionStarter]: For program point mainEXIT(lines 21 48) no Hoare annotation was computed. [2018-11-23 05:34:29,633 INFO L444 ceAbstractionStarter]: At program point L47(line 47) the Hoare annotation is: (let ((.cse1 (bvult (bvadd main_~i~0 (_ bv7 32)) (_ bv16 32))) (.cse2 (bvult (bvadd main_~i~0 (_ bv8 32)) (_ bv16 32))) (.cse0 (bvult (bvadd main_~i~0 (_ bv6 32)) (_ bv16 32))) (.cse8 (bvult (bvadd main_~i~0 (_ bv5 32)) (_ bv16 32))) (.cse17 (bvult (bvadd main_~i~0 (_ bv4 32)) (_ bv16 32))) (.cse7 (bvult (bvadd main_~i~0 (_ bv1 32)) (_ bv16 32))) (.cse3 (bvult (bvadd main_~i~0 (_ bv9 32)) (_ bv16 32))) (.cse6 (bvult (bvadd main_~i~0 (_ bv2 32)) (_ bv16 32))) (.cse18 (bvult (bvadd main_~i~0 (_ bv3 32)) (_ bv16 32)))) (and (or (not .cse0) .cse1) (or (not .cse1) .cse2) (or .cse3 (not .cse2)) (= (let ((.cse4 ((_ zero_extend 16) main_~x~0)) (.cse5 ((_ zero_extend 16) main_~y~0))) (bvor (bvor (bvor (bvor (bvor (bvor (bvor (bvor (bvor (bvor (bvor (bvor (bvor (bvor (bvor (bvor (_ bv0 32) (bvor (bvshl (bvand .cse4 (_ bv1 32)) (_ bv0 32)) (bvshl (bvand .cse5 (_ bv1 32)) (_ bv1 32)))) (bvor (bvshl (bvand .cse4 (_ bv2 32)) (_ bv1 32)) (bvshl (bvand .cse5 (_ bv2 32)) (_ bv2 32)))) (bvor (bvshl (bvand .cse4 (_ bv4 32)) (_ bv2 32)) (bvshl (bvand .cse5 (_ bv4 32)) (_ bv3 32)))) (bvor (bvshl (bvand .cse4 (_ bv8 32)) (_ bv3 32)) (bvshl (bvand .cse5 (_ bv8 32)) (_ bv4 32)))) (bvor (bvshl (bvand .cse4 (_ bv16 32)) (_ bv4 32)) (bvshl (bvand .cse5 (_ bv16 32)) (_ bv5 32)))) (bvor (bvshl (bvand .cse4 (_ bv32 32)) (_ bv5 32)) (bvshl (bvand .cse5 (_ bv32 32)) (_ bv6 32)))) (bvor (bvshl (bvand .cse4 (_ bv64 32)) (_ bv6 32)) (bvshl (bvand .cse5 (_ bv64 32)) (_ bv7 32)))) (bvor (bvshl (bvand .cse4 (_ bv128 32)) (_ bv7 32)) (bvshl (bvand .cse5 (_ bv128 32)) (_ bv8 32)))) (bvor (bvshl (bvand .cse4 (_ bv256 32)) (_ bv8 32)) (bvshl (bvand .cse5 (_ bv256 32)) (_ bv9 32)))) (bvor (bvshl (bvand .cse4 (_ bv512 32)) (_ bv9 32)) (bvshl (bvand .cse5 (_ bv512 32)) (_ bv10 32)))) (bvor (bvshl (bvand .cse4 (_ bv1024 32)) (_ bv10 32)) (bvshl (bvand .cse5 (_ bv1024 32)) (_ bv11 32)))) (bvor (bvshl (bvand .cse4 (_ bv2048 32)) (_ bv11 32)) (bvshl (bvand .cse5 (_ bv2048 32)) (_ bv12 32)))) (bvor (bvshl (bvand .cse4 (_ bv4096 32)) (_ bv12 32)) (bvshl (bvand .cse5 (_ bv4096 32)) (_ bv13 32)))) (bvor (bvshl (bvand .cse4 (_ bv8192 32)) (_ bv13 32)) (bvshl (bvand .cse5 (_ bv8192 32)) (_ bv14 32)))) (bvor (bvshl (bvand .cse4 (_ bv16384 32)) (_ bv14 32)) (bvshl (bvand .cse5 (_ bv16384 32)) (_ bv15 32)))) (bvor (bvshl (bvand .cse4 (_ bv32768 32)) (_ bv15 32)) (bvshl (bvand .cse5 (_ bv32768 32)) (_ bv16 32))))) main_~z~0) (or .cse6 (not .cse7)) (or .cse0 (not .cse8)) (exists ((main_~y~0 (_ BitVec 16)) (main_~x~0 (_ BitVec 16))) (let ((.cse12 ((_ zero_extend 16) main_~x~0)) (.cse16 ((_ zero_extend 16) main_~y~0))) (and (= (bvor (bvand (_ bv1431655765 32) (let ((.cse9 (bvand (_ bv858993459 32) (let ((.cse10 (bvand (_ bv252645135 32) (let ((.cse11 (bvand (_ bv16711935 32) (bvor .cse12 (bvshl .cse12 (_ bv8 32)))))) (bvor .cse11 (bvshl .cse11 (_ bv4 32))))))) (bvor .cse10 (bvshl .cse10 (_ bv2 32))))))) (bvor .cse9 (bvshl .cse9 (_ bv1 32))))) (bvshl (bvand (_ bv1431655765 32) (let ((.cse13 (bvand (_ bv858993459 32) (let ((.cse14 (bvand (_ bv252645135 32) (let ((.cse15 (bvand (_ bv16711935 32) (bvor .cse16 (bvshl .cse16 (_ bv8 32)))))) (bvor .cse15 (bvshl .cse15 (_ bv4 32))))))) (bvor .cse14 (bvshl .cse14 (_ bv2 32))))))) (bvor .cse13 (bvshl .cse13 (_ bv1 32))))) (_ bv1 32))) main_~zz~0) (= (bvor (bvor (bvor (bvor (bvor (bvor (bvor (bvor (bvor (bvor (bvor (bvor (bvor (bvor (bvor (bvor (_ bv0 32) (bvor (bvshl (bvand .cse12 (_ bv1 32)) (_ bv0 32)) (bvshl (bvand .cse16 (_ bv1 32)) (_ bv1 32)))) (bvor (bvshl (bvand .cse12 (_ bv2 32)) (_ bv1 32)) (bvshl (bvand .cse16 (_ bv2 32)) (_ bv2 32)))) (bvor (bvshl (bvand .cse12 (_ bv4 32)) (_ bv2 32)) (bvshl (bvand .cse16 (_ bv4 32)) (_ bv3 32)))) (bvor (bvshl (bvand .cse12 (_ bv8 32)) (_ bv3 32)) (bvshl (bvand .cse16 (_ bv8 32)) (_ bv4 32)))) (bvor (bvshl (bvand .cse12 (_ bv16 32)) (_ bv4 32)) (bvshl (bvand .cse16 (_ bv16 32)) (_ bv5 32)))) (bvor (bvshl (bvand .cse12 (_ bv32 32)) (_ bv5 32)) (bvshl (bvand .cse16 (_ bv32 32)) (_ bv6 32)))) (bvor (bvshl (bvand .cse12 (_ bv64 32)) (_ bv6 32)) (bvshl (bvand .cse16 (_ bv64 32)) (_ bv7 32)))) (bvor (bvshl (bvand .cse12 (_ bv128 32)) (_ bv7 32)) (bvshl (bvand .cse16 (_ bv128 32)) (_ bv8 32)))) (bvor (bvshl (bvand .cse12 (_ bv256 32)) (_ bv8 32)) (bvshl (bvand .cse16 (_ bv256 32)) (_ bv9 32)))) (bvor (bvshl (bvand .cse12 (_ bv512 32)) (_ bv9 32)) (bvshl (bvand .cse16 (_ bv512 32)) (_ bv10 32)))) (bvor (bvshl (bvand .cse12 (_ bv1024 32)) (_ bv10 32)) (bvshl (bvand .cse16 (_ bv1024 32)) (_ bv11 32)))) (bvor (bvshl (bvand .cse12 (_ bv2048 32)) (_ bv11 32)) (bvshl (bvand .cse16 (_ bv2048 32)) (_ bv12 32)))) (bvor (bvshl (bvand .cse12 (_ bv4096 32)) (_ bv12 32)) (bvshl (bvand .cse16 (_ bv4096 32)) (_ bv13 32)))) (bvor (bvshl (bvand .cse12 (_ bv8192 32)) (_ bv13 32)) (bvshl (bvand .cse16 (_ bv8192 32)) (_ bv14 32)))) (bvor (bvshl (bvand .cse12 (_ bv16384 32)) (_ bv14 32)) (bvshl (bvand .cse16 (_ bv16384 32)) (_ bv15 32)))) (bvor (bvshl (bvand .cse12 (_ bv32768 32)) (_ bv15 32)) (bvshl (bvand .cse16 (_ bv32768 32)) (_ bv16 32)))) main_~z~0)))) (or .cse8 (not .cse17)) (or (not .cse18) .cse17) (or .cse7 (not (bvult main_~i~0 (_ bv16 32)))) (or (bvult (bvadd main_~i~0 (_ bv10 32)) (_ bv16 32)) (not .cse3)) (or (not .cse6) .cse18))) [2018-11-23 05:34:29,633 INFO L448 ceAbstractionStarter]: For program point mainFINAL(lines 21 48) no Hoare annotation was computed. [2018-11-23 05:34:29,634 INFO L451 ceAbstractionStarter]: At program point __VERIFIER_assertENTRY(lines 4 9) the Hoare annotation is: true [2018-11-23 05:34:29,634 INFO L448 ceAbstractionStarter]: For program point __VERIFIER_assertEXIT(lines 4 9) no Hoare annotation was computed. [2018-11-23 05:34:29,634 INFO L448 ceAbstractionStarter]: For program point __VERIFIER_assertErr0ASSERT_VIOLATIONERROR_FUNCTION(line 6) no Hoare annotation was computed. [2018-11-23 05:34:29,634 INFO L448 ceAbstractionStarter]: For program point L6(line 6) no Hoare annotation was computed. [2018-11-23 05:34:29,634 INFO L448 ceAbstractionStarter]: For program point L5(lines 5 7) no Hoare annotation was computed. [2018-11-23 05:34:29,634 INFO L448 ceAbstractionStarter]: For program point L5-2(lines 4 9) no Hoare annotation was computed. [2018-11-23 05:34:29,662 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 23.11 05:34:29 BoogieIcfgContainer [2018-11-23 05:34:29,662 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-11-23 05:34:29,663 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-23 05:34:29,663 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-23 05:34:29,663 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-23 05:34:29,664 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 23.11 05:32:39" (3/4) ... [2018-11-23 05:34:29,667 INFO L144 WitnessPrinter]: Generating witness for correct program [2018-11-23 05:34:29,672 INFO L354 RCFGBacktranslator]: Ignoring RootEdge to procedure ULTIMATE.init [2018-11-23 05:34:29,672 INFO L354 RCFGBacktranslator]: Ignoring RootEdge to procedure main [2018-11-23 05:34:29,672 INFO L354 RCFGBacktranslator]: Ignoring RootEdge to procedure __VERIFIER_assert [2018-11-23 05:34:29,675 INFO L879 BoogieBacktranslator]: Reduced CFG by removing 7 nodes and edges [2018-11-23 05:34:29,675 INFO L879 BoogieBacktranslator]: Reduced CFG by removing 2 nodes and edges [2018-11-23 05:34:29,675 INFO L879 BoogieBacktranslator]: Reduced CFG by removing 1 nodes and edges [2018-11-23 05:34:29,713 INFO L145 WitnessManager]: Wrote witness to /tmp/vcloud-vcloud-master/worker/working_dir_0bcc5560-9368-4d8a-9bff-77d43d0a8e71/bin-2019/uautomizer/witness.graphml [2018-11-23 05:34:29,713 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-23 05:34:29,714 INFO L168 Benchmark]: Toolchain (without parser) took 110855.16 ms. Allocated memory was 1.0 GB in the beginning and 1.3 GB in the end (delta: 261.6 MB). Free memory was 949.7 MB in the beginning and 1.2 GB in the end (delta: -232.6 MB). Peak memory consumption was 29.0 MB. Max. memory is 11.5 GB. [2018-11-23 05:34:29,714 INFO L168 Benchmark]: CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 978.7 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-23 05:34:29,714 INFO L168 Benchmark]: CACSL2BoogieTranslator took 181.84 ms. Allocated memory is still 1.0 GB. Free memory was 949.7 MB in the beginning and 937.9 MB in the end (delta: 11.8 MB). Peak memory consumption was 11.8 MB. Max. memory is 11.5 GB. [2018-11-23 05:34:29,715 INFO L168 Benchmark]: Boogie Procedure Inliner took 20.08 ms. Allocated memory is still 1.0 GB. Free memory is still 932.5 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-23 05:34:29,715 INFO L168 Benchmark]: Boogie Preprocessor took 18.76 ms. Allocated memory is still 1.0 GB. Free memory is still 932.5 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-23 05:34:29,715 INFO L168 Benchmark]: RCFGBuilder took 196.55 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 140.5 MB). Free memory was 932.5 MB in the beginning and 1.1 GB in the end (delta: -184.0 MB). Peak memory consumption was 14.9 MB. Max. memory is 11.5 GB. [2018-11-23 05:34:29,716 INFO L168 Benchmark]: TraceAbstraction took 110384.29 ms. Allocated memory was 1.2 GB in the beginning and 1.3 GB in the end (delta: 121.1 MB). Free memory was 1.1 GB in the beginning and 1.2 GB in the end (delta: -74.8 MB). Peak memory consumption was 454.2 MB. Max. memory is 11.5 GB. [2018-11-23 05:34:29,716 INFO L168 Benchmark]: Witness Printer took 50.07 ms. Allocated memory is still 1.3 GB. Free memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 9.0 MB). Peak memory consumption was 9.0 MB. Max. memory is 11.5 GB. [2018-11-23 05:34:29,720 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.15 ms. Allocated memory is still 1.0 GB. Free memory is still 978.7 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 181.84 ms. Allocated memory is still 1.0 GB. Free memory was 949.7 MB in the beginning and 937.9 MB in the end (delta: 11.8 MB). Peak memory consumption was 11.8 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 20.08 ms. Allocated memory is still 1.0 GB. Free memory is still 932.5 MB. There was no memory consumed. Max. memory is 11.5 GB. * Boogie Preprocessor took 18.76 ms. Allocated memory is still 1.0 GB. Free memory is still 932.5 MB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 196.55 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 140.5 MB). Free memory was 932.5 MB in the beginning and 1.1 GB in the end (delta: -184.0 MB). Peak memory consumption was 14.9 MB. Max. memory is 11.5 GB. * TraceAbstraction took 110384.29 ms. Allocated memory was 1.2 GB in the beginning and 1.3 GB in the end (delta: 121.1 MB). Free memory was 1.1 GB in the beginning and 1.2 GB in the end (delta: -74.8 MB). Peak memory consumption was 454.2 MB. Max. memory is 11.5 GB. * Witness Printer took 50.07 ms. Allocated memory is still 1.3 GB. Free memory was 1.2 GB in the beginning and 1.2 GB in the end (delta: 9.0 MB). Peak memory consumption was 9.0 MB. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - PositiveResult [Line: 6]: call of __VERIFIER_error() unreachable For all program executions holds that call of __VERIFIER_error() unreachable at this location - AllSpecificationsHoldResult: All specifications hold 1 specifications checked. All of them hold - InvariantResult [Line: 30]: Loop Invariant Derived loop invariant: ((((((((((((((((6bv32 == i && z == ~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(0bv32, ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 1bv32), 0bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 1bv32), 1bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 2bv32), 1bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 2bv32), 2bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 4bv32), 2bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 4bv32), 3bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 8bv32), 3bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 8bv32), 4bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 16bv32), 4bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 16bv32), 5bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), ~bvshl32(1bv32, ~bvadd64(i, 4294967295bv32))), ~bvadd64(i, 4294967295bv32)), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), ~bvshl32(1bv32, ~bvadd64(i, 4294967295bv32))), i)))) || (z == ~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(0bv32, ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 1bv32), 0bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 1bv32), 1bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 2bv32), 1bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 2bv32), 2bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 4bv32), 2bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 4bv32), 3bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 8bv32), 3bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 8bv32), 4bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 16bv32), 4bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 16bv32), 5bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 32bv32), 5bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 32bv32), 6bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 64bv32), 6bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 64bv32), 7bv32))) && ~bvadd64(i, 4294967289bv32) == 0bv32)) || (z == ~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(0bv32, ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 1bv32), 0bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 1bv32), 1bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 2bv32), 1bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 2bv32), 2bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 4bv32), 2bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 4bv32), 3bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 8bv32), 3bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 8bv32), 4bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 16bv32), 4bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 16bv32), 5bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 32bv32), 5bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 32bv32), 6bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 64bv32), 6bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 64bv32), 7bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 128bv32), 7bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 128bv32), 8bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 256bv32), 8bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 256bv32), 9bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 512bv32), 9bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 512bv32), 10bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 1024bv32), 10bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 1024bv32), 11bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 2048bv32), 11bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 2048bv32), 12bv32))) && ~bvadd64(i, 4294967284bv32) == 0bv32)) || (~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(0bv32, ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 1bv32), 0bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 1bv32), 1bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 2bv32), 1bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 2bv32), 2bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 4bv32), 2bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 4bv32), 3bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 8bv32), 3bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 8bv32), 4bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 16bv32), 4bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 16bv32), 5bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 32bv32), 5bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 32bv32), 6bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 64bv32), 6bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 64bv32), 7bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 128bv32), 7bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 128bv32), 8bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 256bv32), 8bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 256bv32), 9bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 512bv32), 9bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 512bv32), 10bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 1024bv32), 10bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 1024bv32), 11bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 2048bv32), 11bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 2048bv32), 12bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 4096bv32), 12bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 4096bv32), 13bv32))) == z && ~bvadd64(i, 4294967283bv32) == 0bv32)) || (z == ~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(0bv32, ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 1bv32), 0bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 1bv32), 1bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 2bv32), 1bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 2bv32), 2bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 4bv32), 2bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 4bv32), 3bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 8bv32), 3bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 8bv32), 4bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 16bv32), 4bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 16bv32), 5bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 32bv32), 5bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 32bv32), 6bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 64bv32), 6bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 64bv32), 7bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 128bv32), 7bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 128bv32), 8bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 256bv32), 8bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 256bv32), 9bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 512bv32), 9bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 512bv32), 10bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 1024bv32), 10bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 1024bv32), 11bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 2048bv32), 11bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 2048bv32), 12bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 4096bv32), 12bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 4096bv32), 13bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 8192bv32), 13bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 8192bv32), 14bv32))) && ~bvadd64(i, 4294967282bv32) == 0bv32)) || (~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(0bv32, ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 1bv32), 0bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 1bv32), 1bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 2bv32), 1bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 2bv32), 2bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 4bv32), 2bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 4bv32), 3bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 8bv32), 3bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 8bv32), 4bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 16bv32), 4bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 16bv32), 5bv32))) == z && ~bvadd64(i, 4294967291bv32) == 0bv32)) || (z == ~bvor32(~bvor32(~bvor32(~bvor32(0bv32, ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 1bv32), 0bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 1bv32), 1bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 2bv32), 1bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 2bv32), 2bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 4bv32), 2bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 4bv32), 3bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 8bv32), 3bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 8bv32), 4bv32))) && ~bvadd64(i, 4294967292bv32) == 0bv32)) || ~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(0bv32, ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 1bv32), 0bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 1bv32), 1bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 2bv32), 1bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 2bv32), 2bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 4bv32), 2bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 4bv32), 3bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 8bv32), 3bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 8bv32), 4bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 16bv32), 4bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 16bv32), 5bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 32bv32), 5bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 32bv32), 6bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 64bv32), 6bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 64bv32), 7bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 128bv32), 7bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 128bv32), 8bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 256bv32), 8bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 256bv32), 9bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 512bv32), 9bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 512bv32), 10bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 1024bv32), 10bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 1024bv32), 11bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 2048bv32), 11bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 2048bv32), 12bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 4096bv32), 12bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 4096bv32), 13bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 8192bv32), 13bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 8192bv32), 14bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 16384bv32), 14bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 16384bv32), 15bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 32768bv32), 15bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 32768bv32), 16bv32))) == z) || (z == 0bv32 && i == 0bv32)) || (~bvadd64(i, 4294967287bv32) == 0bv32 && z == ~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(0bv32, ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 1bv32), 0bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 1bv32), 1bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 2bv32), 1bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 2bv32), 2bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 4bv32), 2bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 4bv32), 3bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 8bv32), 3bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 8bv32), 4bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 16bv32), 4bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 16bv32), 5bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 32bv32), 5bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 32bv32), 6bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 64bv32), 6bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 64bv32), 7bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 128bv32), 7bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 128bv32), 8bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 256bv32), 8bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 256bv32), 9bv32))))) || (z == ~bvor32(~bvor32(~bvor32(0bv32, ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 1bv32), 0bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 1bv32), 1bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 2bv32), 1bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 2bv32), 2bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 4bv32), 2bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 4bv32), 3bv32))) && ~bvadd64(i, 4294967293bv32) == 0bv32)) || (z == ~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(0bv32, ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 1bv32), 0bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 1bv32), 1bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 2bv32), 1bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 2bv32), 2bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 4bv32), 2bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 4bv32), 3bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 8bv32), 3bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 8bv32), 4bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 16bv32), 4bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 16bv32), 5bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 32bv32), 5bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 32bv32), 6bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 64bv32), 6bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 64bv32), 7bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 128bv32), 7bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 128bv32), 8bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 256bv32), 8bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 256bv32), 9bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 512bv32), 9bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 512bv32), 10bv32))) && 10bv32 == i)) || (z == ~bvor32(0bv32, ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 1bv32), 0bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 1bv32), 1bv32))) && ~bvadd64(i, 4294967295bv32) == 0bv32)) || (11bv32 == i && z == ~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(0bv32, ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 1bv32), 0bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 1bv32), 1bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 2bv32), 1bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 2bv32), 2bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 4bv32), 2bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 4bv32), 3bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 8bv32), 3bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 8bv32), 4bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 16bv32), 4bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 16bv32), 5bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 32bv32), 5bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 32bv32), 6bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 64bv32), 6bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 64bv32), 7bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 128bv32), 7bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 128bv32), 8bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 256bv32), 8bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 256bv32), 9bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 512bv32), 9bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 512bv32), 10bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), ~bvshl32(1bv32, ~bvadd64(i, 4294967295bv32))), ~bvadd64(i, 4294967295bv32)), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), ~bvshl32(1bv32, ~bvadd64(i, 4294967295bv32))), i))))) || (~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(0bv32, ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 1bv32), 0bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 1bv32), 1bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 2bv32), 1bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 2bv32), 2bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 4bv32), 2bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 4bv32), 3bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 8bv32), 3bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 8bv32), 4bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 16bv32), 4bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 16bv32), 5bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 32bv32), 5bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 32bv32), 6bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 64bv32), 6bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 64bv32), 7bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 128bv32), 7bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 128bv32), 8bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 256bv32), 8bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 256bv32), 9bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 512bv32), 9bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 512bv32), 10bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 1024bv32), 10bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 1024bv32), 11bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 2048bv32), 11bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 2048bv32), 12bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 4096bv32), 12bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 4096bv32), 13bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 8192bv32), 13bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 8192bv32), 14bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), ~bvshl32(1bv32, ~bvadd64(i, 4294967295bv32))), ~bvadd64(i, 4294967295bv32)), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), ~bvshl32(1bv32, ~bvadd64(i, 4294967295bv32))), i))) == z && 15bv32 == i)) || (~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(~bvor32(0bv32, ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 1bv32), 0bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 1bv32), 1bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 2bv32), 1bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 2bv32), 2bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 4bv32), 2bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 4bv32), 3bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 8bv32), 3bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 8bv32), 4bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 16bv32), 4bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 16bv32), 5bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 32bv32), 5bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 32bv32), 6bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 64bv32), 6bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 64bv32), 7bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), ~bvshl32(1bv32, ~bvadd64(i, 4294967295bv32))), ~bvadd64(i, 4294967295bv32)), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), ~bvshl32(1bv32, ~bvadd64(i, 4294967295bv32))), i))) == z && 8bv32 == i)) || (z == ~bvor32(~bvor32(0bv32, ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 1bv32), 0bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 1bv32), 1bv32))), ~bvor32(~bvshl32(~bvand32(~zero_extendFrom16To32(x), 2bv32), 1bv32), ~bvshl32(~bvand32(~zero_extendFrom16To32(y), 2bv32), 2bv32))) && 2bv32 == i) - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 18 locations, 1 error locations. SAFE Result, 110.3s OverallTime, 5 OverallIterations, 16 TraceHistogramMax, 9.5s AutomataDifference, 0.0s DeadEndRemovalTime, 1.9s HoareAnnotationTime, HoareTripleCheckerStatistics: 56 SDtfs, 19 SDslu, 334 SDs, 0 SdLazy, 614 SolverSat, 63 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 6.5s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 174 GetRequests, 79 SyntacticMatches, 2 SemanticMatches, 93 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 149 ImplicationChecksByTransitivity, 100.4s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=34occurred in iteration=4, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.0s AutomataMinimizationTime, 5 MinimizatonAttempts, 0 StatesRemovedByMinimization, 0 NontrivialMinimizations, HoareAnnotationStatistics: 0.0s HoareAnnotationTime, 7 LocationsWithAnnotation, 11 PreInvPairs, 34 NumberOfFragments, 2877 HoareAnnotationTreeSize, 11 FomulaSimplifications, 1461 FormulaSimplificationTreeSizeReduction, 0.1s HoareSimplificationTime, 7 FomulaSimplificationsInter, 399 FormulaSimplificationTreeSizeReductionInter, 1.8s HoareSimplificationTimeInter, RefinementEngineStatistics: TraceCheckStatistics: 0.0s SsaConstructionTime, 0.4s SatisfiabilityAnalysisTime, 98.1s InterpolantComputationTime, 86 NumberOfCodeBlocks, 86 NumberOfCodeBlocksAsserted, 11 NumberOfCheckSat, 152 ConstructedInterpolants, 1 QuantifiedInterpolants, 256852 SizeOfPredicates, 12 NumberOfNonLiveVariables, 213 ConjunctsInSsa, 63 ConjunctsInUnsatCore, 9 InterpolantComputations, 1 PerfectInterpolantSequences, 120/404 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be correct! Received shutdown request...