./Ultimate.py --spec ../../sv-benchmarks/c/properties/unreach-call.prp --file ../../sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.c --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for ERROR reachability Using default analysis Version aa418289 Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_a120b706-34a0-496a-9c2e-0ef43eb2ceb0/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_a120b706-34a0-496a-9c2e-0ef43eb2ceb0/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_a120b706-34a0-496a-9c2e-0ef43eb2ceb0/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_a120b706-34a0-496a-9c2e-0ef43eb2ceb0/bin-2019/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.c -s /tmp/vcloud-vcloud-master/worker/working_dir_a120b706-34a0-496a-9c2e-0ef43eb2ceb0/bin-2019/uautomizer/config/svcomp-Reach-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_a120b706-34a0-496a-9c2e-0ef43eb2ceb0/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 62bcb163bcd8d8adcc467bfe735fb02012bcbb37 ........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ Execution finished normally Using bit-precise analysis Retrying with bit-precise analysis Calling Ultimate with: java -Dosgi.configuration.area=/tmp/vcloud-vcloud-master/worker/working_dir_a120b706-34a0-496a-9c2e-0ef43eb2ceb0/bin-2019/uautomizer/data/config -Xmx12G -Xms1G -jar /tmp/vcloud-vcloud-master/worker/working_dir_a120b706-34a0-496a-9c2e-0ef43eb2ceb0/bin-2019/uautomizer/plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata /tmp/vcloud-vcloud-master/worker/working_dir_a120b706-34a0-496a-9c2e-0ef43eb2ceb0/bin-2019/uautomizer/data -tc /tmp/vcloud-vcloud-master/worker/working_dir_a120b706-34a0-496a-9c2e-0ef43eb2ceb0/bin-2019/uautomizer/config/AutomizerReach.xml -i ../../sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.c -s /tmp/vcloud-vcloud-master/worker/working_dir_a120b706-34a0-496a-9c2e-0ef43eb2ceb0/bin-2019/uautomizer/config/svcomp-Reach-64bit-Automizer_Bitvector.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud-vcloud-master/worker/working_dir_a120b706-34a0-496a-9c2e-0ef43eb2ceb0/bin-2019/uautomizer --witnessprinter.witness.filename witness.graphml --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 62bcb163bcd8d8adcc467bfe735fb02012bcbb37 ....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... Execution finished normally Writing output log to file Ultimate.log Result: UNKNOWN: Overapproximated counterexample --- Real Ultimate output --- This is Ultimate 0.1.23-aa41828 [2018-11-22 23:39:52,926 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-11-22 23:39:52,928 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-11-22 23:39:52,935 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-11-22 23:39:52,935 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-11-22 23:39:52,936 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-11-22 23:39:52,937 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-11-22 23:39:52,938 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-11-22 23:39:52,939 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-11-22 23:39:52,939 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-11-22 23:39:52,940 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-11-22 23:39:52,940 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-11-22 23:39:52,941 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-11-22 23:39:52,941 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-11-22 23:39:52,942 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-11-22 23:39:52,943 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-11-22 23:39:52,943 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-11-22 23:39:52,944 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-11-22 23:39:52,946 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-11-22 23:39:52,947 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-11-22 23:39:52,948 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-11-22 23:39:52,948 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-11-22 23:39:52,950 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-11-22 23:39:52,950 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-11-22 23:39:52,950 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-11-22 23:39:52,951 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-11-22 23:39:52,952 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-11-22 23:39:52,952 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-11-22 23:39:52,953 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-11-22 23:39:52,954 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-11-22 23:39:52,954 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-11-22 23:39:52,954 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-11-22 23:39:52,954 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-11-22 23:39:52,954 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-11-22 23:39:52,955 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-11-22 23:39:52,956 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-11-22 23:39:52,956 INFO L98 SettingsManager]: Beginning loading settings from /tmp/vcloud-vcloud-master/worker/working_dir_a120b706-34a0-496a-9c2e-0ef43eb2ceb0/bin-2019/uautomizer/config/svcomp-Reach-64bit-Automizer_Default.epf [2018-11-22 23:39:52,966 INFO L110 SettingsManager]: Loading preferences was successful [2018-11-22 23:39:52,966 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-11-22 23:39:52,966 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-11-22 23:39:52,967 INFO L133 SettingsManager]: * ... calls to implemented procedures=ONLY_FOR_CONCURRENT_PROGRAMS [2018-11-22 23:39:52,967 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-11-22 23:39:52,967 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-11-22 23:39:52,967 INFO L133 SettingsManager]: * Use SBE=true [2018-11-22 23:39:52,968 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-11-22 23:39:52,968 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-11-22 23:39:52,968 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-11-22 23:39:52,968 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-11-22 23:39:52,968 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-11-22 23:39:52,968 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-11-22 23:39:52,968 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-11-22 23:39:52,969 INFO L133 SettingsManager]: * Use constant arrays=true [2018-11-22 23:39:52,969 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-11-22 23:39:52,969 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-11-22 23:39:52,969 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-11-22 23:39:52,969 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-11-22 23:39:52,969 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-11-22 23:39:52,970 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-22 23:39:52,970 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-11-22 23:39:52,970 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-11-22 23:39:52,970 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-11-22 23:39:52,970 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-11-22 23:39:52,970 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-11-22 23:39:52,970 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-11-22 23:39:52,971 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-11-22 23:39:52,971 INFO L133 SettingsManager]: * To the following directory=dump/ Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud-vcloud-master/worker/working_dir_a120b706-34a0-496a-9c2e-0ef43eb2ceb0/bin-2019/uautomizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness.graphml Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(G ! call(__VERIFIER_error())) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 62bcb163bcd8d8adcc467bfe735fb02012bcbb37 [2018-11-22 23:39:52,994 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-11-22 23:39:53,003 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-11-22 23:39:53,006 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-11-22 23:39:53,007 INFO L271 PluginConnector]: Initializing CDTParser... [2018-11-22 23:39:53,007 INFO L276 PluginConnector]: CDTParser initialized [2018-11-22 23:39:53,008 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud-vcloud-master/worker/working_dir_a120b706-34a0-496a-9c2e-0ef43eb2ceb0/bin-2019/uautomizer/../../sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.c [2018-11-22 23:39:53,051 INFO L221 CDTParser]: Created temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_a120b706-34a0-496a-9c2e-0ef43eb2ceb0/bin-2019/uautomizer/data/441382586/27070be4a094491b8221e08298533328/FLAG74835a53e [2018-11-22 23:39:53,474 INFO L307 CDTParser]: Found 1 translation units. [2018-11-22 23:39:53,475 INFO L161 CDTParser]: Scanning /tmp/vcloud-vcloud-master/worker/working_dir_a120b706-34a0-496a-9c2e-0ef43eb2ceb0/sv-benchmarks/c/ldv-validator-v0.6/linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.c [2018-11-22 23:39:53,491 INFO L355 CDTParser]: About to delete temporary CDT project at /tmp/vcloud-vcloud-master/worker/working_dir_a120b706-34a0-496a-9c2e-0ef43eb2ceb0/bin-2019/uautomizer/data/441382586/27070be4a094491b8221e08298533328/FLAG74835a53e [2018-11-22 23:39:53,503 INFO L363 CDTParser]: Successfully deleted /tmp/vcloud-vcloud-master/worker/working_dir_a120b706-34a0-496a-9c2e-0ef43eb2ceb0/bin-2019/uautomizer/data/441382586/27070be4a094491b8221e08298533328 [2018-11-22 23:39:53,505 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-11-22 23:39:53,507 INFO L131 ToolchainWalker]: Walking toolchain with 6 elements. [2018-11-22 23:39:53,507 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-11-22 23:39:53,507 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-11-22 23:39:53,510 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-11-22 23:39:53,511 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 22.11 11:39:53" (1/1) ... [2018-11-22 23:39:53,513 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2c2a9b77 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 11:39:53, skipping insertion in model container [2018-11-22 23:39:53,513 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 22.11 11:39:53" (1/1) ... [2018-11-22 23:39:53,521 INFO L145 MainTranslator]: Starting translation in SV-COMP mode [2018-11-22 23:39:53,572 INFO L176 MainTranslator]: Built tables and reachable declarations [2018-11-22 23:39:54,107 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-22 23:39:54,122 INFO L191 MainTranslator]: Completed pre-run [2018-11-22 23:39:54,221 INFO L201 PostProcessor]: Analyzing one entry point: main [2018-11-22 23:39:54,268 INFO L195 MainTranslator]: Completed translation [2018-11-22 23:39:54,269 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 11:39:54 WrapperNode [2018-11-22 23:39:54,269 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-11-22 23:39:54,269 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-11-22 23:39:54,269 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-11-22 23:39:54,270 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-11-22 23:39:54,277 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 11:39:54" (1/1) ... [2018-11-22 23:39:54,306 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 11:39:54" (1/1) ... [2018-11-22 23:39:54,317 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-11-22 23:39:54,317 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-11-22 23:39:54,318 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-11-22 23:39:54,318 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-11-22 23:39:54,327 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 11:39:54" (1/1) ... [2018-11-22 23:39:54,328 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 11:39:54" (1/1) ... [2018-11-22 23:39:54,334 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 11:39:54" (1/1) ... [2018-11-22 23:39:54,335 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 11:39:54" (1/1) ... [2018-11-22 23:39:54,361 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 11:39:54" (1/1) ... [2018-11-22 23:39:54,367 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 11:39:54" (1/1) ... [2018-11-22 23:39:54,372 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 11:39:54" (1/1) ... [2018-11-22 23:39:54,378 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-11-22 23:39:54,378 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-11-22 23:39:54,378 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-11-22 23:39:54,378 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-11-22 23:39:54,379 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 11:39:54" (1/1) ... No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a120b706-34a0-496a-9c2e-0ef43eb2ceb0/bin-2019/uautomizer/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-11-22 23:39:54,437 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_suspend [2018-11-22 23:39:54,437 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_suspend [2018-11-22 23:39:54,437 INFO L130 BoogieDeclarations]: Found specification of procedure dev_get_drvdata [2018-11-22 23:39:54,438 INFO L130 BoogieDeclarations]: Found specification of procedure platform_driver_unregister [2018-11-22 23:39:54,438 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-11-22 23:39:54,438 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_initialize_platform_driver_2 [2018-11-22 23:39:54,438 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_initialize_platform_driver_2 [2018-11-22 23:39:54,438 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_stop [2018-11-22 23:39:54,438 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_stop [2018-11-22 23:39:54,438 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_initialize [2018-11-22 23:39:54,439 INFO L130 BoogieDeclarations]: Found specification of procedure read~int [2018-11-22 23:39:54,439 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.meminit [2018-11-22 23:39:54,439 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.meminit [2018-11-22 23:39:54,439 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_time_to_tm [2018-11-22 23:39:54,439 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_proc [2018-11-22 23:39:54,439 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_proc [2018-11-22 23:39:54,439 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_read_alarm [2018-11-22 23:39:54,439 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_read_alarm [2018-11-22 23:39:54,440 INFO L130 BoogieDeclarations]: Found specification of procedure irq_set_irq_wake [2018-11-22 23:39:54,440 INFO L130 BoogieDeclarations]: Found specification of procedure outer_sync [2018-11-22 23:39:54,440 INFO L138 BoogieDeclarations]: Found implementation of procedure outer_sync [2018-11-22 23:39:54,440 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_remove [2018-11-22 23:39:54,440 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_remove [2018-11-22 23:39:54,440 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_shutdown [2018-11-22 23:39:54,440 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_shutdown [2018-11-22 23:39:54,440 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_tm_to_time [2018-11-22 23:39:54,441 INFO L130 BoogieDeclarations]: Found specification of procedure __release_region [2018-11-22 23:39:54,441 INFO L130 BoogieDeclarations]: Found specification of procedure kfree [2018-11-22 23:39:54,441 INFO L130 BoogieDeclarations]: Found specification of procedure free_irq [2018-11-22 23:39:54,441 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_set_alarm [2018-11-22 23:39:54,441 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_set_alarm [2018-11-22 23:39:54,441 INFO L130 BoogieDeclarations]: Found specification of procedure write~int [2018-11-22 23:39:54,441 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_error [2018-11-22 23:39:54,441 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_error [2018-11-22 23:39:54,442 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_release_3 [2018-11-22 23:39:54,442 INFO L130 BoogieDeclarations]: Found specification of procedure disable_suitable_irq_1 [2018-11-22 23:39:54,442 INFO L138 BoogieDeclarations]: Found implementation of procedure disable_suitable_irq_1 [2018-11-22 23:39:54,442 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_lock_check [2018-11-22 23:39:54,442 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_lock_check [2018-11-22 23:39:54,442 INFO L130 BoogieDeclarations]: Found specification of procedure kobject_name [2018-11-22 23:39:54,442 INFO L138 BoogieDeclarations]: Found implementation of procedure kobject_name [2018-11-22 23:39:54,442 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_alarm_irq_enable [2018-11-22 23:39:54,443 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_alarm_irq_enable [2018-11-22 23:39:54,443 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset [2018-11-22 23:39:54,443 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset [2018-11-22 23:39:54,443 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_iounmap [2018-11-22 23:39:54,443 INFO L130 BoogieDeclarations]: Found specification of procedure platform_driver_probe [2018-11-22 23:39:54,443 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_valid_tm [2018-11-22 23:39:54,443 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_resume [2018-11-22 23:39:54,443 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_resume [2018-11-22 23:39:54,444 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-11-22 23:39:54,444 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-11-22 23:39:54,444 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_check_busy [2018-11-22 23:39:54,444 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_check_busy [2018-11-22 23:39:54,444 INFO L130 BoogieDeclarations]: Found specification of procedure ##fun~~TO~VOID [2018-11-22 23:39:54,444 INFO L138 BoogieDeclarations]: Found implementation of procedure ##fun~~TO~VOID [2018-11-22 23:39:54,444 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_rtc_device_unregister_27 [2018-11-22 23:39:54,444 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_rtc_device_unregister_27 [2018-11-22 23:39:54,444 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_update_irq [2018-11-22 23:39:54,445 INFO L130 BoogieDeclarations]: Found specification of procedure rtc_device_unregister [2018-11-22 23:39:54,445 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-11-22 23:39:54,445 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-11-22 23:39:54,445 INFO L130 BoogieDeclarations]: Found specification of procedure __const_udelay [2018-11-22 23:39:54,445 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_irq_handler [2018-11-22 23:39:54,445 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_irq_handler [2018-11-22 23:39:54,445 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_irq_1 [2018-11-22 23:39:54,445 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_irq_1 [2018-11-22 23:39:54,445 INFO L130 BoogieDeclarations]: Found specification of procedure _raw_spin_unlock_irqrestore [2018-11-22 23:39:54,446 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2018-11-22 23:39:54,446 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_spin_unlock_irqrestore_9 [2018-11-22 23:39:54,446 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_spin_unlock_irqrestore_9 [2018-11-22 23:39:54,446 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_free_irq_26 [2018-11-22 23:39:54,446 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_free_irq_26 [2018-11-22 23:39:54,446 INFO L130 BoogieDeclarations]: Found specification of procedure device_may_wakeup [2018-11-22 23:39:54,446 INFO L138 BoogieDeclarations]: Found implementation of procedure device_may_wakeup [2018-11-22 23:39:54,446 INFO L130 BoogieDeclarations]: Found specification of procedure spin_unlock_irqrestore [2018-11-22 23:39:54,447 INFO L138 BoogieDeclarations]: Found implementation of procedure spin_unlock_irqrestore [2018-11-22 23:39:54,447 INFO L130 BoogieDeclarations]: Found specification of procedure platform_get_resource [2018-11-22 23:39:54,447 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-11-22 23:39:54,447 INFO L130 BoogieDeclarations]: Found specification of procedure dev_set_drvdata [2018-11-22 23:39:54,447 INFO L130 BoogieDeclarations]: Found specification of procedure platform_set_drvdata [2018-11-22 23:39:54,447 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_set_drvdata [2018-11-22 23:39:54,447 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~$Pointer$ [2018-11-22 23:39:54,447 INFO L130 BoogieDeclarations]: Found specification of procedure platform_get_drvdata [2018-11-22 23:39:54,447 INFO L138 BoogieDeclarations]: Found implementation of procedure platform_get_drvdata [2018-11-22 23:39:54,448 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_init [2018-11-22 23:39:54,448 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_init [2018-11-22 23:39:54,448 INFO L130 BoogieDeclarations]: Found specification of procedure disable_irq_wake [2018-11-22 23:39:54,448 INFO L138 BoogieDeclarations]: Found implementation of procedure disable_irq_wake [2018-11-22 23:39:54,448 INFO L130 BoogieDeclarations]: Found specification of procedure enable_irq_wake [2018-11-22 23:39:54,448 INFO L138 BoogieDeclarations]: Found implementation of procedure enable_irq_wake [2018-11-22 23:39:54,448 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_read_time [2018-11-22 23:39:54,448 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_read_time [2018-11-22 23:39:54,449 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_exit [2018-11-22 23:39:54,449 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_exit [2018-11-22 23:39:54,449 INFO L130 BoogieDeclarations]: Found specification of procedure choose_interrupt_1 [2018-11-22 23:39:54,449 INFO L138 BoogieDeclarations]: Found implementation of procedure choose_interrupt_1 [2018-11-22 23:39:54,449 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_wait_while_busy [2018-11-22 23:39:54,449 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_wait_while_busy [2018-11-22 23:39:54,449 INFO L130 BoogieDeclarations]: Found specification of procedure dev_name [2018-11-22 23:39:54,449 INFO L138 BoogieDeclarations]: Found implementation of procedure dev_name [2018-11-22 23:39:54,449 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int [2018-11-22 23:39:54,450 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_probe_3 [2018-11-22 23:39:54,450 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_probe_2 [2018-11-22 23:39:54,450 INFO L130 BoogieDeclarations]: Found specification of procedure resource_size [2018-11-22 23:39:54,450 INFO L138 BoogieDeclarations]: Found implementation of procedure resource_size [2018-11-22 23:39:54,450 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_check_final_state [2018-11-22 23:39:54,450 INFO L130 BoogieDeclarations]: Found specification of procedure ldv_zalloc [2018-11-22 23:39:54,450 INFO L138 BoogieDeclarations]: Found implementation of procedure ldv_zalloc [2018-11-22 23:39:54,450 INFO L130 BoogieDeclarations]: Found specification of procedure tegra_rtc_set_time [2018-11-22 23:39:54,451 INFO L138 BoogieDeclarations]: Found implementation of procedure tegra_rtc_set_time [2018-11-22 23:39:54,451 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-11-22 23:39:54,451 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-11-22 23:39:55,436 INFO L275 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-11-22 23:39:55,436 INFO L280 CfgBuilder]: Removed 0 assue(true) statements. [2018-11-22 23:39:55,436 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.11 11:39:55 BoogieIcfgContainer [2018-11-22 23:39:55,436 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-11-22 23:39:55,437 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-11-22 23:39:55,437 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-11-22 23:39:55,440 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-11-22 23:39:55,440 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 22.11 11:39:53" (1/3) ... [2018-11-22 23:39:55,441 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@ec5c662 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 22.11 11:39:55, skipping insertion in model container [2018-11-22 23:39:55,441 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 22.11 11:39:54" (2/3) ... [2018-11-22 23:39:55,441 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@ec5c662 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 22.11 11:39:55, skipping insertion in model container [2018-11-22 23:39:55,441 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.11 11:39:55" (3/3) ... [2018-11-22 23:39:55,443 INFO L112 eAbstractionObserver]: Analyzing ICFG linux-stable-9ec4f65-1-110_1a-drivers--rtc--rtc-tegra.ko-entry_point_false-unreach-call.cil.out.c [2018-11-22 23:39:55,452 INFO L156 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-11-22 23:39:55,458 INFO L168 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-11-22 23:39:55,470 INFO L257 AbstractCegarLoop]: Starting to check reachability of 1 error locations. [2018-11-22 23:39:55,496 INFO L133 ementStrategyFactory]: Using default assertion order modulation [2018-11-22 23:39:55,497 INFO L382 AbstractCegarLoop]: Interprodecural is true [2018-11-22 23:39:55,497 INFO L383 AbstractCegarLoop]: Hoare is true [2018-11-22 23:39:55,497 INFO L384 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-11-22 23:39:55,497 INFO L385 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-11-22 23:39:55,497 INFO L386 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-11-22 23:39:55,497 INFO L387 AbstractCegarLoop]: Difference is false [2018-11-22 23:39:55,498 INFO L388 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-11-22 23:39:55,498 INFO L393 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-11-22 23:39:55,519 INFO L276 IsEmpty]: Start isEmpty. Operand 361 states. [2018-11-22 23:39:55,530 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-11-22 23:39:55,530 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 23:39:55,531 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 23:39:55,533 INFO L423 AbstractCegarLoop]: === Iteration 1 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 23:39:55,537 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 23:39:55,538 INFO L82 PathProgramCache]: Analyzing trace with hash 597331850, now seen corresponding path program 1 times [2018-11-22 23:39:55,539 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 23:39:55,539 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 23:39:55,582 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:39:55,583 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 23:39:55,583 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:39:55,677 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 23:39:55,776 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 23:39:55,778 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 23:39:55,778 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-22 23:39:55,782 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-22 23:39:55,793 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-22 23:39:55,793 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 23:39:55,795 INFO L87 Difference]: Start difference. First operand 361 states. Second operand 3 states. [2018-11-22 23:39:55,865 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 23:39:55,865 INFO L93 Difference]: Finished difference Result 610 states and 812 transitions. [2018-11-22 23:39:55,865 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-22 23:39:55,866 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 34 [2018-11-22 23:39:55,867 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 23:39:55,875 INFO L225 Difference]: With dead ends: 610 [2018-11-22 23:39:55,875 INFO L226 Difference]: Without dead ends: 247 [2018-11-22 23:39:55,880 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 23:39:55,892 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 247 states. [2018-11-22 23:39:55,923 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 247 to 247. [2018-11-22 23:39:55,924 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 247 states. [2018-11-22 23:39:55,926 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 247 states to 247 states and 312 transitions. [2018-11-22 23:39:55,927 INFO L78 Accepts]: Start accepts. Automaton has 247 states and 312 transitions. Word has length 34 [2018-11-22 23:39:55,929 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 23:39:55,929 INFO L480 AbstractCegarLoop]: Abstraction has 247 states and 312 transitions. [2018-11-22 23:39:55,929 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-22 23:39:55,929 INFO L276 IsEmpty]: Start isEmpty. Operand 247 states and 312 transitions. [2018-11-22 23:39:55,932 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-11-22 23:39:55,932 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 23:39:55,932 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 23:39:55,932 INFO L423 AbstractCegarLoop]: === Iteration 2 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 23:39:55,933 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 23:39:55,933 INFO L82 PathProgramCache]: Analyzing trace with hash -59782313, now seen corresponding path program 1 times [2018-11-22 23:39:55,933 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 23:39:55,933 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 23:39:55,936 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:39:55,936 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 23:39:55,937 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:39:55,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 23:39:56,066 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 23:39:56,067 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 23:39:56,067 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-22 23:39:56,069 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-22 23:39:56,069 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-22 23:39:56,069 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-22 23:39:56,069 INFO L87 Difference]: Start difference. First operand 247 states and 312 transitions. Second operand 5 states. [2018-11-22 23:39:56,175 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 23:39:56,175 INFO L93 Difference]: Finished difference Result 724 states and 933 transitions. [2018-11-22 23:39:56,176 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-11-22 23:39:56,176 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 47 [2018-11-22 23:39:56,176 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 23:39:56,180 INFO L225 Difference]: With dead ends: 724 [2018-11-22 23:39:56,180 INFO L226 Difference]: Without dead ends: 491 [2018-11-22 23:39:56,182 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-11-22 23:39:56,183 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 491 states. [2018-11-22 23:39:56,216 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 491 to 478. [2018-11-22 23:39:56,216 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 478 states. [2018-11-22 23:39:56,218 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 478 states to 478 states and 611 transitions. [2018-11-22 23:39:56,219 INFO L78 Accepts]: Start accepts. Automaton has 478 states and 611 transitions. Word has length 47 [2018-11-22 23:39:56,219 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 23:39:56,219 INFO L480 AbstractCegarLoop]: Abstraction has 478 states and 611 transitions. [2018-11-22 23:39:56,219 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-22 23:39:56,219 INFO L276 IsEmpty]: Start isEmpty. Operand 478 states and 611 transitions. [2018-11-22 23:39:56,221 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-11-22 23:39:56,221 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 23:39:56,221 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 23:39:56,221 INFO L423 AbstractCegarLoop]: === Iteration 3 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 23:39:56,222 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 23:39:56,222 INFO L82 PathProgramCache]: Analyzing trace with hash -1368063503, now seen corresponding path program 1 times [2018-11-22 23:39:56,222 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 23:39:56,222 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 23:39:56,224 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:39:56,225 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 23:39:56,225 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:39:56,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 23:39:56,309 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 23:39:56,309 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 23:39:56,309 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-22 23:39:56,309 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-22 23:39:56,310 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-22 23:39:56,310 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-22 23:39:56,310 INFO L87 Difference]: Start difference. First operand 478 states and 611 transitions. Second operand 5 states. [2018-11-22 23:39:56,381 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 23:39:56,382 INFO L93 Difference]: Finished difference Result 958 states and 1239 transitions. [2018-11-22 23:39:56,382 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-22 23:39:56,382 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 48 [2018-11-22 23:39:56,383 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 23:39:56,385 INFO L225 Difference]: With dead ends: 958 [2018-11-22 23:39:56,385 INFO L226 Difference]: Without dead ends: 494 [2018-11-22 23:39:56,387 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-11-22 23:39:56,388 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 494 states. [2018-11-22 23:39:56,412 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 494 to 482. [2018-11-22 23:39:56,412 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 482 states. [2018-11-22 23:39:56,414 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 482 states to 482 states and 611 transitions. [2018-11-22 23:39:56,415 INFO L78 Accepts]: Start accepts. Automaton has 482 states and 611 transitions. Word has length 48 [2018-11-22 23:39:56,415 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 23:39:56,415 INFO L480 AbstractCegarLoop]: Abstraction has 482 states and 611 transitions. [2018-11-22 23:39:56,415 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-22 23:39:56,415 INFO L276 IsEmpty]: Start isEmpty. Operand 482 states and 611 transitions. [2018-11-22 23:39:56,417 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-11-22 23:39:56,417 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 23:39:56,417 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 23:39:56,417 INFO L423 AbstractCegarLoop]: === Iteration 4 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 23:39:56,417 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 23:39:56,418 INFO L82 PathProgramCache]: Analyzing trace with hash -1953733175, now seen corresponding path program 1 times [2018-11-22 23:39:56,418 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 23:39:56,418 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 23:39:56,420 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:39:56,420 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 23:39:56,420 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:39:56,441 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 23:39:56,473 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 23:39:56,474 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 23:39:56,474 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-22 23:39:56,474 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-22 23:39:56,474 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-22 23:39:56,475 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 23:39:56,475 INFO L87 Difference]: Start difference. First operand 482 states and 611 transitions. Second operand 3 states. [2018-11-22 23:39:56,552 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 23:39:56,552 INFO L93 Difference]: Finished difference Result 1141 states and 1450 transitions. [2018-11-22 23:39:56,552 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-22 23:39:56,552 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 45 [2018-11-22 23:39:56,553 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 23:39:56,556 INFO L225 Difference]: With dead ends: 1141 [2018-11-22 23:39:56,556 INFO L226 Difference]: Without dead ends: 673 [2018-11-22 23:39:56,558 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 23:39:56,559 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 673 states. [2018-11-22 23:39:56,590 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 673 to 670. [2018-11-22 23:39:56,590 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 670 states. [2018-11-22 23:39:56,593 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 670 states to 670 states and 851 transitions. [2018-11-22 23:39:56,594 INFO L78 Accepts]: Start accepts. Automaton has 670 states and 851 transitions. Word has length 45 [2018-11-22 23:39:56,594 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 23:39:56,594 INFO L480 AbstractCegarLoop]: Abstraction has 670 states and 851 transitions. [2018-11-22 23:39:56,594 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-22 23:39:56,595 INFO L276 IsEmpty]: Start isEmpty. Operand 670 states and 851 transitions. [2018-11-22 23:39:56,595 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 50 [2018-11-22 23:39:56,595 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 23:39:56,596 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 23:39:56,596 INFO L423 AbstractCegarLoop]: === Iteration 5 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 23:39:56,596 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 23:39:56,596 INFO L82 PathProgramCache]: Analyzing trace with hash -1115579532, now seen corresponding path program 1 times [2018-11-22 23:39:56,596 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 23:39:56,596 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 23:39:56,598 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:39:56,598 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 23:39:56,599 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:39:56,616 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 23:39:56,702 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 23:39:56,702 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 23:39:56,702 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-22 23:39:56,703 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-22 23:39:56,703 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-22 23:39:56,703 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-22 23:39:56,703 INFO L87 Difference]: Start difference. First operand 670 states and 851 transitions. Second operand 5 states. [2018-11-22 23:39:56,803 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 23:39:56,803 INFO L93 Difference]: Finished difference Result 1349 states and 1729 transitions. [2018-11-22 23:39:56,804 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-22 23:39:56,804 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 49 [2018-11-22 23:39:56,804 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 23:39:56,807 INFO L225 Difference]: With dead ends: 1349 [2018-11-22 23:39:56,807 INFO L226 Difference]: Without dead ends: 702 [2018-11-22 23:39:56,809 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-11-22 23:39:56,810 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 702 states. [2018-11-22 23:39:56,839 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 702 to 678. [2018-11-22 23:39:56,839 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 678 states. [2018-11-22 23:39:56,842 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 678 states to 678 states and 853 transitions. [2018-11-22 23:39:56,842 INFO L78 Accepts]: Start accepts. Automaton has 678 states and 853 transitions. Word has length 49 [2018-11-22 23:39:56,843 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 23:39:56,843 INFO L480 AbstractCegarLoop]: Abstraction has 678 states and 853 transitions. [2018-11-22 23:39:56,843 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-22 23:39:56,843 INFO L276 IsEmpty]: Start isEmpty. Operand 678 states and 853 transitions. [2018-11-22 23:39:56,844 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-11-22 23:39:56,844 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 23:39:56,844 INFO L402 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 23:39:56,844 INFO L423 AbstractCegarLoop]: === Iteration 6 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 23:39:56,844 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 23:39:56,844 INFO L82 PathProgramCache]: Analyzing trace with hash 275984174, now seen corresponding path program 1 times [2018-11-22 23:39:56,844 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 23:39:56,845 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 23:39:56,847 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:39:56,847 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 23:39:56,847 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:39:56,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 23:39:56,903 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-11-22 23:39:56,904 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 23:39:56,904 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-11-22 23:39:56,904 INFO L459 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-11-22 23:39:56,904 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-11-22 23:39:56,904 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-11-22 23:39:56,905 INFO L87 Difference]: Start difference. First operand 678 states and 853 transitions. Second operand 5 states. [2018-11-22 23:39:56,972 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 23:39:56,973 INFO L93 Difference]: Finished difference Result 1292 states and 1641 transitions. [2018-11-22 23:39:56,973 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-11-22 23:39:56,973 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 50 [2018-11-22 23:39:56,973 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 23:39:56,976 INFO L225 Difference]: With dead ends: 1292 [2018-11-22 23:39:56,976 INFO L226 Difference]: Without dead ends: 637 [2018-11-22 23:39:56,978 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 3 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-11-22 23:39:56,979 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 637 states. [2018-11-22 23:39:57,003 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 637 to 619. [2018-11-22 23:39:57,003 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 619 states. [2018-11-22 23:39:57,005 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 619 states to 619 states and 771 transitions. [2018-11-22 23:39:57,006 INFO L78 Accepts]: Start accepts. Automaton has 619 states and 771 transitions. Word has length 50 [2018-11-22 23:39:57,006 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 23:39:57,006 INFO L480 AbstractCegarLoop]: Abstraction has 619 states and 771 transitions. [2018-11-22 23:39:57,006 INFO L481 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-11-22 23:39:57,006 INFO L276 IsEmpty]: Start isEmpty. Operand 619 states and 771 transitions. [2018-11-22 23:39:57,007 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-11-22 23:39:57,007 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 23:39:57,007 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 23:39:57,007 INFO L423 AbstractCegarLoop]: === Iteration 7 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 23:39:57,008 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 23:39:57,008 INFO L82 PathProgramCache]: Analyzing trace with hash -627832725, now seen corresponding path program 1 times [2018-11-22 23:39:57,008 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 23:39:57,008 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 23:39:57,009 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:39:57,010 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 23:39:57,010 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:39:57,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 23:39:57,111 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 1 proven. 4 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-11-22 23:39:57,111 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-22 23:39:57,111 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a120b706-34a0-496a-9c2e-0ef43eb2ceb0/bin-2019/uautomizer/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-22 23:39:57,125 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 23:39:57,231 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 23:39:57,240 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 23:39:57,277 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-11-22 23:39:57,303 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-11-22 23:39:57,303 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [9] total 11 [2018-11-22 23:39:57,303 INFO L459 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-11-22 23:39:57,303 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-11-22 23:39:57,304 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=91, Unknown=0, NotChecked=0, Total=110 [2018-11-22 23:39:57,304 INFO L87 Difference]: Start difference. First operand 619 states and 771 transitions. Second operand 11 states. [2018-11-22 23:39:58,959 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 23:39:58,959 INFO L93 Difference]: Finished difference Result 1687 states and 2176 transitions. [2018-11-22 23:39:58,959 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-11-22 23:39:58,959 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 62 [2018-11-22 23:39:58,960 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 23:39:58,962 INFO L225 Difference]: With dead ends: 1687 [2018-11-22 23:39:58,962 INFO L226 Difference]: Without dead ends: 1088 [2018-11-22 23:39:58,963 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 88 GetRequests, 66 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 65 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=116, Invalid=436, Unknown=0, NotChecked=0, Total=552 [2018-11-22 23:39:58,964 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1088 states. [2018-11-22 23:39:58,994 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1088 to 879. [2018-11-22 23:39:58,994 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 879 states. [2018-11-22 23:39:58,996 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 879 states to 879 states and 1099 transitions. [2018-11-22 23:39:58,997 INFO L78 Accepts]: Start accepts. Automaton has 879 states and 1099 transitions. Word has length 62 [2018-11-22 23:39:58,997 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 23:39:58,997 INFO L480 AbstractCegarLoop]: Abstraction has 879 states and 1099 transitions. [2018-11-22 23:39:58,997 INFO L481 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-11-22 23:39:58,997 INFO L276 IsEmpty]: Start isEmpty. Operand 879 states and 1099 transitions. [2018-11-22 23:39:58,998 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2018-11-22 23:39:58,998 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 23:39:58,998 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 23:39:58,998 INFO L423 AbstractCegarLoop]: === Iteration 8 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 23:39:58,998 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 23:39:58,999 INFO L82 PathProgramCache]: Analyzing trace with hash 683348043, now seen corresponding path program 1 times [2018-11-22 23:39:58,999 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 23:39:58,999 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 23:39:59,001 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:39:59,001 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 23:39:59,001 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:39:59,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 23:39:59,092 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-11-22 23:39:59,093 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-22 23:39:59,093 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a120b706-34a0-496a-9c2e-0ef43eb2ceb0/bin-2019/uautomizer/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-22 23:39:59,103 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 23:39:59,176 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 23:39:59,180 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 23:39:59,210 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-11-22 23:39:59,226 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-22 23:39:59,226 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 5] total 13 [2018-11-22 23:39:59,227 INFO L459 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-11-22 23:39:59,227 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-11-22 23:39:59,227 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=132, Unknown=0, NotChecked=0, Total=156 [2018-11-22 23:39:59,227 INFO L87 Difference]: Start difference. First operand 879 states and 1099 transitions. Second operand 13 states. [2018-11-22 23:39:59,774 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 23:39:59,774 INFO L93 Difference]: Finished difference Result 2045 states and 2567 transitions. [2018-11-22 23:39:59,774 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-11-22 23:39:59,774 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 64 [2018-11-22 23:39:59,775 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 23:39:59,777 INFO L225 Difference]: With dead ends: 2045 [2018-11-22 23:39:59,777 INFO L226 Difference]: Without dead ends: 1187 [2018-11-22 23:39:59,779 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 92 GetRequests, 66 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 93 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=147, Invalid=609, Unknown=0, NotChecked=0, Total=756 [2018-11-22 23:39:59,780 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1187 states. [2018-11-22 23:39:59,807 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1187 to 1118. [2018-11-22 23:39:59,808 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1118 states. [2018-11-22 23:39:59,810 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1118 states to 1118 states and 1410 transitions. [2018-11-22 23:39:59,810 INFO L78 Accepts]: Start accepts. Automaton has 1118 states and 1410 transitions. Word has length 64 [2018-11-22 23:39:59,810 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 23:39:59,810 INFO L480 AbstractCegarLoop]: Abstraction has 1118 states and 1410 transitions. [2018-11-22 23:39:59,810 INFO L481 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-11-22 23:39:59,810 INFO L276 IsEmpty]: Start isEmpty. Operand 1118 states and 1410 transitions. [2018-11-22 23:39:59,812 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2018-11-22 23:39:59,812 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 23:39:59,812 INFO L402 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 23:39:59,812 INFO L423 AbstractCegarLoop]: === Iteration 9 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 23:39:59,812 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 23:39:59,812 INFO L82 PathProgramCache]: Analyzing trace with hash 1117876484, now seen corresponding path program 1 times [2018-11-22 23:39:59,812 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 23:39:59,812 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 23:39:59,814 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:39:59,814 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 23:39:59,814 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:39:59,830 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 23:39:59,910 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-11-22 23:39:59,910 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-22 23:39:59,910 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a120b706-34a0-496a-9c2e-0ef43eb2ceb0/bin-2019/uautomizer/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-22 23:39:59,922 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 23:40:00,018 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 23:40:00,022 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 23:40:00,078 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-11-22 23:40:00,103 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-22 23:40:00,103 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 6] total 14 [2018-11-22 23:40:00,104 INFO L459 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-11-22 23:40:00,104 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-11-22 23:40:00,104 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=154, Unknown=0, NotChecked=0, Total=182 [2018-11-22 23:40:00,104 INFO L87 Difference]: Start difference. First operand 1118 states and 1410 transitions. Second operand 14 states. [2018-11-22 23:40:00,866 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 23:40:00,866 INFO L93 Difference]: Finished difference Result 2522 states and 3192 transitions. [2018-11-22 23:40:00,867 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-11-22 23:40:00,867 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 66 [2018-11-22 23:40:00,867 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 23:40:00,871 INFO L225 Difference]: With dead ends: 2522 [2018-11-22 23:40:00,871 INFO L226 Difference]: Without dead ends: 1426 [2018-11-22 23:40:00,873 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 95 GetRequests, 67 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 109 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=162, Invalid=708, Unknown=0, NotChecked=0, Total=870 [2018-11-22 23:40:00,874 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1426 states. [2018-11-22 23:40:00,901 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1426 to 1119. [2018-11-22 23:40:00,901 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1119 states. [2018-11-22 23:40:00,903 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1119 states to 1119 states and 1411 transitions. [2018-11-22 23:40:00,904 INFO L78 Accepts]: Start accepts. Automaton has 1119 states and 1411 transitions. Word has length 66 [2018-11-22 23:40:00,904 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 23:40:00,904 INFO L480 AbstractCegarLoop]: Abstraction has 1119 states and 1411 transitions. [2018-11-22 23:40:00,904 INFO L481 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-11-22 23:40:00,904 INFO L276 IsEmpty]: Start isEmpty. Operand 1119 states and 1411 transitions. [2018-11-22 23:40:00,905 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2018-11-22 23:40:00,905 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 23:40:00,905 INFO L402 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 23:40:00,906 INFO L423 AbstractCegarLoop]: === Iteration 10 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 23:40:00,906 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 23:40:00,906 INFO L82 PathProgramCache]: Analyzing trace with hash 978289668, now seen corresponding path program 1 times [2018-11-22 23:40:00,906 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 23:40:00,906 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 23:40:00,908 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:40:00,908 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 23:40:00,908 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:40:00,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 23:40:00,993 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 5 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-11-22 23:40:00,993 INFO L300 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-11-22 23:40:00,993 INFO L223 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /tmp/vcloud-vcloud-master/worker/working_dir_a120b706-34a0-496a-9c2e-0ef43eb2ceb0/bin-2019/uautomizer/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-11-22 23:40:01,014 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 23:40:01,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 23:40:01,090 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-11-22 23:40:01,154 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-11-22 23:40:01,169 INFO L312 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-11-22 23:40:01,169 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 7] total 15 [2018-11-22 23:40:01,170 INFO L459 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-11-22 23:40:01,170 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-11-22 23:40:01,170 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=177, Unknown=0, NotChecked=0, Total=210 [2018-11-22 23:40:01,170 INFO L87 Difference]: Start difference. First operand 1119 states and 1411 transitions. Second operand 15 states. [2018-11-22 23:40:01,712 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 23:40:01,712 INFO L93 Difference]: Finished difference Result 2195 states and 2764 transitions. [2018-11-22 23:40:01,713 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-11-22 23:40:01,713 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 68 [2018-11-22 23:40:01,713 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 23:40:01,717 INFO L225 Difference]: With dead ends: 2195 [2018-11-22 23:40:01,717 INFO L226 Difference]: Without dead ends: 1099 [2018-11-22 23:40:01,720 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 97 GetRequests, 68 SyntacticMatches, 0 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 111 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=172, Invalid=758, Unknown=0, NotChecked=0, Total=930 [2018-11-22 23:40:01,721 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1099 states. [2018-11-22 23:40:01,743 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1099 to 320. [2018-11-22 23:40:01,743 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 320 states. [2018-11-22 23:40:01,744 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 320 states to 320 states and 383 transitions. [2018-11-22 23:40:01,745 INFO L78 Accepts]: Start accepts. Automaton has 320 states and 383 transitions. Word has length 68 [2018-11-22 23:40:01,745 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 23:40:01,745 INFO L480 AbstractCegarLoop]: Abstraction has 320 states and 383 transitions. [2018-11-22 23:40:01,745 INFO L481 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-11-22 23:40:01,745 INFO L276 IsEmpty]: Start isEmpty. Operand 320 states and 383 transitions. [2018-11-22 23:40:01,746 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 74 [2018-11-22 23:40:01,746 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 23:40:01,746 INFO L402 BasicCegarLoop]: trace histogram [4, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 23:40:01,746 INFO L423 AbstractCegarLoop]: === Iteration 11 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 23:40:01,746 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 23:40:01,747 INFO L82 PathProgramCache]: Analyzing trace with hash 764754170, now seen corresponding path program 1 times [2018-11-22 23:40:01,747 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 23:40:01,747 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 23:40:01,748 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:40:01,748 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 23:40:01,749 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:40:01,766 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 23:40:01,802 INFO L134 CoverageAnalysis]: Checked inductivity of 17 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-11-22 23:40:01,802 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 23:40:01,803 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-22 23:40:01,803 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-22 23:40:01,803 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-22 23:40:01,804 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 23:40:01,804 INFO L87 Difference]: Start difference. First operand 320 states and 383 transitions. Second operand 3 states. [2018-11-22 23:40:01,875 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 23:40:01,875 INFO L93 Difference]: Finished difference Result 690 states and 842 transitions. [2018-11-22 23:40:01,876 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-22 23:40:01,876 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 73 [2018-11-22 23:40:01,876 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 23:40:01,878 INFO L225 Difference]: With dead ends: 690 [2018-11-22 23:40:01,878 INFO L226 Difference]: Without dead ends: 397 [2018-11-22 23:40:01,879 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 23:40:01,879 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 397 states. [2018-11-22 23:40:01,898 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 397 to 397. [2018-11-22 23:40:01,899 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 397 states. [2018-11-22 23:40:01,900 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 397 states to 397 states and 479 transitions. [2018-11-22 23:40:01,900 INFO L78 Accepts]: Start accepts. Automaton has 397 states and 479 transitions. Word has length 73 [2018-11-22 23:40:01,900 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 23:40:01,900 INFO L480 AbstractCegarLoop]: Abstraction has 397 states and 479 transitions. [2018-11-22 23:40:01,900 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-22 23:40:01,900 INFO L276 IsEmpty]: Start isEmpty. Operand 397 states and 479 transitions. [2018-11-22 23:40:01,901 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2018-11-22 23:40:01,901 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 23:40:01,902 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 23:40:01,902 INFO L423 AbstractCegarLoop]: === Iteration 12 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 23:40:01,902 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 23:40:01,902 INFO L82 PathProgramCache]: Analyzing trace with hash 1292290178, now seen corresponding path program 1 times [2018-11-22 23:40:01,902 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 23:40:01,902 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 23:40:01,903 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:40:01,904 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 23:40:01,904 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:40:01,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-11-22 23:40:01,953 INFO L134 CoverageAnalysis]: Checked inductivity of 27 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-11-22 23:40:01,953 INFO L312 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-11-22 23:40:01,953 INFO L327 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-11-22 23:40:01,953 INFO L459 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-11-22 23:40:01,954 INFO L142 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-11-22 23:40:01,954 INFO L144 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 23:40:01,954 INFO L87 Difference]: Start difference. First operand 397 states and 479 transitions. Second operand 3 states. [2018-11-22 23:40:02,023 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-11-22 23:40:02,023 INFO L93 Difference]: Finished difference Result 937 states and 1131 transitions. [2018-11-22 23:40:02,024 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-11-22 23:40:02,024 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 85 [2018-11-22 23:40:02,025 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-11-22 23:40:02,026 INFO L225 Difference]: With dead ends: 937 [2018-11-22 23:40:02,026 INFO L226 Difference]: Without dead ends: 567 [2018-11-22 23:40:02,027 INFO L631 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-11-22 23:40:02,028 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 567 states. [2018-11-22 23:40:02,056 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 567 to 564. [2018-11-22 23:40:02,056 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 564 states. [2018-11-22 23:40:02,057 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 564 states to 564 states and 670 transitions. [2018-11-22 23:40:02,057 INFO L78 Accepts]: Start accepts. Automaton has 564 states and 670 transitions. Word has length 85 [2018-11-22 23:40:02,059 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-11-22 23:40:02,059 INFO L480 AbstractCegarLoop]: Abstraction has 564 states and 670 transitions. [2018-11-22 23:40:02,059 INFO L481 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-11-22 23:40:02,059 INFO L276 IsEmpty]: Start isEmpty. Operand 564 states and 670 transitions. [2018-11-22 23:40:02,060 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2018-11-22 23:40:02,060 INFO L394 BasicCegarLoop]: Found error trace [2018-11-22 23:40:02,060 INFO L402 BasicCegarLoop]: trace histogram [4, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-11-22 23:40:02,060 INFO L423 AbstractCegarLoop]: === Iteration 13 === [ldv_errorErr0ASSERT_VIOLATIONERROR_FUNCTION]=== [2018-11-22 23:40:02,060 INFO L141 PredicateUnifier]: Initialized classic predicate unifier [2018-11-22 23:40:02,060 INFO L82 PathProgramCache]: Analyzing trace with hash 1034230670, now seen corresponding path program 1 times [2018-11-22 23:40:02,060 INFO L223 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-11-22 23:40:02,061 INFO L69 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-11-22 23:40:02,064 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:40:02,064 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-11-22 23:40:02,064 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-11-22 23:40:02,090 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 23:40:02,118 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-11-22 23:40:02,197 INFO L469 BasicCegarLoop]: Counterexample might be feasible ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder.RCFGBacktranslator [?] CALL call ULTIMATE.init(); VAL [|#NULL.base|=183, |#NULL.offset|=219, |#t~string125.base|=160, |#t~string125.offset|=163, |#t~string134.base|=235, |#t~string134.offset|=169, |#t~string140.base|=158, |#t~string140.offset|=181, |#t~string148.base|=187, |#t~string148.offset|=207, |#t~string149.base|=229, |#t~string149.offset|=178, |#t~string193.base|=211, |#t~string193.offset|=173, |#t~string195.base|=217, |#t~string195.offset|=228, |#t~string198.base|=176, |#t~string198.offset|=182, |#t~string200.base|=222, |#t~string200.offset|=210, |#t~string222.base|=212, |#t~string222.offset|=191, |#t~string90.base|=166, |#t~string90.offset|=170, |old(#NULL.base)|=183, |old(#NULL.offset)|=219, |old(#t~string125.base)|=160, |old(#t~string125.offset)|=163, |old(#t~string134.base)|=235, |old(#t~string134.offset)|=169, |old(#t~string140.base)|=158, |old(#t~string140.offset)|=181, |old(#t~string148.base)|=187, |old(#t~string148.offset)|=207, |old(#t~string149.base)|=229, |old(#t~string149.offset)|=178, |old(#t~string193.base)|=211, |old(#t~string193.offset)|=173, |old(#t~string195.base)|=217, |old(#t~string195.offset)|=228, |old(#t~string198.base)|=176, |old(#t~string198.offset)|=182, |old(#t~string200.base)|=222, |old(#t~string200.offset)|=210, |old(#t~string222.base)|=212, |old(#t~string222.offset)|=191, |old(#t~string90.base)|=166, |old(#t~string90.offset)|=170, |old(~#tegra_rtc_driver~0.base)|=233, |old(~#tegra_rtc_driver~0.offset)|=190, |old(~#tegra_rtc_ops~0.base)|=226, |old(~#tegra_rtc_ops~0.offset)|=192, |old(~LDV_IN_INTERRUPT~0)|=172, |old(~ldv_init~0)|=196, |old(~ldv_irq_1_0~0)|=205, |old(~ldv_irq_1_1~0)|=195, |old(~ldv_irq_1_2~0)|=208, |old(~ldv_irq_1_3~0)|=194, |old(~ldv_irq_data_1_0~0.base)|=161, |old(~ldv_irq_data_1_0~0.offset)|=197, |old(~ldv_irq_data_1_1~0.base)|=213, |old(~ldv_irq_data_1_1~0.offset)|=185, |old(~ldv_irq_data_1_2~0.base)|=189, |old(~ldv_irq_data_1_2~0.offset)|=177, |old(~ldv_irq_data_1_3~0.base)|=154, |old(~ldv_irq_data_1_3~0.offset)|=202, |old(~ldv_irq_line_1_0~0)|=206, |old(~ldv_irq_line_1_1~0)|=232, |old(~ldv_irq_line_1_2~0)|=227, |old(~ldv_irq_line_1_3~0)|=167, |old(~ldv_retval_0~0)|=171, |old(~ldv_retval_1~0)|=164, |old(~ldv_retval_2~0)|=188, |old(~ldv_state_variable_0~0)|=184, |old(~ldv_state_variable_1~0)|=216, |old(~ldv_state_variable_2~0)|=209, |old(~ldv_state_variable_3~0)|=236, |old(~ref_cnt~0)|=204, |old(~tegra_rtc_driver_group0~0.base)|=223, |old(~tegra_rtc_driver_group0~0.offset)|=198, |old(~tegra_rtc_ops_group0~0.base)|=200, |old(~tegra_rtc_ops_group0~0.offset)|=180, |old(~tegra_rtc_ops_group1~0.base)|=220, |old(~tegra_rtc_ops_group1~0.offset)|=193, |old(~tegra_rtc_ops_group2~0.base)|=174, |old(~tegra_rtc_ops_group2~0.offset)|=157, |~#tegra_rtc_driver~0.base|=233, |~#tegra_rtc_driver~0.offset|=190, |~#tegra_rtc_ops~0.base|=226, |~#tegra_rtc_ops~0.offset|=192, ~LDV_IN_INTERRUPT~0=172, ~ldv_init~0=196, ~ldv_irq_1_0~0=205, ~ldv_irq_1_1~0=195, ~ldv_irq_1_2~0=208, ~ldv_irq_1_3~0=194, ~ldv_irq_data_1_0~0.base=161, ~ldv_irq_data_1_0~0.offset=197, ~ldv_irq_data_1_1~0.base=213, ~ldv_irq_data_1_1~0.offset=185, ~ldv_irq_data_1_2~0.base=189, ~ldv_irq_data_1_2~0.offset=177, ~ldv_irq_data_1_3~0.base=154, ~ldv_irq_data_1_3~0.offset=202, ~ldv_irq_line_1_0~0=206, ~ldv_irq_line_1_1~0=232, ~ldv_irq_line_1_2~0=227, ~ldv_irq_line_1_3~0=167, ~ldv_retval_0~0=171, ~ldv_retval_1~0=164, ~ldv_retval_2~0=188, ~ldv_state_variable_0~0=184, ~ldv_state_variable_1~0=216, ~ldv_state_variable_2~0=209, ~ldv_state_variable_3~0=236, ~ref_cnt~0=204, ~tegra_rtc_driver_group0~0.base=223, ~tegra_rtc_driver_group0~0.offset=198, ~tegra_rtc_ops_group0~0.base=200, ~tegra_rtc_ops_group0~0.offset=180, ~tegra_rtc_ops_group1~0.base=220, ~tegra_rtc_ops_group1~0.offset=193, ~tegra_rtc_ops_group2~0.base=174, ~tegra_rtc_ops_group2~0.offset=157] [?] #NULL.base, #NULL.offset := 0, 0;#valid := #valid[0 := 0];call #t~string90.base, #t~string90.offset := #Ultimate.alloc(36);call #t~string125.base, #t~string125.offset := #Ultimate.alloc(12);call #t~string134.base, #t~string134.offset := #Ultimate.alloc(42);call #t~string140.base, #t~string140.offset := #Ultimate.alloc(42);call #t~string148.base, #t~string148.offset := #Ultimate.alloc(32);call #t~string149.base, #t~string149.offset := #Ultimate.alloc(21);call #t~string193.base, #t~string193.offset := #Ultimate.alloc(37);call #t~string195.base, #t~string195.offset := #Ultimate.alloc(10);call #t~string198.base, #t~string198.offset := #Ultimate.alloc(50);call #t~string200.base, #t~string200.offset := #Ultimate.alloc(32);call #t~string222.base, #t~string222.offset := #Ultimate.alloc(10);~ldv_irq_1_2~0 := 0;~LDV_IN_INTERRUPT~0 := 1;~ldv_irq_1_3~0 := 0;~ldv_irq_data_1_1~0.base, ~ldv_irq_data_1_1~0.offset := 0, 0;~ldv_irq_1_1~0 := 0;~ldv_irq_1_0~0 := 0;~ldv_irq_line_1_3~0 := 0;~ldv_irq_data_1_0~0.base, ~ldv_irq_data_1_0~0.offset := 0, 0;~ldv_state_variable_0~0 := 0;~ldv_state_variable_3~0 := 0;~ldv_irq_line_1_0~0 := 0;~ldv_state_variable_2~0 := 0;~ldv_irq_data_1_3~0.base, ~ldv_irq_data_1_3~0.offset := 0, 0;~ref_cnt~0 := 0;~ldv_irq_line_1_1~0 := 0;~ldv_irq_data_1_2~0.base, ~ldv_irq_data_1_2~0.offset := 0, 0;~ldv_state_variable_1~0 := 0;~ldv_irq_line_1_2~0 := 0;~ldv_retval_2~0 := 0;~ldv_retval_0~0 := 0;~ldv_retval_1~0 := 0;~ldv_init~0 := 0;~tegra_rtc_driver_group0~0.base, ~tegra_rtc_driver_group0~0.offset := 0, 0;~tegra_rtc_ops_group1~0.base, ~tegra_rtc_ops_group1~0.offset := 0, 0;~tegra_rtc_ops_group0~0.base, ~tegra_rtc_ops_group0~0.offset := 0, 0;~tegra_rtc_ops_group2~0.base, ~tegra_rtc_ops_group2~0.offset := 0, 0;call ~#tegra_rtc_ops~0.base, ~#tegra_rtc_ops~0.offset := #Ultimate.alloc(88);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 8 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 16 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_read_time.base, #funAddr~tegra_rtc_read_time.offset, ~#tegra_rtc_ops~0.base, 24 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_set_time.base, #funAddr~tegra_rtc_set_time.offset, ~#tegra_rtc_ops~0.base, 32 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_read_alarm.base, #funAddr~tegra_rtc_read_alarm.offset, ~#tegra_rtc_ops~0.base, 40 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_set_alarm.base, #funAddr~tegra_rtc_set_alarm.offset, ~#tegra_rtc_ops~0.base, 48 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_proc.base, #funAddr~tegra_rtc_proc.offset, ~#tegra_rtc_ops~0.base, 56 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 64 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 72 + ~#tegra_rtc_ops~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_alarm_irq_enable.base, #funAddr~tegra_rtc_alarm_irq_enable.offset, ~#tegra_rtc_ops~0.base, 80 + ~#tegra_rtc_ops~0.offset, 8);call ~#tegra_rtc_driver~0.base, ~#tegra_rtc_driver~0.offset := #Ultimate.alloc(153);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_remove.base, #funAddr~tegra_rtc_remove.offset, ~#tegra_rtc_driver~0.base, 8 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_shutdown.base, #funAddr~tegra_rtc_shutdown.offset, ~#tegra_rtc_driver~0.base, 16 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_suspend.base, #funAddr~tegra_rtc_suspend.offset, ~#tegra_rtc_driver~0.base, 24 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#funAddr~tegra_rtc_resume.base, #funAddr~tegra_rtc_resume.offset, ~#tegra_rtc_driver~0.base, 32 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(#t~string222.base, #t~string222.offset, ~#tegra_rtc_driver~0.base, 40 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 48 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(~#__this_module~0.base, ~#__this_module~0.offset, ~#tegra_rtc_driver~0.base, 56 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 64 + ~#tegra_rtc_driver~0.offset, 8);call write~init~int(0, ~#tegra_rtc_driver~0.base, 72 + ~#tegra_rtc_driver~0.offset, 1);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 73 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 81 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 89 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 97 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 105 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 113 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 121 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 129 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 137 + ~#tegra_rtc_driver~0.offset, 8);call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 145 + ~#tegra_rtc_driver~0.offset, 8); VAL [|#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |old(#NULL.base)|=183, |old(#NULL.offset)|=219, |old(#t~string125.base)|=160, |old(#t~string125.offset)|=163, |old(#t~string134.base)|=235, |old(#t~string134.offset)|=169, |old(#t~string140.base)|=158, |old(#t~string140.offset)|=181, |old(#t~string148.base)|=187, |old(#t~string148.offset)|=207, |old(#t~string149.base)|=229, |old(#t~string149.offset)|=178, |old(#t~string193.base)|=211, |old(#t~string193.offset)|=173, |old(#t~string195.base)|=217, |old(#t~string195.offset)|=228, |old(#t~string198.base)|=176, |old(#t~string198.offset)|=182, |old(#t~string200.base)|=222, |old(#t~string200.offset)|=210, |old(#t~string222.base)|=212, |old(#t~string222.offset)|=191, |old(#t~string90.base)|=166, |old(#t~string90.offset)|=170, |old(~#tegra_rtc_driver~0.base)|=233, |old(~#tegra_rtc_driver~0.offset)|=190, |old(~#tegra_rtc_ops~0.base)|=226, |old(~#tegra_rtc_ops~0.offset)|=192, |old(~LDV_IN_INTERRUPT~0)|=172, |old(~ldv_init~0)|=196, |old(~ldv_irq_1_0~0)|=205, |old(~ldv_irq_1_1~0)|=195, |old(~ldv_irq_1_2~0)|=208, |old(~ldv_irq_1_3~0)|=194, |old(~ldv_irq_data_1_0~0.base)|=161, |old(~ldv_irq_data_1_0~0.offset)|=197, |old(~ldv_irq_data_1_1~0.base)|=213, |old(~ldv_irq_data_1_1~0.offset)|=185, |old(~ldv_irq_data_1_2~0.base)|=189, |old(~ldv_irq_data_1_2~0.offset)|=177, |old(~ldv_irq_data_1_3~0.base)|=154, |old(~ldv_irq_data_1_3~0.offset)|=202, |old(~ldv_irq_line_1_0~0)|=206, |old(~ldv_irq_line_1_1~0)|=232, |old(~ldv_irq_line_1_2~0)|=227, |old(~ldv_irq_line_1_3~0)|=167, |old(~ldv_retval_0~0)|=171, |old(~ldv_retval_1~0)|=164, |old(~ldv_retval_2~0)|=188, |old(~ldv_state_variable_0~0)|=184, |old(~ldv_state_variable_1~0)|=216, |old(~ldv_state_variable_2~0)|=209, |old(~ldv_state_variable_3~0)|=236, |old(~ref_cnt~0)|=204, |old(~tegra_rtc_driver_group0~0.base)|=223, |old(~tegra_rtc_driver_group0~0.offset)|=198, |old(~tegra_rtc_ops_group0~0.base)|=200, |old(~tegra_rtc_ops_group0~0.offset)|=180, |old(~tegra_rtc_ops_group1~0.base)|=220, |old(~tegra_rtc_ops_group1~0.offset)|=193, |old(~tegra_rtc_ops_group2~0.base)|=174, |old(~tegra_rtc_ops_group2~0.offset)|=157, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume true; VAL [|#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |old(#NULL.base)|=183, |old(#NULL.offset)|=219, |old(#t~string125.base)|=160, |old(#t~string125.offset)|=163, |old(#t~string134.base)|=235, |old(#t~string134.offset)|=169, |old(#t~string140.base)|=158, |old(#t~string140.offset)|=181, |old(#t~string148.base)|=187, |old(#t~string148.offset)|=207, |old(#t~string149.base)|=229, |old(#t~string149.offset)|=178, |old(#t~string193.base)|=211, |old(#t~string193.offset)|=173, |old(#t~string195.base)|=217, |old(#t~string195.offset)|=228, |old(#t~string198.base)|=176, |old(#t~string198.offset)|=182, |old(#t~string200.base)|=222, |old(#t~string200.offset)|=210, |old(#t~string222.base)|=212, |old(#t~string222.offset)|=191, |old(#t~string90.base)|=166, |old(#t~string90.offset)|=170, |old(~#tegra_rtc_driver~0.base)|=233, |old(~#tegra_rtc_driver~0.offset)|=190, |old(~#tegra_rtc_ops~0.base)|=226, |old(~#tegra_rtc_ops~0.offset)|=192, |old(~LDV_IN_INTERRUPT~0)|=172, |old(~ldv_init~0)|=196, |old(~ldv_irq_1_0~0)|=205, |old(~ldv_irq_1_1~0)|=195, |old(~ldv_irq_1_2~0)|=208, |old(~ldv_irq_1_3~0)|=194, |old(~ldv_irq_data_1_0~0.base)|=161, |old(~ldv_irq_data_1_0~0.offset)|=197, |old(~ldv_irq_data_1_1~0.base)|=213, |old(~ldv_irq_data_1_1~0.offset)|=185, |old(~ldv_irq_data_1_2~0.base)|=189, |old(~ldv_irq_data_1_2~0.offset)|=177, |old(~ldv_irq_data_1_3~0.base)|=154, |old(~ldv_irq_data_1_3~0.offset)|=202, |old(~ldv_irq_line_1_0~0)|=206, |old(~ldv_irq_line_1_1~0)|=232, |old(~ldv_irq_line_1_2~0)|=227, |old(~ldv_irq_line_1_3~0)|=167, |old(~ldv_retval_0~0)|=171, |old(~ldv_retval_1~0)|=164, |old(~ldv_retval_2~0)|=188, |old(~ldv_state_variable_0~0)|=184, |old(~ldv_state_variable_1~0)|=216, |old(~ldv_state_variable_2~0)|=209, |old(~ldv_state_variable_3~0)|=236, |old(~ref_cnt~0)|=204, |old(~tegra_rtc_driver_group0~0.base)|=223, |old(~tegra_rtc_driver_group0~0.offset)|=198, |old(~tegra_rtc_ops_group0~0.base)|=200, |old(~tegra_rtc_ops_group0~0.offset)|=180, |old(~tegra_rtc_ops_group1~0.base)|=220, |old(~tegra_rtc_ops_group1~0.offset)|=193, |old(~tegra_rtc_ops_group2~0.base)|=174, |old(~tegra_rtc_ops_group2~0.offset)|=157, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] RET #874#return; VAL [|#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] CALL call #t~ret277 := main(); VAL [|#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] havoc ~ldvarg1~0.base, ~ldvarg1~0.offset;havoc ~tmp~27.base, ~tmp~27.offset;havoc ~ldvarg0~0;havoc ~tmp___0~8;call ~#ldvarg2~0.base, ~#ldvarg2~0.offset := #Ultimate.alloc(4);havoc ~tmp___1~5;havoc ~tmp___2~1;havoc ~tmp___3~1;havoc ~tmp___4~1; VAL [|#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |main_~#ldvarg2~0.base|=225, |main_~#ldvarg2~0.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] CALL call #t~ret237.base, #t~ret237.offset := ldv_zalloc(136); VAL [|#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |ldv_zalloc_#in~size|=136, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] ~size := #in~size;havoc ~p~1.base, ~p~1.offset;havoc ~tmp~1.base, ~tmp~1.offset;havoc ~tmp___0~1;assume -2147483648 <= #t~nondet12 && #t~nondet12 <= 2147483647;~tmp___0~1 := #t~nondet12;havoc #t~nondet12; VAL [ldv_zalloc_~size=136, ldv_zalloc_~tmp___0~1=1, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |ldv_zalloc_#in~size|=136, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume 0 != ~tmp___0~1;#res.base, #res.offset := 0, 0; VAL [ldv_zalloc_~size=136, ldv_zalloc_~tmp___0~1=1, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |ldv_zalloc_#in~size|=136, |ldv_zalloc_#res.base|=0, |ldv_zalloc_#res.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume true; VAL [ldv_zalloc_~size=136, ldv_zalloc_~tmp___0~1=1, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |ldv_zalloc_#in~size|=136, |ldv_zalloc_#res.base|=0, |ldv_zalloc_#res.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] RET #738#return; VAL [|#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |main_#t~ret237.base|=0, |main_#t~ret237.offset|=0, |main_~#ldvarg2~0.base|=225, |main_~#ldvarg2~0.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] ~tmp~27.base, ~tmp~27.offset := #t~ret237.base, #t~ret237.offset;havoc #t~ret237.base, #t~ret237.offset;~ldvarg1~0.base, ~ldvarg1~0.offset := ~tmp~27.base, ~tmp~27.offset;~tmp___0~8 := #t~nondet238;havoc #t~nondet238;~ldvarg0~0 := ~tmp___0~8;call ldv_initialize(); VAL [main_~ldvarg0~0=179, main_~ldvarg1~0.base=0, main_~ldvarg1~0.offset=0, main_~tmp___0~8=179, main_~tmp~27.base=0, main_~tmp~27.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |main_~#ldvarg2~0.base|=225, |main_~#ldvarg2~0.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] CALL call #t~memset~res239.base, #t~memset~res239.offset := #Ultimate.C_memset(~#ldvarg2~0.base, ~#ldvarg2~0.offset, 0, 4); VAL [|#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |#Ultimate.C_memset_#amount|=4, |#Ultimate.C_memset_#ptr.base|=225, |#Ultimate.C_memset_#ptr.offset|=0, |#Ultimate.C_memset_#value|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] #t~loopctr278 := 0; VAL [|#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |#Ultimate.C_memset_#amount|=4, |#Ultimate.C_memset_#ptr.base|=225, |#Ultimate.C_memset_#ptr.offset|=0, |#Ultimate.C_memset_#t~loopctr278|=0, |#Ultimate.C_memset_#value|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume #t~loopctr278 < #amount;#memory_$Pointer$.base, #memory_$Pointer$.offset := #memory_$Pointer$.base[#ptr.base,#ptr.offset + #t~loopctr278 := 0], #memory_$Pointer$.offset[#ptr.base,#ptr.offset + #t~loopctr278 := #value % 256];#memory_int := #memory_int[#ptr.base,#ptr.offset + #t~loopctr278 := #value];#t~loopctr278 := 1 + #t~loopctr278; VAL [|#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |#Ultimate.C_memset_#amount|=4, |#Ultimate.C_memset_#ptr.base|=225, |#Ultimate.C_memset_#ptr.offset|=0, |#Ultimate.C_memset_#t~loopctr278|=1, |#Ultimate.C_memset_#value|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume #t~loopctr278 < #amount;#memory_$Pointer$.base, #memory_$Pointer$.offset := #memory_$Pointer$.base[#ptr.base,#ptr.offset + #t~loopctr278 := 0], #memory_$Pointer$.offset[#ptr.base,#ptr.offset + #t~loopctr278 := #value % 256];#memory_int := #memory_int[#ptr.base,#ptr.offset + #t~loopctr278 := #value];#t~loopctr278 := 1 + #t~loopctr278; VAL [|#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |#Ultimate.C_memset_#amount|=4, |#Ultimate.C_memset_#ptr.base|=225, |#Ultimate.C_memset_#ptr.offset|=0, |#Ultimate.C_memset_#t~loopctr278|=2, |#Ultimate.C_memset_#value|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume #t~loopctr278 < #amount;#memory_$Pointer$.base, #memory_$Pointer$.offset := #memory_$Pointer$.base[#ptr.base,#ptr.offset + #t~loopctr278 := 0], #memory_$Pointer$.offset[#ptr.base,#ptr.offset + #t~loopctr278 := #value % 256];#memory_int := #memory_int[#ptr.base,#ptr.offset + #t~loopctr278 := #value];#t~loopctr278 := 1 + #t~loopctr278; VAL [|#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |#Ultimate.C_memset_#amount|=4, |#Ultimate.C_memset_#ptr.base|=225, |#Ultimate.C_memset_#ptr.offset|=0, |#Ultimate.C_memset_#t~loopctr278|=3, |#Ultimate.C_memset_#value|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume #t~loopctr278 < #amount;#memory_$Pointer$.base, #memory_$Pointer$.offset := #memory_$Pointer$.base[#ptr.base,#ptr.offset + #t~loopctr278 := 0], #memory_$Pointer$.offset[#ptr.base,#ptr.offset + #t~loopctr278 := #value % 256];#memory_int := #memory_int[#ptr.base,#ptr.offset + #t~loopctr278 := #value];#t~loopctr278 := 1 + #t~loopctr278; VAL [|#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |#Ultimate.C_memset_#amount|=4, |#Ultimate.C_memset_#ptr.base|=225, |#Ultimate.C_memset_#ptr.offset|=0, |#Ultimate.C_memset_#t~loopctr278|=4, |#Ultimate.C_memset_#value|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume !(#t~loopctr278 < #amount); VAL [|#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |#Ultimate.C_memset_#amount|=4, |#Ultimate.C_memset_#ptr.base|=225, |#Ultimate.C_memset_#ptr.offset|=0, |#Ultimate.C_memset_#t~loopctr278|=4, |#Ultimate.C_memset_#value|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume #res.base == #ptr.base && #res.offset == #ptr.offset; VAL [|#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |#Ultimate.C_memset_#amount|=4, |#Ultimate.C_memset_#ptr.base|=225, |#Ultimate.C_memset_#ptr.offset|=0, |#Ultimate.C_memset_#res.base|=225, |#Ultimate.C_memset_#res.offset|=0, |#Ultimate.C_memset_#t~loopctr278|=4, |#Ultimate.C_memset_#value|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] RET #740#return; VAL [main_~ldvarg0~0=179, main_~ldvarg1~0.base=0, main_~ldvarg1~0.offset=0, main_~tmp___0~8=179, main_~tmp~27.base=0, main_~tmp~27.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |main_#t~memset~res239.base|=225, |main_#t~memset~res239.offset|=0, |main_~#ldvarg2~0.base|=225, |main_~#ldvarg2~0.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] havoc #t~memset~res239.base, #t~memset~res239.offset;~ldv_state_variable_1~0 := 1;~ref_cnt~0 := 0;~ldv_state_variable_0~0 := 1;~ldv_state_variable_3~0 := 0;~ldv_state_variable_2~0 := 0; VAL [main_~ldvarg0~0=179, main_~ldvarg1~0.base=0, main_~ldvarg1~0.offset=0, main_~tmp___0~8=179, main_~tmp~27.base=0, main_~tmp~27.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |main_~#ldvarg2~0.base|=225, |main_~#ldvarg2~0.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume -2147483648 <= #t~nondet240 && #t~nondet240 <= 2147483647;~tmp___1~5 := #t~nondet240;havoc #t~nondet240;#t~switch241 := 0 == ~tmp___1~5; VAL [main_~ldvarg0~0=179, main_~ldvarg1~0.base=0, main_~ldvarg1~0.offset=0, main_~tmp___0~8=179, main_~tmp___1~5=1, main_~tmp~27.base=0, main_~tmp~27.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |main_#t~switch241|=false, |main_~#ldvarg2~0.base|=225, |main_~#ldvarg2~0.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume !#t~switch241;#t~switch241 := #t~switch241 || 1 == ~tmp___1~5; VAL [main_~ldvarg0~0=179, main_~ldvarg1~0.base=0, main_~ldvarg1~0.offset=0, main_~tmp___0~8=179, main_~tmp___1~5=1, main_~tmp~27.base=0, main_~tmp~27.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |main_#t~switch241|=true, |main_~#ldvarg2~0.base|=225, |main_~#ldvarg2~0.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume #t~switch241; VAL [main_~ldvarg0~0=179, main_~ldvarg1~0.base=0, main_~ldvarg1~0.offset=0, main_~tmp___0~8=179, main_~tmp___1~5=1, main_~tmp~27.base=0, main_~tmp~27.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |main_#t~switch241|=true, |main_~#ldvarg2~0.base|=225, |main_~#ldvarg2~0.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume 0 != ~ldv_state_variable_0~0;assume -2147483648 <= #t~nondet242 && #t~nondet242 <= 2147483647;~tmp___2~1 := #t~nondet242;havoc #t~nondet242;#t~switch243 := 0 == ~tmp___2~1; VAL [main_~ldvarg0~0=179, main_~ldvarg1~0.base=0, main_~ldvarg1~0.offset=0, main_~tmp___0~8=179, main_~tmp___1~5=1, main_~tmp___2~1=1, main_~tmp~27.base=0, main_~tmp~27.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |main_#t~switch241|=true, |main_#t~switch243|=false, |main_~#ldvarg2~0.base|=225, |main_~#ldvarg2~0.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume !#t~switch243;#t~switch243 := #t~switch243 || 1 == ~tmp___2~1; VAL [main_~ldvarg0~0=179, main_~ldvarg1~0.base=0, main_~ldvarg1~0.offset=0, main_~tmp___0~8=179, main_~tmp___1~5=1, main_~tmp___2~1=1, main_~tmp~27.base=0, main_~tmp~27.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |main_#t~switch241|=true, |main_#t~switch243|=true, |main_~#ldvarg2~0.base|=225, |main_~#ldvarg2~0.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume #t~switch243; VAL [main_~ldvarg0~0=179, main_~ldvarg1~0.base=0, main_~ldvarg1~0.offset=0, main_~tmp___0~8=179, main_~tmp___1~5=1, main_~tmp___2~1=1, main_~tmp~27.base=0, main_~tmp~27.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |main_#t~switch241|=true, |main_#t~switch243|=true, |main_~#ldvarg2~0.base|=225, |main_~#ldvarg2~0.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume 1 == ~ldv_state_variable_0~0; VAL [main_~ldvarg0~0=179, main_~ldvarg1~0.base=0, main_~ldvarg1~0.offset=0, main_~tmp___0~8=179, main_~tmp___1~5=1, main_~tmp___2~1=1, main_~tmp~27.base=0, main_~tmp~27.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |main_#t~switch241|=true, |main_#t~switch243|=true, |main_~#ldvarg2~0.base|=225, |main_~#ldvarg2~0.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] CALL call #t~ret244 := tegra_rtc_init(); VAL [|#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] havoc ~tmp~22;call #t~ret223 := platform_driver_probe(~#tegra_rtc_driver~0.base, ~#tegra_rtc_driver~0.offset, #funAddr~tegra_rtc_probe.base, #funAddr~tegra_rtc_probe.offset);assume -2147483648 <= #t~ret223 && #t~ret223 <= 2147483647;~tmp~22 := #t~ret223;havoc #t~ret223;#res := ~tmp~22; VAL [tegra_rtc_init_~tmp~22=0, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |tegra_rtc_init_#res|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume true; VAL [tegra_rtc_init_~tmp~22=0, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |tegra_rtc_init_#res|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] RET #746#return; VAL [main_~ldvarg0~0=179, main_~ldvarg1~0.base=0, main_~ldvarg1~0.offset=0, main_~tmp___0~8=179, main_~tmp___1~5=1, main_~tmp___2~1=1, main_~tmp~27.base=0, main_~tmp~27.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |main_#t~ret244|=0, |main_#t~switch241|=true, |main_#t~switch243|=true, |main_~#ldvarg2~0.base|=225, |main_~#ldvarg2~0.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume -2147483648 <= #t~ret244 && #t~ret244 <= 2147483647;~ldv_retval_0~0 := #t~ret244;havoc #t~ret244; VAL [main_~ldvarg0~0=179, main_~ldvarg1~0.base=0, main_~ldvarg1~0.offset=0, main_~tmp___0~8=179, main_~tmp___1~5=1, main_~tmp___2~1=1, main_~tmp~27.base=0, main_~tmp~27.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |main_#t~switch241|=true, |main_#t~switch243|=true, |main_~#ldvarg2~0.base|=225, |main_~#ldvarg2~0.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume 0 == ~ldv_retval_0~0;~ldv_state_variable_0~0 := 3;~ldv_state_variable_2~0 := 1; VAL [main_~ldvarg0~0=179, main_~ldvarg1~0.base=0, main_~ldvarg1~0.offset=0, main_~tmp___0~8=179, main_~tmp___1~5=1, main_~tmp___2~1=1, main_~tmp~27.base=0, main_~tmp~27.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |main_#t~switch241|=true, |main_#t~switch243|=true, |main_~#ldvarg2~0.base|=225, |main_~#ldvarg2~0.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] CALL call ldv_initialize_platform_driver_2(); VAL [|#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] havoc ~tmp~26.base, ~tmp~26.offset; VAL [|#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] CALL call #t~ret236.base, #t~ret236.offset := ldv_zalloc(624); VAL [|#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |ldv_zalloc_#in~size|=624, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] ~size := #in~size;havoc ~p~1.base, ~p~1.offset;havoc ~tmp~1.base, ~tmp~1.offset;havoc ~tmp___0~1;assume -2147483648 <= #t~nondet12 && #t~nondet12 <= 2147483647;~tmp___0~1 := #t~nondet12;havoc #t~nondet12; VAL [ldv_zalloc_~size=624, ldv_zalloc_~tmp___0~1=1, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |ldv_zalloc_#in~size|=624, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume 0 != ~tmp___0~1;#res.base, #res.offset := 0, 0; VAL [ldv_zalloc_~size=624, ldv_zalloc_~tmp___0~1=1, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |ldv_zalloc_#in~size|=624, |ldv_zalloc_#res.base|=0, |ldv_zalloc_#res.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume true; VAL [ldv_zalloc_~size=624, ldv_zalloc_~tmp___0~1=1, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |ldv_zalloc_#in~size|=624, |ldv_zalloc_#res.base|=0, |ldv_zalloc_#res.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] RET #804#return; VAL [|#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |ldv_initialize_platform_driver_2_#t~ret236.base|=0, |ldv_initialize_platform_driver_2_#t~ret236.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] ~tmp~26.base, ~tmp~26.offset := #t~ret236.base, #t~ret236.offset;havoc #t~ret236.base, #t~ret236.offset;~tegra_rtc_driver_group0~0.base, ~tegra_rtc_driver_group0~0.offset := ~tmp~26.base, ~tmp~26.offset; VAL [ldv_initialize_platform_driver_2_~tmp~26.base=0, ldv_initialize_platform_driver_2_~tmp~26.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume true; VAL [ldv_initialize_platform_driver_2_~tmp~26.base=0, ldv_initialize_platform_driver_2_~tmp~26.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] RET #748#return; VAL [main_~ldvarg0~0=179, main_~ldvarg1~0.base=0, main_~ldvarg1~0.offset=0, main_~tmp___0~8=179, main_~tmp___1~5=1, main_~tmp___2~1=1, main_~tmp~27.base=0, main_~tmp~27.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |main_#t~switch241|=true, |main_#t~switch243|=true, |main_~#ldvarg2~0.base|=225, |main_~#ldvarg2~0.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume !(0 != ~ldv_retval_0~0); VAL [main_~ldvarg0~0=179, main_~ldvarg1~0.base=0, main_~ldvarg1~0.offset=0, main_~tmp___0~8=179, main_~tmp___1~5=1, main_~tmp___2~1=1, main_~tmp~27.base=0, main_~tmp~27.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |main_#t~switch241|=true, |main_#t~switch243|=true, |main_~#ldvarg2~0.base|=225, |main_~#ldvarg2~0.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume -2147483648 <= #t~nondet240 && #t~nondet240 <= 2147483647;~tmp___1~5 := #t~nondet240;havoc #t~nondet240;#t~switch241 := 0 == ~tmp___1~5; VAL [main_~ldvarg0~0=179, main_~ldvarg1~0.base=0, main_~ldvarg1~0.offset=0, main_~tmp___0~8=179, main_~tmp___1~5=3, main_~tmp___2~1=1, main_~tmp~27.base=0, main_~tmp~27.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |main_#t~switch241|=false, |main_#t~switch243|=true, |main_~#ldvarg2~0.base|=225, |main_~#ldvarg2~0.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume !#t~switch241;#t~switch241 := #t~switch241 || 1 == ~tmp___1~5; VAL [main_~ldvarg0~0=179, main_~ldvarg1~0.base=0, main_~ldvarg1~0.offset=0, main_~tmp___0~8=179, main_~tmp___1~5=3, main_~tmp___2~1=1, main_~tmp~27.base=0, main_~tmp~27.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |main_#t~switch241|=false, |main_#t~switch243|=true, |main_~#ldvarg2~0.base|=225, |main_~#ldvarg2~0.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume !#t~switch241;#t~switch241 := #t~switch241 || 2 == ~tmp___1~5; VAL [main_~ldvarg0~0=179, main_~ldvarg1~0.base=0, main_~ldvarg1~0.offset=0, main_~tmp___0~8=179, main_~tmp___1~5=3, main_~tmp___2~1=1, main_~tmp~27.base=0, main_~tmp~27.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |main_#t~switch241|=false, |main_#t~switch243|=true, |main_~#ldvarg2~0.base|=225, |main_~#ldvarg2~0.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume !#t~switch241;#t~switch241 := #t~switch241 || 3 == ~tmp___1~5; VAL [main_~ldvarg0~0=179, main_~ldvarg1~0.base=0, main_~ldvarg1~0.offset=0, main_~tmp___0~8=179, main_~tmp___1~5=3, main_~tmp___2~1=1, main_~tmp~27.base=0, main_~tmp~27.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |main_#t~switch241|=true, |main_#t~switch243|=true, |main_~#ldvarg2~0.base|=225, |main_~#ldvarg2~0.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume #t~switch241; VAL [main_~ldvarg0~0=179, main_~ldvarg1~0.base=0, main_~ldvarg1~0.offset=0, main_~tmp___0~8=179, main_~tmp___1~5=3, main_~tmp___2~1=1, main_~tmp~27.base=0, main_~tmp~27.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |main_#t~switch241|=true, |main_#t~switch243|=true, |main_~#ldvarg2~0.base|=225, |main_~#ldvarg2~0.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume 0 != ~ldv_state_variable_2~0;assume -2147483648 <= #t~nondet260 && #t~nondet260 <= 2147483647;~tmp___4~1 := #t~nondet260;havoc #t~nondet260;#t~switch261 := 0 == ~tmp___4~1; VAL [main_~ldvarg0~0=179, main_~ldvarg1~0.base=0, main_~ldvarg1~0.offset=0, main_~tmp___0~8=179, main_~tmp___1~5=3, main_~tmp___2~1=1, main_~tmp___4~1=4, main_~tmp~27.base=0, main_~tmp~27.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |main_#t~switch241|=true, |main_#t~switch243|=true, |main_#t~switch261|=false, |main_~#ldvarg2~0.base|=225, |main_~#ldvarg2~0.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume !#t~switch261;#t~switch261 := #t~switch261 || 1 == ~tmp___4~1; VAL [main_~ldvarg0~0=179, main_~ldvarg1~0.base=0, main_~ldvarg1~0.offset=0, main_~tmp___0~8=179, main_~tmp___1~5=3, main_~tmp___2~1=1, main_~tmp___4~1=4, main_~tmp~27.base=0, main_~tmp~27.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |main_#t~switch241|=true, |main_#t~switch243|=true, |main_#t~switch261|=false, |main_~#ldvarg2~0.base|=225, |main_~#ldvarg2~0.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume !#t~switch261;#t~switch261 := #t~switch261 || 2 == ~tmp___4~1; VAL [main_~ldvarg0~0=179, main_~ldvarg1~0.base=0, main_~ldvarg1~0.offset=0, main_~tmp___0~8=179, main_~tmp___1~5=3, main_~tmp___2~1=1, main_~tmp___4~1=4, main_~tmp~27.base=0, main_~tmp~27.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |main_#t~switch241|=true, |main_#t~switch243|=true, |main_#t~switch261|=false, |main_~#ldvarg2~0.base|=225, |main_~#ldvarg2~0.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume !#t~switch261;#t~switch261 := #t~switch261 || 3 == ~tmp___4~1; VAL [main_~ldvarg0~0=179, main_~ldvarg1~0.base=0, main_~ldvarg1~0.offset=0, main_~tmp___0~8=179, main_~tmp___1~5=3, main_~tmp___2~1=1, main_~tmp___4~1=4, main_~tmp~27.base=0, main_~tmp~27.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |main_#t~switch241|=true, |main_#t~switch243|=true, |main_#t~switch261|=false, |main_~#ldvarg2~0.base|=225, |main_~#ldvarg2~0.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume !#t~switch261;#t~switch261 := #t~switch261 || 4 == ~tmp___4~1; VAL [main_~ldvarg0~0=179, main_~ldvarg1~0.base=0, main_~ldvarg1~0.offset=0, main_~tmp___0~8=179, main_~tmp___1~5=3, main_~tmp___2~1=1, main_~tmp___4~1=4, main_~tmp~27.base=0, main_~tmp~27.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |main_#t~switch241|=true, |main_#t~switch243|=true, |main_#t~switch261|=true, |main_~#ldvarg2~0.base|=225, |main_~#ldvarg2~0.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume #t~switch261; VAL [main_~ldvarg0~0=179, main_~ldvarg1~0.base=0, main_~ldvarg1~0.offset=0, main_~tmp___0~8=179, main_~tmp___1~5=3, main_~tmp___2~1=1, main_~tmp___4~1=4, main_~tmp~27.base=0, main_~tmp~27.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |main_#t~switch241|=true, |main_#t~switch243|=true, |main_#t~switch261|=true, |main_~#ldvarg2~0.base|=225, |main_~#ldvarg2~0.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume 1 == ~ldv_state_variable_2~0;call #t~ret268 := ldv_probe_2();assume -2147483648 <= #t~ret268 && #t~ret268 <= 2147483647;havoc #t~ret268;~ldv_state_variable_2~0 := 2;~ref_cnt~0 := 1 + ~ref_cnt~0; VAL [main_~ldvarg0~0=179, main_~ldvarg1~0.base=0, main_~ldvarg1~0.offset=0, main_~tmp___0~8=179, main_~tmp___1~5=3, main_~tmp___2~1=1, main_~tmp___4~1=4, main_~tmp~27.base=0, main_~tmp~27.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |main_#t~switch241|=true, |main_#t~switch243|=true, |main_#t~switch261|=true, |main_~#ldvarg2~0.base|=225, |main_~#ldvarg2~0.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume -2147483648 <= #t~nondet240 && #t~nondet240 <= 2147483647;~tmp___1~5 := #t~nondet240;havoc #t~nondet240;#t~switch241 := 0 == ~tmp___1~5; VAL [main_~ldvarg0~0=179, main_~ldvarg1~0.base=0, main_~ldvarg1~0.offset=0, main_~tmp___0~8=179, main_~tmp___1~5=3, main_~tmp___2~1=1, main_~tmp___4~1=4, main_~tmp~27.base=0, main_~tmp~27.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |main_#t~switch241|=false, |main_#t~switch243|=true, |main_#t~switch261|=true, |main_~#ldvarg2~0.base|=225, |main_~#ldvarg2~0.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume !#t~switch241;#t~switch241 := #t~switch241 || 1 == ~tmp___1~5; VAL [main_~ldvarg0~0=179, main_~ldvarg1~0.base=0, main_~ldvarg1~0.offset=0, main_~tmp___0~8=179, main_~tmp___1~5=3, main_~tmp___2~1=1, main_~tmp___4~1=4, main_~tmp~27.base=0, main_~tmp~27.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |main_#t~switch241|=false, |main_#t~switch243|=true, |main_#t~switch261|=true, |main_~#ldvarg2~0.base|=225, |main_~#ldvarg2~0.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume !#t~switch241;#t~switch241 := #t~switch241 || 2 == ~tmp___1~5; VAL [main_~ldvarg0~0=179, main_~ldvarg1~0.base=0, main_~ldvarg1~0.offset=0, main_~tmp___0~8=179, main_~tmp___1~5=3, main_~tmp___2~1=1, main_~tmp___4~1=4, main_~tmp~27.base=0, main_~tmp~27.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |main_#t~switch241|=false, |main_#t~switch243|=true, |main_#t~switch261|=true, |main_~#ldvarg2~0.base|=225, |main_~#ldvarg2~0.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume !#t~switch241;#t~switch241 := #t~switch241 || 3 == ~tmp___1~5; VAL [main_~ldvarg0~0=179, main_~ldvarg1~0.base=0, main_~ldvarg1~0.offset=0, main_~tmp___0~8=179, main_~tmp___1~5=3, main_~tmp___2~1=1, main_~tmp___4~1=4, main_~tmp~27.base=0, main_~tmp~27.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |main_#t~switch241|=true, |main_#t~switch243|=true, |main_#t~switch261|=true, |main_~#ldvarg2~0.base|=225, |main_~#ldvarg2~0.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume #t~switch241; VAL [main_~ldvarg0~0=179, main_~ldvarg1~0.base=0, main_~ldvarg1~0.offset=0, main_~tmp___0~8=179, main_~tmp___1~5=3, main_~tmp___2~1=1, main_~tmp___4~1=4, main_~tmp~27.base=0, main_~tmp~27.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |main_#t~switch241|=true, |main_#t~switch243|=true, |main_#t~switch261|=true, |main_~#ldvarg2~0.base|=225, |main_~#ldvarg2~0.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume 0 != ~ldv_state_variable_2~0;assume -2147483648 <= #t~nondet260 && #t~nondet260 <= 2147483647;~tmp___4~1 := #t~nondet260;havoc #t~nondet260;#t~switch261 := 0 == ~tmp___4~1; VAL [main_~ldvarg0~0=179, main_~ldvarg1~0.base=0, main_~ldvarg1~0.offset=0, main_~tmp___0~8=179, main_~tmp___1~5=3, main_~tmp___2~1=1, main_~tmp___4~1=0, main_~tmp~27.base=0, main_~tmp~27.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |main_#t~switch241|=true, |main_#t~switch243|=true, |main_#t~switch261|=true, |main_~#ldvarg2~0.base|=225, |main_~#ldvarg2~0.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume #t~switch261; VAL [main_~ldvarg0~0=179, main_~ldvarg1~0.base=0, main_~ldvarg1~0.offset=0, main_~tmp___0~8=179, main_~tmp___1~5=3, main_~tmp___2~1=1, main_~tmp___4~1=0, main_~tmp~27.base=0, main_~tmp~27.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |main_#t~switch241|=true, |main_#t~switch243|=true, |main_#t~switch261|=true, |main_~#ldvarg2~0.base|=225, |main_~#ldvarg2~0.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume !(4 == ~ldv_state_variable_2~0); VAL [main_~ldvarg0~0=179, main_~ldvarg1~0.base=0, main_~ldvarg1~0.offset=0, main_~tmp___0~8=179, main_~tmp___1~5=3, main_~tmp___2~1=1, main_~tmp___4~1=0, main_~tmp~27.base=0, main_~tmp~27.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |main_#t~switch241|=true, |main_#t~switch243|=true, |main_#t~switch261|=true, |main_~#ldvarg2~0.base|=225, |main_~#ldvarg2~0.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume 2 == ~ldv_state_variable_2~0; VAL [main_~ldvarg0~0=179, main_~ldvarg1~0.base=0, main_~ldvarg1~0.offset=0, main_~tmp___0~8=179, main_~tmp___1~5=3, main_~tmp___2~1=1, main_~tmp___4~1=0, main_~tmp~27.base=0, main_~tmp~27.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |main_#t~switch241|=true, |main_#t~switch243|=true, |main_#t~switch261|=true, |main_~#ldvarg2~0.base|=225, |main_~#ldvarg2~0.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] CALL call tegra_rtc_shutdown(~tegra_rtc_driver_group0~0.base, ~tegra_rtc_driver_group0~0.offset); VAL [|#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |tegra_rtc_shutdown_#in~pdev.base|=0, |tegra_rtc_shutdown_#in~pdev.offset|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] ~pdev.base, ~pdev.offset := #in~pdev.base, #in~pdev.offset; VAL [tegra_rtc_shutdown_~pdev.base=0, tegra_rtc_shutdown_~pdev.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |tegra_rtc_shutdown_#in~pdev.base|=0, |tegra_rtc_shutdown_#in~pdev.offset|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] CALL call #t~ret221 := tegra_rtc_alarm_irq_enable(~pdev.base, 12 + ~pdev.offset, 0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |tegra_rtc_alarm_irq_enable_#in~dev.base|=0, |tegra_rtc_alarm_irq_enable_#in~dev.offset|=12, |tegra_rtc_alarm_irq_enable_#in~enabled|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] ~dev.base, ~dev.offset := #in~dev.base, #in~dev.offset;~enabled := #in~enabled;havoc ~info~4.base, ~info~4.offset;havoc ~tmp~14.base, ~tmp~14.offset;havoc ~status~0;havoc ~sl_irq_flags~1;havoc ~__v~3;havoc ~__v___0~3;call #t~ret107.base, #t~ret107.offset := dev_get_drvdata(~dev.base, ~dev.offset);~tmp~14.base, ~tmp~14.offset := #t~ret107.base, #t~ret107.offset;havoc #t~ret107.base, #t~ret107.offset;~info~4.base, ~info~4.offset := ~tmp~14.base, ~tmp~14.offset; VAL [tegra_rtc_alarm_irq_enable_~dev.base=0, tegra_rtc_alarm_irq_enable_~dev.offset=12, tegra_rtc_alarm_irq_enable_~enabled=0, tegra_rtc_alarm_irq_enable_~info~4.base=156, tegra_rtc_alarm_irq_enable_~info~4.offset=215, tegra_rtc_alarm_irq_enable_~tmp~14.base=156, tegra_rtc_alarm_irq_enable_~tmp~14.offset=215, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |tegra_rtc_alarm_irq_enable_#in~dev.base|=0, |tegra_rtc_alarm_irq_enable_#in~dev.offset|=12, |tegra_rtc_alarm_irq_enable_#in~enabled|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] CALL call #t~ret108 := tegra_rtc_wait_while_busy(~dev.base, ~dev.offset); VAL [|#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |tegra_rtc_wait_while_busy_#in~dev.base|=0, |tegra_rtc_wait_while_busy_#in~dev.offset|=12, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] ~dev.base, ~dev.offset := #in~dev.base, #in~dev.offset;havoc ~info~0.base, ~info~0.offset;havoc ~tmp~10.base, ~tmp~10.offset;havoc ~retries~0;havoc ~tmp___0~2;havoc ~tmp___1~0;call #t~ret87.base, #t~ret87.offset := dev_get_drvdata(~dev.base, ~dev.offset);~tmp~10.base, ~tmp~10.offset := #t~ret87.base, #t~ret87.offset;havoc #t~ret87.base, #t~ret87.offset;~info~0.base, ~info~0.offset := ~tmp~10.base, ~tmp~10.offset;~retries~0 := 500; VAL [tegra_rtc_wait_while_busy_~dev.base=0, tegra_rtc_wait_while_busy_~dev.offset=12, tegra_rtc_wait_while_busy_~info~0.base=165, tegra_rtc_wait_while_busy_~info~0.offset=0, tegra_rtc_wait_while_busy_~retries~0=500, tegra_rtc_wait_while_busy_~tmp~10.base=165, tegra_rtc_wait_while_busy_~tmp~10.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |tegra_rtc_wait_while_busy_#in~dev.base|=0, |tegra_rtc_wait_while_busy_#in~dev.offset|=12, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] CALL call #t~ret88 := tegra_rtc_check_busy(~info~0.base, ~info~0.offset); VAL [|#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |tegra_rtc_check_busy_#in~info.base|=165, |tegra_rtc_check_busy_#in~info.offset|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] ~info.base, ~info.offset := #in~info.base, #in~info.offset;havoc ~__v~0;havoc ~__v___0~0;call #t~mem85.base, #t~mem85.offset := read~$Pointer$(~info.base, 16 + ~info.offset, 8);call #t~mem86 := read~int(#t~mem85.base, 16 + #t~mem85.offset, 4);~__v___0~0 := #t~mem86;havoc #t~mem86;havoc #t~mem85.base, #t~mem85.offset;~__v~0 := ~__v___0~0;#res := ~bitwiseAnd(~__v~0, 1); VAL [tegra_rtc_check_busy_~__v___0~0=201, tegra_rtc_check_busy_~__v~0=201, tegra_rtc_check_busy_~info.base=165, tegra_rtc_check_busy_~info.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |tegra_rtc_check_busy_#in~info.base|=165, |tegra_rtc_check_busy_#in~info.offset|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume true; VAL [tegra_rtc_check_busy_~__v___0~0=201, tegra_rtc_check_busy_~__v~0=201, tegra_rtc_check_busy_~info.base=165, tegra_rtc_check_busy_~info.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |tegra_rtc_check_busy_#in~info.base|=165, |tegra_rtc_check_busy_#in~info.offset|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] RET #850#return; VAL [tegra_rtc_wait_while_busy_~dev.base=0, tegra_rtc_wait_while_busy_~dev.offset=12, tegra_rtc_wait_while_busy_~info~0.base=165, tegra_rtc_wait_while_busy_~info~0.offset=0, tegra_rtc_wait_while_busy_~retries~0=500, tegra_rtc_wait_while_busy_~tmp~10.base=165, tegra_rtc_wait_while_busy_~tmp~10.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |tegra_rtc_wait_while_busy_#in~dev.base|=0, |tegra_rtc_wait_while_busy_#in~dev.offset|=12, |tegra_rtc_wait_while_busy_#t~ret88|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] ~tmp___1~0 := #t~ret88;havoc #t~ret88; VAL [tegra_rtc_wait_while_busy_~dev.base=0, tegra_rtc_wait_while_busy_~dev.offset=12, tegra_rtc_wait_while_busy_~info~0.base=165, tegra_rtc_wait_while_busy_~info~0.offset=0, tegra_rtc_wait_while_busy_~retries~0=500, tegra_rtc_wait_while_busy_~tmp___1~0=0, tegra_rtc_wait_while_busy_~tmp~10.base=165, tegra_rtc_wait_while_busy_~tmp~10.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |tegra_rtc_wait_while_busy_#in~dev.base|=0, |tegra_rtc_wait_while_busy_#in~dev.offset|=12, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume !(0 != ~tmp___1~0 % 4294967296);#res := 0; VAL [tegra_rtc_wait_while_busy_~dev.base=0, tegra_rtc_wait_while_busy_~dev.offset=12, tegra_rtc_wait_while_busy_~info~0.base=165, tegra_rtc_wait_while_busy_~info~0.offset=0, tegra_rtc_wait_while_busy_~retries~0=500, tegra_rtc_wait_while_busy_~tmp___1~0=0, tegra_rtc_wait_while_busy_~tmp~10.base=165, tegra_rtc_wait_while_busy_~tmp~10.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |tegra_rtc_wait_while_busy_#in~dev.base|=0, |tegra_rtc_wait_while_busy_#in~dev.offset|=12, |tegra_rtc_wait_while_busy_#res|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume true; VAL [tegra_rtc_wait_while_busy_~dev.base=0, tegra_rtc_wait_while_busy_~dev.offset=12, tegra_rtc_wait_while_busy_~info~0.base=165, tegra_rtc_wait_while_busy_~info~0.offset=0, tegra_rtc_wait_while_busy_~retries~0=500, tegra_rtc_wait_while_busy_~tmp___1~0=0, tegra_rtc_wait_while_busy_~tmp~10.base=165, tegra_rtc_wait_while_busy_~tmp~10.offset=0, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |tegra_rtc_wait_while_busy_#in~dev.base|=0, |tegra_rtc_wait_while_busy_#in~dev.offset|=12, |tegra_rtc_wait_while_busy_#res|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] RET #854#return; VAL [tegra_rtc_alarm_irq_enable_~dev.base=0, tegra_rtc_alarm_irq_enable_~dev.offset=12, tegra_rtc_alarm_irq_enable_~enabled=0, tegra_rtc_alarm_irq_enable_~info~4.base=156, tegra_rtc_alarm_irq_enable_~info~4.offset=215, tegra_rtc_alarm_irq_enable_~tmp~14.base=156, tegra_rtc_alarm_irq_enable_~tmp~14.offset=215, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |tegra_rtc_alarm_irq_enable_#in~dev.base|=0, |tegra_rtc_alarm_irq_enable_#in~dev.offset|=12, |tegra_rtc_alarm_irq_enable_#in~enabled|=0, |tegra_rtc_alarm_irq_enable_#t~ret108|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume -2147483648 <= #t~ret108 && #t~ret108 <= 2147483647;havoc #t~ret108; VAL [tegra_rtc_alarm_irq_enable_~dev.base=0, tegra_rtc_alarm_irq_enable_~dev.offset=12, tegra_rtc_alarm_irq_enable_~enabled=0, tegra_rtc_alarm_irq_enable_~info~4.base=156, tegra_rtc_alarm_irq_enable_~info~4.offset=215, tegra_rtc_alarm_irq_enable_~tmp~14.base=156, tegra_rtc_alarm_irq_enable_~tmp~14.offset=215, |#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |tegra_rtc_alarm_irq_enable_#in~dev.base|=0, |tegra_rtc_alarm_irq_enable_#in~dev.offset|=12, |tegra_rtc_alarm_irq_enable_#in~enabled|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] CALL call ldv_spin_lock_check(); VAL [|#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume !(1 == ~ldv_init~0); VAL [|#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] CALL call ldv_error(); VAL [|#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume !false; VAL [|#NULL.base|=0, |#NULL.offset|=0, |#t~string125.base|=159, |#t~string125.offset|=0, |#t~string134.base|=237, |#t~string134.offset|=0, |#t~string140.base|=155, |#t~string140.offset|=0, |#t~string148.base|=186, |#t~string148.offset|=0, |#t~string149.base|=230, |#t~string149.offset|=0, |#t~string193.base|=218, |#t~string193.offset|=0, |#t~string195.base|=214, |#t~string195.offset|=0, |#t~string198.base|=175, |#t~string198.offset|=0, |#t~string200.base|=221, |#t~string200.offset|=0, |#t~string222.base|=234, |#t~string222.offset|=0, |#t~string90.base|=168, |#t~string90.offset|=0, |old(~LDV_IN_INTERRUPT~0)|=1, |old(~ldv_irq_1_0~0)|=0, |old(~ldv_irq_1_1~0)|=0, |old(~ldv_irq_1_2~0)|=0, |old(~ldv_irq_1_3~0)|=0, |old(~ldv_retval_0~0)|=0, |old(~ldv_retval_1~0)|=0, |old(~ldv_retval_2~0)|=0, |old(~ldv_state_variable_0~0)|=0, |old(~ldv_state_variable_1~0)|=0, |old(~ldv_state_variable_2~0)|=0, |old(~ldv_state_variable_3~0)|=0, |old(~ref_cnt~0)|=0, |old(~tegra_rtc_driver_group0~0.base)|=0, |old(~tegra_rtc_driver_group0~0.offset)|=0, |~#__this_module~0.base|=162, |~#__this_module~0.offset|=199, |~#tegra_rtc_driver~0.base|=231, |~#tegra_rtc_driver~0.offset|=0, |~#tegra_rtc_ops~0.base|=224, |~#tegra_rtc_ops~0.offset|=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] CALL call ULTIMATE.init(); VAL [#NULL.base=183, #NULL.offset=219, #t~string125.base=160, #t~string125.offset=163, #t~string134.base=235, #t~string134.offset=169, #t~string140.base=158, #t~string140.offset=181, #t~string148.base=187, #t~string148.offset=207, #t~string149.base=229, #t~string149.offset=178, #t~string193.base=211, #t~string193.offset=173, #t~string195.base=217, #t~string195.offset=228, #t~string198.base=176, #t~string198.offset=182, #t~string200.base=222, #t~string200.offset=210, #t~string222.base=212, #t~string222.offset=191, #t~string90.base=166, #t~string90.offset=170, old(#NULL.base)=183, old(#NULL.offset)=219, old(#t~string125.base)=160, old(#t~string125.offset)=163, old(#t~string134.base)=235, old(#t~string134.offset)=169, old(#t~string140.base)=158, old(#t~string140.offset)=181, old(#t~string148.base)=187, old(#t~string148.offset)=207, old(#t~string149.base)=229, old(#t~string149.offset)=178, old(#t~string193.base)=211, old(#t~string193.offset)=173, old(#t~string195.base)=217, old(#t~string195.offset)=228, old(#t~string198.base)=176, old(#t~string198.offset)=182, old(#t~string200.base)=222, old(#t~string200.offset)=210, old(#t~string222.base)=212, old(#t~string222.offset)=191, old(#t~string90.base)=166, old(#t~string90.offset)=170, old(~#tegra_rtc_driver~0.base)=233, old(~#tegra_rtc_driver~0.offset)=190, old(~#tegra_rtc_ops~0.base)=226, old(~#tegra_rtc_ops~0.offset)=192, old(~LDV_IN_INTERRUPT~0)=172, old(~ldv_init~0)=196, old(~ldv_irq_1_0~0)=205, old(~ldv_irq_1_1~0)=195, old(~ldv_irq_1_2~0)=208, old(~ldv_irq_1_3~0)=194, old(~ldv_irq_data_1_0~0.base)=161, old(~ldv_irq_data_1_0~0.offset)=197, old(~ldv_irq_data_1_1~0.base)=213, old(~ldv_irq_data_1_1~0.offset)=185, old(~ldv_irq_data_1_2~0.base)=189, old(~ldv_irq_data_1_2~0.offset)=177, old(~ldv_irq_data_1_3~0.base)=154, old(~ldv_irq_data_1_3~0.offset)=202, old(~ldv_irq_line_1_0~0)=206, old(~ldv_irq_line_1_1~0)=232, old(~ldv_irq_line_1_2~0)=227, old(~ldv_irq_line_1_3~0)=167, old(~ldv_retval_0~0)=171, old(~ldv_retval_1~0)=164, old(~ldv_retval_2~0)=188, old(~ldv_state_variable_0~0)=184, old(~ldv_state_variable_1~0)=216, old(~ldv_state_variable_2~0)=209, old(~ldv_state_variable_3~0)=236, old(~ref_cnt~0)=204, old(~tegra_rtc_driver_group0~0.base)=223, old(~tegra_rtc_driver_group0~0.offset)=198, old(~tegra_rtc_ops_group0~0.base)=200, old(~tegra_rtc_ops_group0~0.offset)=180, old(~tegra_rtc_ops_group1~0.base)=220, old(~tegra_rtc_ops_group1~0.offset)=193, old(~tegra_rtc_ops_group2~0.base)=174, old(~tegra_rtc_ops_group2~0.offset)=157, ~#tegra_rtc_driver~0.base=233, ~#tegra_rtc_driver~0.offset=190, ~#tegra_rtc_ops~0.base=226, ~#tegra_rtc_ops~0.offset=192, ~LDV_IN_INTERRUPT~0=172, ~ldv_init~0=196, ~ldv_irq_1_0~0=205, ~ldv_irq_1_1~0=195, ~ldv_irq_1_2~0=208, ~ldv_irq_1_3~0=194, ~ldv_irq_data_1_0~0.base=161, ~ldv_irq_data_1_0~0.offset=197, ~ldv_irq_data_1_1~0.base=213, ~ldv_irq_data_1_1~0.offset=185, ~ldv_irq_data_1_2~0.base=189, ~ldv_irq_data_1_2~0.offset=177, ~ldv_irq_data_1_3~0.base=154, ~ldv_irq_data_1_3~0.offset=202, ~ldv_irq_line_1_0~0=206, ~ldv_irq_line_1_1~0=232, ~ldv_irq_line_1_2~0=227, ~ldv_irq_line_1_3~0=167, ~ldv_retval_0~0=171, ~ldv_retval_1~0=164, ~ldv_retval_2~0=188, ~ldv_state_variable_0~0=184, ~ldv_state_variable_1~0=216, ~ldv_state_variable_2~0=209, ~ldv_state_variable_3~0=236, ~ref_cnt~0=204, ~tegra_rtc_driver_group0~0.base=223, ~tegra_rtc_driver_group0~0.offset=198, ~tegra_rtc_ops_group0~0.base=200, ~tegra_rtc_ops_group0~0.offset=180, ~tegra_rtc_ops_group1~0.base=220, ~tegra_rtc_ops_group1~0.offset=193, ~tegra_rtc_ops_group2~0.base=174, ~tegra_rtc_ops_group2~0.offset=157] [?] #NULL.base, #NULL.offset := 0, 0; [?] #valid := #valid[0 := 0]; [L1905] call #t~string90.base, #t~string90.offset := #Ultimate.alloc(36); [L2072] call #t~string125.base, #t~string125.offset := #Ultimate.alloc(12); [L2150] call #t~string134.base, #t~string134.offset := #Ultimate.alloc(42); [L2159] call #t~string140.base, #t~string140.offset := #Ultimate.alloc(42); [L2175] call #t~string148.base, #t~string148.offset := #Ultimate.alloc(32); [L2189] call #t~string149.base, #t~string149.offset := #Ultimate.alloc(21); [L2211] call #t~string193.base, #t~string193.offset := #Ultimate.alloc(37); [L2218] call #t~string195.base, #t~string195.offset := #Ultimate.alloc(10); [L2220] call #t~string198.base, #t~string198.offset := #Ultimate.alloc(50); [L2226] call #t~string200.base, #t~string200.offset := #Ultimate.alloc(32); [L2323] call #t~string222.base, #t~string222.offset := #Ultimate.alloc(10); [L1713] ~ldv_irq_1_2~0 := 0; [L1714] ~LDV_IN_INTERRUPT~0 := 1; [L1715] ~ldv_irq_1_3~0 := 0; [L1717] ~ldv_irq_data_1_1~0.base, ~ldv_irq_data_1_1~0.offset := 0, 0; [L1718] ~ldv_irq_1_1~0 := 0; [L1719] ~ldv_irq_1_0~0 := 0; [L1720] ~ldv_irq_line_1_3~0 := 0; [L1721] ~ldv_irq_data_1_0~0.base, ~ldv_irq_data_1_0~0.offset := 0, 0; [L1722] ~ldv_state_variable_0~0 := 0; [L1724] ~ldv_state_variable_3~0 := 0; [L1725] ~ldv_irq_line_1_0~0 := 0; [L1726] ~ldv_state_variable_2~0 := 0; [L1727] ~ldv_irq_data_1_3~0.base, ~ldv_irq_data_1_3~0.offset := 0, 0; [L1728] ~ref_cnt~0 := 0; [L1729] ~ldv_irq_line_1_1~0 := 0; [L1731] ~ldv_irq_data_1_2~0.base, ~ldv_irq_data_1_2~0.offset := 0, 0; [L1732] ~ldv_state_variable_1~0 := 0; [L1733] ~ldv_irq_line_1_2~0 := 0; [L2342] ~ldv_retval_2~0 := 0; [L2343] ~ldv_retval_0~0 := 0; [L2345] ~ldv_retval_1~0 := 0; [L2943] ~ldv_init~0 := 0; [L1716] ~tegra_rtc_driver_group0~0.base, ~tegra_rtc_driver_group0~0.offset := 0, 0; [L1723] ~tegra_rtc_ops_group1~0.base, ~tegra_rtc_ops_group1~0.offset := 0, 0; [L1730] ~tegra_rtc_ops_group0~0.base, ~tegra_rtc_ops_group0~0.offset := 0, 0; [L1734] ~tegra_rtc_ops_group2~0.base, ~tegra_rtc_ops_group2~0.offset := 0, 0; [L2123-L2125] call ~#tegra_rtc_ops~0.base, ~#tegra_rtc_ops~0.offset := #Ultimate.alloc(88); [L2123-L2125] call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, ~#tegra_rtc_ops~0.offset, 8); [L2123-L2125] call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 8 + ~#tegra_rtc_ops~0.offset, 8); [L2123-L2125] call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 16 + ~#tegra_rtc_ops~0.offset, 8); [L2123-L2125] call write~init~$Pointer$(#funAddr~tegra_rtc_read_time.base, #funAddr~tegra_rtc_read_time.offset, ~#tegra_rtc_ops~0.base, 24 + ~#tegra_rtc_ops~0.offset, 8); [L2123-L2125] call write~init~$Pointer$(#funAddr~tegra_rtc_set_time.base, #funAddr~tegra_rtc_set_time.offset, ~#tegra_rtc_ops~0.base, 32 + ~#tegra_rtc_ops~0.offset, 8); [L2123-L2125] call write~init~$Pointer$(#funAddr~tegra_rtc_read_alarm.base, #funAddr~tegra_rtc_read_alarm.offset, ~#tegra_rtc_ops~0.base, 40 + ~#tegra_rtc_ops~0.offset, 8); [L2123-L2125] call write~init~$Pointer$(#funAddr~tegra_rtc_set_alarm.base, #funAddr~tegra_rtc_set_alarm.offset, ~#tegra_rtc_ops~0.base, 48 + ~#tegra_rtc_ops~0.offset, 8); [L2123-L2125] call write~init~$Pointer$(#funAddr~tegra_rtc_proc.base, #funAddr~tegra_rtc_proc.offset, ~#tegra_rtc_ops~0.base, 56 + ~#tegra_rtc_ops~0.offset, 8); [L2123-L2125] call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 64 + ~#tegra_rtc_ops~0.offset, 8); [L2123-L2125] call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 72 + ~#tegra_rtc_ops~0.offset, 8); [L2123-L2125] call write~init~$Pointer$(#funAddr~tegra_rtc_alarm_irq_enable.base, #funAddr~tegra_rtc_alarm_irq_enable.offset, ~#tegra_rtc_ops~0.base, 80 + ~#tegra_rtc_ops~0.offset, 8); [L2322-L2323] call ~#tegra_rtc_driver~0.base, ~#tegra_rtc_driver~0.offset := #Ultimate.alloc(153); [L2322-L2323] call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, ~#tegra_rtc_driver~0.offset, 8); [L2322-L2323] call write~init~$Pointer$(#funAddr~tegra_rtc_remove.base, #funAddr~tegra_rtc_remove.offset, ~#tegra_rtc_driver~0.base, 8 + ~#tegra_rtc_driver~0.offset, 8); [L2322-L2323] call write~init~$Pointer$(#funAddr~tegra_rtc_shutdown.base, #funAddr~tegra_rtc_shutdown.offset, ~#tegra_rtc_driver~0.base, 16 + ~#tegra_rtc_driver~0.offset, 8); [L2322-L2323] call write~init~$Pointer$(#funAddr~tegra_rtc_suspend.base, #funAddr~tegra_rtc_suspend.offset, ~#tegra_rtc_driver~0.base, 24 + ~#tegra_rtc_driver~0.offset, 8); [L2322-L2323] call write~init~$Pointer$(#funAddr~tegra_rtc_resume.base, #funAddr~tegra_rtc_resume.offset, ~#tegra_rtc_driver~0.base, 32 + ~#tegra_rtc_driver~0.offset, 8); [L2322-L2323] call write~init~$Pointer$(#t~string222.base, #t~string222.offset, ~#tegra_rtc_driver~0.base, 40 + ~#tegra_rtc_driver~0.offset, 8); [L2322-L2323] call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 48 + ~#tegra_rtc_driver~0.offset, 8); [L2322-L2323] call write~init~$Pointer$(~#__this_module~0.base, ~#__this_module~0.offset, ~#tegra_rtc_driver~0.base, 56 + ~#tegra_rtc_driver~0.offset, 8); [L2322-L2323] call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 64 + ~#tegra_rtc_driver~0.offset, 8); [L2322-L2323] call write~init~int(0, ~#tegra_rtc_driver~0.base, 72 + ~#tegra_rtc_driver~0.offset, 1); [L2322-L2323] call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 73 + ~#tegra_rtc_driver~0.offset, 8); [L2322-L2323] call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 81 + ~#tegra_rtc_driver~0.offset, 8); [L2322-L2323] call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 89 + ~#tegra_rtc_driver~0.offset, 8); [L2322-L2323] call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 97 + ~#tegra_rtc_driver~0.offset, 8); [L2322-L2323] call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 105 + ~#tegra_rtc_driver~0.offset, 8); [L2322-L2323] call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 113 + ~#tegra_rtc_driver~0.offset, 8); [L2322-L2323] call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 121 + ~#tegra_rtc_driver~0.offset, 8); [L2322-L2323] call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 129 + ~#tegra_rtc_driver~0.offset, 8); [L2322-L2323] call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 137 + ~#tegra_rtc_driver~0.offset, 8); [L2322-L2323] call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 145 + ~#tegra_rtc_driver~0.offset, 8); VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(#NULL.base)=183, old(#NULL.offset)=219, old(#t~string125.base)=160, old(#t~string125.offset)=163, old(#t~string134.base)=235, old(#t~string134.offset)=169, old(#t~string140.base)=158, old(#t~string140.offset)=181, old(#t~string148.base)=187, old(#t~string148.offset)=207, old(#t~string149.base)=229, old(#t~string149.offset)=178, old(#t~string193.base)=211, old(#t~string193.offset)=173, old(#t~string195.base)=217, old(#t~string195.offset)=228, old(#t~string198.base)=176, old(#t~string198.offset)=182, old(#t~string200.base)=222, old(#t~string200.offset)=210, old(#t~string222.base)=212, old(#t~string222.offset)=191, old(#t~string90.base)=166, old(#t~string90.offset)=170, old(~#tegra_rtc_driver~0.base)=233, old(~#tegra_rtc_driver~0.offset)=190, old(~#tegra_rtc_ops~0.base)=226, old(~#tegra_rtc_ops~0.offset)=192, old(~LDV_IN_INTERRUPT~0)=172, old(~ldv_init~0)=196, old(~ldv_irq_1_0~0)=205, old(~ldv_irq_1_1~0)=195, old(~ldv_irq_1_2~0)=208, old(~ldv_irq_1_3~0)=194, old(~ldv_irq_data_1_0~0.base)=161, old(~ldv_irq_data_1_0~0.offset)=197, old(~ldv_irq_data_1_1~0.base)=213, old(~ldv_irq_data_1_1~0.offset)=185, old(~ldv_irq_data_1_2~0.base)=189, old(~ldv_irq_data_1_2~0.offset)=177, old(~ldv_irq_data_1_3~0.base)=154, old(~ldv_irq_data_1_3~0.offset)=202, old(~ldv_irq_line_1_0~0)=206, old(~ldv_irq_line_1_1~0)=232, old(~ldv_irq_line_1_2~0)=227, old(~ldv_irq_line_1_3~0)=167, old(~ldv_retval_0~0)=171, old(~ldv_retval_1~0)=164, old(~ldv_retval_2~0)=188, old(~ldv_state_variable_0~0)=184, old(~ldv_state_variable_1~0)=216, old(~ldv_state_variable_2~0)=209, old(~ldv_state_variable_3~0)=236, old(~ref_cnt~0)=204, old(~tegra_rtc_driver_group0~0.base)=223, old(~tegra_rtc_driver_group0~0.offset)=198, old(~tegra_rtc_ops_group0~0.base)=200, old(~tegra_rtc_ops_group0~0.offset)=180, old(~tegra_rtc_ops_group1~0.base)=220, old(~tegra_rtc_ops_group1~0.offset)=193, old(~tegra_rtc_ops_group2~0.base)=174, old(~tegra_rtc_ops_group2~0.offset)=157, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] ensures true; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(#NULL.base)=183, old(#NULL.offset)=219, old(#t~string125.base)=160, old(#t~string125.offset)=163, old(#t~string134.base)=235, old(#t~string134.offset)=169, old(#t~string140.base)=158, old(#t~string140.offset)=181, old(#t~string148.base)=187, old(#t~string148.offset)=207, old(#t~string149.base)=229, old(#t~string149.offset)=178, old(#t~string193.base)=211, old(#t~string193.offset)=173, old(#t~string195.base)=217, old(#t~string195.offset)=228, old(#t~string198.base)=176, old(#t~string198.offset)=182, old(#t~string200.base)=222, old(#t~string200.offset)=210, old(#t~string222.base)=212, old(#t~string222.offset)=191, old(#t~string90.base)=166, old(#t~string90.offset)=170, old(~#tegra_rtc_driver~0.base)=233, old(~#tegra_rtc_driver~0.offset)=190, old(~#tegra_rtc_ops~0.base)=226, old(~#tegra_rtc_ops~0.offset)=192, old(~LDV_IN_INTERRUPT~0)=172, old(~ldv_init~0)=196, old(~ldv_irq_1_0~0)=205, old(~ldv_irq_1_1~0)=195, old(~ldv_irq_1_2~0)=208, old(~ldv_irq_1_3~0)=194, old(~ldv_irq_data_1_0~0.base)=161, old(~ldv_irq_data_1_0~0.offset)=197, old(~ldv_irq_data_1_1~0.base)=213, old(~ldv_irq_data_1_1~0.offset)=185, old(~ldv_irq_data_1_2~0.base)=189, old(~ldv_irq_data_1_2~0.offset)=177, old(~ldv_irq_data_1_3~0.base)=154, old(~ldv_irq_data_1_3~0.offset)=202, old(~ldv_irq_line_1_0~0)=206, old(~ldv_irq_line_1_1~0)=232, old(~ldv_irq_line_1_2~0)=227, old(~ldv_irq_line_1_3~0)=167, old(~ldv_retval_0~0)=171, old(~ldv_retval_1~0)=164, old(~ldv_retval_2~0)=188, old(~ldv_state_variable_0~0)=184, old(~ldv_state_variable_1~0)=216, old(~ldv_state_variable_2~0)=209, old(~ldv_state_variable_3~0)=236, old(~ref_cnt~0)=204, old(~tegra_rtc_driver_group0~0.base)=223, old(~tegra_rtc_driver_group0~0.offset)=198, old(~tegra_rtc_ops_group0~0.base)=200, old(~tegra_rtc_ops_group0~0.offset)=180, old(~tegra_rtc_ops_group1~0.base)=220, old(~tegra_rtc_ops_group1~0.offset)=193, old(~tegra_rtc_ops_group2~0.base)=174, old(~tegra_rtc_ops_group2~0.offset)=157, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] RET call ULTIMATE.init(); VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] CALL call #t~ret277 := main(); VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [L2518] havoc ~ldvarg1~0.base, ~ldvarg1~0.offset; [L2519] havoc ~tmp~27.base, ~tmp~27.offset; [L2520] havoc ~ldvarg0~0; [L2521] havoc ~tmp___0~8; [L2522] call ~#ldvarg2~0.base, ~#ldvarg2~0.offset := #Ultimate.alloc(4); [L2523] havoc ~tmp___1~5; [L2524] havoc ~tmp___2~1; [L2525] havoc ~tmp___3~1; [L2526] havoc ~tmp___4~1; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [L2529] CALL call #t~ret237.base, #t~ret237.offset := ldv_zalloc(136); VAL [#in~size=136, #NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [L1633-L1650] ~size := #in~size; [L1635] havoc ~p~1.base, ~p~1.offset; [L1636] havoc ~tmp~1.base, ~tmp~1.offset; [L1637] havoc ~tmp___0~1; [L1640] assume -2147483648 <= #t~nondet12 && #t~nondet12 <= 2147483647; [L1640] ~tmp___0~1 := #t~nondet12; [L1640] havoc #t~nondet12; VAL [#in~size=136, #NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~size=136, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~1=1] [L1641-L1648] assume 0 != ~tmp___0~1; [L1642] #res.base, #res.offset := 0, 0; VAL [#in~size=136, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~size=136, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~1=1] [L1584] ensures true; VAL [#in~size=136, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~size=136, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~1=1] [L2529] RET call #t~ret237.base, #t~ret237.offset := ldv_zalloc(136); VAL [#NULL.base=0, #NULL.offset=0, #t~ret237.base=0, #t~ret237.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [L2529] ~tmp~27.base, ~tmp~27.offset := #t~ret237.base, #t~ret237.offset; [L2529] havoc #t~ret237.base, #t~ret237.offset; [L2530] ~ldvarg1~0.base, ~ldvarg1~0.offset := ~tmp~27.base, ~tmp~27.offset; [L2531] ~tmp___0~8 := #t~nondet238; [L2531] havoc #t~nondet238; [L2532] ~ldvarg0~0 := ~tmp___0~8; [L2533] call ldv_initialize(); VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp~27.base=0, ~tmp~27.offset=0] [L2534] CALL call #t~memset~res239.base, #t~memset~res239.offset := #Ultimate.C_memset(~#ldvarg2~0.base, ~#ldvarg2~0.offset, 0, 4); VAL [#amount=4, #NULL.base=0, #NULL.offset=0, #ptr.base=225, #ptr.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #value=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] #t~loopctr278 := 0; VAL [#amount=4, #NULL.base=0, #NULL.offset=0, #ptr.base=225, #ptr.offset=0, #t~loopctr278=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #value=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume #t~loopctr278 < #amount; [?] #memory_$Pointer$.base, #memory_$Pointer$.offset := #memory_$Pointer$.base[#ptr.base,#ptr.offset + #t~loopctr278 := 0], #memory_$Pointer$.offset[#ptr.base,#ptr.offset + #t~loopctr278 := #value % 256]; [?] #memory_int := #memory_int[#ptr.base,#ptr.offset + #t~loopctr278 := #value]; [?] #t~loopctr278 := 1 + #t~loopctr278; VAL [#amount=4, #NULL.base=0, #NULL.offset=0, #ptr.base=225, #ptr.offset=0, #t~loopctr278=1, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #value=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume #t~loopctr278 < #amount; [?] #memory_$Pointer$.base, #memory_$Pointer$.offset := #memory_$Pointer$.base[#ptr.base,#ptr.offset + #t~loopctr278 := 0], #memory_$Pointer$.offset[#ptr.base,#ptr.offset + #t~loopctr278 := #value % 256]; [?] #memory_int := #memory_int[#ptr.base,#ptr.offset + #t~loopctr278 := #value]; [?] #t~loopctr278 := 1 + #t~loopctr278; VAL [#amount=4, #NULL.base=0, #NULL.offset=0, #ptr.base=225, #ptr.offset=0, #t~loopctr278=2, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #value=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume #t~loopctr278 < #amount; [?] #memory_$Pointer$.base, #memory_$Pointer$.offset := #memory_$Pointer$.base[#ptr.base,#ptr.offset + #t~loopctr278 := 0], #memory_$Pointer$.offset[#ptr.base,#ptr.offset + #t~loopctr278 := #value % 256]; [?] #memory_int := #memory_int[#ptr.base,#ptr.offset + #t~loopctr278 := #value]; [?] #t~loopctr278 := 1 + #t~loopctr278; VAL [#amount=4, #NULL.base=0, #NULL.offset=0, #ptr.base=225, #ptr.offset=0, #t~loopctr278=3, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #value=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume #t~loopctr278 < #amount; [?] #memory_$Pointer$.base, #memory_$Pointer$.offset := #memory_$Pointer$.base[#ptr.base,#ptr.offset + #t~loopctr278 := 0], #memory_$Pointer$.offset[#ptr.base,#ptr.offset + #t~loopctr278 := #value % 256]; [?] #memory_int := #memory_int[#ptr.base,#ptr.offset + #t~loopctr278 := #value]; [?] #t~loopctr278 := 1 + #t~loopctr278; VAL [#amount=4, #NULL.base=0, #NULL.offset=0, #ptr.base=225, #ptr.offset=0, #t~loopctr278=4, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #value=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume !(#t~loopctr278 < #amount); VAL [#amount=4, #NULL.base=0, #NULL.offset=0, #ptr.base=225, #ptr.offset=0, #t~loopctr278=4, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #value=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] free ensures #res.base == #ptr.base && #res.offset == #ptr.offset; VAL [#amount=4, #NULL.base=0, #NULL.offset=0, #ptr.base=225, #ptr.offset=0, #res.base=225, #res.offset=0, #t~loopctr278=4, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #value=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [L2534] RET call #t~memset~res239.base, #t~memset~res239.offset := #Ultimate.C_memset(~#ldvarg2~0.base, ~#ldvarg2~0.offset, 0, 4); VAL [#NULL.base=0, #NULL.offset=0, #t~memset~res239.base=225, #t~memset~res239.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp~27.base=0, ~tmp~27.offset=0] [L2534] havoc #t~memset~res239.base, #t~memset~res239.offset; [L2535] ~ldv_state_variable_1~0 := 1; [L2536] ~ref_cnt~0 := 0; [L2537] ~ldv_state_variable_0~0 := 1; [L2538] ~ldv_state_variable_3~0 := 0; [L2539] ~ldv_state_variable_2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp~27.base=0, ~tmp~27.offset=0] [L2541] assume -2147483648 <= #t~nondet240 && #t~nondet240 <= 2147483647; [L2541] ~tmp___1~5 := #t~nondet240; [L2541] havoc #t~nondet240; [L2543] #t~switch241 := 0 == ~tmp___1~5; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=false, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=1, ~tmp~27.base=0, ~tmp~27.offset=0] [L2543] assume !#t~switch241; [L2550] #t~switch241 := #t~switch241 || 1 == ~tmp___1~5; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=1, ~tmp~27.base=0, ~tmp~27.offset=0] [L2550] assume #t~switch241; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=1, ~tmp~27.base=0, ~tmp~27.offset=0] [L2551-L2589] assume 0 != ~ldv_state_variable_0~0; [L2552] assume -2147483648 <= #t~nondet242 && #t~nondet242 <= 2147483647; [L2552] ~tmp___2~1 := #t~nondet242; [L2552] havoc #t~nondet242; [L2554] #t~switch243 := 0 == ~tmp___2~1; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=true, #t~switch243=false, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=1, ~tmp___2~1=1, ~tmp~27.base=0, ~tmp~27.offset=0] [L2554] assume !#t~switch243; [L2563] #t~switch243 := #t~switch243 || 1 == ~tmp___2~1; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=1, ~tmp___2~1=1, ~tmp~27.base=0, ~tmp~27.offset=0] [L2563] assume #t~switch243; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=1, ~tmp___2~1=1, ~tmp~27.base=0, ~tmp~27.offset=0] [L2564-L2581] assume 1 == ~ldv_state_variable_0~0; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=1, ~tmp___2~1=1, ~tmp~27.base=0, ~tmp~27.offset=0] [L2565] CALL call #t~ret244 := tegra_rtc_init(); VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [L2326] havoc ~tmp~22; [L2329] call #t~ret223 := platform_driver_probe(~#tegra_rtc_driver~0.base, ~#tegra_rtc_driver~0.offset, #funAddr~tegra_rtc_probe.base, #funAddr~tegra_rtc_probe.offset); [L2329] assume -2147483648 <= #t~ret223 && #t~ret223 <= 2147483647; [L2329] ~tmp~22 := #t~ret223; [L2329] havoc #t~ret223; [L2330] #res := ~tmp~22; VAL [#NULL.base=0, #NULL.offset=0, #res=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp~22=0] [L2324-L2332] ensures true; VAL [#NULL.base=0, #NULL.offset=0, #res=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp~22=0] [L2565] RET call #t~ret244 := tegra_rtc_init(); VAL [#NULL.base=0, #NULL.offset=0, #t~ret244=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=1, ~tmp___2~1=1, ~tmp~27.base=0, ~tmp~27.offset=0] [L2565] assume -2147483648 <= #t~ret244 && #t~ret244 <= 2147483647; [L2565] ~ldv_retval_0~0 := #t~ret244; [L2565] havoc #t~ret244; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=1, ~tmp___2~1=1, ~tmp~27.base=0, ~tmp~27.offset=0] [L2566-L2572] assume 0 == ~ldv_retval_0~0; [L2567] ~ldv_state_variable_0~0 := 3; [L2568] ~ldv_state_variable_2~0 := 1; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=1, ~tmp___2~1=1, ~tmp~27.base=0, ~tmp~27.offset=0] [L2569] CALL call ldv_initialize_platform_driver_2(); VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [L2476] havoc ~tmp~26.base, ~tmp~26.offset; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [L2479] CALL call #t~ret236.base, #t~ret236.offset := ldv_zalloc(624); VAL [#in~size=624, #NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [L1633-L1650] ~size := #in~size; [L1635] havoc ~p~1.base, ~p~1.offset; [L1636] havoc ~tmp~1.base, ~tmp~1.offset; [L1637] havoc ~tmp___0~1; [L1640] assume -2147483648 <= #t~nondet12 && #t~nondet12 <= 2147483647; [L1640] ~tmp___0~1 := #t~nondet12; [L1640] havoc #t~nondet12; VAL [#in~size=624, #NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~size=624, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~1=1] [L1641-L1648] assume 0 != ~tmp___0~1; [L1642] #res.base, #res.offset := 0, 0; VAL [#in~size=624, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~size=624, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~1=1] [L1584] ensures true; VAL [#in~size=624, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~size=624, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~1=1] [L2479] RET call #t~ret236.base, #t~ret236.offset := ldv_zalloc(624); VAL [#NULL.base=0, #NULL.offset=0, #t~ret236.base=0, #t~ret236.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [L2479] ~tmp~26.base, ~tmp~26.offset := #t~ret236.base, #t~ret236.offset; [L2479] havoc #t~ret236.base, #t~ret236.offset; [L2480] ~tegra_rtc_driver_group0~0.base, ~tegra_rtc_driver_group0~0.offset := ~tmp~26.base, ~tmp~26.offset; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp~26.base=0, ~tmp~26.offset=0] [L1740] ensures true; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp~26.base=0, ~tmp~26.offset=0] [L2569] RET call ldv_initialize_platform_driver_2(); VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=1, ~tmp___2~1=1, ~tmp~27.base=0, ~tmp~27.offset=0] [L2573-L2578] assume !(0 != ~ldv_retval_0~0); VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=1, ~tmp___2~1=1, ~tmp~27.base=0, ~tmp~27.offset=0] [L2541] assume -2147483648 <= #t~nondet240 && #t~nondet240 <= 2147483647; [L2541] ~tmp___1~5 := #t~nondet240; [L2541] havoc #t~nondet240; [L2543] #t~switch241 := 0 == ~tmp___1~5; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=false, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp~27.base=0, ~tmp~27.offset=0] [L2543] assume !#t~switch241; [L2550] #t~switch241 := #t~switch241 || 1 == ~tmp___1~5; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=false, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp~27.base=0, ~tmp~27.offset=0] [L2550] assume !#t~switch241; [L2591] #t~switch241 := #t~switch241 || 2 == ~tmp___1~5; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=false, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp~27.base=0, ~tmp~27.offset=0] [L2591] assume !#t~switch241; [L2699] #t~switch241 := #t~switch241 || 3 == ~tmp___1~5; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp~27.base=0, ~tmp~27.offset=0] [L2699] assume #t~switch241; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp~27.base=0, ~tmp~27.offset=0] [L2700-L2779] assume 0 != ~ldv_state_variable_2~0; [L2701] assume -2147483648 <= #t~nondet260 && #t~nondet260 <= 2147483647; [L2701] ~tmp___4~1 := #t~nondet260; [L2701] havoc #t~nondet260; [L2703] #t~switch261 := 0 == ~tmp___4~1; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=true, #t~switch243=true, #t~switch261=false, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp___4~1=4, ~tmp~27.base=0, ~tmp~27.offset=0] [L2703] assume !#t~switch261; [L2717] #t~switch261 := #t~switch261 || 1 == ~tmp___4~1; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=true, #t~switch243=true, #t~switch261=false, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp___4~1=4, ~tmp~27.base=0, ~tmp~27.offset=0] [L2717] assume !#t~switch261; [L2729] #t~switch261 := #t~switch261 || 2 == ~tmp___4~1; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=true, #t~switch243=true, #t~switch261=false, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp___4~1=4, ~tmp~27.base=0, ~tmp~27.offset=0] [L2729] assume !#t~switch261; [L2752] #t~switch261 := #t~switch261 || 3 == ~tmp___4~1; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=true, #t~switch243=true, #t~switch261=false, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp___4~1=4, ~tmp~27.base=0, ~tmp~27.offset=0] [L2752] assume !#t~switch261; [L2764] #t~switch261 := #t~switch261 || 4 == ~tmp___4~1; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp___4~1=4, ~tmp~27.base=0, ~tmp~27.offset=0] [L2764] assume #t~switch261; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp___4~1=4, ~tmp~27.base=0, ~tmp~27.offset=0] [L2765-L2771] assume 1 == ~ldv_state_variable_2~0; [L2766] call #t~ret268 := ldv_probe_2(); [L2766] assume -2147483648 <= #t~ret268 && #t~ret268 <= 2147483647; [L2766] havoc #t~ret268; [L2767] ~ldv_state_variable_2~0 := 2; [L2768] ~ref_cnt~0 := 1 + ~ref_cnt~0; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp___4~1=4, ~tmp~27.base=0, ~tmp~27.offset=0] [L2541] assume -2147483648 <= #t~nondet240 && #t~nondet240 <= 2147483647; [L2541] ~tmp___1~5 := #t~nondet240; [L2541] havoc #t~nondet240; [L2543] #t~switch241 := 0 == ~tmp___1~5; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=false, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp___4~1=4, ~tmp~27.base=0, ~tmp~27.offset=0] [L2543] assume !#t~switch241; [L2550] #t~switch241 := #t~switch241 || 1 == ~tmp___1~5; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=false, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp___4~1=4, ~tmp~27.base=0, ~tmp~27.offset=0] [L2550] assume !#t~switch241; [L2591] #t~switch241 := #t~switch241 || 2 == ~tmp___1~5; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=false, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp___4~1=4, ~tmp~27.base=0, ~tmp~27.offset=0] [L2591] assume !#t~switch241; [L2699] #t~switch241 := #t~switch241 || 3 == ~tmp___1~5; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp___4~1=4, ~tmp~27.base=0, ~tmp~27.offset=0] [L2699] assume #t~switch241; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp___4~1=4, ~tmp~27.base=0, ~tmp~27.offset=0] [L2700-L2779] assume 0 != ~ldv_state_variable_2~0; [L2701] assume -2147483648 <= #t~nondet260 && #t~nondet260 <= 2147483647; [L2701] ~tmp___4~1 := #t~nondet260; [L2701] havoc #t~nondet260; [L2703] #t~switch261 := 0 == ~tmp___4~1; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp___4~1=0, ~tmp~27.base=0, ~tmp~27.offset=0] [L2703] assume #t~switch261; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp___4~1=0, ~tmp~27.base=0, ~tmp~27.offset=0] [L2704-L2709] assume !(4 == ~ldv_state_variable_2~0); VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp___4~1=0, ~tmp~27.base=0, ~tmp~27.offset=0] [L2710-L2715] assume 2 == ~ldv_state_variable_2~0; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp___4~1=0, ~tmp~27.base=0, ~tmp~27.offset=0] [L2711] CALL call tegra_rtc_shutdown(~tegra_rtc_driver_group0~0.base, ~tegra_rtc_driver_group0~0.offset); VAL [#in~pdev.base=0, #in~pdev.offset=0, #NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [L2313-L2321] ~pdev.base, ~pdev.offset := #in~pdev.base, #in~pdev.offset; VAL [#in~pdev.base=0, #in~pdev.offset=0, #NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~pdev.base=0, ~pdev.offset=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [L2318] CALL call #t~ret221 := tegra_rtc_alarm_irq_enable(~pdev.base, 12 + ~pdev.offset, 0); VAL [#in~dev.base=0, #in~dev.offset=12, #in~enabled=0, #NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [L2004-L2033] ~dev.base, ~dev.offset := #in~dev.base, #in~dev.offset; [L2004-L2033] ~enabled := #in~enabled; [L2006] havoc ~info~4.base, ~info~4.offset; [L2007] havoc ~tmp~14.base, ~tmp~14.offset; [L2008] havoc ~status~0; [L2009] havoc ~sl_irq_flags~1; [L2010] havoc ~__v~3; [L2011] havoc ~__v___0~3; [L2014] call #t~ret107.base, #t~ret107.offset := dev_get_drvdata(~dev.base, ~dev.offset); [L2014] ~tmp~14.base, ~tmp~14.offset := #t~ret107.base, #t~ret107.offset; [L2014] havoc #t~ret107.base, #t~ret107.offset; [L2015] ~info~4.base, ~info~4.offset := ~tmp~14.base, ~tmp~14.offset; VAL [#in~dev.base=0, #in~dev.offset=12, #in~enabled=0, #NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~dev.base=0, ~dev.offset=12, ~enabled=0, ~info~4.base=156, ~info~4.offset=215, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp~14.base=156, ~tmp~14.offset=215] [L2016] CALL call #t~ret108 := tegra_rtc_wait_while_busy(~dev.base, ~dev.offset); VAL [#in~dev.base=0, #in~dev.offset=12, #NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [L1873-L1908] ~dev.base, ~dev.offset := #in~dev.base, #in~dev.offset; [L1875] havoc ~info~0.base, ~info~0.offset; [L1876] havoc ~tmp~10.base, ~tmp~10.offset; [L1877] havoc ~retries~0; [L1878] havoc ~tmp___0~2; [L1879] havoc ~tmp___1~0; [L1882] call #t~ret87.base, #t~ret87.offset := dev_get_drvdata(~dev.base, ~dev.offset); [L1882] ~tmp~10.base, ~tmp~10.offset := #t~ret87.base, #t~ret87.offset; [L1882] havoc #t~ret87.base, #t~ret87.offset; [L1883] ~info~0.base, ~info~0.offset := ~tmp~10.base, ~tmp~10.offset; [L1884] ~retries~0 := 500; VAL [#in~dev.base=0, #in~dev.offset=12, #NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~dev.base=0, ~dev.offset=12, ~info~0.base=165, ~info~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~retries~0=500, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp~10.base=165, ~tmp~10.offset=0] [L1896] CALL call #t~ret88 := tegra_rtc_check_busy(~info~0.base, ~info~0.offset); VAL [#in~info.base=165, #in~info.offset=0, #NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [L1861-L1872] ~info.base, ~info.offset := #in~info.base, #in~info.offset; [L1863] havoc ~__v~0; [L1864] havoc ~__v___0~0; [L1867] call #t~mem85.base, #t~mem85.offset := read~$Pointer$(~info.base, 16 + ~info.offset, 8); [L1867] call #t~mem86 := read~int(#t~mem85.base, 16 + #t~mem85.offset, 4); [L1867] ~__v___0~0 := #t~mem86; [L1867] havoc #t~mem86; [L1867] havoc #t~mem85.base, #t~mem85.offset; [L1868] ~__v~0 := ~__v___0~0; [L1870] #res := ~bitwiseAnd(~__v~0, 1); VAL [#in~info.base=165, #in~info.offset=0, #NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~__v___0~0=201, ~__v~0=201, ~info.base=165, ~info.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [L1861-L1872] ensures true; VAL [#in~info.base=165, #in~info.offset=0, #NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~__v___0~0=201, ~__v~0=201, ~info.base=165, ~info.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [L1896] RET call #t~ret88 := tegra_rtc_check_busy(~info~0.base, ~info~0.offset); VAL [#in~dev.base=0, #in~dev.offset=12, #NULL.base=0, #NULL.offset=0, #t~ret88=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~dev.base=0, ~dev.offset=12, ~info~0.base=165, ~info~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~retries~0=500, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp~10.base=165, ~tmp~10.offset=0] [L1896] ~tmp___1~0 := #t~ret88; [L1896] havoc #t~ret88; VAL [#in~dev.base=0, #in~dev.offset=12, #NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~dev.base=0, ~dev.offset=12, ~info~0.base=165, ~info~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~retries~0=500, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___1~0=0, ~tmp~10.base=165, ~tmp~10.offset=0] [L1897-L1901] assume !(0 != ~tmp___1~0 % 4294967296); [L1903] #res := 0; VAL [#in~dev.base=0, #in~dev.offset=12, #NULL.base=0, #NULL.offset=0, #res=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~dev.base=0, ~dev.offset=12, ~info~0.base=165, ~info~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~retries~0=500, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___1~0=0, ~tmp~10.base=165, ~tmp~10.offset=0] [L1873-L1908] ensures true; VAL [#in~dev.base=0, #in~dev.offset=12, #NULL.base=0, #NULL.offset=0, #res=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~dev.base=0, ~dev.offset=12, ~info~0.base=165, ~info~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~retries~0=500, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___1~0=0, ~tmp~10.base=165, ~tmp~10.offset=0] [L2016] RET call #t~ret108 := tegra_rtc_wait_while_busy(~dev.base, ~dev.offset); VAL [#in~dev.base=0, #in~dev.offset=12, #in~enabled=0, #NULL.base=0, #NULL.offset=0, #t~ret108=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~dev.base=0, ~dev.offset=12, ~enabled=0, ~info~4.base=156, ~info~4.offset=215, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp~14.base=156, ~tmp~14.offset=215] [L2016] assume -2147483648 <= #t~ret108 && #t~ret108 <= 2147483647; [L2016] havoc #t~ret108; VAL [#in~dev.base=0, #in~dev.offset=12, #in~enabled=0, #NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~dev.base=0, ~dev.offset=12, ~enabled=0, ~info~4.base=156, ~info~4.offset=215, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp~14.base=156, ~tmp~14.offset=215] [L2017] CALL call ldv_spin_lock_check(); VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [L2962-L2966] assume !(1 == ~ldv_init~0); VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [L2965] CALL call ldv_error(); VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [L1684] assert false; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] ----- [2018-11-22 23:40:02,643 WARN L416 cessorBacktranslator]: Generated EnsuresSpecification free ensures #res.base == #ptr.base && #res.offset == #ptr.offset; is not ensure(true) ----- class de.uni_freiburg.informatik.ultimate.boogie.preprocessor.BoogiePreprocessorBacktranslator [?] CALL call ULTIMATE.init(); VAL [#NULL.base=183, #NULL.offset=219, #t~string125.base=160, #t~string125.offset=163, #t~string134.base=235, #t~string134.offset=169, #t~string140.base=158, #t~string140.offset=181, #t~string148.base=187, #t~string148.offset=207, #t~string149.base=229, #t~string149.offset=178, #t~string193.base=211, #t~string193.offset=173, #t~string195.base=217, #t~string195.offset=228, #t~string198.base=176, #t~string198.offset=182, #t~string200.base=222, #t~string200.offset=210, #t~string222.base=212, #t~string222.offset=191, #t~string90.base=166, #t~string90.offset=170, old(#NULL.base)=183, old(#NULL.offset)=219, old(#t~string125.base)=160, old(#t~string125.offset)=163, old(#t~string134.base)=235, old(#t~string134.offset)=169, old(#t~string140.base)=158, old(#t~string140.offset)=181, old(#t~string148.base)=187, old(#t~string148.offset)=207, old(#t~string149.base)=229, old(#t~string149.offset)=178, old(#t~string193.base)=211, old(#t~string193.offset)=173, old(#t~string195.base)=217, old(#t~string195.offset)=228, old(#t~string198.base)=176, old(#t~string198.offset)=182, old(#t~string200.base)=222, old(#t~string200.offset)=210, old(#t~string222.base)=212, old(#t~string222.offset)=191, old(#t~string90.base)=166, old(#t~string90.offset)=170, old(~#tegra_rtc_driver~0.base)=233, old(~#tegra_rtc_driver~0.offset)=190, old(~#tegra_rtc_ops~0.base)=226, old(~#tegra_rtc_ops~0.offset)=192, old(~LDV_IN_INTERRUPT~0)=172, old(~ldv_init~0)=196, old(~ldv_irq_1_0~0)=205, old(~ldv_irq_1_1~0)=195, old(~ldv_irq_1_2~0)=208, old(~ldv_irq_1_3~0)=194, old(~ldv_irq_data_1_0~0.base)=161, old(~ldv_irq_data_1_0~0.offset)=197, old(~ldv_irq_data_1_1~0.base)=213, old(~ldv_irq_data_1_1~0.offset)=185, old(~ldv_irq_data_1_2~0.base)=189, old(~ldv_irq_data_1_2~0.offset)=177, old(~ldv_irq_data_1_3~0.base)=154, old(~ldv_irq_data_1_3~0.offset)=202, old(~ldv_irq_line_1_0~0)=206, old(~ldv_irq_line_1_1~0)=232, old(~ldv_irq_line_1_2~0)=227, old(~ldv_irq_line_1_3~0)=167, old(~ldv_retval_0~0)=171, old(~ldv_retval_1~0)=164, old(~ldv_retval_2~0)=188, old(~ldv_state_variable_0~0)=184, old(~ldv_state_variable_1~0)=216, old(~ldv_state_variable_2~0)=209, old(~ldv_state_variable_3~0)=236, old(~ref_cnt~0)=204, old(~tegra_rtc_driver_group0~0.base)=223, old(~tegra_rtc_driver_group0~0.offset)=198, old(~tegra_rtc_ops_group0~0.base)=200, old(~tegra_rtc_ops_group0~0.offset)=180, old(~tegra_rtc_ops_group1~0.base)=220, old(~tegra_rtc_ops_group1~0.offset)=193, old(~tegra_rtc_ops_group2~0.base)=174, old(~tegra_rtc_ops_group2~0.offset)=157, ~#tegra_rtc_driver~0.base=233, ~#tegra_rtc_driver~0.offset=190, ~#tegra_rtc_ops~0.base=226, ~#tegra_rtc_ops~0.offset=192, ~LDV_IN_INTERRUPT~0=172, ~ldv_init~0=196, ~ldv_irq_1_0~0=205, ~ldv_irq_1_1~0=195, ~ldv_irq_1_2~0=208, ~ldv_irq_1_3~0=194, ~ldv_irq_data_1_0~0.base=161, ~ldv_irq_data_1_0~0.offset=197, ~ldv_irq_data_1_1~0.base=213, ~ldv_irq_data_1_1~0.offset=185, ~ldv_irq_data_1_2~0.base=189, ~ldv_irq_data_1_2~0.offset=177, ~ldv_irq_data_1_3~0.base=154, ~ldv_irq_data_1_3~0.offset=202, ~ldv_irq_line_1_0~0=206, ~ldv_irq_line_1_1~0=232, ~ldv_irq_line_1_2~0=227, ~ldv_irq_line_1_3~0=167, ~ldv_retval_0~0=171, ~ldv_retval_1~0=164, ~ldv_retval_2~0=188, ~ldv_state_variable_0~0=184, ~ldv_state_variable_1~0=216, ~ldv_state_variable_2~0=209, ~ldv_state_variable_3~0=236, ~ref_cnt~0=204, ~tegra_rtc_driver_group0~0.base=223, ~tegra_rtc_driver_group0~0.offset=198, ~tegra_rtc_ops_group0~0.base=200, ~tegra_rtc_ops_group0~0.offset=180, ~tegra_rtc_ops_group1~0.base=220, ~tegra_rtc_ops_group1~0.offset=193, ~tegra_rtc_ops_group2~0.base=174, ~tegra_rtc_ops_group2~0.offset=157] [?] #NULL.base, #NULL.offset := 0, 0; [?] #valid := #valid[0 := 0]; [L1905] call #t~string90.base, #t~string90.offset := #Ultimate.alloc(36); [L2072] call #t~string125.base, #t~string125.offset := #Ultimate.alloc(12); [L2150] call #t~string134.base, #t~string134.offset := #Ultimate.alloc(42); [L2159] call #t~string140.base, #t~string140.offset := #Ultimate.alloc(42); [L2175] call #t~string148.base, #t~string148.offset := #Ultimate.alloc(32); [L2189] call #t~string149.base, #t~string149.offset := #Ultimate.alloc(21); [L2211] call #t~string193.base, #t~string193.offset := #Ultimate.alloc(37); [L2218] call #t~string195.base, #t~string195.offset := #Ultimate.alloc(10); [L2220] call #t~string198.base, #t~string198.offset := #Ultimate.alloc(50); [L2226] call #t~string200.base, #t~string200.offset := #Ultimate.alloc(32); [L2323] call #t~string222.base, #t~string222.offset := #Ultimate.alloc(10); [L1713] ~ldv_irq_1_2~0 := 0; [L1714] ~LDV_IN_INTERRUPT~0 := 1; [L1715] ~ldv_irq_1_3~0 := 0; [L1717] ~ldv_irq_data_1_1~0.base, ~ldv_irq_data_1_1~0.offset := 0, 0; [L1718] ~ldv_irq_1_1~0 := 0; [L1719] ~ldv_irq_1_0~0 := 0; [L1720] ~ldv_irq_line_1_3~0 := 0; [L1721] ~ldv_irq_data_1_0~0.base, ~ldv_irq_data_1_0~0.offset := 0, 0; [L1722] ~ldv_state_variable_0~0 := 0; [L1724] ~ldv_state_variable_3~0 := 0; [L1725] ~ldv_irq_line_1_0~0 := 0; [L1726] ~ldv_state_variable_2~0 := 0; [L1727] ~ldv_irq_data_1_3~0.base, ~ldv_irq_data_1_3~0.offset := 0, 0; [L1728] ~ref_cnt~0 := 0; [L1729] ~ldv_irq_line_1_1~0 := 0; [L1731] ~ldv_irq_data_1_2~0.base, ~ldv_irq_data_1_2~0.offset := 0, 0; [L1732] ~ldv_state_variable_1~0 := 0; [L1733] ~ldv_irq_line_1_2~0 := 0; [L2342] ~ldv_retval_2~0 := 0; [L2343] ~ldv_retval_0~0 := 0; [L2345] ~ldv_retval_1~0 := 0; [L2943] ~ldv_init~0 := 0; [L1716] ~tegra_rtc_driver_group0~0.base, ~tegra_rtc_driver_group0~0.offset := 0, 0; [L1723] ~tegra_rtc_ops_group1~0.base, ~tegra_rtc_ops_group1~0.offset := 0, 0; [L1730] ~tegra_rtc_ops_group0~0.base, ~tegra_rtc_ops_group0~0.offset := 0, 0; [L1734] ~tegra_rtc_ops_group2~0.base, ~tegra_rtc_ops_group2~0.offset := 0, 0; [L2123-L2125] call ~#tegra_rtc_ops~0.base, ~#tegra_rtc_ops~0.offset := #Ultimate.alloc(88); [L2123-L2125] call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, ~#tegra_rtc_ops~0.offset, 8); [L2123-L2125] call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 8 + ~#tegra_rtc_ops~0.offset, 8); [L2123-L2125] call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 16 + ~#tegra_rtc_ops~0.offset, 8); [L2123-L2125] call write~init~$Pointer$(#funAddr~tegra_rtc_read_time.base, #funAddr~tegra_rtc_read_time.offset, ~#tegra_rtc_ops~0.base, 24 + ~#tegra_rtc_ops~0.offset, 8); [L2123-L2125] call write~init~$Pointer$(#funAddr~tegra_rtc_set_time.base, #funAddr~tegra_rtc_set_time.offset, ~#tegra_rtc_ops~0.base, 32 + ~#tegra_rtc_ops~0.offset, 8); [L2123-L2125] call write~init~$Pointer$(#funAddr~tegra_rtc_read_alarm.base, #funAddr~tegra_rtc_read_alarm.offset, ~#tegra_rtc_ops~0.base, 40 + ~#tegra_rtc_ops~0.offset, 8); [L2123-L2125] call write~init~$Pointer$(#funAddr~tegra_rtc_set_alarm.base, #funAddr~tegra_rtc_set_alarm.offset, ~#tegra_rtc_ops~0.base, 48 + ~#tegra_rtc_ops~0.offset, 8); [L2123-L2125] call write~init~$Pointer$(#funAddr~tegra_rtc_proc.base, #funAddr~tegra_rtc_proc.offset, ~#tegra_rtc_ops~0.base, 56 + ~#tegra_rtc_ops~0.offset, 8); [L2123-L2125] call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 64 + ~#tegra_rtc_ops~0.offset, 8); [L2123-L2125] call write~init~$Pointer$(0, 0, ~#tegra_rtc_ops~0.base, 72 + ~#tegra_rtc_ops~0.offset, 8); [L2123-L2125] call write~init~$Pointer$(#funAddr~tegra_rtc_alarm_irq_enable.base, #funAddr~tegra_rtc_alarm_irq_enable.offset, ~#tegra_rtc_ops~0.base, 80 + ~#tegra_rtc_ops~0.offset, 8); [L2322-L2323] call ~#tegra_rtc_driver~0.base, ~#tegra_rtc_driver~0.offset := #Ultimate.alloc(153); [L2322-L2323] call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, ~#tegra_rtc_driver~0.offset, 8); [L2322-L2323] call write~init~$Pointer$(#funAddr~tegra_rtc_remove.base, #funAddr~tegra_rtc_remove.offset, ~#tegra_rtc_driver~0.base, 8 + ~#tegra_rtc_driver~0.offset, 8); [L2322-L2323] call write~init~$Pointer$(#funAddr~tegra_rtc_shutdown.base, #funAddr~tegra_rtc_shutdown.offset, ~#tegra_rtc_driver~0.base, 16 + ~#tegra_rtc_driver~0.offset, 8); [L2322-L2323] call write~init~$Pointer$(#funAddr~tegra_rtc_suspend.base, #funAddr~tegra_rtc_suspend.offset, ~#tegra_rtc_driver~0.base, 24 + ~#tegra_rtc_driver~0.offset, 8); [L2322-L2323] call write~init~$Pointer$(#funAddr~tegra_rtc_resume.base, #funAddr~tegra_rtc_resume.offset, ~#tegra_rtc_driver~0.base, 32 + ~#tegra_rtc_driver~0.offset, 8); [L2322-L2323] call write~init~$Pointer$(#t~string222.base, #t~string222.offset, ~#tegra_rtc_driver~0.base, 40 + ~#tegra_rtc_driver~0.offset, 8); [L2322-L2323] call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 48 + ~#tegra_rtc_driver~0.offset, 8); [L2322-L2323] call write~init~$Pointer$(~#__this_module~0.base, ~#__this_module~0.offset, ~#tegra_rtc_driver~0.base, 56 + ~#tegra_rtc_driver~0.offset, 8); [L2322-L2323] call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 64 + ~#tegra_rtc_driver~0.offset, 8); [L2322-L2323] call write~init~int(0, ~#tegra_rtc_driver~0.base, 72 + ~#tegra_rtc_driver~0.offset, 1); [L2322-L2323] call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 73 + ~#tegra_rtc_driver~0.offset, 8); [L2322-L2323] call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 81 + ~#tegra_rtc_driver~0.offset, 8); [L2322-L2323] call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 89 + ~#tegra_rtc_driver~0.offset, 8); [L2322-L2323] call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 97 + ~#tegra_rtc_driver~0.offset, 8); [L2322-L2323] call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 105 + ~#tegra_rtc_driver~0.offset, 8); [L2322-L2323] call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 113 + ~#tegra_rtc_driver~0.offset, 8); [L2322-L2323] call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 121 + ~#tegra_rtc_driver~0.offset, 8); [L2322-L2323] call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 129 + ~#tegra_rtc_driver~0.offset, 8); [L2322-L2323] call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 137 + ~#tegra_rtc_driver~0.offset, 8); [L2322-L2323] call write~init~$Pointer$(0, 0, ~#tegra_rtc_driver~0.base, 145 + ~#tegra_rtc_driver~0.offset, 8); VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(#NULL.base)=183, old(#NULL.offset)=219, old(#t~string125.base)=160, old(#t~string125.offset)=163, old(#t~string134.base)=235, old(#t~string134.offset)=169, old(#t~string140.base)=158, old(#t~string140.offset)=181, old(#t~string148.base)=187, old(#t~string148.offset)=207, old(#t~string149.base)=229, old(#t~string149.offset)=178, old(#t~string193.base)=211, old(#t~string193.offset)=173, old(#t~string195.base)=217, old(#t~string195.offset)=228, old(#t~string198.base)=176, old(#t~string198.offset)=182, old(#t~string200.base)=222, old(#t~string200.offset)=210, old(#t~string222.base)=212, old(#t~string222.offset)=191, old(#t~string90.base)=166, old(#t~string90.offset)=170, old(~#tegra_rtc_driver~0.base)=233, old(~#tegra_rtc_driver~0.offset)=190, old(~#tegra_rtc_ops~0.base)=226, old(~#tegra_rtc_ops~0.offset)=192, old(~LDV_IN_INTERRUPT~0)=172, old(~ldv_init~0)=196, old(~ldv_irq_1_0~0)=205, old(~ldv_irq_1_1~0)=195, old(~ldv_irq_1_2~0)=208, old(~ldv_irq_1_3~0)=194, old(~ldv_irq_data_1_0~0.base)=161, old(~ldv_irq_data_1_0~0.offset)=197, old(~ldv_irq_data_1_1~0.base)=213, old(~ldv_irq_data_1_1~0.offset)=185, old(~ldv_irq_data_1_2~0.base)=189, old(~ldv_irq_data_1_2~0.offset)=177, old(~ldv_irq_data_1_3~0.base)=154, old(~ldv_irq_data_1_3~0.offset)=202, old(~ldv_irq_line_1_0~0)=206, old(~ldv_irq_line_1_1~0)=232, old(~ldv_irq_line_1_2~0)=227, old(~ldv_irq_line_1_3~0)=167, old(~ldv_retval_0~0)=171, old(~ldv_retval_1~0)=164, old(~ldv_retval_2~0)=188, old(~ldv_state_variable_0~0)=184, old(~ldv_state_variable_1~0)=216, old(~ldv_state_variable_2~0)=209, old(~ldv_state_variable_3~0)=236, old(~ref_cnt~0)=204, old(~tegra_rtc_driver_group0~0.base)=223, old(~tegra_rtc_driver_group0~0.offset)=198, old(~tegra_rtc_ops_group0~0.base)=200, old(~tegra_rtc_ops_group0~0.offset)=180, old(~tegra_rtc_ops_group1~0.base)=220, old(~tegra_rtc_ops_group1~0.offset)=193, old(~tegra_rtc_ops_group2~0.base)=174, old(~tegra_rtc_ops_group2~0.offset)=157, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] ensures true; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(#NULL.base)=183, old(#NULL.offset)=219, old(#t~string125.base)=160, old(#t~string125.offset)=163, old(#t~string134.base)=235, old(#t~string134.offset)=169, old(#t~string140.base)=158, old(#t~string140.offset)=181, old(#t~string148.base)=187, old(#t~string148.offset)=207, old(#t~string149.base)=229, old(#t~string149.offset)=178, old(#t~string193.base)=211, old(#t~string193.offset)=173, old(#t~string195.base)=217, old(#t~string195.offset)=228, old(#t~string198.base)=176, old(#t~string198.offset)=182, old(#t~string200.base)=222, old(#t~string200.offset)=210, old(#t~string222.base)=212, old(#t~string222.offset)=191, old(#t~string90.base)=166, old(#t~string90.offset)=170, old(~#tegra_rtc_driver~0.base)=233, old(~#tegra_rtc_driver~0.offset)=190, old(~#tegra_rtc_ops~0.base)=226, old(~#tegra_rtc_ops~0.offset)=192, old(~LDV_IN_INTERRUPT~0)=172, old(~ldv_init~0)=196, old(~ldv_irq_1_0~0)=205, old(~ldv_irq_1_1~0)=195, old(~ldv_irq_1_2~0)=208, old(~ldv_irq_1_3~0)=194, old(~ldv_irq_data_1_0~0.base)=161, old(~ldv_irq_data_1_0~0.offset)=197, old(~ldv_irq_data_1_1~0.base)=213, old(~ldv_irq_data_1_1~0.offset)=185, old(~ldv_irq_data_1_2~0.base)=189, old(~ldv_irq_data_1_2~0.offset)=177, old(~ldv_irq_data_1_3~0.base)=154, old(~ldv_irq_data_1_3~0.offset)=202, old(~ldv_irq_line_1_0~0)=206, old(~ldv_irq_line_1_1~0)=232, old(~ldv_irq_line_1_2~0)=227, old(~ldv_irq_line_1_3~0)=167, old(~ldv_retval_0~0)=171, old(~ldv_retval_1~0)=164, old(~ldv_retval_2~0)=188, old(~ldv_state_variable_0~0)=184, old(~ldv_state_variable_1~0)=216, old(~ldv_state_variable_2~0)=209, old(~ldv_state_variable_3~0)=236, old(~ref_cnt~0)=204, old(~tegra_rtc_driver_group0~0.base)=223, old(~tegra_rtc_driver_group0~0.offset)=198, old(~tegra_rtc_ops_group0~0.base)=200, old(~tegra_rtc_ops_group0~0.offset)=180, old(~tegra_rtc_ops_group1~0.base)=220, old(~tegra_rtc_ops_group1~0.offset)=193, old(~tegra_rtc_ops_group2~0.base)=174, old(~tegra_rtc_ops_group2~0.offset)=157, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] RET call ULTIMATE.init(); VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] CALL call #t~ret277 := main(); VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [L2518] havoc ~ldvarg1~0.base, ~ldvarg1~0.offset; [L2519] havoc ~tmp~27.base, ~tmp~27.offset; [L2520] havoc ~ldvarg0~0; [L2521] havoc ~tmp___0~8; [L2522] call ~#ldvarg2~0.base, ~#ldvarg2~0.offset := #Ultimate.alloc(4); [L2523] havoc ~tmp___1~5; [L2524] havoc ~tmp___2~1; [L2525] havoc ~tmp___3~1; [L2526] havoc ~tmp___4~1; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [L2529] CALL call #t~ret237.base, #t~ret237.offset := ldv_zalloc(136); VAL [#in~size=136, #NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [L1633-L1650] ~size := #in~size; [L1635] havoc ~p~1.base, ~p~1.offset; [L1636] havoc ~tmp~1.base, ~tmp~1.offset; [L1637] havoc ~tmp___0~1; [L1640] assume -2147483648 <= #t~nondet12 && #t~nondet12 <= 2147483647; [L1640] ~tmp___0~1 := #t~nondet12; [L1640] havoc #t~nondet12; VAL [#in~size=136, #NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~size=136, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~1=1] [L1641-L1648] assume 0 != ~tmp___0~1; [L1642] #res.base, #res.offset := 0, 0; VAL [#in~size=136, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~size=136, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~1=1] [L1584] ensures true; VAL [#in~size=136, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~size=136, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~1=1] [L2529] RET call #t~ret237.base, #t~ret237.offset := ldv_zalloc(136); VAL [#NULL.base=0, #NULL.offset=0, #t~ret237.base=0, #t~ret237.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [L2529] ~tmp~27.base, ~tmp~27.offset := #t~ret237.base, #t~ret237.offset; [L2529] havoc #t~ret237.base, #t~ret237.offset; [L2530] ~ldvarg1~0.base, ~ldvarg1~0.offset := ~tmp~27.base, ~tmp~27.offset; [L2531] ~tmp___0~8 := #t~nondet238; [L2531] havoc #t~nondet238; [L2532] ~ldvarg0~0 := ~tmp___0~8; [L2533] call ldv_initialize(); VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp~27.base=0, ~tmp~27.offset=0] [L2534] CALL call #t~memset~res239.base, #t~memset~res239.offset := #Ultimate.C_memset(~#ldvarg2~0.base, ~#ldvarg2~0.offset, 0, 4); VAL [#amount=4, #NULL.base=0, #NULL.offset=0, #ptr.base=225, #ptr.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #value=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] #t~loopctr278 := 0; VAL [#amount=4, #NULL.base=0, #NULL.offset=0, #ptr.base=225, #ptr.offset=0, #t~loopctr278=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #value=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume #t~loopctr278 < #amount; [?] #memory_$Pointer$.base, #memory_$Pointer$.offset := #memory_$Pointer$.base[#ptr.base,#ptr.offset + #t~loopctr278 := 0], #memory_$Pointer$.offset[#ptr.base,#ptr.offset + #t~loopctr278 := #value % 256]; [?] #memory_int := #memory_int[#ptr.base,#ptr.offset + #t~loopctr278 := #value]; [?] #t~loopctr278 := 1 + #t~loopctr278; VAL [#amount=4, #NULL.base=0, #NULL.offset=0, #ptr.base=225, #ptr.offset=0, #t~loopctr278=1, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #value=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume #t~loopctr278 < #amount; [?] #memory_$Pointer$.base, #memory_$Pointer$.offset := #memory_$Pointer$.base[#ptr.base,#ptr.offset + #t~loopctr278 := 0], #memory_$Pointer$.offset[#ptr.base,#ptr.offset + #t~loopctr278 := #value % 256]; [?] #memory_int := #memory_int[#ptr.base,#ptr.offset + #t~loopctr278 := #value]; [?] #t~loopctr278 := 1 + #t~loopctr278; VAL [#amount=4, #NULL.base=0, #NULL.offset=0, #ptr.base=225, #ptr.offset=0, #t~loopctr278=2, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #value=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume #t~loopctr278 < #amount; [?] #memory_$Pointer$.base, #memory_$Pointer$.offset := #memory_$Pointer$.base[#ptr.base,#ptr.offset + #t~loopctr278 := 0], #memory_$Pointer$.offset[#ptr.base,#ptr.offset + #t~loopctr278 := #value % 256]; [?] #memory_int := #memory_int[#ptr.base,#ptr.offset + #t~loopctr278 := #value]; [?] #t~loopctr278 := 1 + #t~loopctr278; VAL [#amount=4, #NULL.base=0, #NULL.offset=0, #ptr.base=225, #ptr.offset=0, #t~loopctr278=3, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #value=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume #t~loopctr278 < #amount; [?] #memory_$Pointer$.base, #memory_$Pointer$.offset := #memory_$Pointer$.base[#ptr.base,#ptr.offset + #t~loopctr278 := 0], #memory_$Pointer$.offset[#ptr.base,#ptr.offset + #t~loopctr278 := #value % 256]; [?] #memory_int := #memory_int[#ptr.base,#ptr.offset + #t~loopctr278 := #value]; [?] #t~loopctr278 := 1 + #t~loopctr278; VAL [#amount=4, #NULL.base=0, #NULL.offset=0, #ptr.base=225, #ptr.offset=0, #t~loopctr278=4, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #value=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] assume !(#t~loopctr278 < #amount); VAL [#amount=4, #NULL.base=0, #NULL.offset=0, #ptr.base=225, #ptr.offset=0, #t~loopctr278=4, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #value=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] free ensures #res.base == #ptr.base && #res.offset == #ptr.offset; VAL [#amount=4, #NULL.base=0, #NULL.offset=0, #ptr.base=225, #ptr.offset=0, #res.base=225, #res.offset=0, #t~loopctr278=4, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #value=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [L2534] RET call #t~memset~res239.base, #t~memset~res239.offset := #Ultimate.C_memset(~#ldvarg2~0.base, ~#ldvarg2~0.offset, 0, 4); VAL [#NULL.base=0, #NULL.offset=0, #t~memset~res239.base=225, #t~memset~res239.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp~27.base=0, ~tmp~27.offset=0] [L2534] havoc #t~memset~res239.base, #t~memset~res239.offset; [L2535] ~ldv_state_variable_1~0 := 1; [L2536] ~ref_cnt~0 := 0; [L2537] ~ldv_state_variable_0~0 := 1; [L2538] ~ldv_state_variable_3~0 := 0; [L2539] ~ldv_state_variable_2~0 := 0; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp~27.base=0, ~tmp~27.offset=0] [L2541] assume -2147483648 <= #t~nondet240 && #t~nondet240 <= 2147483647; [L2541] ~tmp___1~5 := #t~nondet240; [L2541] havoc #t~nondet240; [L2543] #t~switch241 := 0 == ~tmp___1~5; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=false, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=1, ~tmp~27.base=0, ~tmp~27.offset=0] [L2543] assume !#t~switch241; [L2550] #t~switch241 := #t~switch241 || 1 == ~tmp___1~5; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=1, ~tmp~27.base=0, ~tmp~27.offset=0] [L2550] assume #t~switch241; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=1, ~tmp~27.base=0, ~tmp~27.offset=0] [L2551-L2589] assume 0 != ~ldv_state_variable_0~0; [L2552] assume -2147483648 <= #t~nondet242 && #t~nondet242 <= 2147483647; [L2552] ~tmp___2~1 := #t~nondet242; [L2552] havoc #t~nondet242; [L2554] #t~switch243 := 0 == ~tmp___2~1; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=true, #t~switch243=false, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=1, ~tmp___2~1=1, ~tmp~27.base=0, ~tmp~27.offset=0] [L2554] assume !#t~switch243; [L2563] #t~switch243 := #t~switch243 || 1 == ~tmp___2~1; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=1, ~tmp___2~1=1, ~tmp~27.base=0, ~tmp~27.offset=0] [L2563] assume #t~switch243; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=1, ~tmp___2~1=1, ~tmp~27.base=0, ~tmp~27.offset=0] [L2564-L2581] assume 1 == ~ldv_state_variable_0~0; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=1, ~tmp___2~1=1, ~tmp~27.base=0, ~tmp~27.offset=0] [L2565] CALL call #t~ret244 := tegra_rtc_init(); VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [L2326] havoc ~tmp~22; [L2329] call #t~ret223 := platform_driver_probe(~#tegra_rtc_driver~0.base, ~#tegra_rtc_driver~0.offset, #funAddr~tegra_rtc_probe.base, #funAddr~tegra_rtc_probe.offset); [L2329] assume -2147483648 <= #t~ret223 && #t~ret223 <= 2147483647; [L2329] ~tmp~22 := #t~ret223; [L2329] havoc #t~ret223; [L2330] #res := ~tmp~22; VAL [#NULL.base=0, #NULL.offset=0, #res=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp~22=0] [L2324-L2332] ensures true; VAL [#NULL.base=0, #NULL.offset=0, #res=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp~22=0] [L2565] RET call #t~ret244 := tegra_rtc_init(); VAL [#NULL.base=0, #NULL.offset=0, #t~ret244=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=1, ~tmp___2~1=1, ~tmp~27.base=0, ~tmp~27.offset=0] [L2565] assume -2147483648 <= #t~ret244 && #t~ret244 <= 2147483647; [L2565] ~ldv_retval_0~0 := #t~ret244; [L2565] havoc #t~ret244; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=1, ~tmp___2~1=1, ~tmp~27.base=0, ~tmp~27.offset=0] [L2566-L2572] assume 0 == ~ldv_retval_0~0; [L2567] ~ldv_state_variable_0~0 := 3; [L2568] ~ldv_state_variable_2~0 := 1; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=1, ~tmp___2~1=1, ~tmp~27.base=0, ~tmp~27.offset=0] [L2569] CALL call ldv_initialize_platform_driver_2(); VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [L2476] havoc ~tmp~26.base, ~tmp~26.offset; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [L2479] CALL call #t~ret236.base, #t~ret236.offset := ldv_zalloc(624); VAL [#in~size=624, #NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [L1633-L1650] ~size := #in~size; [L1635] havoc ~p~1.base, ~p~1.offset; [L1636] havoc ~tmp~1.base, ~tmp~1.offset; [L1637] havoc ~tmp___0~1; [L1640] assume -2147483648 <= #t~nondet12 && #t~nondet12 <= 2147483647; [L1640] ~tmp___0~1 := #t~nondet12; [L1640] havoc #t~nondet12; VAL [#in~size=624, #NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~size=624, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~1=1] [L1641-L1648] assume 0 != ~tmp___0~1; [L1642] #res.base, #res.offset := 0, 0; VAL [#in~size=624, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~size=624, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~1=1] [L1584] ensures true; VAL [#in~size=624, #NULL.base=0, #NULL.offset=0, #res.base=0, #res.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~size=624, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~1=1] [L2479] RET call #t~ret236.base, #t~ret236.offset := ldv_zalloc(624); VAL [#NULL.base=0, #NULL.offset=0, #t~ret236.base=0, #t~ret236.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [L2479] ~tmp~26.base, ~tmp~26.offset := #t~ret236.base, #t~ret236.offset; [L2479] havoc #t~ret236.base, #t~ret236.offset; [L2480] ~tegra_rtc_driver_group0~0.base, ~tegra_rtc_driver_group0~0.offset := ~tmp~26.base, ~tmp~26.offset; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp~26.base=0, ~tmp~26.offset=0] [L1740] ensures true; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp~26.base=0, ~tmp~26.offset=0] [L2569] RET call ldv_initialize_platform_driver_2(); VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=1, ~tmp___2~1=1, ~tmp~27.base=0, ~tmp~27.offset=0] [L2573-L2578] assume !(0 != ~ldv_retval_0~0); VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=1, ~tmp___2~1=1, ~tmp~27.base=0, ~tmp~27.offset=0] [L2541] assume -2147483648 <= #t~nondet240 && #t~nondet240 <= 2147483647; [L2541] ~tmp___1~5 := #t~nondet240; [L2541] havoc #t~nondet240; [L2543] #t~switch241 := 0 == ~tmp___1~5; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=false, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp~27.base=0, ~tmp~27.offset=0] [L2543] assume !#t~switch241; [L2550] #t~switch241 := #t~switch241 || 1 == ~tmp___1~5; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=false, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp~27.base=0, ~tmp~27.offset=0] [L2550] assume !#t~switch241; [L2591] #t~switch241 := #t~switch241 || 2 == ~tmp___1~5; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=false, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp~27.base=0, ~tmp~27.offset=0] [L2591] assume !#t~switch241; [L2699] #t~switch241 := #t~switch241 || 3 == ~tmp___1~5; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp~27.base=0, ~tmp~27.offset=0] [L2699] assume #t~switch241; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp~27.base=0, ~tmp~27.offset=0] [L2700-L2779] assume 0 != ~ldv_state_variable_2~0; [L2701] assume -2147483648 <= #t~nondet260 && #t~nondet260 <= 2147483647; [L2701] ~tmp___4~1 := #t~nondet260; [L2701] havoc #t~nondet260; [L2703] #t~switch261 := 0 == ~tmp___4~1; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=true, #t~switch243=true, #t~switch261=false, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp___4~1=4, ~tmp~27.base=0, ~tmp~27.offset=0] [L2703] assume !#t~switch261; [L2717] #t~switch261 := #t~switch261 || 1 == ~tmp___4~1; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=true, #t~switch243=true, #t~switch261=false, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp___4~1=4, ~tmp~27.base=0, ~tmp~27.offset=0] [L2717] assume !#t~switch261; [L2729] #t~switch261 := #t~switch261 || 2 == ~tmp___4~1; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=true, #t~switch243=true, #t~switch261=false, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp___4~1=4, ~tmp~27.base=0, ~tmp~27.offset=0] [L2729] assume !#t~switch261; [L2752] #t~switch261 := #t~switch261 || 3 == ~tmp___4~1; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=true, #t~switch243=true, #t~switch261=false, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp___4~1=4, ~tmp~27.base=0, ~tmp~27.offset=0] [L2752] assume !#t~switch261; [L2764] #t~switch261 := #t~switch261 || 4 == ~tmp___4~1; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp___4~1=4, ~tmp~27.base=0, ~tmp~27.offset=0] [L2764] assume #t~switch261; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp___4~1=4, ~tmp~27.base=0, ~tmp~27.offset=0] [L2765-L2771] assume 1 == ~ldv_state_variable_2~0; [L2766] call #t~ret268 := ldv_probe_2(); [L2766] assume -2147483648 <= #t~ret268 && #t~ret268 <= 2147483647; [L2766] havoc #t~ret268; [L2767] ~ldv_state_variable_2~0 := 2; [L2768] ~ref_cnt~0 := 1 + ~ref_cnt~0; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp___4~1=4, ~tmp~27.base=0, ~tmp~27.offset=0] [L2541] assume -2147483648 <= #t~nondet240 && #t~nondet240 <= 2147483647; [L2541] ~tmp___1~5 := #t~nondet240; [L2541] havoc #t~nondet240; [L2543] #t~switch241 := 0 == ~tmp___1~5; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=false, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp___4~1=4, ~tmp~27.base=0, ~tmp~27.offset=0] [L2543] assume !#t~switch241; [L2550] #t~switch241 := #t~switch241 || 1 == ~tmp___1~5; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=false, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp___4~1=4, ~tmp~27.base=0, ~tmp~27.offset=0] [L2550] assume !#t~switch241; [L2591] #t~switch241 := #t~switch241 || 2 == ~tmp___1~5; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=false, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp___4~1=4, ~tmp~27.base=0, ~tmp~27.offset=0] [L2591] assume !#t~switch241; [L2699] #t~switch241 := #t~switch241 || 3 == ~tmp___1~5; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp___4~1=4, ~tmp~27.base=0, ~tmp~27.offset=0] [L2699] assume #t~switch241; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp___4~1=4, ~tmp~27.base=0, ~tmp~27.offset=0] [L2700-L2779] assume 0 != ~ldv_state_variable_2~0; [L2701] assume -2147483648 <= #t~nondet260 && #t~nondet260 <= 2147483647; [L2701] ~tmp___4~1 := #t~nondet260; [L2701] havoc #t~nondet260; [L2703] #t~switch261 := 0 == ~tmp___4~1; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp___4~1=0, ~tmp~27.base=0, ~tmp~27.offset=0] [L2703] assume #t~switch261; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp___4~1=0, ~tmp~27.base=0, ~tmp~27.offset=0] [L2704-L2709] assume !(4 == ~ldv_state_variable_2~0); VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp___4~1=0, ~tmp~27.base=0, ~tmp~27.offset=0] [L2710-L2715] assume 2 == ~ldv_state_variable_2~0; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#ldvarg2~0.base=225, ~#ldvarg2~0.offset=0, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0.base=0, ~ldvarg1~0.offset=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp___4~1=0, ~tmp~27.base=0, ~tmp~27.offset=0] [L2711] CALL call tegra_rtc_shutdown(~tegra_rtc_driver_group0~0.base, ~tegra_rtc_driver_group0~0.offset); VAL [#in~pdev.base=0, #in~pdev.offset=0, #NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [L2313-L2321] ~pdev.base, ~pdev.offset := #in~pdev.base, #in~pdev.offset; VAL [#in~pdev.base=0, #in~pdev.offset=0, #NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~pdev.base=0, ~pdev.offset=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [L2318] CALL call #t~ret221 := tegra_rtc_alarm_irq_enable(~pdev.base, 12 + ~pdev.offset, 0); VAL [#in~dev.base=0, #in~dev.offset=12, #in~enabled=0, #NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [L2004-L2033] ~dev.base, ~dev.offset := #in~dev.base, #in~dev.offset; [L2004-L2033] ~enabled := #in~enabled; [L2006] havoc ~info~4.base, ~info~4.offset; [L2007] havoc ~tmp~14.base, ~tmp~14.offset; [L2008] havoc ~status~0; [L2009] havoc ~sl_irq_flags~1; [L2010] havoc ~__v~3; [L2011] havoc ~__v___0~3; [L2014] call #t~ret107.base, #t~ret107.offset := dev_get_drvdata(~dev.base, ~dev.offset); [L2014] ~tmp~14.base, ~tmp~14.offset := #t~ret107.base, #t~ret107.offset; [L2014] havoc #t~ret107.base, #t~ret107.offset; [L2015] ~info~4.base, ~info~4.offset := ~tmp~14.base, ~tmp~14.offset; VAL [#in~dev.base=0, #in~dev.offset=12, #in~enabled=0, #NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~dev.base=0, ~dev.offset=12, ~enabled=0, ~info~4.base=156, ~info~4.offset=215, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp~14.base=156, ~tmp~14.offset=215] [L2016] CALL call #t~ret108 := tegra_rtc_wait_while_busy(~dev.base, ~dev.offset); VAL [#in~dev.base=0, #in~dev.offset=12, #NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [L1873-L1908] ~dev.base, ~dev.offset := #in~dev.base, #in~dev.offset; [L1875] havoc ~info~0.base, ~info~0.offset; [L1876] havoc ~tmp~10.base, ~tmp~10.offset; [L1877] havoc ~retries~0; [L1878] havoc ~tmp___0~2; [L1879] havoc ~tmp___1~0; [L1882] call #t~ret87.base, #t~ret87.offset := dev_get_drvdata(~dev.base, ~dev.offset); [L1882] ~tmp~10.base, ~tmp~10.offset := #t~ret87.base, #t~ret87.offset; [L1882] havoc #t~ret87.base, #t~ret87.offset; [L1883] ~info~0.base, ~info~0.offset := ~tmp~10.base, ~tmp~10.offset; [L1884] ~retries~0 := 500; VAL [#in~dev.base=0, #in~dev.offset=12, #NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~dev.base=0, ~dev.offset=12, ~info~0.base=165, ~info~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~retries~0=500, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp~10.base=165, ~tmp~10.offset=0] [L1896] CALL call #t~ret88 := tegra_rtc_check_busy(~info~0.base, ~info~0.offset); VAL [#in~info.base=165, #in~info.offset=0, #NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [L1861-L1872] ~info.base, ~info.offset := #in~info.base, #in~info.offset; [L1863] havoc ~__v~0; [L1864] havoc ~__v___0~0; [L1867] call #t~mem85.base, #t~mem85.offset := read~$Pointer$(~info.base, 16 + ~info.offset, 8); [L1867] call #t~mem86 := read~int(#t~mem85.base, 16 + #t~mem85.offset, 4); [L1867] ~__v___0~0 := #t~mem86; [L1867] havoc #t~mem86; [L1867] havoc #t~mem85.base, #t~mem85.offset; [L1868] ~__v~0 := ~__v___0~0; [L1870] #res := ~bitwiseAnd(~__v~0, 1); VAL [#in~info.base=165, #in~info.offset=0, #NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~__v___0~0=201, ~__v~0=201, ~info.base=165, ~info.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [L1861-L1872] ensures true; VAL [#in~info.base=165, #in~info.offset=0, #NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~__v___0~0=201, ~__v~0=201, ~info.base=165, ~info.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [L1896] RET call #t~ret88 := tegra_rtc_check_busy(~info~0.base, ~info~0.offset); VAL [#in~dev.base=0, #in~dev.offset=12, #NULL.base=0, #NULL.offset=0, #t~ret88=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~dev.base=0, ~dev.offset=12, ~info~0.base=165, ~info~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~retries~0=500, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp~10.base=165, ~tmp~10.offset=0] [L1896] ~tmp___1~0 := #t~ret88; [L1896] havoc #t~ret88; VAL [#in~dev.base=0, #in~dev.offset=12, #NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~dev.base=0, ~dev.offset=12, ~info~0.base=165, ~info~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~retries~0=500, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___1~0=0, ~tmp~10.base=165, ~tmp~10.offset=0] [L1897-L1901] assume !(0 != ~tmp___1~0 % 4294967296); [L1903] #res := 0; VAL [#in~dev.base=0, #in~dev.offset=12, #NULL.base=0, #NULL.offset=0, #res=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~dev.base=0, ~dev.offset=12, ~info~0.base=165, ~info~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~retries~0=500, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___1~0=0, ~tmp~10.base=165, ~tmp~10.offset=0] [L1873-L1908] ensures true; VAL [#in~dev.base=0, #in~dev.offset=12, #NULL.base=0, #NULL.offset=0, #res=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~dev.base=0, ~dev.offset=12, ~info~0.base=165, ~info~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~retries~0=500, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp___1~0=0, ~tmp~10.base=165, ~tmp~10.offset=0] [L2016] RET call #t~ret108 := tegra_rtc_wait_while_busy(~dev.base, ~dev.offset); VAL [#in~dev.base=0, #in~dev.offset=12, #in~enabled=0, #NULL.base=0, #NULL.offset=0, #t~ret108=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~dev.base=0, ~dev.offset=12, ~enabled=0, ~info~4.base=156, ~info~4.offset=215, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp~14.base=156, ~tmp~14.offset=215] [L2016] assume -2147483648 <= #t~ret108 && #t~ret108 <= 2147483647; [L2016] havoc #t~ret108; VAL [#in~dev.base=0, #in~dev.offset=12, #in~enabled=0, #NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~dev.base=0, ~dev.offset=12, ~enabled=0, ~info~4.base=156, ~info~4.offset=215, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0, ~tmp~14.base=156, ~tmp~14.offset=215] [L2017] CALL call ldv_spin_lock_check(); VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [L2962-L2966] assume !(1 == ~ldv_init~0); VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [L2965] CALL call ldv_error(); VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [L1684] assert false; VAL [#NULL.base=0, #NULL.offset=0, #t~string125.base=159, #t~string125.offset=0, #t~string134.base=237, #t~string134.offset=0, #t~string140.base=155, #t~string140.offset=0, #t~string148.base=186, #t~string148.offset=0, #t~string149.base=230, #t~string149.offset=0, #t~string193.base=218, #t~string193.offset=0, #t~string195.base=214, #t~string195.offset=0, #t~string198.base=175, #t~string198.offset=0, #t~string200.base=221, #t~string200.offset=0, #t~string222.base=234, #t~string222.offset=0, #t~string90.base=168, #t~string90.offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0.base)=0, old(~tegra_rtc_driver_group0~0.offset)=0, ~#__this_module~0.base=162, ~#__this_module~0.offset=199, ~#tegra_rtc_driver~0.base=231, ~#tegra_rtc_driver~0.offset=0, ~#tegra_rtc_ops~0.base=224, ~#tegra_rtc_ops~0.offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0.base=0, ~ldv_irq_data_1_0~0.offset=0, ~ldv_irq_data_1_1~0.base=0, ~ldv_irq_data_1_1~0.offset=0, ~ldv_irq_data_1_2~0.base=0, ~ldv_irq_data_1_2~0.offset=0, ~ldv_irq_data_1_3~0.base=0, ~ldv_irq_data_1_3~0.offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0.base=0, ~tegra_rtc_driver_group0~0.offset=0, ~tegra_rtc_ops_group0~0.base=0, ~tegra_rtc_ops_group0~0.offset=0, ~tegra_rtc_ops_group1~0.base=0, ~tegra_rtc_ops_group1~0.offset=0, ~tegra_rtc_ops_group2~0.base=0, ~tegra_rtc_ops_group2~0.offset=0] [?] CALL call ULTIMATE.init(); VAL [#NULL!base=183, #NULL!offset=219, #t~string125!base=160, #t~string125!offset=163, #t~string134!base=235, #t~string134!offset=169, #t~string140!base=158, #t~string140!offset=181, #t~string148!base=187, #t~string148!offset=207, #t~string149!base=229, #t~string149!offset=178, #t~string193!base=211, #t~string193!offset=173, #t~string195!base=217, #t~string195!offset=228, #t~string198!base=176, #t~string198!offset=182, #t~string200!base=222, #t~string200!offset=210, #t~string222!base=212, #t~string222!offset=191, #t~string90!base=166, #t~string90!offset=170, old(#NULL!base)=183, old(#NULL!offset)=219, old(#t~string125!base)=160, old(#t~string125!offset)=163, old(#t~string134!base)=235, old(#t~string134!offset)=169, old(#t~string140!base)=158, old(#t~string140!offset)=181, old(#t~string148!base)=187, old(#t~string148!offset)=207, old(#t~string149!base)=229, old(#t~string149!offset)=178, old(#t~string193!base)=211, old(#t~string193!offset)=173, old(#t~string195!base)=217, old(#t~string195!offset)=228, old(#t~string198!base)=176, old(#t~string198!offset)=182, old(#t~string200!base)=222, old(#t~string200!offset)=210, old(#t~string222!base)=212, old(#t~string222!offset)=191, old(#t~string90!base)=166, old(#t~string90!offset)=170, old(~#tegra_rtc_driver~0!base)=233, old(~#tegra_rtc_driver~0!offset)=190, old(~#tegra_rtc_ops~0!base)=226, old(~#tegra_rtc_ops~0!offset)=192, old(~LDV_IN_INTERRUPT~0)=172, old(~ldv_init~0)=196, old(~ldv_irq_1_0~0)=205, old(~ldv_irq_1_1~0)=195, old(~ldv_irq_1_2~0)=208, old(~ldv_irq_1_3~0)=194, old(~ldv_irq_data_1_0~0!base)=161, old(~ldv_irq_data_1_0~0!offset)=197, old(~ldv_irq_data_1_1~0!base)=213, old(~ldv_irq_data_1_1~0!offset)=185, old(~ldv_irq_data_1_2~0!base)=189, old(~ldv_irq_data_1_2~0!offset)=177, old(~ldv_irq_data_1_3~0!base)=154, old(~ldv_irq_data_1_3~0!offset)=202, old(~ldv_irq_line_1_0~0)=206, old(~ldv_irq_line_1_1~0)=232, old(~ldv_irq_line_1_2~0)=227, old(~ldv_irq_line_1_3~0)=167, old(~ldv_retval_0~0)=171, old(~ldv_retval_1~0)=164, old(~ldv_retval_2~0)=188, old(~ldv_state_variable_0~0)=184, old(~ldv_state_variable_1~0)=216, old(~ldv_state_variable_2~0)=209, old(~ldv_state_variable_3~0)=236, old(~ref_cnt~0)=204, old(~tegra_rtc_driver_group0~0!base)=223, old(~tegra_rtc_driver_group0~0!offset)=198, old(~tegra_rtc_ops_group0~0!base)=200, old(~tegra_rtc_ops_group0~0!offset)=180, old(~tegra_rtc_ops_group1~0!base)=220, old(~tegra_rtc_ops_group1~0!offset)=193, old(~tegra_rtc_ops_group2~0!base)=174, old(~tegra_rtc_ops_group2~0!offset)=157, ~#tegra_rtc_driver~0!base=233, ~#tegra_rtc_driver~0!offset=190, ~#tegra_rtc_ops~0!base=226, ~#tegra_rtc_ops~0!offset=192, ~LDV_IN_INTERRUPT~0=172, ~ldv_init~0=196, ~ldv_irq_1_0~0=205, ~ldv_irq_1_1~0=195, ~ldv_irq_1_2~0=208, ~ldv_irq_1_3~0=194, ~ldv_irq_data_1_0~0!base=161, ~ldv_irq_data_1_0~0!offset=197, ~ldv_irq_data_1_1~0!base=213, ~ldv_irq_data_1_1~0!offset=185, ~ldv_irq_data_1_2~0!base=189, ~ldv_irq_data_1_2~0!offset=177, ~ldv_irq_data_1_3~0!base=154, ~ldv_irq_data_1_3~0!offset=202, ~ldv_irq_line_1_0~0=206, ~ldv_irq_line_1_1~0=232, ~ldv_irq_line_1_2~0=227, ~ldv_irq_line_1_3~0=167, ~ldv_retval_0~0=171, ~ldv_retval_1~0=164, ~ldv_retval_2~0=188, ~ldv_state_variable_0~0=184, ~ldv_state_variable_1~0=216, ~ldv_state_variable_2~0=209, ~ldv_state_variable_3~0=236, ~ref_cnt~0=204, ~tegra_rtc_driver_group0~0!base=223, ~tegra_rtc_driver_group0~0!offset=198, ~tegra_rtc_ops_group0~0!base=200, ~tegra_rtc_ops_group0~0!offset=180, ~tegra_rtc_ops_group1~0!base=220, ~tegra_rtc_ops_group1~0!offset=193, ~tegra_rtc_ops_group2~0!base=174, ~tegra_rtc_ops_group2~0!offset=157] [?] #NULL := { base: 0, offset: 0 }; [?] #valid[0] := 0; [L1905] FCALL call #t~string90 := #Ultimate.alloc(36); [L2072] FCALL call #t~string125 := #Ultimate.alloc(12); [L2150] FCALL call #t~string134 := #Ultimate.alloc(42); [L2159] FCALL call #t~string140 := #Ultimate.alloc(42); [L2175] FCALL call #t~string148 := #Ultimate.alloc(32); [L2189] FCALL call #t~string149 := #Ultimate.alloc(21); [L2211] FCALL call #t~string193 := #Ultimate.alloc(37); [L2218] FCALL call #t~string195 := #Ultimate.alloc(10); [L2220] FCALL call #t~string198 := #Ultimate.alloc(50); [L2226] FCALL call #t~string200 := #Ultimate.alloc(32); [L2323] FCALL call #t~string222 := #Ultimate.alloc(10); [L1713] ~ldv_irq_1_2~0 := 0; [L1714] ~LDV_IN_INTERRUPT~0 := 1; [L1715] ~ldv_irq_1_3~0 := 0; [L1717] ~ldv_irq_data_1_1~0 := { base: 0, offset: 0 }; [L1718] ~ldv_irq_1_1~0 := 0; [L1719] ~ldv_irq_1_0~0 := 0; [L1720] ~ldv_irq_line_1_3~0 := 0; [L1721] ~ldv_irq_data_1_0~0 := { base: 0, offset: 0 }; [L1722] ~ldv_state_variable_0~0 := 0; [L1724] ~ldv_state_variable_3~0 := 0; [L1725] ~ldv_irq_line_1_0~0 := 0; [L1726] ~ldv_state_variable_2~0 := 0; [L1727] ~ldv_irq_data_1_3~0 := { base: 0, offset: 0 }; [L1728] ~ref_cnt~0 := 0; [L1729] ~ldv_irq_line_1_1~0 := 0; [L1731] ~ldv_irq_data_1_2~0 := { base: 0, offset: 0 }; [L1732] ~ldv_state_variable_1~0 := 0; [L1733] ~ldv_irq_line_1_2~0 := 0; [L2342] ~ldv_retval_2~0 := 0; [L2343] ~ldv_retval_0~0 := 0; [L2345] ~ldv_retval_1~0 := 0; [L2943] ~ldv_init~0 := 0; [L1716] ~tegra_rtc_driver_group0~0 := { base: 0, offset: 0 }; [L1723] ~tegra_rtc_ops_group1~0 := { base: 0, offset: 0 }; [L1730] ~tegra_rtc_ops_group0~0 := { base: 0, offset: 0 }; [L1734] ~tegra_rtc_ops_group2~0 := { base: 0, offset: 0 }; [L2123-L2125] FCALL call ~#tegra_rtc_ops~0 := #Ultimate.alloc(88); [L2123-L2125] FCALL call write~init~$Pointer$({ base: 0, offset: 0 }, { base: ~#tegra_rtc_ops~0!base, offset: ~#tegra_rtc_ops~0!offset }, 8); [L2123-L2125] FCALL call write~init~$Pointer$({ base: 0, offset: 0 }, { base: ~#tegra_rtc_ops~0!base, offset: 8 + ~#tegra_rtc_ops~0!offset }, 8); [L2123-L2125] FCALL call write~init~$Pointer$({ base: 0, offset: 0 }, { base: ~#tegra_rtc_ops~0!base, offset: 16 + ~#tegra_rtc_ops~0!offset }, 8); [L2123-L2125] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_read_time, { base: ~#tegra_rtc_ops~0!base, offset: 24 + ~#tegra_rtc_ops~0!offset }, 8); [L2123-L2125] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_set_time, { base: ~#tegra_rtc_ops~0!base, offset: 32 + ~#tegra_rtc_ops~0!offset }, 8); [L2123-L2125] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_read_alarm, { base: ~#tegra_rtc_ops~0!base, offset: 40 + ~#tegra_rtc_ops~0!offset }, 8); [L2123-L2125] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_set_alarm, { base: ~#tegra_rtc_ops~0!base, offset: 48 + ~#tegra_rtc_ops~0!offset }, 8); [L2123-L2125] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_proc, { base: ~#tegra_rtc_ops~0!base, offset: 56 + ~#tegra_rtc_ops~0!offset }, 8); [L2123-L2125] FCALL call write~init~$Pointer$({ base: 0, offset: 0 }, { base: ~#tegra_rtc_ops~0!base, offset: 64 + ~#tegra_rtc_ops~0!offset }, 8); [L2123-L2125] FCALL call write~init~$Pointer$({ base: 0, offset: 0 }, { base: ~#tegra_rtc_ops~0!base, offset: 72 + ~#tegra_rtc_ops~0!offset }, 8); [L2123-L2125] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_alarm_irq_enable, { base: ~#tegra_rtc_ops~0!base, offset: 80 + ~#tegra_rtc_ops~0!offset }, 8); [L2322-L2323] FCALL call ~#tegra_rtc_driver~0 := #Ultimate.alloc(153); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0, offset: 0 }, { base: ~#tegra_rtc_driver~0!base, offset: ~#tegra_rtc_driver~0!offset }, 8); [L2322-L2323] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_remove, { base: ~#tegra_rtc_driver~0!base, offset: 8 + ~#tegra_rtc_driver~0!offset }, 8); [L2322-L2323] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_shutdown, { base: ~#tegra_rtc_driver~0!base, offset: 16 + ~#tegra_rtc_driver~0!offset }, 8); [L2322-L2323] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_suspend, { base: ~#tegra_rtc_driver~0!base, offset: 24 + ~#tegra_rtc_driver~0!offset }, 8); [L2322-L2323] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_resume, { base: ~#tegra_rtc_driver~0!base, offset: 32 + ~#tegra_rtc_driver~0!offset }, 8); [L2322-L2323] FCALL call write~init~$Pointer$(#t~string222, { base: ~#tegra_rtc_driver~0!base, offset: 40 + ~#tegra_rtc_driver~0!offset }, 8); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0, offset: 0 }, { base: ~#tegra_rtc_driver~0!base, offset: 48 + ~#tegra_rtc_driver~0!offset }, 8); [L2322-L2323] FCALL call write~init~$Pointer$(~#__this_module~0, { base: ~#tegra_rtc_driver~0!base, offset: 56 + ~#tegra_rtc_driver~0!offset }, 8); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0, offset: 0 }, { base: ~#tegra_rtc_driver~0!base, offset: 64 + ~#tegra_rtc_driver~0!offset }, 8); [L2322-L2323] FCALL call write~init~int(0, { base: ~#tegra_rtc_driver~0!base, offset: 72 + ~#tegra_rtc_driver~0!offset }, 1); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0, offset: 0 }, { base: ~#tegra_rtc_driver~0!base, offset: 73 + ~#tegra_rtc_driver~0!offset }, 8); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0, offset: 0 }, { base: ~#tegra_rtc_driver~0!base, offset: 81 + ~#tegra_rtc_driver~0!offset }, 8); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0, offset: 0 }, { base: ~#tegra_rtc_driver~0!base, offset: 89 + ~#tegra_rtc_driver~0!offset }, 8); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0, offset: 0 }, { base: ~#tegra_rtc_driver~0!base, offset: 97 + ~#tegra_rtc_driver~0!offset }, 8); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0, offset: 0 }, { base: ~#tegra_rtc_driver~0!base, offset: 105 + ~#tegra_rtc_driver~0!offset }, 8); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0, offset: 0 }, { base: ~#tegra_rtc_driver~0!base, offset: 113 + ~#tegra_rtc_driver~0!offset }, 8); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0, offset: 0 }, { base: ~#tegra_rtc_driver~0!base, offset: 121 + ~#tegra_rtc_driver~0!offset }, 8); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0, offset: 0 }, { base: ~#tegra_rtc_driver~0!base, offset: 129 + ~#tegra_rtc_driver~0!offset }, 8); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0, offset: 0 }, { base: ~#tegra_rtc_driver~0!base, offset: 137 + ~#tegra_rtc_driver~0!offset }, 8); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0, offset: 0 }, { base: ~#tegra_rtc_driver~0!base, offset: 145 + ~#tegra_rtc_driver~0!offset }, 8); VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, old(#NULL!base)=183, old(#NULL!offset)=219, old(#t~string125!base)=160, old(#t~string125!offset)=163, old(#t~string134!base)=235, old(#t~string134!offset)=169, old(#t~string140!base)=158, old(#t~string140!offset)=181, old(#t~string148!base)=187, old(#t~string148!offset)=207, old(#t~string149!base)=229, old(#t~string149!offset)=178, old(#t~string193!base)=211, old(#t~string193!offset)=173, old(#t~string195!base)=217, old(#t~string195!offset)=228, old(#t~string198!base)=176, old(#t~string198!offset)=182, old(#t~string200!base)=222, old(#t~string200!offset)=210, old(#t~string222!base)=212, old(#t~string222!offset)=191, old(#t~string90!base)=166, old(#t~string90!offset)=170, old(~#tegra_rtc_driver~0!base)=233, old(~#tegra_rtc_driver~0!offset)=190, old(~#tegra_rtc_ops~0!base)=226, old(~#tegra_rtc_ops~0!offset)=192, old(~LDV_IN_INTERRUPT~0)=172, old(~ldv_init~0)=196, old(~ldv_irq_1_0~0)=205, old(~ldv_irq_1_1~0)=195, old(~ldv_irq_1_2~0)=208, old(~ldv_irq_1_3~0)=194, old(~ldv_irq_data_1_0~0!base)=161, old(~ldv_irq_data_1_0~0!offset)=197, old(~ldv_irq_data_1_1~0!base)=213, old(~ldv_irq_data_1_1~0!offset)=185, old(~ldv_irq_data_1_2~0!base)=189, old(~ldv_irq_data_1_2~0!offset)=177, old(~ldv_irq_data_1_3~0!base)=154, old(~ldv_irq_data_1_3~0!offset)=202, old(~ldv_irq_line_1_0~0)=206, old(~ldv_irq_line_1_1~0)=232, old(~ldv_irq_line_1_2~0)=227, old(~ldv_irq_line_1_3~0)=167, old(~ldv_retval_0~0)=171, old(~ldv_retval_1~0)=164, old(~ldv_retval_2~0)=188, old(~ldv_state_variable_0~0)=184, old(~ldv_state_variable_1~0)=216, old(~ldv_state_variable_2~0)=209, old(~ldv_state_variable_3~0)=236, old(~ref_cnt~0)=204, old(~tegra_rtc_driver_group0~0!base)=223, old(~tegra_rtc_driver_group0~0!offset)=198, old(~tegra_rtc_ops_group0~0!base)=200, old(~tegra_rtc_ops_group0~0!offset)=180, old(~tegra_rtc_ops_group1~0!base)=220, old(~tegra_rtc_ops_group1~0!offset)=193, old(~tegra_rtc_ops_group2~0!base)=174, old(~tegra_rtc_ops_group2~0!offset)=157, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0] [?] RET call ULTIMATE.init(); VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0] [?] CALL call #t~ret277 := main(); VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0] [L2518] havoc ~ldvarg1~0; [L2519] havoc ~tmp~27; [L2520] havoc ~ldvarg0~0; [L2521] havoc ~tmp___0~8; [L2522] FCALL call ~#ldvarg2~0 := #Ultimate.alloc(4); [L2523] havoc ~tmp___1~5; [L2524] havoc ~tmp___2~1; [L2525] havoc ~tmp___3~1; [L2526] havoc ~tmp___4~1; VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#ldvarg2~0!base=225, ~#ldvarg2~0!offset=0, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0] [L2529] CALL call #t~ret237 := ldv_zalloc(136); VAL [#in~size=136, #NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0] [L1633-L1650] ~size := #in~size; [L1635] havoc ~p~1; [L1636] havoc ~tmp~1; [L1637] havoc ~tmp___0~1; [L1640] assume -2147483648 <= #t~nondet12 && #t~nondet12 <= 2147483647; [L1640] ~tmp___0~1 := #t~nondet12; [L1640] havoc #t~nondet12; VAL [#in~size=136, #NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~size=136, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp___0~1=1] [L1641] COND TRUE 0 != ~tmp___0~1 [L1642] #res := { base: 0, offset: 0 }; VAL [#in~size=136, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~size=136, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp___0~1=1] [L2529] RET call #t~ret237 := ldv_zalloc(136); VAL [#NULL!base=0, #NULL!offset=0, #t~ret237!base=0, #t~ret237!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#ldvarg2~0!base=225, ~#ldvarg2~0!offset=0, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0] [L2529] ~tmp~27 := #t~ret237; [L2529] havoc #t~ret237; [L2530] ~ldvarg1~0 := ~tmp~27; [L2531] ~tmp___0~8 := #t~nondet238; [L2531] havoc #t~nondet238; [L2532] ~ldvarg0~0 := ~tmp___0~8; [L2533] FCALL call ldv_initialize(); VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#ldvarg2~0!base=225, ~#ldvarg2~0!offset=0, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0!base=0, ~ldvarg1~0!offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp___0~8=179, ~tmp~27!base=0, ~tmp~27!offset=0] [L2534] CALL call #t~memset~res239 := #Ultimate.C_memset(~#ldvarg2~0, 0, 4); VAL [#amount=4, #NULL!base=0, #NULL!offset=0, #ptr!base=225, #ptr!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, #value=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0] [?] #t~loopctr278 := 0; VAL [#amount=4, #NULL!base=0, #NULL!offset=0, #ptr!base=225, #ptr!offset=0, #t~loopctr278=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, #value=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0] [?] COND TRUE #t~loopctr278 < #amount [?] #memory_$Pointer$[{ base: #ptr!base, offset: #ptr!offset + #t~loopctr278 }] := { base: 0, offset: #value % 256 }; [?] #memory_int[{ base: #ptr!base, offset: #ptr!offset + #t~loopctr278 }] := #value; [?] #t~loopctr278 := 1 + #t~loopctr278; VAL [#amount=4, #NULL!base=0, #NULL!offset=0, #ptr!base=225, #ptr!offset=0, #t~loopctr278=1, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, #value=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0] [?] COND TRUE #t~loopctr278 < #amount [?] #memory_$Pointer$[{ base: #ptr!base, offset: #ptr!offset + #t~loopctr278 }] := { base: 0, offset: #value % 256 }; [?] #memory_int[{ base: #ptr!base, offset: #ptr!offset + #t~loopctr278 }] := #value; [?] #t~loopctr278 := 1 + #t~loopctr278; VAL [#amount=4, #NULL!base=0, #NULL!offset=0, #ptr!base=225, #ptr!offset=0, #t~loopctr278=2, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, #value=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0] [?] COND TRUE #t~loopctr278 < #amount [?] #memory_$Pointer$[{ base: #ptr!base, offset: #ptr!offset + #t~loopctr278 }] := { base: 0, offset: #value % 256 }; [?] #memory_int[{ base: #ptr!base, offset: #ptr!offset + #t~loopctr278 }] := #value; [?] #t~loopctr278 := 1 + #t~loopctr278; VAL [#amount=4, #NULL!base=0, #NULL!offset=0, #ptr!base=225, #ptr!offset=0, #t~loopctr278=3, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, #value=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0] [?] COND TRUE #t~loopctr278 < #amount [?] #memory_$Pointer$[{ base: #ptr!base, offset: #ptr!offset + #t~loopctr278 }] := { base: 0, offset: #value % 256 }; [?] #memory_int[{ base: #ptr!base, offset: #ptr!offset + #t~loopctr278 }] := #value; [?] #t~loopctr278 := 1 + #t~loopctr278; VAL [#amount=4, #NULL!base=0, #NULL!offset=0, #ptr!base=225, #ptr!offset=0, #t~loopctr278=4, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, #value=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0] [?] COND FALSE !(#t~loopctr278 < #amount) VAL [#amount=4, #NULL!base=0, #NULL!offset=0, #ptr!base=225, #ptr!offset=0, #t~loopctr278=4, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, #value=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0] [L2534] RET call #t~memset~res239 := #Ultimate.C_memset(~#ldvarg2~0, 0, 4); VAL [#NULL!base=0, #NULL!offset=0, #t~memset~res239!base=225, #t~memset~res239!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#ldvarg2~0!base=225, ~#ldvarg2~0!offset=0, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0!base=0, ~ldvarg1~0!offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp___0~8=179, ~tmp~27!base=0, ~tmp~27!offset=0] [L2534] havoc #t~memset~res239; [L2535] ~ldv_state_variable_1~0 := 1; [L2536] ~ref_cnt~0 := 0; [L2537] ~ldv_state_variable_0~0 := 1; [L2538] ~ldv_state_variable_3~0 := 0; [L2539] ~ldv_state_variable_2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#ldvarg2~0!base=225, ~#ldvarg2~0!offset=0, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0!base=0, ~ldvarg1~0!offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp___0~8=179, ~tmp~27!base=0, ~tmp~27!offset=0] [L2541] assume -2147483648 <= #t~nondet240 && #t~nondet240 <= 2147483647; [L2541] ~tmp___1~5 := #t~nondet240; [L2541] havoc #t~nondet240; [L2543] #t~switch241 := 0 == ~tmp___1~5; VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, #t~switch241=false, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#ldvarg2~0!base=225, ~#ldvarg2~0!offset=0, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0!base=0, ~ldvarg1~0!offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp___0~8=179, ~tmp___1~5=1, ~tmp~27!base=0, ~tmp~27!offset=0] [L2542-L2783] COND FALSE !(#t~switch241) [L2550] #t~switch241 := #t~switch241 || 1 == ~tmp___1~5; VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, #t~switch241=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#ldvarg2~0!base=225, ~#ldvarg2~0!offset=0, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0!base=0, ~ldvarg1~0!offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp___0~8=179, ~tmp___1~5=1, ~tmp~27!base=0, ~tmp~27!offset=0] [L2542-L2783] COND TRUE #t~switch241 VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, #t~switch241=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#ldvarg2~0!base=225, ~#ldvarg2~0!offset=0, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0!base=0, ~ldvarg1~0!offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp___0~8=179, ~tmp___1~5=1, ~tmp~27!base=0, ~tmp~27!offset=0] [L2551] COND TRUE 0 != ~ldv_state_variable_0~0 [L2552] assume -2147483648 <= #t~nondet242 && #t~nondet242 <= 2147483647; [L2552] ~tmp___2~1 := #t~nondet242; [L2552] havoc #t~nondet242; [L2554] #t~switch243 := 0 == ~tmp___2~1; VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, #t~switch241=true, #t~switch243=false, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#ldvarg2~0!base=225, ~#ldvarg2~0!offset=0, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0!base=0, ~ldvarg1~0!offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp___0~8=179, ~tmp___1~5=1, ~tmp___2~1=1, ~tmp~27!base=0, ~tmp~27!offset=0] [L2553-L2585] COND FALSE !(#t~switch243) [L2563] #t~switch243 := #t~switch243 || 1 == ~tmp___2~1; VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#ldvarg2~0!base=225, ~#ldvarg2~0!offset=0, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0!base=0, ~ldvarg1~0!offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp___0~8=179, ~tmp___1~5=1, ~tmp___2~1=1, ~tmp~27!base=0, ~tmp~27!offset=0] [L2553-L2585] COND TRUE #t~switch243 VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#ldvarg2~0!base=225, ~#ldvarg2~0!offset=0, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0!base=0, ~ldvarg1~0!offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp___0~8=179, ~tmp___1~5=1, ~tmp___2~1=1, ~tmp~27!base=0, ~tmp~27!offset=0] [L2564] COND TRUE 1 == ~ldv_state_variable_0~0 VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#ldvarg2~0!base=225, ~#ldvarg2~0!offset=0, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0!base=0, ~ldvarg1~0!offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp___0~8=179, ~tmp___1~5=1, ~tmp___2~1=1, ~tmp~27!base=0, ~tmp~27!offset=0] [L2565] CALL call #t~ret244 := tegra_rtc_init(); VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0] [L2326] havoc ~tmp~22; [L2329] FCALL call #t~ret223 := platform_driver_probe(~#tegra_rtc_driver~0, #funAddr~tegra_rtc_probe); [L2329] assume -2147483648 <= #t~ret223 && #t~ret223 <= 2147483647; [L2329] ~tmp~22 := #t~ret223; [L2329] havoc #t~ret223; [L2330] #res := ~tmp~22; VAL [#NULL!base=0, #NULL!offset=0, #res=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp~22=0] [L2565] RET call #t~ret244 := tegra_rtc_init(); VAL [#NULL!base=0, #NULL!offset=0, #t~ret244=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#ldvarg2~0!base=225, ~#ldvarg2~0!offset=0, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0!base=0, ~ldvarg1~0!offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp___0~8=179, ~tmp___1~5=1, ~tmp___2~1=1, ~tmp~27!base=0, ~tmp~27!offset=0] [L2565] assume -2147483648 <= #t~ret244 && #t~ret244 <= 2147483647; [L2565] ~ldv_retval_0~0 := #t~ret244; [L2565] havoc #t~ret244; VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#ldvarg2~0!base=225, ~#ldvarg2~0!offset=0, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0!base=0, ~ldvarg1~0!offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp___0~8=179, ~tmp___1~5=1, ~tmp___2~1=1, ~tmp~27!base=0, ~tmp~27!offset=0] [L2566] COND TRUE 0 == ~ldv_retval_0~0 [L2567] ~ldv_state_variable_0~0 := 3; [L2568] ~ldv_state_variable_2~0 := 1; VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#ldvarg2~0!base=225, ~#ldvarg2~0!offset=0, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0!base=0, ~ldvarg1~0!offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp___0~8=179, ~tmp___1~5=1, ~tmp___2~1=1, ~tmp~27!base=0, ~tmp~27!offset=0] [L2569] CALL call ldv_initialize_platform_driver_2(); VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0] [L2476] havoc ~tmp~26; VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0] [L2479] CALL call #t~ret236 := ldv_zalloc(624); VAL [#in~size=624, #NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0] [L1633-L1650] ~size := #in~size; [L1635] havoc ~p~1; [L1636] havoc ~tmp~1; [L1637] havoc ~tmp___0~1; [L1640] assume -2147483648 <= #t~nondet12 && #t~nondet12 <= 2147483647; [L1640] ~tmp___0~1 := #t~nondet12; [L1640] havoc #t~nondet12; VAL [#in~size=624, #NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~size=624, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp___0~1=1] [L1641] COND TRUE 0 != ~tmp___0~1 [L1642] #res := { base: 0, offset: 0 }; VAL [#in~size=624, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~size=624, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp___0~1=1] [L2479] RET call #t~ret236 := ldv_zalloc(624); VAL [#NULL!base=0, #NULL!offset=0, #t~ret236!base=0, #t~ret236!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0] [L2479] ~tmp~26 := #t~ret236; [L2479] havoc #t~ret236; [L2480] ~tegra_rtc_driver_group0~0 := ~tmp~26; VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp~26!base=0, ~tmp~26!offset=0] [L2569] RET call ldv_initialize_platform_driver_2(); VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#ldvarg2~0!base=225, ~#ldvarg2~0!offset=0, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0!base=0, ~ldvarg1~0!offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp___0~8=179, ~tmp___1~5=1, ~tmp___2~1=1, ~tmp~27!base=0, ~tmp~27!offset=0] [L2573] COND FALSE !(0 != ~ldv_retval_0~0) VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#ldvarg2~0!base=225, ~#ldvarg2~0!offset=0, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0!base=0, ~ldvarg1~0!offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp___0~8=179, ~tmp___1~5=1, ~tmp___2~1=1, ~tmp~27!base=0, ~tmp~27!offset=0] [L2541] assume -2147483648 <= #t~nondet240 && #t~nondet240 <= 2147483647; [L2541] ~tmp___1~5 := #t~nondet240; [L2541] havoc #t~nondet240; [L2543] #t~switch241 := 0 == ~tmp___1~5; VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, #t~switch241=false, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#ldvarg2~0!base=225, ~#ldvarg2~0!offset=0, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0!base=0, ~ldvarg1~0!offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp~27!base=0, ~tmp~27!offset=0] [L2542-L2783] COND FALSE !(#t~switch241) [L2550] #t~switch241 := #t~switch241 || 1 == ~tmp___1~5; VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, #t~switch241=false, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#ldvarg2~0!base=225, ~#ldvarg2~0!offset=0, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0!base=0, ~ldvarg1~0!offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp~27!base=0, ~tmp~27!offset=0] [L2542-L2783] COND FALSE !(#t~switch241) [L2591] #t~switch241 := #t~switch241 || 2 == ~tmp___1~5; VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, #t~switch241=false, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#ldvarg2~0!base=225, ~#ldvarg2~0!offset=0, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0!base=0, ~ldvarg1~0!offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp~27!base=0, ~tmp~27!offset=0] [L2542-L2783] COND FALSE !(#t~switch241) [L2699] #t~switch241 := #t~switch241 || 3 == ~tmp___1~5; VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#ldvarg2~0!base=225, ~#ldvarg2~0!offset=0, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0!base=0, ~ldvarg1~0!offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp~27!base=0, ~tmp~27!offset=0] [L2542-L2783] COND TRUE #t~switch241 VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#ldvarg2~0!base=225, ~#ldvarg2~0!offset=0, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0!base=0, ~ldvarg1~0!offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp~27!base=0, ~tmp~27!offset=0] [L2700] COND TRUE 0 != ~ldv_state_variable_2~0 [L2701] assume -2147483648 <= #t~nondet260 && #t~nondet260 <= 2147483647; [L2701] ~tmp___4~1 := #t~nondet260; [L2701] havoc #t~nondet260; [L2703] #t~switch261 := 0 == ~tmp___4~1; VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, #t~switch241=true, #t~switch243=true, #t~switch261=false, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#ldvarg2~0!base=225, ~#ldvarg2~0!offset=0, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0!base=0, ~ldvarg1~0!offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp___4~1=4, ~tmp~27!base=0, ~tmp~27!offset=0] [L2702-L2775] COND FALSE !(#t~switch261) [L2717] #t~switch261 := #t~switch261 || 1 == ~tmp___4~1; VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, #t~switch241=true, #t~switch243=true, #t~switch261=false, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#ldvarg2~0!base=225, ~#ldvarg2~0!offset=0, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0!base=0, ~ldvarg1~0!offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp___4~1=4, ~tmp~27!base=0, ~tmp~27!offset=0] [L2702-L2775] COND FALSE !(#t~switch261) [L2729] #t~switch261 := #t~switch261 || 2 == ~tmp___4~1; VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, #t~switch241=true, #t~switch243=true, #t~switch261=false, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#ldvarg2~0!base=225, ~#ldvarg2~0!offset=0, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0!base=0, ~ldvarg1~0!offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp___4~1=4, ~tmp~27!base=0, ~tmp~27!offset=0] [L2702-L2775] COND FALSE !(#t~switch261) [L2752] #t~switch261 := #t~switch261 || 3 == ~tmp___4~1; VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, #t~switch241=true, #t~switch243=true, #t~switch261=false, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#ldvarg2~0!base=225, ~#ldvarg2~0!offset=0, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0!base=0, ~ldvarg1~0!offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp___4~1=4, ~tmp~27!base=0, ~tmp~27!offset=0] [L2702-L2775] COND FALSE !(#t~switch261) [L2764] #t~switch261 := #t~switch261 || 4 == ~tmp___4~1; VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#ldvarg2~0!base=225, ~#ldvarg2~0!offset=0, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0!base=0, ~ldvarg1~0!offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp___4~1=4, ~tmp~27!base=0, ~tmp~27!offset=0] [L2702-L2775] COND TRUE #t~switch261 VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#ldvarg2~0!base=225, ~#ldvarg2~0!offset=0, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=1, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0!base=0, ~ldvarg1~0!offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp___4~1=4, ~tmp~27!base=0, ~tmp~27!offset=0] [L2765] COND TRUE 1 == ~ldv_state_variable_2~0 [L2766] FCALL call #t~ret268 := ldv_probe_2(); [L2766] assume -2147483648 <= #t~ret268 && #t~ret268 <= 2147483647; [L2766] havoc #t~ret268; [L2767] ~ldv_state_variable_2~0 := 2; [L2768] ~ref_cnt~0 := 1 + ~ref_cnt~0; VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#ldvarg2~0!base=225, ~#ldvarg2~0!offset=0, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0!base=0, ~ldvarg1~0!offset=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp___4~1=4, ~tmp~27!base=0, ~tmp~27!offset=0] [L2541] assume -2147483648 <= #t~nondet240 && #t~nondet240 <= 2147483647; [L2541] ~tmp___1~5 := #t~nondet240; [L2541] havoc #t~nondet240; [L2543] #t~switch241 := 0 == ~tmp___1~5; VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, #t~switch241=false, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#ldvarg2~0!base=225, ~#ldvarg2~0!offset=0, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0!base=0, ~ldvarg1~0!offset=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp___4~1=4, ~tmp~27!base=0, ~tmp~27!offset=0] [L2542-L2783] COND FALSE !(#t~switch241) [L2550] #t~switch241 := #t~switch241 || 1 == ~tmp___1~5; VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, #t~switch241=false, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#ldvarg2~0!base=225, ~#ldvarg2~0!offset=0, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0!base=0, ~ldvarg1~0!offset=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp___4~1=4, ~tmp~27!base=0, ~tmp~27!offset=0] [L2542-L2783] COND FALSE !(#t~switch241) [L2591] #t~switch241 := #t~switch241 || 2 == ~tmp___1~5; VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, #t~switch241=false, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#ldvarg2~0!base=225, ~#ldvarg2~0!offset=0, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0!base=0, ~ldvarg1~0!offset=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp___4~1=4, ~tmp~27!base=0, ~tmp~27!offset=0] [L2542-L2783] COND FALSE !(#t~switch241) [L2699] #t~switch241 := #t~switch241 || 3 == ~tmp___1~5; VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#ldvarg2~0!base=225, ~#ldvarg2~0!offset=0, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0!base=0, ~ldvarg1~0!offset=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp___4~1=4, ~tmp~27!base=0, ~tmp~27!offset=0] [L2542-L2783] COND TRUE #t~switch241 VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#ldvarg2~0!base=225, ~#ldvarg2~0!offset=0, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0!base=0, ~ldvarg1~0!offset=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp___4~1=4, ~tmp~27!base=0, ~tmp~27!offset=0] [L2700] COND TRUE 0 != ~ldv_state_variable_2~0 [L2701] assume -2147483648 <= #t~nondet260 && #t~nondet260 <= 2147483647; [L2701] ~tmp___4~1 := #t~nondet260; [L2701] havoc #t~nondet260; [L2703] #t~switch261 := 0 == ~tmp___4~1; VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#ldvarg2~0!base=225, ~#ldvarg2~0!offset=0, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0!base=0, ~ldvarg1~0!offset=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp___4~1=0, ~tmp~27!base=0, ~tmp~27!offset=0] [L2702-L2775] COND TRUE #t~switch261 VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#ldvarg2~0!base=225, ~#ldvarg2~0!offset=0, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0!base=0, ~ldvarg1~0!offset=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp___4~1=0, ~tmp~27!base=0, ~tmp~27!offset=0] [L2704] COND FALSE !(4 == ~ldv_state_variable_2~0) VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#ldvarg2~0!base=225, ~#ldvarg2~0!offset=0, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0!base=0, ~ldvarg1~0!offset=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp___4~1=0, ~tmp~27!base=0, ~tmp~27!offset=0] [L2710] COND TRUE 2 == ~ldv_state_variable_2~0 VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#ldvarg2~0!base=225, ~#ldvarg2~0!offset=0, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0!base=0, ~ldvarg1~0!offset=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp___0~8=179, ~tmp___1~5=3, ~tmp___2~1=1, ~tmp___4~1=0, ~tmp~27!base=0, ~tmp~27!offset=0] [L2711] CALL call tegra_rtc_shutdown(~tegra_rtc_driver_group0~0); VAL [#in~pdev!base=0, #in~pdev!offset=0, #NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0] [L2313-L2321] ~pdev := #in~pdev; VAL [#in~pdev!base=0, #in~pdev!offset=0, #NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~pdev!base=0, ~pdev!offset=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0] [L2318] CALL call #t~ret221 := tegra_rtc_alarm_irq_enable({ base: ~pdev!base, offset: 12 + ~pdev!offset }, 0); VAL [#in~dev!base=0, #in~dev!offset=12, #in~enabled=0, #NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0] [L2004-L2033] ~dev := #in~dev; [L2004-L2033] ~enabled := #in~enabled; [L2006] havoc ~info~4; [L2007] havoc ~tmp~14; [L2008] havoc ~status~0; [L2009] havoc ~sl_irq_flags~1; [L2010] havoc ~__v~3; [L2011] havoc ~__v___0~3; [L2014] FCALL call #t~ret107 := dev_get_drvdata(~dev); [L2014] ~tmp~14 := #t~ret107; [L2014] havoc #t~ret107; [L2015] ~info~4 := ~tmp~14; VAL [#in~dev!base=0, #in~dev!offset=12, #in~enabled=0, #NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~dev!base=0, ~dev!offset=12, ~enabled=0, ~info~4!base=156, ~info~4!offset=215, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp~14!base=156, ~tmp~14!offset=215] [L2016] CALL call #t~ret108 := tegra_rtc_wait_while_busy(~dev); VAL [#in~dev!base=0, #in~dev!offset=12, #NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0] [L1873-L1908] ~dev := #in~dev; [L1875] havoc ~info~0; [L1876] havoc ~tmp~10; [L1877] havoc ~retries~0; [L1878] havoc ~tmp___0~2; [L1879] havoc ~tmp___1~0; [L1882] FCALL call #t~ret87 := dev_get_drvdata(~dev); [L1882] ~tmp~10 := #t~ret87; [L1882] havoc #t~ret87; [L1883] ~info~0 := ~tmp~10; [L1884] ~retries~0 := 500; VAL [#in~dev!base=0, #in~dev!offset=12, #NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~dev!base=0, ~dev!offset=12, ~info~0!base=165, ~info~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~retries~0=500, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp~10!base=165, ~tmp~10!offset=0] [L1896] CALL call #t~ret88 := tegra_rtc_check_busy(~info~0); VAL [#in~info!base=165, #in~info!offset=0, #NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0] [L1861-L1872] ~info := #in~info; [L1863] havoc ~__v~0; [L1864] havoc ~__v___0~0; [L1867] FCALL call #t~mem85 := read~$Pointer$({ base: ~info!base, offset: 16 + ~info!offset }, 8); [L1867] FCALL call #t~mem86 := read~int({ base: #t~mem85!base, offset: 16 + #t~mem85!offset }, 4); [L1867] ~__v___0~0 := #t~mem86; [L1867] havoc #t~mem86; [L1867] havoc #t~mem85; [L1868] ~__v~0 := ~__v___0~0; [L1870] #res := ~bitwiseAnd(~__v~0, 1); VAL [#in~info!base=165, #in~info!offset=0, #NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~__v___0~0=201, ~__v~0=201, ~info!base=165, ~info!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0] [L1896] RET call #t~ret88 := tegra_rtc_check_busy(~info~0); VAL [#in~dev!base=0, #in~dev!offset=12, #NULL!base=0, #NULL!offset=0, #t~ret88=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~dev!base=0, ~dev!offset=12, ~info~0!base=165, ~info~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~retries~0=500, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp~10!base=165, ~tmp~10!offset=0] [L1896] ~tmp___1~0 := #t~ret88; [L1896] havoc #t~ret88; VAL [#in~dev!base=0, #in~dev!offset=12, #NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~dev!base=0, ~dev!offset=12, ~info~0!base=165, ~info~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~retries~0=500, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp___1~0=0, ~tmp~10!base=165, ~tmp~10!offset=0] [L1897] COND FALSE !(0 != ~tmp___1~0 % 4294967296) [L1903] #res := 0; VAL [#in~dev!base=0, #in~dev!offset=12, #NULL!base=0, #NULL!offset=0, #res=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~dev!base=0, ~dev!offset=12, ~info~0!base=165, ~info~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~retries~0=500, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp___1~0=0, ~tmp~10!base=165, ~tmp~10!offset=0] [L2016] RET call #t~ret108 := tegra_rtc_wait_while_busy(~dev); VAL [#in~dev!base=0, #in~dev!offset=12, #in~enabled=0, #NULL!base=0, #NULL!offset=0, #t~ret108=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~dev!base=0, ~dev!offset=12, ~enabled=0, ~info~4!base=156, ~info~4!offset=215, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp~14!base=156, ~tmp~14!offset=215] [L2016] assume -2147483648 <= #t~ret108 && #t~ret108 <= 2147483647; [L2016] havoc #t~ret108; VAL [#in~dev!base=0, #in~dev!offset=12, #in~enabled=0, #NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~dev!base=0, ~dev!offset=12, ~enabled=0, ~info~4!base=156, ~info~4!offset=215, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp~14!base=156, ~tmp~14!offset=215] [L2017] CALL call ldv_spin_lock_check(); VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0] [L2962] COND FALSE !(1 == ~ldv_init~0) VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0] [L2965] CALL call ldv_error(); VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0] [L1684] assert false; VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=3, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=2, ~ldv_state_variable_3~0=0, ~ref_cnt~0=1, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [?] CALL call ULTIMATE.init(); VAL [#NULL!base=183, #NULL!offset=219, #t~string125!base=160, #t~string125!offset=163, #t~string134!base=235, #t~string134!offset=169, #t~string140!base=158, #t~string140!offset=181, #t~string148!base=187, #t~string148!offset=207, #t~string149!base=229, #t~string149!offset=178, #t~string193!base=211, #t~string193!offset=173, #t~string195!base=217, #t~string195!offset=228, #t~string198!base=176, #t~string198!offset=182, #t~string200!base=222, #t~string200!offset=210, #t~string222!base=212, #t~string222!offset=191, #t~string90!base=166, #t~string90!offset=170, old(#NULL!base)=183, old(#NULL!offset)=219, old(#t~string125!base)=160, old(#t~string125!offset)=163, old(#t~string134!base)=235, old(#t~string134!offset)=169, old(#t~string140!base)=158, old(#t~string140!offset)=181, old(#t~string148!base)=187, old(#t~string148!offset)=207, old(#t~string149!base)=229, old(#t~string149!offset)=178, old(#t~string193!base)=211, old(#t~string193!offset)=173, old(#t~string195!base)=217, old(#t~string195!offset)=228, old(#t~string198!base)=176, old(#t~string198!offset)=182, old(#t~string200!base)=222, old(#t~string200!offset)=210, old(#t~string222!base)=212, old(#t~string222!offset)=191, old(#t~string90!base)=166, old(#t~string90!offset)=170, old(~#tegra_rtc_driver~0!base)=233, old(~#tegra_rtc_driver~0!offset)=190, old(~#tegra_rtc_ops~0!base)=226, old(~#tegra_rtc_ops~0!offset)=192, old(~LDV_IN_INTERRUPT~0)=172, old(~ldv_init~0)=196, old(~ldv_irq_1_0~0)=205, old(~ldv_irq_1_1~0)=195, old(~ldv_irq_1_2~0)=208, old(~ldv_irq_1_3~0)=194, old(~ldv_irq_data_1_0~0!base)=161, old(~ldv_irq_data_1_0~0!offset)=197, old(~ldv_irq_data_1_1~0!base)=213, old(~ldv_irq_data_1_1~0!offset)=185, old(~ldv_irq_data_1_2~0!base)=189, old(~ldv_irq_data_1_2~0!offset)=177, old(~ldv_irq_data_1_3~0!base)=154, old(~ldv_irq_data_1_3~0!offset)=202, old(~ldv_irq_line_1_0~0)=206, old(~ldv_irq_line_1_1~0)=232, old(~ldv_irq_line_1_2~0)=227, old(~ldv_irq_line_1_3~0)=167, old(~ldv_retval_0~0)=171, old(~ldv_retval_1~0)=164, old(~ldv_retval_2~0)=188, old(~ldv_state_variable_0~0)=184, old(~ldv_state_variable_1~0)=216, old(~ldv_state_variable_2~0)=209, old(~ldv_state_variable_3~0)=236, old(~ref_cnt~0)=204, old(~tegra_rtc_driver_group0~0!base)=223, old(~tegra_rtc_driver_group0~0!offset)=198, old(~tegra_rtc_ops_group0~0!base)=200, old(~tegra_rtc_ops_group0~0!offset)=180, old(~tegra_rtc_ops_group1~0!base)=220, old(~tegra_rtc_ops_group1~0!offset)=193, old(~tegra_rtc_ops_group2~0!base)=174, old(~tegra_rtc_ops_group2~0!offset)=157, ~#tegra_rtc_driver~0!base=233, ~#tegra_rtc_driver~0!offset=190, ~#tegra_rtc_ops~0!base=226, ~#tegra_rtc_ops~0!offset=192, ~LDV_IN_INTERRUPT~0=172, ~ldv_init~0=196, ~ldv_irq_1_0~0=205, ~ldv_irq_1_1~0=195, ~ldv_irq_1_2~0=208, ~ldv_irq_1_3~0=194, ~ldv_irq_data_1_0~0!base=161, ~ldv_irq_data_1_0~0!offset=197, ~ldv_irq_data_1_1~0!base=213, ~ldv_irq_data_1_1~0!offset=185, ~ldv_irq_data_1_2~0!base=189, ~ldv_irq_data_1_2~0!offset=177, ~ldv_irq_data_1_3~0!base=154, ~ldv_irq_data_1_3~0!offset=202, ~ldv_irq_line_1_0~0=206, ~ldv_irq_line_1_1~0=232, ~ldv_irq_line_1_2~0=227, ~ldv_irq_line_1_3~0=167, ~ldv_retval_0~0=171, ~ldv_retval_1~0=164, ~ldv_retval_2~0=188, ~ldv_state_variable_0~0=184, ~ldv_state_variable_1~0=216, ~ldv_state_variable_2~0=209, ~ldv_state_variable_3~0=236, ~ref_cnt~0=204, ~tegra_rtc_driver_group0~0!base=223, ~tegra_rtc_driver_group0~0!offset=198, ~tegra_rtc_ops_group0~0!base=200, ~tegra_rtc_ops_group0~0!offset=180, ~tegra_rtc_ops_group1~0!base=220, ~tegra_rtc_ops_group1~0!offset=193, ~tegra_rtc_ops_group2~0!base=174, ~tegra_rtc_ops_group2~0!offset=157] [?] #NULL := { base: 0, offset: 0 }; [?] #valid[0] := 0; [L1905] FCALL call #t~string90 := #Ultimate.alloc(36); [L2072] FCALL call #t~string125 := #Ultimate.alloc(12); [L2150] FCALL call #t~string134 := #Ultimate.alloc(42); [L2159] FCALL call #t~string140 := #Ultimate.alloc(42); [L2175] FCALL call #t~string148 := #Ultimate.alloc(32); [L2189] FCALL call #t~string149 := #Ultimate.alloc(21); [L2211] FCALL call #t~string193 := #Ultimate.alloc(37); [L2218] FCALL call #t~string195 := #Ultimate.alloc(10); [L2220] FCALL call #t~string198 := #Ultimate.alloc(50); [L2226] FCALL call #t~string200 := #Ultimate.alloc(32); [L2323] FCALL call #t~string222 := #Ultimate.alloc(10); [L1713] ~ldv_irq_1_2~0 := 0; [L1714] ~LDV_IN_INTERRUPT~0 := 1; [L1715] ~ldv_irq_1_3~0 := 0; [L1717] ~ldv_irq_data_1_1~0 := { base: 0, offset: 0 }; [L1718] ~ldv_irq_1_1~0 := 0; [L1719] ~ldv_irq_1_0~0 := 0; [L1720] ~ldv_irq_line_1_3~0 := 0; [L1721] ~ldv_irq_data_1_0~0 := { base: 0, offset: 0 }; [L1722] ~ldv_state_variable_0~0 := 0; [L1724] ~ldv_state_variable_3~0 := 0; [L1725] ~ldv_irq_line_1_0~0 := 0; [L1726] ~ldv_state_variable_2~0 := 0; [L1727] ~ldv_irq_data_1_3~0 := { base: 0, offset: 0 }; [L1728] ~ref_cnt~0 := 0; [L1729] ~ldv_irq_line_1_1~0 := 0; [L1731] ~ldv_irq_data_1_2~0 := { base: 0, offset: 0 }; [L1732] ~ldv_state_variable_1~0 := 0; [L1733] ~ldv_irq_line_1_2~0 := 0; [L2342] ~ldv_retval_2~0 := 0; [L2343] ~ldv_retval_0~0 := 0; [L2345] ~ldv_retval_1~0 := 0; [L2943] ~ldv_init~0 := 0; [L1716] ~tegra_rtc_driver_group0~0 := { base: 0, offset: 0 }; [L1723] ~tegra_rtc_ops_group1~0 := { base: 0, offset: 0 }; [L1730] ~tegra_rtc_ops_group0~0 := { base: 0, offset: 0 }; [L1734] ~tegra_rtc_ops_group2~0 := { base: 0, offset: 0 }; [L2123-L2125] FCALL call ~#tegra_rtc_ops~0 := #Ultimate.alloc(88); [L2123-L2125] FCALL call write~init~$Pointer$({ base: 0, offset: 0 }, { base: ~#tegra_rtc_ops~0!base, offset: ~#tegra_rtc_ops~0!offset }, 8); [L2123-L2125] FCALL call write~init~$Pointer$({ base: 0, offset: 0 }, { base: ~#tegra_rtc_ops~0!base, offset: 8 + ~#tegra_rtc_ops~0!offset }, 8); [L2123-L2125] FCALL call write~init~$Pointer$({ base: 0, offset: 0 }, { base: ~#tegra_rtc_ops~0!base, offset: 16 + ~#tegra_rtc_ops~0!offset }, 8); [L2123-L2125] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_read_time, { base: ~#tegra_rtc_ops~0!base, offset: 24 + ~#tegra_rtc_ops~0!offset }, 8); [L2123-L2125] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_set_time, { base: ~#tegra_rtc_ops~0!base, offset: 32 + ~#tegra_rtc_ops~0!offset }, 8); [L2123-L2125] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_read_alarm, { base: ~#tegra_rtc_ops~0!base, offset: 40 + ~#tegra_rtc_ops~0!offset }, 8); [L2123-L2125] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_set_alarm, { base: ~#tegra_rtc_ops~0!base, offset: 48 + ~#tegra_rtc_ops~0!offset }, 8); [L2123-L2125] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_proc, { base: ~#tegra_rtc_ops~0!base, offset: 56 + ~#tegra_rtc_ops~0!offset }, 8); [L2123-L2125] FCALL call write~init~$Pointer$({ base: 0, offset: 0 }, { base: ~#tegra_rtc_ops~0!base, offset: 64 + ~#tegra_rtc_ops~0!offset }, 8); [L2123-L2125] FCALL call write~init~$Pointer$({ base: 0, offset: 0 }, { base: ~#tegra_rtc_ops~0!base, offset: 72 + ~#tegra_rtc_ops~0!offset }, 8); [L2123-L2125] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_alarm_irq_enable, { base: ~#tegra_rtc_ops~0!base, offset: 80 + ~#tegra_rtc_ops~0!offset }, 8); [L2322-L2323] FCALL call ~#tegra_rtc_driver~0 := #Ultimate.alloc(153); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0, offset: 0 }, { base: ~#tegra_rtc_driver~0!base, offset: ~#tegra_rtc_driver~0!offset }, 8); [L2322-L2323] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_remove, { base: ~#tegra_rtc_driver~0!base, offset: 8 + ~#tegra_rtc_driver~0!offset }, 8); [L2322-L2323] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_shutdown, { base: ~#tegra_rtc_driver~0!base, offset: 16 + ~#tegra_rtc_driver~0!offset }, 8); [L2322-L2323] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_suspend, { base: ~#tegra_rtc_driver~0!base, offset: 24 + ~#tegra_rtc_driver~0!offset }, 8); [L2322-L2323] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_resume, { base: ~#tegra_rtc_driver~0!base, offset: 32 + ~#tegra_rtc_driver~0!offset }, 8); [L2322-L2323] FCALL call write~init~$Pointer$(#t~string222, { base: ~#tegra_rtc_driver~0!base, offset: 40 + ~#tegra_rtc_driver~0!offset }, 8); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0, offset: 0 }, { base: ~#tegra_rtc_driver~0!base, offset: 48 + ~#tegra_rtc_driver~0!offset }, 8); [L2322-L2323] FCALL call write~init~$Pointer$(~#__this_module~0, { base: ~#tegra_rtc_driver~0!base, offset: 56 + ~#tegra_rtc_driver~0!offset }, 8); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0, offset: 0 }, { base: ~#tegra_rtc_driver~0!base, offset: 64 + ~#tegra_rtc_driver~0!offset }, 8); [L2322-L2323] FCALL call write~init~int(0, { base: ~#tegra_rtc_driver~0!base, offset: 72 + ~#tegra_rtc_driver~0!offset }, 1); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0, offset: 0 }, { base: ~#tegra_rtc_driver~0!base, offset: 73 + ~#tegra_rtc_driver~0!offset }, 8); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0, offset: 0 }, { base: ~#tegra_rtc_driver~0!base, offset: 81 + ~#tegra_rtc_driver~0!offset }, 8); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0, offset: 0 }, { base: ~#tegra_rtc_driver~0!base, offset: 89 + ~#tegra_rtc_driver~0!offset }, 8); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0, offset: 0 }, { base: ~#tegra_rtc_driver~0!base, offset: 97 + ~#tegra_rtc_driver~0!offset }, 8); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0, offset: 0 }, { base: ~#tegra_rtc_driver~0!base, offset: 105 + ~#tegra_rtc_driver~0!offset }, 8); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0, offset: 0 }, { base: ~#tegra_rtc_driver~0!base, offset: 113 + ~#tegra_rtc_driver~0!offset }, 8); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0, offset: 0 }, { base: ~#tegra_rtc_driver~0!base, offset: 121 + ~#tegra_rtc_driver~0!offset }, 8); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0, offset: 0 }, { base: ~#tegra_rtc_driver~0!base, offset: 129 + ~#tegra_rtc_driver~0!offset }, 8); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0, offset: 0 }, { base: ~#tegra_rtc_driver~0!base, offset: 137 + ~#tegra_rtc_driver~0!offset }, 8); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0, offset: 0 }, { base: ~#tegra_rtc_driver~0!base, offset: 145 + ~#tegra_rtc_driver~0!offset }, 8); VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, old(#NULL!base)=183, old(#NULL!offset)=219, old(#t~string125!base)=160, old(#t~string125!offset)=163, old(#t~string134!base)=235, old(#t~string134!offset)=169, old(#t~string140!base)=158, old(#t~string140!offset)=181, old(#t~string148!base)=187, old(#t~string148!offset)=207, old(#t~string149!base)=229, old(#t~string149!offset)=178, old(#t~string193!base)=211, old(#t~string193!offset)=173, old(#t~string195!base)=217, old(#t~string195!offset)=228, old(#t~string198!base)=176, old(#t~string198!offset)=182, old(#t~string200!base)=222, old(#t~string200!offset)=210, old(#t~string222!base)=212, old(#t~string222!offset)=191, old(#t~string90!base)=166, old(#t~string90!offset)=170, old(~#tegra_rtc_driver~0!base)=233, old(~#tegra_rtc_driver~0!offset)=190, old(~#tegra_rtc_ops~0!base)=226, old(~#tegra_rtc_ops~0!offset)=192, old(~LDV_IN_INTERRUPT~0)=172, old(~ldv_init~0)=196, old(~ldv_irq_1_0~0)=205, old(~ldv_irq_1_1~0)=195, old(~ldv_irq_1_2~0)=208, old(~ldv_irq_1_3~0)=194, old(~ldv_irq_data_1_0~0!base)=161, old(~ldv_irq_data_1_0~0!offset)=197, old(~ldv_irq_data_1_1~0!base)=213, old(~ldv_irq_data_1_1~0!offset)=185, old(~ldv_irq_data_1_2~0!base)=189, old(~ldv_irq_data_1_2~0!offset)=177, old(~ldv_irq_data_1_3~0!base)=154, old(~ldv_irq_data_1_3~0!offset)=202, old(~ldv_irq_line_1_0~0)=206, old(~ldv_irq_line_1_1~0)=232, old(~ldv_irq_line_1_2~0)=227, old(~ldv_irq_line_1_3~0)=167, old(~ldv_retval_0~0)=171, old(~ldv_retval_1~0)=164, old(~ldv_retval_2~0)=188, old(~ldv_state_variable_0~0)=184, old(~ldv_state_variable_1~0)=216, old(~ldv_state_variable_2~0)=209, old(~ldv_state_variable_3~0)=236, old(~ref_cnt~0)=204, old(~tegra_rtc_driver_group0~0!base)=223, old(~tegra_rtc_driver_group0~0!offset)=198, old(~tegra_rtc_ops_group0~0!base)=200, old(~tegra_rtc_ops_group0~0!offset)=180, old(~tegra_rtc_ops_group1~0!base)=220, old(~tegra_rtc_ops_group1~0!offset)=193, old(~tegra_rtc_ops_group2~0!base)=174, old(~tegra_rtc_ops_group2~0!offset)=157, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0] [?] RET call ULTIMATE.init(); VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0] [?] CALL call #t~ret277 := main(); VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0] [L2518] havoc ~ldvarg1~0; [L2519] havoc ~tmp~27; [L2520] havoc ~ldvarg0~0; [L2521] havoc ~tmp___0~8; [L2522] FCALL call ~#ldvarg2~0 := #Ultimate.alloc(4); [L2523] havoc ~tmp___1~5; [L2524] havoc ~tmp___2~1; [L2525] havoc ~tmp___3~1; [L2526] havoc ~tmp___4~1; VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#ldvarg2~0!base=225, ~#ldvarg2~0!offset=0, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0] [L2529] CALL call #t~ret237 := ldv_zalloc(136); VAL [#in~size=136, #NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0] [L1633-L1650] ~size := #in~size; [L1635] havoc ~p~1; [L1636] havoc ~tmp~1; [L1637] havoc ~tmp___0~1; [L1640] assume -2147483648 <= #t~nondet12 && #t~nondet12 <= 2147483647; [L1640] ~tmp___0~1 := #t~nondet12; [L1640] havoc #t~nondet12; VAL [#in~size=136, #NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~size=136, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp___0~1=1] [L1641] COND TRUE 0 != ~tmp___0~1 [L1642] #res := { base: 0, offset: 0 }; VAL [#in~size=136, #NULL!base=0, #NULL!offset=0, #res!base=0, #res!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~size=136, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp___0~1=1] [L2529] RET call #t~ret237 := ldv_zalloc(136); VAL [#NULL!base=0, #NULL!offset=0, #t~ret237!base=0, #t~ret237!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#ldvarg2~0!base=225, ~#ldvarg2~0!offset=0, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0] [L2529] ~tmp~27 := #t~ret237; [L2529] havoc #t~ret237; [L2530] ~ldvarg1~0 := ~tmp~27; [L2531] ~tmp___0~8 := #t~nondet238; [L2531] havoc #t~nondet238; [L2532] ~ldvarg0~0 := ~tmp___0~8; [L2533] FCALL call ldv_initialize(); VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#ldvarg2~0!base=225, ~#ldvarg2~0!offset=0, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0!base=0, ~ldvarg1~0!offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp___0~8=179, ~tmp~27!base=0, ~tmp~27!offset=0] [L2534] CALL call #t~memset~res239 := #Ultimate.C_memset(~#ldvarg2~0, 0, 4); VAL [#amount=4, #NULL!base=0, #NULL!offset=0, #ptr!base=225, #ptr!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, #value=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0] [?] #t~loopctr278 := 0; VAL [#amount=4, #NULL!base=0, #NULL!offset=0, #ptr!base=225, #ptr!offset=0, #t~loopctr278=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, #value=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0] [?] COND TRUE #t~loopctr278 < #amount [?] #memory_$Pointer$[{ base: #ptr!base, offset: #ptr!offset + #t~loopctr278 }] := { base: 0, offset: #value % 256 }; [?] #memory_int[{ base: #ptr!base, offset: #ptr!offset + #t~loopctr278 }] := #value; [?] #t~loopctr278 := 1 + #t~loopctr278; VAL [#amount=4, #NULL!base=0, #NULL!offset=0, #ptr!base=225, #ptr!offset=0, #t~loopctr278=1, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, #value=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0] [?] COND TRUE #t~loopctr278 < #amount [?] #memory_$Pointer$[{ base: #ptr!base, offset: #ptr!offset + #t~loopctr278 }] := { base: 0, offset: #value % 256 }; [?] #memory_int[{ base: #ptr!base, offset: #ptr!offset + #t~loopctr278 }] := #value; [?] #t~loopctr278 := 1 + #t~loopctr278; VAL [#amount=4, #NULL!base=0, #NULL!offset=0, #ptr!base=225, #ptr!offset=0, #t~loopctr278=2, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, #value=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0] [?] COND TRUE #t~loopctr278 < #amount [?] #memory_$Pointer$[{ base: #ptr!base, offset: #ptr!offset + #t~loopctr278 }] := { base: 0, offset: #value % 256 }; [?] #memory_int[{ base: #ptr!base, offset: #ptr!offset + #t~loopctr278 }] := #value; [?] #t~loopctr278 := 1 + #t~loopctr278; VAL [#amount=4, #NULL!base=0, #NULL!offset=0, #ptr!base=225, #ptr!offset=0, #t~loopctr278=3, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, #value=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0] [?] COND TRUE #t~loopctr278 < #amount [?] #memory_$Pointer$[{ base: #ptr!base, offset: #ptr!offset + #t~loopctr278 }] := { base: 0, offset: #value % 256 }; [?] #memory_int[{ base: #ptr!base, offset: #ptr!offset + #t~loopctr278 }] := #value; [?] #t~loopctr278 := 1 + #t~loopctr278; VAL [#amount=4, #NULL!base=0, #NULL!offset=0, #ptr!base=225, #ptr!offset=0, #t~loopctr278=4, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, #value=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0] [?] COND FALSE !(#t~loopctr278 < #amount) VAL [#amount=4, #NULL!base=0, #NULL!offset=0, #ptr!base=225, #ptr!offset=0, #t~loopctr278=4, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, #value=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0] [L2534] RET call #t~memset~res239 := #Ultimate.C_memset(~#ldvarg2~0, 0, 4); VAL [#NULL!base=0, #NULL!offset=0, #t~memset~res239!base=225, #t~memset~res239!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#ldvarg2~0!base=225, ~#ldvarg2~0!offset=0, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=0, ~ldv_state_variable_1~0=0, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0!base=0, ~ldvarg1~0!offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp___0~8=179, ~tmp~27!base=0, ~tmp~27!offset=0] [L2534] havoc #t~memset~res239; [L2535] ~ldv_state_variable_1~0 := 1; [L2536] ~ref_cnt~0 := 0; [L2537] ~ldv_state_variable_0~0 := 1; [L2538] ~ldv_state_variable_3~0 := 0; [L2539] ~ldv_state_variable_2~0 := 0; VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#ldvarg2~0!base=225, ~#ldvarg2~0!offset=0, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0!base=0, ~ldvarg1~0!offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp___0~8=179, ~tmp~27!base=0, ~tmp~27!offset=0] [L2541] assume -2147483648 <= #t~nondet240 && #t~nondet240 <= 2147483647; [L2541] ~tmp___1~5 := #t~nondet240; [L2541] havoc #t~nondet240; [L2543] #t~switch241 := 0 == ~tmp___1~5; VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, #t~switch241=false, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#ldvarg2~0!base=225, ~#ldvarg2~0!offset=0, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0!base=0, ~ldvarg1~0!offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp___0~8=179, ~tmp___1~5=1, ~tmp~27!base=0, ~tmp~27!offset=0] [L2542-L2783] COND FALSE !(#t~switch241) [L2550] #t~switch241 := #t~switch241 || 1 == ~tmp___1~5; VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, #t~switch241=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#ldvarg2~0!base=225, ~#ldvarg2~0!offset=0, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0!base=0, ~ldvarg1~0!offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp___0~8=179, ~tmp___1~5=1, ~tmp~27!base=0, ~tmp~27!offset=0] [L2542-L2783] COND TRUE #t~switch241 VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, #t~switch241=true, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#ldvarg2~0!base=225, ~#ldvarg2~0!offset=0, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0!base=0, ~ldvarg1~0!offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp___0~8=179, ~tmp___1~5=1, ~tmp~27!base=0, ~tmp~27!offset=0] [L2551] COND TRUE 0 != ~ldv_state_variable_0~0 [L2552] assume -2147483648 <= #t~nondet242 && #t~nondet242 <= 2147483647; [L2552] ~tmp___2~1 := #t~nondet242; [L2552] havoc #t~nondet242; [L2554] #t~switch243 := 0 == ~tmp___2~1; VAL [#NULL!base=0, #NULL!offset=0, #t~string125!base=159, #t~string125!offset=0, #t~string134!base=237, #t~string134!offset=0, #t~string140!base=155, #t~string140!offset=0, #t~string148!base=186, #t~string148!offset=0, #t~string149!base=230, #t~string149!offset=0, #t~string193!base=218, #t~string193!offset=0, #t~string195!base=214, #t~string195!offset=0, #t~string198!base=175, #t~string198!offset=0, #t~string200!base=221, #t~string200!offset=0, #t~string222!base=234, #t~string222!offset=0, #t~string90!base=168, #t~string90!offset=0, #t~switch241=true, #t~switch243=false, old(~LDV_IN_INTERRUPT~0)=1, old(~ldv_irq_1_0~0)=0, old(~ldv_irq_1_1~0)=0, old(~ldv_irq_1_2~0)=0, old(~ldv_irq_1_3~0)=0, old(~ldv_retval_0~0)=0, old(~ldv_retval_1~0)=0, old(~ldv_retval_2~0)=0, old(~ldv_state_variable_0~0)=0, old(~ldv_state_variable_1~0)=0, old(~ldv_state_variable_2~0)=0, old(~ldv_state_variable_3~0)=0, old(~ref_cnt~0)=0, old(~tegra_rtc_driver_group0~0!base)=0, old(~tegra_rtc_driver_group0~0!offset)=0, ~#__this_module~0!base=162, ~#__this_module~0!offset=199, ~#ldvarg2~0!base=225, ~#ldvarg2~0!offset=0, ~#tegra_rtc_driver~0!base=231, ~#tegra_rtc_driver~0!offset=0, ~#tegra_rtc_ops~0!base=224, ~#tegra_rtc_ops~0!offset=0, ~LDV_IN_INTERRUPT~0=1, ~ldv_init~0=0, ~ldv_irq_1_0~0=0, ~ldv_irq_1_1~0=0, ~ldv_irq_1_2~0=0, ~ldv_irq_1_3~0=0, ~ldv_irq_data_1_0~0!base=0, ~ldv_irq_data_1_0~0!offset=0, ~ldv_irq_data_1_1~0!base=0, ~ldv_irq_data_1_1~0!offset=0, ~ldv_irq_data_1_2~0!base=0, ~ldv_irq_data_1_2~0!offset=0, ~ldv_irq_data_1_3~0!base=0, ~ldv_irq_data_1_3~0!offset=0, ~ldv_irq_line_1_0~0=0, ~ldv_irq_line_1_1~0=0, ~ldv_irq_line_1_2~0=0, ~ldv_irq_line_1_3~0=0, ~ldv_retval_0~0=0, ~ldv_retval_1~0=0, ~ldv_retval_2~0=0, ~ldv_state_variable_0~0=1, ~ldv_state_variable_1~0=1, ~ldv_state_variable_2~0=0, ~ldv_state_variable_3~0=0, ~ldvarg0~0=179, ~ldvarg1~0!base=0, ~ldvarg1~0!offset=0, ~ref_cnt~0=0, ~tegra_rtc_driver_group0~0!base=0, ~tegra_rtc_driver_group0~0!offset=0, ~tegra_rtc_ops_group0~0!base=0, ~tegra_rtc_ops_group0~0!offset=0, ~tegra_rtc_ops_group1~0!base=0, ~tegra_rtc_ops_group1~0!offset=0, ~tegra_rtc_ops_group2~0!base=0, ~tegra_rtc_ops_group2~0!offset=0, ~tmp___0~8=179, ~tmp___1~5=1, ~tmp___2~1=1, ~tmp~27!base=0, ~tmp~27!offset=0] WARNING: YOUR LOGFILE WAS TOO LONG, SOME LINES IN THE MIDDLE WERE REMOVED. [L2553-L2585] COND TRUE #t~switch243 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2564] COND TRUE 1bv32 == ~ldv_state_variable_0~0 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2565] CALL call #t~ret244 := tegra_rtc_init(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2326] havoc ~tmp~22; [L2329] FCALL call #t~ret223 := platform_driver_probe(~#tegra_rtc_driver~0, #funAddr~tegra_rtc_probe); [L2329] ~tmp~22 := #t~ret223; [L2329] havoc #t~ret223; [L2330] #res := ~tmp~22; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #res=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~22=0bv32] [L2565] RET call #t~ret244 := tegra_rtc_init(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~ret244=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2565] ~ldv_retval_0~0 := #t~ret244; [L2565] havoc #t~ret244; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2566] COND TRUE 0bv32 == ~ldv_retval_0~0 [L2567] ~ldv_state_variable_0~0 := 3bv32; [L2568] ~ldv_state_variable_2~0 := 1bv32; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2569] CALL call ldv_initialize_platform_driver_2(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2476] havoc ~tmp~26; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2479] CALL call #t~ret236 := ldv_zalloc(624bv32); VAL [#in~size=624bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L1633-L1650] ~size := #in~size; [L1635] havoc ~p~1; [L1636] havoc ~tmp~1; [L1637] havoc ~tmp___0~1; [L1640] ~tmp___0~1 := #t~nondet12; [L1640] havoc #t~nondet12; VAL [#in~size=624bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~size=624bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~1=1bv32] [L1641] COND TRUE 0bv32 != ~tmp___0~1 [L1642] #res := { base: 0bv32, offset: 0bv32 }; VAL [#in~size=624bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #res!base=0bv32, #res!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~size=624bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~1=1bv32] [L2479] RET call #t~ret236 := ldv_zalloc(624bv32); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~ret236!base=0bv32, #t~ret236!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2479] ~tmp~26 := #t~ret236; [L2479] havoc #t~ret236; [L2480] ~tegra_rtc_driver_group0~0 := ~tmp~26; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~26!base=0bv32, ~tmp~26!offset=0bv32] [L2569] RET call ldv_initialize_platform_driver_2(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2573] COND FALSE !(0bv32 != ~ldv_retval_0~0) VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2541] ~tmp___1~5 := #t~nondet240; [L2541] havoc #t~nondet240; [L2543] #t~switch241 := 0bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=false, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND FALSE !(#t~switch241) [L2550] #t~switch241 := #t~switch241 || 1bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=false, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND FALSE !(#t~switch241) [L2591] #t~switch241 := #t~switch241 || 2bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=false, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND FALSE !(#t~switch241) [L2699] #t~switch241 := #t~switch241 || 3bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND TRUE #t~switch241 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2700] COND TRUE 0bv32 != ~ldv_state_variable_2~0 [L2701] ~tmp___4~1 := #t~nondet260; [L2701] havoc #t~nondet260; [L2703] #t~switch261 := 0bv32 == ~tmp___4~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2702-L2775] COND FALSE !(#t~switch261) [L2717] #t~switch261 := #t~switch261 || 1bv32 == ~tmp___4~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2702-L2775] COND FALSE !(#t~switch261) [L2729] #t~switch261 := #t~switch261 || 2bv32 == ~tmp___4~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2702-L2775] COND FALSE !(#t~switch261) [L2752] #t~switch261 := #t~switch261 || 3bv32 == ~tmp___4~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2702-L2775] COND FALSE !(#t~switch261) [L2764] #t~switch261 := #t~switch261 || 4bv32 == ~tmp___4~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2702-L2775] COND TRUE #t~switch261 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2765] COND TRUE 1bv32 == ~ldv_state_variable_2~0 [L2766] FCALL call #t~ret268 := ldv_probe_2(); [L2766] havoc #t~ret268; [L2767] ~ldv_state_variable_2~0 := 2bv32; [L2768] ~ref_cnt~0 := ~bvadd32(1bv32, ~ref_cnt~0); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2541] ~tmp___1~5 := #t~nondet240; [L2541] havoc #t~nondet240; [L2543] #t~switch241 := 0bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=false, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND FALSE !(#t~switch241) [L2550] #t~switch241 := #t~switch241 || 1bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=false, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND FALSE !(#t~switch241) [L2591] #t~switch241 := #t~switch241 || 2bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=false, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND FALSE !(#t~switch241) [L2699] #t~switch241 := #t~switch241 || 3bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND TRUE #t~switch241 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2700] COND TRUE 0bv32 != ~ldv_state_variable_2~0 [L2701] ~tmp___4~1 := #t~nondet260; [L2701] havoc #t~nondet260; [L2703] #t~switch261 := 0bv32 == ~tmp___4~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=0bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2702-L2775] COND TRUE #t~switch261 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=0bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2704] COND FALSE !(4bv32 == ~ldv_state_variable_2~0) VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=0bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2710] COND TRUE 2bv32 == ~ldv_state_variable_2~0 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=0bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2711] CALL call tegra_rtc_shutdown(~tegra_rtc_driver_group0~0); VAL [#in~pdev!base=0bv32, #in~pdev!offset=0bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2313-L2321] ~pdev := #in~pdev; VAL [#in~pdev!base=0bv32, #in~pdev!offset=0bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~pdev!base=0bv32, ~pdev!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2318] CALL call #t~ret221 := tegra_rtc_alarm_irq_enable({ base: ~pdev!base, offset: ~bvadd32(12bv32, ~pdev!offset) }, 0bv32); VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #in~enabled=0bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2004-L2033] ~dev := #in~dev; [L2004-L2033] ~enabled := #in~enabled; [L2006] havoc ~info~4; [L2007] havoc ~tmp~14; [L2008] havoc ~status~0; [L2009] havoc ~sl_irq_flags~1; [L2010] havoc ~__v~3; [L2011] havoc ~__v___0~3; [L2014] FCALL call #t~ret107 := dev_get_drvdata(~dev); [L2014] ~tmp~14 := #t~ret107; [L2014] havoc #t~ret107; [L2015] ~info~4 := ~tmp~14; VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #in~enabled=0bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~enabled=0bv32, ~info~4!base=0bv32, ~info~4!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~14!base=0bv32, ~tmp~14!offset=0bv32] [L2016] CALL call #t~ret108 := tegra_rtc_wait_while_busy(~dev); VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L1873-L1908] ~dev := #in~dev; [L1875] havoc ~info~0; [L1876] havoc ~tmp~10; [L1877] havoc ~retries~0; [L1878] havoc ~tmp___0~2; [L1879] havoc ~tmp___1~0; [L1882] FCALL call #t~ret87 := dev_get_drvdata(~dev); [L1882] ~tmp~10 := #t~ret87; [L1882] havoc #t~ret87; [L1883] ~info~0 := ~tmp~10; [L1884] ~retries~0 := 500bv32; VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~info~0!base=67108865bv32, ~info~0!offset=4294967283bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~retries~0=500bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~10!base=67108865bv32, ~tmp~10!offset=4294967283bv32] [L1896] CALL call #t~ret88 := tegra_rtc_check_busy(~info~0); VAL [#in~info!base=67108865bv32, #in~info!offset=4294967283bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L1861-L1872] ~info := #in~info; [L1863] havoc ~__v~0; [L1864] havoc ~__v___0~0; [L1867] FCALL call #t~mem85 := read~$Pointer$({ base: ~info!base, offset: ~bvadd32(16bv32, ~info!offset) }, 8bv32); [L1867] FCALL call #t~mem86 := read~intINTTYPE4({ base: #t~mem85!base, offset: ~bvadd32(16bv32, #t~mem85!offset) }, 4bv32); [L1867] ~__v___0~0 := #t~mem86; [L1867] havoc #t~mem85; [L1867] havoc #t~mem86; [L1868] ~__v~0 := ~__v___0~0; [L1870] #res := ~bvand32(1bv32, ~__v~0); VAL [#in~info!base=67108865bv32, #in~info!offset=4294967283bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #res=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~__v___0~0=0bv32, ~__v~0=0bv32, ~info!base=67108865bv32, ~info!offset=4294967283bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L1896] RET call #t~ret88 := tegra_rtc_check_busy(~info~0); VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~ret88=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~info~0!base=67108865bv32, ~info~0!offset=4294967283bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~retries~0=500bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~10!base=67108865bv32, ~tmp~10!offset=4294967283bv32] [L1896] ~tmp___1~0 := #t~ret88; [L1896] havoc #t~ret88; VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~info~0!base=67108865bv32, ~info~0!offset=4294967283bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~retries~0=500bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___1~0=0bv32, ~tmp~10!base=67108865bv32, ~tmp~10!offset=4294967283bv32] [L1897] COND FALSE !(0bv32 != ~tmp___1~0) [L1903] #res := 0bv32; VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #res=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~info~0!base=67108865bv32, ~info~0!offset=4294967283bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~retries~0=500bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___1~0=0bv32, ~tmp~10!base=67108865bv32, ~tmp~10!offset=4294967283bv32] [L2016] RET call #t~ret108 := tegra_rtc_wait_while_busy(~dev); VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #in~enabled=0bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~ret108=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~enabled=0bv32, ~info~4!base=0bv32, ~info~4!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~14!base=0bv32, ~tmp~14!offset=0bv32] [L2016] havoc #t~ret108; VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #in~enabled=0bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~enabled=0bv32, ~info~4!base=0bv32, ~info~4!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~14!base=0bv32, ~tmp~14!offset=0bv32] [L2017] CALL call ldv_spin_lock_check(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2962] COND FALSE !(1bv32 == ~ldv_init~0) VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2965] CALL call ldv_error(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L1684] assert false; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] ----- ----- class de.uni_freiburg.informatik.ultimate.boogie.procedureinliner.backtranslation.InlinerBacktranslator [?] CALL call ULTIMATE.init(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=0bv32, #t~string125!offset=0bv32, #t~string134!base=0bv32, #t~string134!offset=0bv32, #t~string140!base=0bv32, #t~string140!offset=0bv32, #t~string148!base=0bv32, #t~string148!offset=0bv32, #t~string149!base=0bv32, #t~string149!offset=0bv32, #t~string193!base=0bv32, #t~string193!offset=0bv32, #t~string195!base=0bv32, #t~string195!offset=0bv32, #t~string198!base=0bv32, #t~string198!offset=0bv32, #t~string200!base=0bv32, #t~string200!offset=0bv32, #t~string222!base=0bv32, #t~string222!offset=0bv32, #t~string90!base=0bv32, #t~string90!offset=0bv32, old(#NULL!base)=0bv32, old(#NULL!offset)=0bv32, old(#t~string125!base)=0bv32, old(#t~string125!offset)=0bv32, old(#t~string134!base)=0bv32, old(#t~string134!offset)=0bv32, old(#t~string140!base)=0bv32, old(#t~string140!offset)=0bv32, old(#t~string148!base)=0bv32, old(#t~string148!offset)=0bv32, old(#t~string149!base)=0bv32, old(#t~string149!offset)=0bv32, old(#t~string193!base)=0bv32, old(#t~string193!offset)=0bv32, old(#t~string195!base)=0bv32, old(#t~string195!offset)=0bv32, old(#t~string198!base)=0bv32, old(#t~string198!offset)=0bv32, old(#t~string200!base)=0bv32, old(#t~string200!offset)=0bv32, old(#t~string222!base)=0bv32, old(#t~string222!offset)=0bv32, old(#t~string90!base)=0bv32, old(#t~string90!offset)=0bv32, old(~#tegra_rtc_driver~0!base)=0bv32, old(~#tegra_rtc_driver~0!offset)=0bv32, old(~#tegra_rtc_ops~0!base)=0bv32, old(~#tegra_rtc_ops~0!offset)=0bv32, old(~LDV_IN_INTERRUPT~0)=0bv32, old(~ldv_init~0)=0bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_irq_data_1_0~0!base)=0bv32, old(~ldv_irq_data_1_0~0!offset)=0bv32, old(~ldv_irq_data_1_1~0!base)=0bv32, old(~ldv_irq_data_1_1~0!offset)=0bv32, old(~ldv_irq_data_1_2~0!base)=0bv32, old(~ldv_irq_data_1_2~0!offset)=0bv32, old(~ldv_irq_data_1_3~0!base)=0bv32, old(~ldv_irq_data_1_3~0!offset)=0bv32, old(~ldv_irq_line_1_0~0)=0bv32, old(~ldv_irq_line_1_1~0)=0bv32, old(~ldv_irq_line_1_2~0)=0bv32, old(~ldv_irq_line_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, old(~tegra_rtc_ops_group0~0!base)=0bv32, old(~tegra_rtc_ops_group0~0!offset)=0bv32, old(~tegra_rtc_ops_group1~0!base)=0bv32, old(~tegra_rtc_ops_group1~0!offset)=0bv32, old(~tegra_rtc_ops_group2~0!base)=0bv32, old(~tegra_rtc_ops_group2~0!offset)=0bv32, ~#tegra_rtc_driver~0!base=0bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=0bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=0bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] #NULL := { base: 0bv32, offset: 0bv32 }; [?] #valid[0bv32] := 0bv1; [L1905] FCALL call #t~string90 := #Ultimate.alloc(36bv32); [L2072] FCALL call #t~string125 := #Ultimate.alloc(12bv32); [L2150] FCALL call #t~string134 := #Ultimate.alloc(42bv32); [L2159] FCALL call #t~string140 := #Ultimate.alloc(42bv32); [L2175] FCALL call #t~string148 := #Ultimate.alloc(32bv32); [L2189] FCALL call #t~string149 := #Ultimate.alloc(21bv32); [L2211] FCALL call #t~string193 := #Ultimate.alloc(37bv32); [L2218] FCALL call #t~string195 := #Ultimate.alloc(10bv32); [L2220] FCALL call #t~string198 := #Ultimate.alloc(50bv32); [L2226] FCALL call #t~string200 := #Ultimate.alloc(32bv32); [L2323] FCALL call #t~string222 := #Ultimate.alloc(10bv32); [L1713] ~ldv_irq_1_2~0 := 0bv32; [L1714] ~LDV_IN_INTERRUPT~0 := 1bv32; [L1715] ~ldv_irq_1_3~0 := 0bv32; [L1717] ~ldv_irq_data_1_1~0 := { base: 0bv32, offset: 0bv32 }; [L1718] ~ldv_irq_1_1~0 := 0bv32; [L1719] ~ldv_irq_1_0~0 := 0bv32; [L1720] ~ldv_irq_line_1_3~0 := 0bv32; [L1721] ~ldv_irq_data_1_0~0 := { base: 0bv32, offset: 0bv32 }; [L1722] ~ldv_state_variable_0~0 := 0bv32; [L1724] ~ldv_state_variable_3~0 := 0bv32; [L1725] ~ldv_irq_line_1_0~0 := 0bv32; [L1726] ~ldv_state_variable_2~0 := 0bv32; [L1727] ~ldv_irq_data_1_3~0 := { base: 0bv32, offset: 0bv32 }; [L1728] ~ref_cnt~0 := 0bv32; [L1729] ~ldv_irq_line_1_1~0 := 0bv32; [L1731] ~ldv_irq_data_1_2~0 := { base: 0bv32, offset: 0bv32 }; [L1732] ~ldv_state_variable_1~0 := 0bv32; [L1733] ~ldv_irq_line_1_2~0 := 0bv32; [L2342] ~ldv_retval_2~0 := 0bv32; [L2343] ~ldv_retval_0~0 := 0bv32; [L2345] ~ldv_retval_1~0 := 0bv32; [L2943] ~ldv_init~0 := 0bv32; [L1716] ~tegra_rtc_driver_group0~0 := { base: 0bv32, offset: 0bv32 }; [L1723] ~tegra_rtc_ops_group1~0 := { base: 0bv32, offset: 0bv32 }; [L1730] ~tegra_rtc_ops_group0~0 := { base: 0bv32, offset: 0bv32 }; [L1734] ~tegra_rtc_ops_group2~0 := { base: 0bv32, offset: 0bv32 }; [L2123-L2125] FCALL call ~#tegra_rtc_ops~0 := #Ultimate.alloc(88bv32); [L2123-L2125] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_ops~0!base, offset: ~#tegra_rtc_ops~0!offset }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(8bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(16bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_read_time, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(24bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_set_time, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(32bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_read_alarm, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(40bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_set_alarm, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(48bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_proc, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(56bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(64bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(72bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_alarm_irq_enable, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(80bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2322-L2323] FCALL call ~#tegra_rtc_driver~0 := #Ultimate.alloc(153bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~#tegra_rtc_driver~0!offset }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_remove, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(8bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_shutdown, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(16bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_suspend, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(24bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_resume, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(32bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$(#t~string222, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(40bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(48bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$(~#__this_module~0, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(56bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(64bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~intINTTYPE1(0bv8, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(72bv32, ~#tegra_rtc_driver~0!offset) }, 1bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(73bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(81bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(89bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(97bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(105bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(113bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(121bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(129bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(137bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(145bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(#NULL!base)=0bv32, old(#NULL!offset)=0bv32, old(#t~string125!base)=0bv32, old(#t~string125!offset)=0bv32, old(#t~string134!base)=0bv32, old(#t~string134!offset)=0bv32, old(#t~string140!base)=0bv32, old(#t~string140!offset)=0bv32, old(#t~string148!base)=0bv32, old(#t~string148!offset)=0bv32, old(#t~string149!base)=0bv32, old(#t~string149!offset)=0bv32, old(#t~string193!base)=0bv32, old(#t~string193!offset)=0bv32, old(#t~string195!base)=0bv32, old(#t~string195!offset)=0bv32, old(#t~string198!base)=0bv32, old(#t~string198!offset)=0bv32, old(#t~string200!base)=0bv32, old(#t~string200!offset)=0bv32, old(#t~string222!base)=0bv32, old(#t~string222!offset)=0bv32, old(#t~string90!base)=0bv32, old(#t~string90!offset)=0bv32, old(~#tegra_rtc_driver~0!base)=0bv32, old(~#tegra_rtc_driver~0!offset)=0bv32, old(~#tegra_rtc_ops~0!base)=0bv32, old(~#tegra_rtc_ops~0!offset)=0bv32, old(~LDV_IN_INTERRUPT~0)=0bv32, old(~ldv_init~0)=0bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_irq_data_1_0~0!base)=0bv32, old(~ldv_irq_data_1_0~0!offset)=0bv32, old(~ldv_irq_data_1_1~0!base)=0bv32, old(~ldv_irq_data_1_1~0!offset)=0bv32, old(~ldv_irq_data_1_2~0!base)=0bv32, old(~ldv_irq_data_1_2~0!offset)=0bv32, old(~ldv_irq_data_1_3~0!base)=0bv32, old(~ldv_irq_data_1_3~0!offset)=0bv32, old(~ldv_irq_line_1_0~0)=0bv32, old(~ldv_irq_line_1_1~0)=0bv32, old(~ldv_irq_line_1_2~0)=0bv32, old(~ldv_irq_line_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, old(~tegra_rtc_ops_group0~0!base)=0bv32, old(~tegra_rtc_ops_group0~0!offset)=0bv32, old(~tegra_rtc_ops_group1~0!base)=0bv32, old(~tegra_rtc_ops_group1~0!offset)=0bv32, old(~tegra_rtc_ops_group2~0!base)=0bv32, old(~tegra_rtc_ops_group2~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] RET call ULTIMATE.init(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] CALL call #t~ret277 := main(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2518] havoc ~ldvarg1~0; [L2519] havoc ~tmp~27; [L2520] havoc ~ldvarg0~0; [L2521] havoc ~tmp___0~8; [L2522] FCALL call ~#ldvarg2~0 := #Ultimate.alloc(4bv32); [L2523] havoc ~tmp___1~5; [L2524] havoc ~tmp___2~1; [L2525] havoc ~tmp___3~1; [L2526] havoc ~tmp___4~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2529] CALL call #t~ret237 := ldv_zalloc(136bv32); VAL [#in~size=136bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L1633-L1650] ~size := #in~size; [L1635] havoc ~p~1; [L1636] havoc ~tmp~1; [L1637] havoc ~tmp___0~1; [L1640] ~tmp___0~1 := #t~nondet12; [L1640] havoc #t~nondet12; VAL [#in~size=136bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~size=136bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~1=1bv32] [L1641] COND TRUE 0bv32 != ~tmp___0~1 [L1642] #res := { base: 0bv32, offset: 0bv32 }; VAL [#in~size=136bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #res!base=0bv32, #res!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~size=136bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~1=1bv32] [L2529] RET call #t~ret237 := ldv_zalloc(136bv32); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~ret237!base=0bv32, #t~ret237!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2529] ~tmp~27 := #t~ret237; [L2529] havoc #t~ret237; [L2530] ~ldvarg1~0 := ~tmp~27; [L2531] ~tmp___0~8 := #t~nondet238; [L2531] havoc #t~nondet238; [L2532] ~ldvarg0~0 := ~tmp___0~8; [L2533] FCALL call ldv_initialize(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2534] CALL call #t~memset~res239 := #Ultimate.C_memset(~#ldvarg2~0, 0bv32, 4bv32); VAL [#amount=4bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #ptr!base=67108864bv32, #ptr!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] #t~loopctr278 := 0bv32; VAL [#amount=4bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #ptr!base=67108864bv32, #ptr!offset=0bv32, #t~loopctr278=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] COND TRUE ~bvslt32(#t~loopctr278, #amount) [?] #memory_$Pointer$[{ base: #ptr!base, offset: ~bvadd32(#ptr!offset, #t~loopctr278) }] := { base: 0bv32, offset: ~zero_extendFrom8To32(#value[8:0]) }; [?] #memory_int[{ base: #ptr!base, offset: ~bvadd32(#ptr!offset, #t~loopctr278) }] := ~zero_extendFrom8To32(#value[8:0]); [?] #t~loopctr278 := ~bvadd32(1bv32, #t~loopctr278); VAL [#amount=4bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #ptr!base=67108864bv32, #ptr!offset=0bv32, #t~loopctr278=1bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] COND TRUE ~bvslt32(#t~loopctr278, #amount) [?] #memory_$Pointer$[{ base: #ptr!base, offset: ~bvadd32(#ptr!offset, #t~loopctr278) }] := { base: 0bv32, offset: ~zero_extendFrom8To32(#value[8:0]) }; [?] #memory_int[{ base: #ptr!base, offset: ~bvadd32(#ptr!offset, #t~loopctr278) }] := ~zero_extendFrom8To32(#value[8:0]); [?] #t~loopctr278 := ~bvadd32(1bv32, #t~loopctr278); VAL [#amount=4bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #ptr!base=67108864bv32, #ptr!offset=0bv32, #t~loopctr278=2bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] COND TRUE ~bvslt32(#t~loopctr278, #amount) [?] #memory_$Pointer$[{ base: #ptr!base, offset: ~bvadd32(#ptr!offset, #t~loopctr278) }] := { base: 0bv32, offset: ~zero_extendFrom8To32(#value[8:0]) }; [?] #memory_int[{ base: #ptr!base, offset: ~bvadd32(#ptr!offset, #t~loopctr278) }] := ~zero_extendFrom8To32(#value[8:0]); [?] #t~loopctr278 := ~bvadd32(1bv32, #t~loopctr278); VAL [#amount=4bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #ptr!base=67108864bv32, #ptr!offset=0bv32, #t~loopctr278=3bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] COND TRUE ~bvslt32(#t~loopctr278, #amount) [?] #memory_$Pointer$[{ base: #ptr!base, offset: ~bvadd32(#ptr!offset, #t~loopctr278) }] := { base: 0bv32, offset: ~zero_extendFrom8To32(#value[8:0]) }; [?] #memory_int[{ base: #ptr!base, offset: ~bvadd32(#ptr!offset, #t~loopctr278) }] := ~zero_extendFrom8To32(#value[8:0]); [?] #t~loopctr278 := ~bvadd32(1bv32, #t~loopctr278); VAL [#amount=4bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #ptr!base=67108864bv32, #ptr!offset=0bv32, #t~loopctr278=4bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] COND FALSE !(~bvslt32(#t~loopctr278, #amount)) VAL [#amount=4bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #ptr!base=67108864bv32, #ptr!offset=0bv32, #t~loopctr278=4bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2534] RET call #t~memset~res239 := #Ultimate.C_memset(~#ldvarg2~0, 0bv32, 4bv32); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~memset~res239!base=67108864bv32, #t~memset~res239!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2534] havoc #t~memset~res239; [L2535] ~ldv_state_variable_1~0 := 1bv32; [L2536] ~ref_cnt~0 := 0bv32; [L2537] ~ldv_state_variable_0~0 := 1bv32; [L2538] ~ldv_state_variable_3~0 := 0bv32; [L2539] ~ldv_state_variable_2~0 := 0bv32; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2541] ~tmp___1~5 := #t~nondet240; [L2541] havoc #t~nondet240; [L2543] #t~switch241 := 0bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND FALSE !(#t~switch241) [L2550] #t~switch241 := #t~switch241 || 1bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND TRUE #t~switch241 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2551] COND TRUE 0bv32 != ~ldv_state_variable_0~0 [L2552] ~tmp___2~1 := #t~nondet242; [L2552] havoc #t~nondet242; [L2554] #t~switch243 := 0bv32 == ~tmp___2~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2553-L2585] COND FALSE !(#t~switch243) [L2563] #t~switch243 := #t~switch243 || 1bv32 == ~tmp___2~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2553-L2585] COND TRUE #t~switch243 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2564] COND TRUE 1bv32 == ~ldv_state_variable_0~0 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2565] CALL call #t~ret244 := tegra_rtc_init(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2326] havoc ~tmp~22; [L2329] FCALL call #t~ret223 := platform_driver_probe(~#tegra_rtc_driver~0, #funAddr~tegra_rtc_probe); [L2329] ~tmp~22 := #t~ret223; [L2329] havoc #t~ret223; [L2330] #res := ~tmp~22; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #res=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~22=0bv32] [L2565] RET call #t~ret244 := tegra_rtc_init(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~ret244=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2565] ~ldv_retval_0~0 := #t~ret244; [L2565] havoc #t~ret244; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2566] COND TRUE 0bv32 == ~ldv_retval_0~0 [L2567] ~ldv_state_variable_0~0 := 3bv32; [L2568] ~ldv_state_variable_2~0 := 1bv32; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2569] CALL call ldv_initialize_platform_driver_2(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2476] havoc ~tmp~26; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2479] CALL call #t~ret236 := ldv_zalloc(624bv32); VAL [#in~size=624bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L1633-L1650] ~size := #in~size; [L1635] havoc ~p~1; [L1636] havoc ~tmp~1; [L1637] havoc ~tmp___0~1; [L1640] ~tmp___0~1 := #t~nondet12; [L1640] havoc #t~nondet12; VAL [#in~size=624bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~size=624bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~1=1bv32] [L1641] COND TRUE 0bv32 != ~tmp___0~1 [L1642] #res := { base: 0bv32, offset: 0bv32 }; VAL [#in~size=624bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #res!base=0bv32, #res!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~size=624bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~1=1bv32] [L2479] RET call #t~ret236 := ldv_zalloc(624bv32); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~ret236!base=0bv32, #t~ret236!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2479] ~tmp~26 := #t~ret236; [L2479] havoc #t~ret236; [L2480] ~tegra_rtc_driver_group0~0 := ~tmp~26; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~26!base=0bv32, ~tmp~26!offset=0bv32] [L2569] RET call ldv_initialize_platform_driver_2(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2573] COND FALSE !(0bv32 != ~ldv_retval_0~0) VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2541] ~tmp___1~5 := #t~nondet240; [L2541] havoc #t~nondet240; [L2543] #t~switch241 := 0bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=false, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND FALSE !(#t~switch241) [L2550] #t~switch241 := #t~switch241 || 1bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=false, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND FALSE !(#t~switch241) [L2591] #t~switch241 := #t~switch241 || 2bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=false, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND FALSE !(#t~switch241) [L2699] #t~switch241 := #t~switch241 || 3bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND TRUE #t~switch241 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2700] COND TRUE 0bv32 != ~ldv_state_variable_2~0 [L2701] ~tmp___4~1 := #t~nondet260; [L2701] havoc #t~nondet260; [L2703] #t~switch261 := 0bv32 == ~tmp___4~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2702-L2775] COND FALSE !(#t~switch261) [L2717] #t~switch261 := #t~switch261 || 1bv32 == ~tmp___4~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2702-L2775] COND FALSE !(#t~switch261) [L2729] #t~switch261 := #t~switch261 || 2bv32 == ~tmp___4~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2702-L2775] COND FALSE !(#t~switch261) [L2752] #t~switch261 := #t~switch261 || 3bv32 == ~tmp___4~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2702-L2775] COND FALSE !(#t~switch261) [L2764] #t~switch261 := #t~switch261 || 4bv32 == ~tmp___4~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2702-L2775] COND TRUE #t~switch261 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2765] COND TRUE 1bv32 == ~ldv_state_variable_2~0 [L2766] FCALL call #t~ret268 := ldv_probe_2(); [L2766] havoc #t~ret268; [L2767] ~ldv_state_variable_2~0 := 2bv32; [L2768] ~ref_cnt~0 := ~bvadd32(1bv32, ~ref_cnt~0); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2541] ~tmp___1~5 := #t~nondet240; [L2541] havoc #t~nondet240; [L2543] #t~switch241 := 0bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=false, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND FALSE !(#t~switch241) [L2550] #t~switch241 := #t~switch241 || 1bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=false, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND FALSE !(#t~switch241) [L2591] #t~switch241 := #t~switch241 || 2bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=false, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND FALSE !(#t~switch241) [L2699] #t~switch241 := #t~switch241 || 3bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND TRUE #t~switch241 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2700] COND TRUE 0bv32 != ~ldv_state_variable_2~0 [L2701] ~tmp___4~1 := #t~nondet260; [L2701] havoc #t~nondet260; [L2703] #t~switch261 := 0bv32 == ~tmp___4~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=0bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2702-L2775] COND TRUE #t~switch261 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=0bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2704] COND FALSE !(4bv32 == ~ldv_state_variable_2~0) VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=0bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2710] COND TRUE 2bv32 == ~ldv_state_variable_2~0 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=0bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2711] CALL call tegra_rtc_shutdown(~tegra_rtc_driver_group0~0); VAL [#in~pdev!base=0bv32, #in~pdev!offset=0bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2313-L2321] ~pdev := #in~pdev; VAL [#in~pdev!base=0bv32, #in~pdev!offset=0bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~pdev!base=0bv32, ~pdev!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2318] CALL call #t~ret221 := tegra_rtc_alarm_irq_enable({ base: ~pdev!base, offset: ~bvadd32(12bv32, ~pdev!offset) }, 0bv32); VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #in~enabled=0bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2004-L2033] ~dev := #in~dev; [L2004-L2033] ~enabled := #in~enabled; [L2006] havoc ~info~4; [L2007] havoc ~tmp~14; [L2008] havoc ~status~0; [L2009] havoc ~sl_irq_flags~1; [L2010] havoc ~__v~3; [L2011] havoc ~__v___0~3; [L2014] FCALL call #t~ret107 := dev_get_drvdata(~dev); [L2014] ~tmp~14 := #t~ret107; [L2014] havoc #t~ret107; [L2015] ~info~4 := ~tmp~14; VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #in~enabled=0bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~enabled=0bv32, ~info~4!base=0bv32, ~info~4!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~14!base=0bv32, ~tmp~14!offset=0bv32] [L2016] CALL call #t~ret108 := tegra_rtc_wait_while_busy(~dev); VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L1873-L1908] ~dev := #in~dev; [L1875] havoc ~info~0; [L1876] havoc ~tmp~10; [L1877] havoc ~retries~0; [L1878] havoc ~tmp___0~2; [L1879] havoc ~tmp___1~0; [L1882] FCALL call #t~ret87 := dev_get_drvdata(~dev); [L1882] ~tmp~10 := #t~ret87; [L1882] havoc #t~ret87; [L1883] ~info~0 := ~tmp~10; [L1884] ~retries~0 := 500bv32; VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~info~0!base=67108865bv32, ~info~0!offset=4294967283bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~retries~0=500bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~10!base=67108865bv32, ~tmp~10!offset=4294967283bv32] [L1896] CALL call #t~ret88 := tegra_rtc_check_busy(~info~0); VAL [#in~info!base=67108865bv32, #in~info!offset=4294967283bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L1861-L1872] ~info := #in~info; [L1863] havoc ~__v~0; [L1864] havoc ~__v___0~0; [L1867] FCALL call #t~mem85 := read~$Pointer$({ base: ~info!base, offset: ~bvadd32(16bv32, ~info!offset) }, 8bv32); [L1867] FCALL call #t~mem86 := read~intINTTYPE4({ base: #t~mem85!base, offset: ~bvadd32(16bv32, #t~mem85!offset) }, 4bv32); [L1867] ~__v___0~0 := #t~mem86; [L1867] havoc #t~mem85; [L1867] havoc #t~mem86; [L1868] ~__v~0 := ~__v___0~0; [L1870] #res := ~bvand32(1bv32, ~__v~0); VAL [#in~info!base=67108865bv32, #in~info!offset=4294967283bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #res=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~__v___0~0=0bv32, ~__v~0=0bv32, ~info!base=67108865bv32, ~info!offset=4294967283bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L1896] RET call #t~ret88 := tegra_rtc_check_busy(~info~0); VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~ret88=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~info~0!base=67108865bv32, ~info~0!offset=4294967283bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~retries~0=500bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~10!base=67108865bv32, ~tmp~10!offset=4294967283bv32] [L1896] ~tmp___1~0 := #t~ret88; [L1896] havoc #t~ret88; VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~info~0!base=67108865bv32, ~info~0!offset=4294967283bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~retries~0=500bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___1~0=0bv32, ~tmp~10!base=67108865bv32, ~tmp~10!offset=4294967283bv32] [L1897] COND FALSE !(0bv32 != ~tmp___1~0) [L1903] #res := 0bv32; VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #res=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~info~0!base=67108865bv32, ~info~0!offset=4294967283bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~retries~0=500bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___1~0=0bv32, ~tmp~10!base=67108865bv32, ~tmp~10!offset=4294967283bv32] [L2016] RET call #t~ret108 := tegra_rtc_wait_while_busy(~dev); VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #in~enabled=0bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~ret108=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~enabled=0bv32, ~info~4!base=0bv32, ~info~4!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~14!base=0bv32, ~tmp~14!offset=0bv32] [L2016] havoc #t~ret108; VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #in~enabled=0bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~enabled=0bv32, ~info~4!base=0bv32, ~info~4!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~14!base=0bv32, ~tmp~14!offset=0bv32] [L2017] CALL call ldv_spin_lock_check(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2962] COND FALSE !(1bv32 == ~ldv_init~0) VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2965] CALL call ldv_error(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L1684] assert false; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] CALL call ULTIMATE.init(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=0bv32, #t~string125!offset=0bv32, #t~string134!base=0bv32, #t~string134!offset=0bv32, #t~string140!base=0bv32, #t~string140!offset=0bv32, #t~string148!base=0bv32, #t~string148!offset=0bv32, #t~string149!base=0bv32, #t~string149!offset=0bv32, #t~string193!base=0bv32, #t~string193!offset=0bv32, #t~string195!base=0bv32, #t~string195!offset=0bv32, #t~string198!base=0bv32, #t~string198!offset=0bv32, #t~string200!base=0bv32, #t~string200!offset=0bv32, #t~string222!base=0bv32, #t~string222!offset=0bv32, #t~string90!base=0bv32, #t~string90!offset=0bv32, old(#NULL!base)=0bv32, old(#NULL!offset)=0bv32, old(#t~string125!base)=0bv32, old(#t~string125!offset)=0bv32, old(#t~string134!base)=0bv32, old(#t~string134!offset)=0bv32, old(#t~string140!base)=0bv32, old(#t~string140!offset)=0bv32, old(#t~string148!base)=0bv32, old(#t~string148!offset)=0bv32, old(#t~string149!base)=0bv32, old(#t~string149!offset)=0bv32, old(#t~string193!base)=0bv32, old(#t~string193!offset)=0bv32, old(#t~string195!base)=0bv32, old(#t~string195!offset)=0bv32, old(#t~string198!base)=0bv32, old(#t~string198!offset)=0bv32, old(#t~string200!base)=0bv32, old(#t~string200!offset)=0bv32, old(#t~string222!base)=0bv32, old(#t~string222!offset)=0bv32, old(#t~string90!base)=0bv32, old(#t~string90!offset)=0bv32, old(~#tegra_rtc_driver~0!base)=0bv32, old(~#tegra_rtc_driver~0!offset)=0bv32, old(~#tegra_rtc_ops~0!base)=0bv32, old(~#tegra_rtc_ops~0!offset)=0bv32, old(~LDV_IN_INTERRUPT~0)=0bv32, old(~ldv_init~0)=0bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_irq_data_1_0~0!base)=0bv32, old(~ldv_irq_data_1_0~0!offset)=0bv32, old(~ldv_irq_data_1_1~0!base)=0bv32, old(~ldv_irq_data_1_1~0!offset)=0bv32, old(~ldv_irq_data_1_2~0!base)=0bv32, old(~ldv_irq_data_1_2~0!offset)=0bv32, old(~ldv_irq_data_1_3~0!base)=0bv32, old(~ldv_irq_data_1_3~0!offset)=0bv32, old(~ldv_irq_line_1_0~0)=0bv32, old(~ldv_irq_line_1_1~0)=0bv32, old(~ldv_irq_line_1_2~0)=0bv32, old(~ldv_irq_line_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, old(~tegra_rtc_ops_group0~0!base)=0bv32, old(~tegra_rtc_ops_group0~0!offset)=0bv32, old(~tegra_rtc_ops_group1~0!base)=0bv32, old(~tegra_rtc_ops_group1~0!offset)=0bv32, old(~tegra_rtc_ops_group2~0!base)=0bv32, old(~tegra_rtc_ops_group2~0!offset)=0bv32, ~#tegra_rtc_driver~0!base=0bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=0bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=0bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] #NULL := { base: 0bv32, offset: 0bv32 }; [?] #valid[0bv32] := 0bv1; [L1905] FCALL call #t~string90 := #Ultimate.alloc(36bv32); [L2072] FCALL call #t~string125 := #Ultimate.alloc(12bv32); [L2150] FCALL call #t~string134 := #Ultimate.alloc(42bv32); [L2159] FCALL call #t~string140 := #Ultimate.alloc(42bv32); [L2175] FCALL call #t~string148 := #Ultimate.alloc(32bv32); [L2189] FCALL call #t~string149 := #Ultimate.alloc(21bv32); [L2211] FCALL call #t~string193 := #Ultimate.alloc(37bv32); [L2218] FCALL call #t~string195 := #Ultimate.alloc(10bv32); [L2220] FCALL call #t~string198 := #Ultimate.alloc(50bv32); [L2226] FCALL call #t~string200 := #Ultimate.alloc(32bv32); [L2323] FCALL call #t~string222 := #Ultimate.alloc(10bv32); [L1713] ~ldv_irq_1_2~0 := 0bv32; [L1714] ~LDV_IN_INTERRUPT~0 := 1bv32; [L1715] ~ldv_irq_1_3~0 := 0bv32; [L1717] ~ldv_irq_data_1_1~0 := { base: 0bv32, offset: 0bv32 }; [L1718] ~ldv_irq_1_1~0 := 0bv32; [L1719] ~ldv_irq_1_0~0 := 0bv32; [L1720] ~ldv_irq_line_1_3~0 := 0bv32; [L1721] ~ldv_irq_data_1_0~0 := { base: 0bv32, offset: 0bv32 }; [L1722] ~ldv_state_variable_0~0 := 0bv32; [L1724] ~ldv_state_variable_3~0 := 0bv32; [L1725] ~ldv_irq_line_1_0~0 := 0bv32; [L1726] ~ldv_state_variable_2~0 := 0bv32; [L1727] ~ldv_irq_data_1_3~0 := { base: 0bv32, offset: 0bv32 }; [L1728] ~ref_cnt~0 := 0bv32; [L1729] ~ldv_irq_line_1_1~0 := 0bv32; [L1731] ~ldv_irq_data_1_2~0 := { base: 0bv32, offset: 0bv32 }; [L1732] ~ldv_state_variable_1~0 := 0bv32; [L1733] ~ldv_irq_line_1_2~0 := 0bv32; [L2342] ~ldv_retval_2~0 := 0bv32; [L2343] ~ldv_retval_0~0 := 0bv32; [L2345] ~ldv_retval_1~0 := 0bv32; [L2943] ~ldv_init~0 := 0bv32; [L1716] ~tegra_rtc_driver_group0~0 := { base: 0bv32, offset: 0bv32 }; [L1723] ~tegra_rtc_ops_group1~0 := { base: 0bv32, offset: 0bv32 }; [L1730] ~tegra_rtc_ops_group0~0 := { base: 0bv32, offset: 0bv32 }; [L1734] ~tegra_rtc_ops_group2~0 := { base: 0bv32, offset: 0bv32 }; [L2123-L2125] FCALL call ~#tegra_rtc_ops~0 := #Ultimate.alloc(88bv32); [L2123-L2125] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_ops~0!base, offset: ~#tegra_rtc_ops~0!offset }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(8bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(16bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_read_time, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(24bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_set_time, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(32bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_read_alarm, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(40bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_set_alarm, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(48bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_proc, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(56bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(64bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(72bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_alarm_irq_enable, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(80bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2322-L2323] FCALL call ~#tegra_rtc_driver~0 := #Ultimate.alloc(153bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~#tegra_rtc_driver~0!offset }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_remove, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(8bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_shutdown, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(16bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_suspend, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(24bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_resume, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(32bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$(#t~string222, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(40bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(48bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$(~#__this_module~0, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(56bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(64bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~intINTTYPE1(0bv8, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(72bv32, ~#tegra_rtc_driver~0!offset) }, 1bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(73bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(81bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(89bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(97bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(105bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(113bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(121bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(129bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(137bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(145bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(#NULL!base)=0bv32, old(#NULL!offset)=0bv32, old(#t~string125!base)=0bv32, old(#t~string125!offset)=0bv32, old(#t~string134!base)=0bv32, old(#t~string134!offset)=0bv32, old(#t~string140!base)=0bv32, old(#t~string140!offset)=0bv32, old(#t~string148!base)=0bv32, old(#t~string148!offset)=0bv32, old(#t~string149!base)=0bv32, old(#t~string149!offset)=0bv32, old(#t~string193!base)=0bv32, old(#t~string193!offset)=0bv32, old(#t~string195!base)=0bv32, old(#t~string195!offset)=0bv32, old(#t~string198!base)=0bv32, old(#t~string198!offset)=0bv32, old(#t~string200!base)=0bv32, old(#t~string200!offset)=0bv32, old(#t~string222!base)=0bv32, old(#t~string222!offset)=0bv32, old(#t~string90!base)=0bv32, old(#t~string90!offset)=0bv32, old(~#tegra_rtc_driver~0!base)=0bv32, old(~#tegra_rtc_driver~0!offset)=0bv32, old(~#tegra_rtc_ops~0!base)=0bv32, old(~#tegra_rtc_ops~0!offset)=0bv32, old(~LDV_IN_INTERRUPT~0)=0bv32, old(~ldv_init~0)=0bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_irq_data_1_0~0!base)=0bv32, old(~ldv_irq_data_1_0~0!offset)=0bv32, old(~ldv_irq_data_1_1~0!base)=0bv32, old(~ldv_irq_data_1_1~0!offset)=0bv32, old(~ldv_irq_data_1_2~0!base)=0bv32, old(~ldv_irq_data_1_2~0!offset)=0bv32, old(~ldv_irq_data_1_3~0!base)=0bv32, old(~ldv_irq_data_1_3~0!offset)=0bv32, old(~ldv_irq_line_1_0~0)=0bv32, old(~ldv_irq_line_1_1~0)=0bv32, old(~ldv_irq_line_1_2~0)=0bv32, old(~ldv_irq_line_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, old(~tegra_rtc_ops_group0~0!base)=0bv32, old(~tegra_rtc_ops_group0~0!offset)=0bv32, old(~tegra_rtc_ops_group1~0!base)=0bv32, old(~tegra_rtc_ops_group1~0!offset)=0bv32, old(~tegra_rtc_ops_group2~0!base)=0bv32, old(~tegra_rtc_ops_group2~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] RET call ULTIMATE.init(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] CALL call #t~ret277 := main(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2518] havoc ~ldvarg1~0; [L2519] havoc ~tmp~27; [L2520] havoc ~ldvarg0~0; [L2521] havoc ~tmp___0~8; [L2522] FCALL call ~#ldvarg2~0 := #Ultimate.alloc(4bv32); [L2523] havoc ~tmp___1~5; [L2524] havoc ~tmp___2~1; [L2525] havoc ~tmp___3~1; [L2526] havoc ~tmp___4~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2529] CALL call #t~ret237 := ldv_zalloc(136bv32); VAL [#in~size=136bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L1633-L1650] ~size := #in~size; [L1635] havoc ~p~1; [L1636] havoc ~tmp~1; [L1637] havoc ~tmp___0~1; [L1640] ~tmp___0~1 := #t~nondet12; [L1640] havoc #t~nondet12; VAL [#in~size=136bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~size=136bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~1=1bv32] [L1641] COND TRUE 0bv32 != ~tmp___0~1 [L1642] #res := { base: 0bv32, offset: 0bv32 }; VAL [#in~size=136bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #res!base=0bv32, #res!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~size=136bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~1=1bv32] [L2529] RET call #t~ret237 := ldv_zalloc(136bv32); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~ret237!base=0bv32, #t~ret237!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2529] ~tmp~27 := #t~ret237; [L2529] havoc #t~ret237; [L2530] ~ldvarg1~0 := ~tmp~27; [L2531] ~tmp___0~8 := #t~nondet238; [L2531] havoc #t~nondet238; [L2532] ~ldvarg0~0 := ~tmp___0~8; [L2533] FCALL call ldv_initialize(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2534] CALL call #t~memset~res239 := #Ultimate.C_memset(~#ldvarg2~0, 0bv32, 4bv32); VAL [#amount=4bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #ptr!base=67108864bv32, #ptr!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] #t~loopctr278 := 0bv32; VAL [#amount=4bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #ptr!base=67108864bv32, #ptr!offset=0bv32, #t~loopctr278=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] COND TRUE ~bvslt32(#t~loopctr278, #amount) [?] #memory_$Pointer$[{ base: #ptr!base, offset: ~bvadd32(#ptr!offset, #t~loopctr278) }] := { base: 0bv32, offset: ~zero_extendFrom8To32(#value[8:0]) }; [?] #memory_int[{ base: #ptr!base, offset: ~bvadd32(#ptr!offset, #t~loopctr278) }] := ~zero_extendFrom8To32(#value[8:0]); [?] #t~loopctr278 := ~bvadd32(1bv32, #t~loopctr278); VAL [#amount=4bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #ptr!base=67108864bv32, #ptr!offset=0bv32, #t~loopctr278=1bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] COND TRUE ~bvslt32(#t~loopctr278, #amount) [?] #memory_$Pointer$[{ base: #ptr!base, offset: ~bvadd32(#ptr!offset, #t~loopctr278) }] := { base: 0bv32, offset: ~zero_extendFrom8To32(#value[8:0]) }; [?] #memory_int[{ base: #ptr!base, offset: ~bvadd32(#ptr!offset, #t~loopctr278) }] := ~zero_extendFrom8To32(#value[8:0]); [?] #t~loopctr278 := ~bvadd32(1bv32, #t~loopctr278); VAL [#amount=4bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #ptr!base=67108864bv32, #ptr!offset=0bv32, #t~loopctr278=2bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] COND TRUE ~bvslt32(#t~loopctr278, #amount) [?] #memory_$Pointer$[{ base: #ptr!base, offset: ~bvadd32(#ptr!offset, #t~loopctr278) }] := { base: 0bv32, offset: ~zero_extendFrom8To32(#value[8:0]) }; [?] #memory_int[{ base: #ptr!base, offset: ~bvadd32(#ptr!offset, #t~loopctr278) }] := ~zero_extendFrom8To32(#value[8:0]); [?] #t~loopctr278 := ~bvadd32(1bv32, #t~loopctr278); VAL [#amount=4bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #ptr!base=67108864bv32, #ptr!offset=0bv32, #t~loopctr278=3bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] COND TRUE ~bvslt32(#t~loopctr278, #amount) [?] #memory_$Pointer$[{ base: #ptr!base, offset: ~bvadd32(#ptr!offset, #t~loopctr278) }] := { base: 0bv32, offset: ~zero_extendFrom8To32(#value[8:0]) }; [?] #memory_int[{ base: #ptr!base, offset: ~bvadd32(#ptr!offset, #t~loopctr278) }] := ~zero_extendFrom8To32(#value[8:0]); [?] #t~loopctr278 := ~bvadd32(1bv32, #t~loopctr278); VAL [#amount=4bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #ptr!base=67108864bv32, #ptr!offset=0bv32, #t~loopctr278=4bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] COND FALSE !(~bvslt32(#t~loopctr278, #amount)) VAL [#amount=4bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #ptr!base=67108864bv32, #ptr!offset=0bv32, #t~loopctr278=4bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2534] RET call #t~memset~res239 := #Ultimate.C_memset(~#ldvarg2~0, 0bv32, 4bv32); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~memset~res239!base=67108864bv32, #t~memset~res239!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2534] havoc #t~memset~res239; [L2535] ~ldv_state_variable_1~0 := 1bv32; [L2536] ~ref_cnt~0 := 0bv32; [L2537] ~ldv_state_variable_0~0 := 1bv32; [L2538] ~ldv_state_variable_3~0 := 0bv32; [L2539] ~ldv_state_variable_2~0 := 0bv32; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2541] ~tmp___1~5 := #t~nondet240; [L2541] havoc #t~nondet240; [L2543] #t~switch241 := 0bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND FALSE !(#t~switch241) [L2550] #t~switch241 := #t~switch241 || 1bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND TRUE #t~switch241 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2551] COND TRUE 0bv32 != ~ldv_state_variable_0~0 [L2552] ~tmp___2~1 := #t~nondet242; [L2552] havoc #t~nondet242; [L2554] #t~switch243 := 0bv32 == ~tmp___2~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2553-L2585] COND FALSE !(#t~switch243) [L2563] #t~switch243 := #t~switch243 || 1bv32 == ~tmp___2~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2553-L2585] COND TRUE #t~switch243 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2564] COND TRUE 1bv32 == ~ldv_state_variable_0~0 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2565] CALL call #t~ret244 := tegra_rtc_init(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2326] havoc ~tmp~22; [L2329] FCALL call #t~ret223 := platform_driver_probe(~#tegra_rtc_driver~0, #funAddr~tegra_rtc_probe); [L2329] ~tmp~22 := #t~ret223; [L2329] havoc #t~ret223; [L2330] #res := ~tmp~22; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #res=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~22=0bv32] [L2565] RET call #t~ret244 := tegra_rtc_init(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~ret244=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2565] ~ldv_retval_0~0 := #t~ret244; [L2565] havoc #t~ret244; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2566] COND TRUE 0bv32 == ~ldv_retval_0~0 [L2567] ~ldv_state_variable_0~0 := 3bv32; [L2568] ~ldv_state_variable_2~0 := 1bv32; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2569] CALL call ldv_initialize_platform_driver_2(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2476] havoc ~tmp~26; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2479] CALL call #t~ret236 := ldv_zalloc(624bv32); VAL [#in~size=624bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L1633-L1650] ~size := #in~size; [L1635] havoc ~p~1; [L1636] havoc ~tmp~1; [L1637] havoc ~tmp___0~1; [L1640] ~tmp___0~1 := #t~nondet12; [L1640] havoc #t~nondet12; VAL [#in~size=624bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~size=624bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~1=1bv32] [L1641] COND TRUE 0bv32 != ~tmp___0~1 [L1642] #res := { base: 0bv32, offset: 0bv32 }; VAL [#in~size=624bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #res!base=0bv32, #res!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~size=624bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~1=1bv32] [L2479] RET call #t~ret236 := ldv_zalloc(624bv32); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~ret236!base=0bv32, #t~ret236!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2479] ~tmp~26 := #t~ret236; [L2479] havoc #t~ret236; [L2480] ~tegra_rtc_driver_group0~0 := ~tmp~26; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~26!base=0bv32, ~tmp~26!offset=0bv32] [L2569] RET call ldv_initialize_platform_driver_2(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2573] COND FALSE !(0bv32 != ~ldv_retval_0~0) VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2541] ~tmp___1~5 := #t~nondet240; [L2541] havoc #t~nondet240; [L2543] #t~switch241 := 0bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=false, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND FALSE !(#t~switch241) [L2550] #t~switch241 := #t~switch241 || 1bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=false, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND FALSE !(#t~switch241) [L2591] #t~switch241 := #t~switch241 || 2bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=false, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND FALSE !(#t~switch241) [L2699] #t~switch241 := #t~switch241 || 3bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND TRUE #t~switch241 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2700] COND TRUE 0bv32 != ~ldv_state_variable_2~0 [L2701] ~tmp___4~1 := #t~nondet260; [L2701] havoc #t~nondet260; [L2703] #t~switch261 := 0bv32 == ~tmp___4~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2702-L2775] COND FALSE !(#t~switch261) [L2717] #t~switch261 := #t~switch261 || 1bv32 == ~tmp___4~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2702-L2775] COND FALSE !(#t~switch261) [L2729] #t~switch261 := #t~switch261 || 2bv32 == ~tmp___4~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2702-L2775] COND FALSE !(#t~switch261) [L2752] #t~switch261 := #t~switch261 || 3bv32 == ~tmp___4~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2702-L2775] COND FALSE !(#t~switch261) [L2764] #t~switch261 := #t~switch261 || 4bv32 == ~tmp___4~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2702-L2775] COND TRUE #t~switch261 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2765] COND TRUE 1bv32 == ~ldv_state_variable_2~0 [L2766] FCALL call #t~ret268 := ldv_probe_2(); [L2766] havoc #t~ret268; [L2767] ~ldv_state_variable_2~0 := 2bv32; [L2768] ~ref_cnt~0 := ~bvadd32(1bv32, ~ref_cnt~0); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2541] ~tmp___1~5 := #t~nondet240; [L2541] havoc #t~nondet240; [L2543] #t~switch241 := 0bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=false, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND FALSE !(#t~switch241) [L2550] #t~switch241 := #t~switch241 || 1bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=false, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND FALSE !(#t~switch241) [L2591] #t~switch241 := #t~switch241 || 2bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=false, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND FALSE !(#t~switch241) [L2699] #t~switch241 := #t~switch241 || 3bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND TRUE #t~switch241 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2700] COND TRUE 0bv32 != ~ldv_state_variable_2~0 [L2701] ~tmp___4~1 := #t~nondet260; [L2701] havoc #t~nondet260; [L2703] #t~switch261 := 0bv32 == ~tmp___4~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=0bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2702-L2775] COND TRUE #t~switch261 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=0bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2704] COND FALSE !(4bv32 == ~ldv_state_variable_2~0) VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=0bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2710] COND TRUE 2bv32 == ~ldv_state_variable_2~0 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=0bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2711] CALL call tegra_rtc_shutdown(~tegra_rtc_driver_group0~0); VAL [#in~pdev!base=0bv32, #in~pdev!offset=0bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2313-L2321] ~pdev := #in~pdev; VAL [#in~pdev!base=0bv32, #in~pdev!offset=0bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~pdev!base=0bv32, ~pdev!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2318] CALL call #t~ret221 := tegra_rtc_alarm_irq_enable({ base: ~pdev!base, offset: ~bvadd32(12bv32, ~pdev!offset) }, 0bv32); VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #in~enabled=0bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2004-L2033] ~dev := #in~dev; [L2004-L2033] ~enabled := #in~enabled; [L2006] havoc ~info~4; [L2007] havoc ~tmp~14; [L2008] havoc ~status~0; [L2009] havoc ~sl_irq_flags~1; [L2010] havoc ~__v~3; [L2011] havoc ~__v___0~3; [L2014] FCALL call #t~ret107 := dev_get_drvdata(~dev); [L2014] ~tmp~14 := #t~ret107; [L2014] havoc #t~ret107; [L2015] ~info~4 := ~tmp~14; VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #in~enabled=0bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~enabled=0bv32, ~info~4!base=0bv32, ~info~4!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~14!base=0bv32, ~tmp~14!offset=0bv32] [L2016] CALL call #t~ret108 := tegra_rtc_wait_while_busy(~dev); VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L1873-L1908] ~dev := #in~dev; [L1875] havoc ~info~0; [L1876] havoc ~tmp~10; [L1877] havoc ~retries~0; [L1878] havoc ~tmp___0~2; [L1879] havoc ~tmp___1~0; [L1882] FCALL call #t~ret87 := dev_get_drvdata(~dev); [L1882] ~tmp~10 := #t~ret87; [L1882] havoc #t~ret87; [L1883] ~info~0 := ~tmp~10; [L1884] ~retries~0 := 500bv32; VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~info~0!base=67108865bv32, ~info~0!offset=4294967283bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~retries~0=500bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~10!base=67108865bv32, ~tmp~10!offset=4294967283bv32] [L1896] CALL call #t~ret88 := tegra_rtc_check_busy(~info~0); VAL [#in~info!base=67108865bv32, #in~info!offset=4294967283bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L1861-L1872] ~info := #in~info; [L1863] havoc ~__v~0; [L1864] havoc ~__v___0~0; [L1867] FCALL call #t~mem85 := read~$Pointer$({ base: ~info!base, offset: ~bvadd32(16bv32, ~info!offset) }, 8bv32); [L1867] FCALL call #t~mem86 := read~intINTTYPE4({ base: #t~mem85!base, offset: ~bvadd32(16bv32, #t~mem85!offset) }, 4bv32); [L1867] ~__v___0~0 := #t~mem86; [L1867] havoc #t~mem85; [L1867] havoc #t~mem86; [L1868] ~__v~0 := ~__v___0~0; [L1870] #res := ~bvand32(1bv32, ~__v~0); VAL [#in~info!base=67108865bv32, #in~info!offset=4294967283bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #res=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~__v___0~0=0bv32, ~__v~0=0bv32, ~info!base=67108865bv32, ~info!offset=4294967283bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L1896] RET call #t~ret88 := tegra_rtc_check_busy(~info~0); VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~ret88=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~info~0!base=67108865bv32, ~info~0!offset=4294967283bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~retries~0=500bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~10!base=67108865bv32, ~tmp~10!offset=4294967283bv32] [L1896] ~tmp___1~0 := #t~ret88; [L1896] havoc #t~ret88; VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~info~0!base=67108865bv32, ~info~0!offset=4294967283bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~retries~0=500bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___1~0=0bv32, ~tmp~10!base=67108865bv32, ~tmp~10!offset=4294967283bv32] [L1897] COND FALSE !(0bv32 != ~tmp___1~0) [L1903] #res := 0bv32; VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #res=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~info~0!base=67108865bv32, ~info~0!offset=4294967283bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~retries~0=500bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___1~0=0bv32, ~tmp~10!base=67108865bv32, ~tmp~10!offset=4294967283bv32] [L2016] RET call #t~ret108 := tegra_rtc_wait_while_busy(~dev); VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #in~enabled=0bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~ret108=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~enabled=0bv32, ~info~4!base=0bv32, ~info~4!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~14!base=0bv32, ~tmp~14!offset=0bv32] [L2016] havoc #t~ret108; VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #in~enabled=0bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~enabled=0bv32, ~info~4!base=0bv32, ~info~4!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~14!base=0bv32, ~tmp~14!offset=0bv32] [L2017] CALL call ldv_spin_lock_check(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2962] COND FALSE !(1bv32 == ~ldv_init~0) VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2965] CALL call ldv_error(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L1684] assert false; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] ----- [2018-11-22 23:40:28,370 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType STRUCT~~rtc_class_ops?open~*((*device ) : INT)?release~*((*device ) : VOID)?ioctl~*((*device UINT ULONG ) : INT)?read_time~*((*device *rtc_time ) : INT)?set_time~*((*device *rtc_time ) : INT)?read_alarm~*((*device *rtc_wkalrm ) : INT)?set_alarm~*((*device *rtc_wkalrm ) : INT)?proc~*((*device *seq_file ) : INT)?set_mmss~*((*device ULONG ) : INT)?read_callback~*((*device INT ) : INT)?alarm_irq_enable~*((*device UINT ) : INT)# [2018-11-22 23:40:28,371 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID [2018-11-22 23:40:28,371 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID [2018-11-22 23:40:28,371 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,371 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID [2018-11-22 23:40:28,371 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType STRUCT~~platform_driver?probe~*((*platform_device ) : INT)?remove~*((*platform_device ) : INT)?shutdown~*((*platform_device ) : VOID)?suspend~*((*platform_device ~pm_message_t~0 ) : INT)?resume~*((*platform_device ) : INT)?driver~STRUCT~~device_driver?name~*CHAR?bus~*bus_type?owner~*module?mod_name~*CHAR?suppress_bind_attrs~~bool~0?of_match_table~*of_device_id?probe~*((*device ) : INT)?remove~*((*device ) : INT)?shutdown~*((*device ) : VOID)?suspend~*((*device ~pm_message_t~0 ) : INT)?resume~*((*device ) : INT)?groups~**attribute_group?pm~*dev_pm_ops?p~*driver_private#?id_table~*platform_device_id# [2018-11-22 23:40:28,372 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *rtc_wkalrm [2018-11-22 23:40:28,372 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID [2018-11-22 23:40:28,372 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,372 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *device [2018-11-22 23:40:28,372 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID [2018-11-22 23:40:28,373 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType STRUCT~~rtc_class_ops?open~*((*device ) : INT)?release~*((*device ) : VOID)?ioctl~*((*device UINT ULONG ) : INT)?read_time~*((*device *rtc_time ) : INT)?set_time~*((*device *rtc_time ) : INT)?read_alarm~*((*device *rtc_wkalrm ) : INT)?set_alarm~*((*device *rtc_wkalrm ) : INT)?proc~*((*device *seq_file ) : INT)?set_mmss~*((*device ULONG ) : INT)?read_callback~*((*device INT ) : INT)?alarm_irq_enable~*((*device UINT ) : INT)# [2018-11-22 23:40:28,373 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID [2018-11-22 23:40:28,373 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *rtc_time [2018-11-22 23:40:28,373 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *rtc_time [2018-11-22 23:40:28,374 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType STRUCT~~platform_driver?probe~*((*platform_device ) : INT)?remove~*((*platform_device ) : INT)?shutdown~*((*platform_device ) : VOID)?suspend~*((*platform_device ~pm_message_t~0 ) : INT)?resume~*((*platform_device ) : INT)?driver~STRUCT~~device_driver?name~*CHAR?bus~*bus_type?owner~*module?mod_name~*CHAR?suppress_bind_attrs~~bool~0?of_match_table~*of_device_id?probe~*((*device ) : INT)?remove~*((*device ) : INT)?shutdown~*((*device ) : VOID)?suspend~*((*device ~pm_message_t~0 ) : INT)?resume~*((*device ) : INT)?groups~**attribute_group?pm~*dev_pm_ops?p~*driver_private#?id_table~*platform_device_id# [2018-11-22 23:40:28,374 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *rtc_wkalrm [2018-11-22 23:40:28,374 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *device [2018-11-22 23:40:28,374 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID [2018-11-22 23:40:28,375 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID [2018-11-22 23:40:28,377 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,377 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,378 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,378 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,380 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,380 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,382 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,382 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,384 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,384 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,385 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,386 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,393 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,393 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,394 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-22 23:40:28,395 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,395 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,396 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-22 23:40:28,396 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-22 23:40:28,398 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,398 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-22 23:40:28,399 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,407 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-22 23:40:28,408 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,409 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,410 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,410 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,416 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,416 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-22 23:40:28,417 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,417 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-22 23:40:28,418 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,418 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,418 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-22 23:40:28,418 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-22 23:40:28,419 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,420 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,420 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,421 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,422 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,422 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,423 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,423 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,425 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,425 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,426 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,426 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,427 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,427 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,428 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-22 23:40:28,428 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-22 23:40:28,429 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,429 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,429 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-22 23:40:28,429 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-22 23:40:28,430 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,430 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,430 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-22 23:40:28,430 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-22 23:40:28,431 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,431 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,431 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-22 23:40:28,431 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-22 23:40:28,431 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-22 23:40:28,432 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,432 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-22 23:40:28,432 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-22 23:40:28,432 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-22 23:40:28,432 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,433 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-22 23:40:28,433 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-22 23:40:28,433 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,433 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,433 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-22 23:40:28,433 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,434 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,434 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-22 23:40:28,434 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-22 23:40:28,434 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-22 23:40:28,434 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,435 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,435 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-22 23:40:28,435 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-22 23:40:28,435 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-22 23:40:28,435 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,435 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,436 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-22 23:40:28,436 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-22 23:40:28,436 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement [2018-11-22 23:40:28,437 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,437 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,437 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,438 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,438 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,439 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,440 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,440 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,441 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,441 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,441 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,442 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,442 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,443 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,444 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,446 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,447 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,448 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,448 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,449 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,449 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,450 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,450 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,450 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,451 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,451 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,452 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device [2018-11-22 23:40:28,452 WARN L1272 BoogieBacktranslator]: Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device ----- class de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.CACSL2BoogieBacktranslator [?] CALL call ULTIMATE.init(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=0bv32, #t~string125!offset=0bv32, #t~string134!base=0bv32, #t~string134!offset=0bv32, #t~string140!base=0bv32, #t~string140!offset=0bv32, #t~string148!base=0bv32, #t~string148!offset=0bv32, #t~string149!base=0bv32, #t~string149!offset=0bv32, #t~string193!base=0bv32, #t~string193!offset=0bv32, #t~string195!base=0bv32, #t~string195!offset=0bv32, #t~string198!base=0bv32, #t~string198!offset=0bv32, #t~string200!base=0bv32, #t~string200!offset=0bv32, #t~string222!base=0bv32, #t~string222!offset=0bv32, #t~string90!base=0bv32, #t~string90!offset=0bv32, old(#NULL!base)=0bv32, old(#NULL!offset)=0bv32, old(#t~string125!base)=0bv32, old(#t~string125!offset)=0bv32, old(#t~string134!base)=0bv32, old(#t~string134!offset)=0bv32, old(#t~string140!base)=0bv32, old(#t~string140!offset)=0bv32, old(#t~string148!base)=0bv32, old(#t~string148!offset)=0bv32, old(#t~string149!base)=0bv32, old(#t~string149!offset)=0bv32, old(#t~string193!base)=0bv32, old(#t~string193!offset)=0bv32, old(#t~string195!base)=0bv32, old(#t~string195!offset)=0bv32, old(#t~string198!base)=0bv32, old(#t~string198!offset)=0bv32, old(#t~string200!base)=0bv32, old(#t~string200!offset)=0bv32, old(#t~string222!base)=0bv32, old(#t~string222!offset)=0bv32, old(#t~string90!base)=0bv32, old(#t~string90!offset)=0bv32, old(~#tegra_rtc_driver~0!base)=0bv32, old(~#tegra_rtc_driver~0!offset)=0bv32, old(~#tegra_rtc_ops~0!base)=0bv32, old(~#tegra_rtc_ops~0!offset)=0bv32, old(~LDV_IN_INTERRUPT~0)=0bv32, old(~ldv_init~0)=0bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_irq_data_1_0~0!base)=0bv32, old(~ldv_irq_data_1_0~0!offset)=0bv32, old(~ldv_irq_data_1_1~0!base)=0bv32, old(~ldv_irq_data_1_1~0!offset)=0bv32, old(~ldv_irq_data_1_2~0!base)=0bv32, old(~ldv_irq_data_1_2~0!offset)=0bv32, old(~ldv_irq_data_1_3~0!base)=0bv32, old(~ldv_irq_data_1_3~0!offset)=0bv32, old(~ldv_irq_line_1_0~0)=0bv32, old(~ldv_irq_line_1_1~0)=0bv32, old(~ldv_irq_line_1_2~0)=0bv32, old(~ldv_irq_line_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, old(~tegra_rtc_ops_group0~0!base)=0bv32, old(~tegra_rtc_ops_group0~0!offset)=0bv32, old(~tegra_rtc_ops_group1~0!base)=0bv32, old(~tegra_rtc_ops_group1~0!offset)=0bv32, old(~tegra_rtc_ops_group2~0!base)=0bv32, old(~tegra_rtc_ops_group2~0!offset)=0bv32, ~#tegra_rtc_driver~0!base=0bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=0bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=0bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] #NULL := { base: 0bv32, offset: 0bv32 }; [?] #valid[0bv32] := 0bv1; [L1905] FCALL call #t~string90 := #Ultimate.alloc(36bv32); [L2072] FCALL call #t~string125 := #Ultimate.alloc(12bv32); [L2150] FCALL call #t~string134 := #Ultimate.alloc(42bv32); [L2159] FCALL call #t~string140 := #Ultimate.alloc(42bv32); [L2175] FCALL call #t~string148 := #Ultimate.alloc(32bv32); [L2189] FCALL call #t~string149 := #Ultimate.alloc(21bv32); [L2211] FCALL call #t~string193 := #Ultimate.alloc(37bv32); [L2218] FCALL call #t~string195 := #Ultimate.alloc(10bv32); [L2220] FCALL call #t~string198 := #Ultimate.alloc(50bv32); [L2226] FCALL call #t~string200 := #Ultimate.alloc(32bv32); [L2323] FCALL call #t~string222 := #Ultimate.alloc(10bv32); [L1713] ~ldv_irq_1_2~0 := 0bv32; [L1714] ~LDV_IN_INTERRUPT~0 := 1bv32; [L1715] ~ldv_irq_1_3~0 := 0bv32; [L1717] ~ldv_irq_data_1_1~0 := { base: 0bv32, offset: 0bv32 }; [L1718] ~ldv_irq_1_1~0 := 0bv32; [L1719] ~ldv_irq_1_0~0 := 0bv32; [L1720] ~ldv_irq_line_1_3~0 := 0bv32; [L1721] ~ldv_irq_data_1_0~0 := { base: 0bv32, offset: 0bv32 }; [L1722] ~ldv_state_variable_0~0 := 0bv32; [L1724] ~ldv_state_variable_3~0 := 0bv32; [L1725] ~ldv_irq_line_1_0~0 := 0bv32; [L1726] ~ldv_state_variable_2~0 := 0bv32; [L1727] ~ldv_irq_data_1_3~0 := { base: 0bv32, offset: 0bv32 }; [L1728] ~ref_cnt~0 := 0bv32; [L1729] ~ldv_irq_line_1_1~0 := 0bv32; [L1731] ~ldv_irq_data_1_2~0 := { base: 0bv32, offset: 0bv32 }; [L1732] ~ldv_state_variable_1~0 := 0bv32; [L1733] ~ldv_irq_line_1_2~0 := 0bv32; [L2342] ~ldv_retval_2~0 := 0bv32; [L2343] ~ldv_retval_0~0 := 0bv32; [L2345] ~ldv_retval_1~0 := 0bv32; [L2943] ~ldv_init~0 := 0bv32; [L1716] ~tegra_rtc_driver_group0~0 := { base: 0bv32, offset: 0bv32 }; [L1723] ~tegra_rtc_ops_group1~0 := { base: 0bv32, offset: 0bv32 }; [L1730] ~tegra_rtc_ops_group0~0 := { base: 0bv32, offset: 0bv32 }; [L1734] ~tegra_rtc_ops_group2~0 := { base: 0bv32, offset: 0bv32 }; [L2123-L2125] FCALL call ~#tegra_rtc_ops~0 := #Ultimate.alloc(88bv32); [L2123-L2125] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_ops~0!base, offset: ~#tegra_rtc_ops~0!offset }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(8bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(16bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_read_time, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(24bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_set_time, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(32bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_read_alarm, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(40bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_set_alarm, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(48bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_proc, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(56bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(64bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(72bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2123-L2125] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_alarm_irq_enable, { base: ~#tegra_rtc_ops~0!base, offset: ~bvadd32(80bv32, ~#tegra_rtc_ops~0!offset) }, 8bv32); [L2322-L2323] FCALL call ~#tegra_rtc_driver~0 := #Ultimate.alloc(153bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~#tegra_rtc_driver~0!offset }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_remove, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(8bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_shutdown, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(16bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_suspend, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(24bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$(#funAddr~tegra_rtc_resume, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(32bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$(#t~string222, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(40bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(48bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$(~#__this_module~0, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(56bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(64bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~intINTTYPE1(0bv8, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(72bv32, ~#tegra_rtc_driver~0!offset) }, 1bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(73bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(81bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(89bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(97bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(105bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(113bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(121bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(129bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(137bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); [L2322-L2323] FCALL call write~init~$Pointer$({ base: 0bv32, offset: 0bv32 }, { base: ~#tegra_rtc_driver~0!base, offset: ~bvadd32(145bv32, ~#tegra_rtc_driver~0!offset) }, 8bv32); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(#NULL!base)=0bv32, old(#NULL!offset)=0bv32, old(#t~string125!base)=0bv32, old(#t~string125!offset)=0bv32, old(#t~string134!base)=0bv32, old(#t~string134!offset)=0bv32, old(#t~string140!base)=0bv32, old(#t~string140!offset)=0bv32, old(#t~string148!base)=0bv32, old(#t~string148!offset)=0bv32, old(#t~string149!base)=0bv32, old(#t~string149!offset)=0bv32, old(#t~string193!base)=0bv32, old(#t~string193!offset)=0bv32, old(#t~string195!base)=0bv32, old(#t~string195!offset)=0bv32, old(#t~string198!base)=0bv32, old(#t~string198!offset)=0bv32, old(#t~string200!base)=0bv32, old(#t~string200!offset)=0bv32, old(#t~string222!base)=0bv32, old(#t~string222!offset)=0bv32, old(#t~string90!base)=0bv32, old(#t~string90!offset)=0bv32, old(~#tegra_rtc_driver~0!base)=0bv32, old(~#tegra_rtc_driver~0!offset)=0bv32, old(~#tegra_rtc_ops~0!base)=0bv32, old(~#tegra_rtc_ops~0!offset)=0bv32, old(~LDV_IN_INTERRUPT~0)=0bv32, old(~ldv_init~0)=0bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_irq_data_1_0~0!base)=0bv32, old(~ldv_irq_data_1_0~0!offset)=0bv32, old(~ldv_irq_data_1_1~0!base)=0bv32, old(~ldv_irq_data_1_1~0!offset)=0bv32, old(~ldv_irq_data_1_2~0!base)=0bv32, old(~ldv_irq_data_1_2~0!offset)=0bv32, old(~ldv_irq_data_1_3~0!base)=0bv32, old(~ldv_irq_data_1_3~0!offset)=0bv32, old(~ldv_irq_line_1_0~0)=0bv32, old(~ldv_irq_line_1_1~0)=0bv32, old(~ldv_irq_line_1_2~0)=0bv32, old(~ldv_irq_line_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, old(~tegra_rtc_ops_group0~0!base)=0bv32, old(~tegra_rtc_ops_group0~0!offset)=0bv32, old(~tegra_rtc_ops_group1~0!base)=0bv32, old(~tegra_rtc_ops_group1~0!offset)=0bv32, old(~tegra_rtc_ops_group2~0!base)=0bv32, old(~tegra_rtc_ops_group2~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] RET call ULTIMATE.init(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] CALL call #t~ret277 := main(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2518] havoc ~ldvarg1~0; [L2519] havoc ~tmp~27; [L2520] havoc ~ldvarg0~0; [L2521] havoc ~tmp___0~8; [L2522] FCALL call ~#ldvarg2~0 := #Ultimate.alloc(4bv32); [L2523] havoc ~tmp___1~5; [L2524] havoc ~tmp___2~1; [L2525] havoc ~tmp___3~1; [L2526] havoc ~tmp___4~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2529] CALL call #t~ret237 := ldv_zalloc(136bv32); VAL [#in~size=136bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L1633-L1650] ~size := #in~size; [L1635] havoc ~p~1; [L1636] havoc ~tmp~1; [L1637] havoc ~tmp___0~1; [L1640] ~tmp___0~1 := #t~nondet12; [L1640] havoc #t~nondet12; VAL [#in~size=136bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~size=136bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~1=1bv32] [L1641] COND TRUE 0bv32 != ~tmp___0~1 [L1642] #res := { base: 0bv32, offset: 0bv32 }; VAL [#in~size=136bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #res!base=0bv32, #res!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~size=136bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~1=1bv32] [L2529] RET call #t~ret237 := ldv_zalloc(136bv32); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~ret237!base=0bv32, #t~ret237!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2529] ~tmp~27 := #t~ret237; [L2529] havoc #t~ret237; [L2530] ~ldvarg1~0 := ~tmp~27; [L2531] ~tmp___0~8 := #t~nondet238; [L2531] havoc #t~nondet238; [L2532] ~ldvarg0~0 := ~tmp___0~8; [L2533] FCALL call ldv_initialize(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2534] CALL call #t~memset~res239 := #Ultimate.C_memset(~#ldvarg2~0, 0bv32, 4bv32); VAL [#amount=4bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #ptr!base=67108864bv32, #ptr!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] #t~loopctr278 := 0bv32; VAL [#amount=4bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #ptr!base=67108864bv32, #ptr!offset=0bv32, #t~loopctr278=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] COND TRUE ~bvslt32(#t~loopctr278, #amount) [?] #memory_$Pointer$[{ base: #ptr!base, offset: ~bvadd32(#ptr!offset, #t~loopctr278) }] := { base: 0bv32, offset: ~zero_extendFrom8To32(#value[8:0]) }; [?] #memory_int[{ base: #ptr!base, offset: ~bvadd32(#ptr!offset, #t~loopctr278) }] := ~zero_extendFrom8To32(#value[8:0]); [?] #t~loopctr278 := ~bvadd32(1bv32, #t~loopctr278); VAL [#amount=4bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #ptr!base=67108864bv32, #ptr!offset=0bv32, #t~loopctr278=1bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] COND TRUE ~bvslt32(#t~loopctr278, #amount) [?] #memory_$Pointer$[{ base: #ptr!base, offset: ~bvadd32(#ptr!offset, #t~loopctr278) }] := { base: 0bv32, offset: ~zero_extendFrom8To32(#value[8:0]) }; [?] #memory_int[{ base: #ptr!base, offset: ~bvadd32(#ptr!offset, #t~loopctr278) }] := ~zero_extendFrom8To32(#value[8:0]); [?] #t~loopctr278 := ~bvadd32(1bv32, #t~loopctr278); VAL [#amount=4bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #ptr!base=67108864bv32, #ptr!offset=0bv32, #t~loopctr278=2bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] COND TRUE ~bvslt32(#t~loopctr278, #amount) [?] #memory_$Pointer$[{ base: #ptr!base, offset: ~bvadd32(#ptr!offset, #t~loopctr278) }] := { base: 0bv32, offset: ~zero_extendFrom8To32(#value[8:0]) }; [?] #memory_int[{ base: #ptr!base, offset: ~bvadd32(#ptr!offset, #t~loopctr278) }] := ~zero_extendFrom8To32(#value[8:0]); [?] #t~loopctr278 := ~bvadd32(1bv32, #t~loopctr278); VAL [#amount=4bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #ptr!base=67108864bv32, #ptr!offset=0bv32, #t~loopctr278=3bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] COND TRUE ~bvslt32(#t~loopctr278, #amount) [?] #memory_$Pointer$[{ base: #ptr!base, offset: ~bvadd32(#ptr!offset, #t~loopctr278) }] := { base: 0bv32, offset: ~zero_extendFrom8To32(#value[8:0]) }; [?] #memory_int[{ base: #ptr!base, offset: ~bvadd32(#ptr!offset, #t~loopctr278) }] := ~zero_extendFrom8To32(#value[8:0]); [?] #t~loopctr278 := ~bvadd32(1bv32, #t~loopctr278); VAL [#amount=4bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #ptr!base=67108864bv32, #ptr!offset=0bv32, #t~loopctr278=4bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [?] COND FALSE !(~bvslt32(#t~loopctr278, #amount)) VAL [#amount=4bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #ptr!base=67108864bv32, #ptr!offset=0bv32, #t~loopctr278=4bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #value=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2534] RET call #t~memset~res239 := #Ultimate.C_memset(~#ldvarg2~0, 0bv32, 4bv32); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~memset~res239!base=67108864bv32, #t~memset~res239!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=0bv32, ~ldv_state_variable_1~0=0bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2534] havoc #t~memset~res239; [L2535] ~ldv_state_variable_1~0 := 1bv32; [L2536] ~ref_cnt~0 := 0bv32; [L2537] ~ldv_state_variable_0~0 := 1bv32; [L2538] ~ldv_state_variable_3~0 := 0bv32; [L2539] ~ldv_state_variable_2~0 := 0bv32; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2541] ~tmp___1~5 := #t~nondet240; [L2541] havoc #t~nondet240; [L2543] #t~switch241 := 0bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND FALSE !(#t~switch241) [L2550] #t~switch241 := #t~switch241 || 1bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND TRUE #t~switch241 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2551] COND TRUE 0bv32 != ~ldv_state_variable_0~0 [L2552] ~tmp___2~1 := #t~nondet242; [L2552] havoc #t~nondet242; [L2554] #t~switch243 := 0bv32 == ~tmp___2~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2553-L2585] COND FALSE !(#t~switch243) [L2563] #t~switch243 := #t~switch243 || 1bv32 == ~tmp___2~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2553-L2585] COND TRUE #t~switch243 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2564] COND TRUE 1bv32 == ~ldv_state_variable_0~0 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2565] CALL call #t~ret244 := tegra_rtc_init(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2326] havoc ~tmp~22; [L2329] FCALL call #t~ret223 := platform_driver_probe(~#tegra_rtc_driver~0, #funAddr~tegra_rtc_probe); [L2329] ~tmp~22 := #t~ret223; [L2329] havoc #t~ret223; [L2330] #res := ~tmp~22; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #res=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~22=0bv32] [L2565] RET call #t~ret244 := tegra_rtc_init(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~ret244=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2565] ~ldv_retval_0~0 := #t~ret244; [L2565] havoc #t~ret244; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=1bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=0bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2566] COND TRUE 0bv32 == ~ldv_retval_0~0 [L2567] ~ldv_state_variable_0~0 := 3bv32; [L2568] ~ldv_state_variable_2~0 := 1bv32; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2569] CALL call ldv_initialize_platform_driver_2(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2476] havoc ~tmp~26; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2479] CALL call #t~ret236 := ldv_zalloc(624bv32); VAL [#in~size=624bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L1633-L1650] ~size := #in~size; [L1635] havoc ~p~1; [L1636] havoc ~tmp~1; [L1637] havoc ~tmp___0~1; [L1640] ~tmp___0~1 := #t~nondet12; [L1640] havoc #t~nondet12; VAL [#in~size=624bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~size=624bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~1=1bv32] [L1641] COND TRUE 0bv32 != ~tmp___0~1 [L1642] #res := { base: 0bv32, offset: 0bv32 }; VAL [#in~size=624bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #res!base=0bv32, #res!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~size=624bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~1=1bv32] [L2479] RET call #t~ret236 := ldv_zalloc(624bv32); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~ret236!base=0bv32, #t~ret236!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2479] ~tmp~26 := #t~ret236; [L2479] havoc #t~ret236; [L2480] ~tegra_rtc_driver_group0~0 := ~tmp~26; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~26!base=0bv32, ~tmp~26!offset=0bv32] [L2569] RET call ldv_initialize_platform_driver_2(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2573] COND FALSE !(0bv32 != ~ldv_retval_0~0) VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=1bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2541] ~tmp___1~5 := #t~nondet240; [L2541] havoc #t~nondet240; [L2543] #t~switch241 := 0bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=false, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND FALSE !(#t~switch241) [L2550] #t~switch241 := #t~switch241 || 1bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=false, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND FALSE !(#t~switch241) [L2591] #t~switch241 := #t~switch241 || 2bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=false, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND FALSE !(#t~switch241) [L2699] #t~switch241 := #t~switch241 || 3bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND TRUE #t~switch241 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2700] COND TRUE 0bv32 != ~ldv_state_variable_2~0 [L2701] ~tmp___4~1 := #t~nondet260; [L2701] havoc #t~nondet260; [L2703] #t~switch261 := 0bv32 == ~tmp___4~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2702-L2775] COND FALSE !(#t~switch261) [L2717] #t~switch261 := #t~switch261 || 1bv32 == ~tmp___4~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2702-L2775] COND FALSE !(#t~switch261) [L2729] #t~switch261 := #t~switch261 || 2bv32 == ~tmp___4~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2702-L2775] COND FALSE !(#t~switch261) [L2752] #t~switch261 := #t~switch261 || 3bv32 == ~tmp___4~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=false, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2702-L2775] COND FALSE !(#t~switch261) [L2764] #t~switch261 := #t~switch261 || 4bv32 == ~tmp___4~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2702-L2775] COND TRUE #t~switch261 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=1bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=0bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2765] COND TRUE 1bv32 == ~ldv_state_variable_2~0 [L2766] FCALL call #t~ret268 := ldv_probe_2(); [L2766] havoc #t~ret268; [L2767] ~ldv_state_variable_2~0 := 2bv32; [L2768] ~ref_cnt~0 := ~bvadd32(1bv32, ~ref_cnt~0); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2541] ~tmp___1~5 := #t~nondet240; [L2541] havoc #t~nondet240; [L2543] #t~switch241 := 0bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=false, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND FALSE !(#t~switch241) [L2550] #t~switch241 := #t~switch241 || 1bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=false, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND FALSE !(#t~switch241) [L2591] #t~switch241 := #t~switch241 || 2bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=false, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND FALSE !(#t~switch241) [L2699] #t~switch241 := #t~switch241 || 3bv32 == ~tmp___1~5; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2542-L2783] COND TRUE #t~switch241 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=4bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2700] COND TRUE 0bv32 != ~ldv_state_variable_2~0 [L2701] ~tmp___4~1 := #t~nondet260; [L2701] havoc #t~nondet260; [L2703] #t~switch261 := 0bv32 == ~tmp___4~1; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=0bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2702-L2775] COND TRUE #t~switch261 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=0bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2704] COND FALSE !(4bv32 == ~ldv_state_variable_2~0) VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=0bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2710] COND TRUE 2bv32 == ~ldv_state_variable_2~0 VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, #t~switch241=true, #t~switch243=true, #t~switch261=true, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#ldvarg2~0!base=67108864bv32, ~#ldvarg2~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ldvarg0~0=0bv32, ~ldvarg1~0!base=0bv32, ~ldvarg1~0!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___0~8=0bv32, ~tmp___1~5=3bv32, ~tmp___2~1=1bv32, ~tmp___4~1=0bv32, ~tmp~27!base=0bv32, ~tmp~27!offset=0bv32] [L2711] CALL call tegra_rtc_shutdown(~tegra_rtc_driver_group0~0); VAL [#in~pdev!base=0bv32, #in~pdev!offset=0bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2313-L2321] ~pdev := #in~pdev; VAL [#in~pdev!base=0bv32, #in~pdev!offset=0bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~pdev!base=0bv32, ~pdev!offset=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2318] CALL call #t~ret221 := tegra_rtc_alarm_irq_enable({ base: ~pdev!base, offset: ~bvadd32(12bv32, ~pdev!offset) }, 0bv32); VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #in~enabled=0bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2004-L2033] ~dev := #in~dev; [L2004-L2033] ~enabled := #in~enabled; [L2006] havoc ~info~4; [L2007] havoc ~tmp~14; [L2008] havoc ~status~0; [L2009] havoc ~sl_irq_flags~1; [L2010] havoc ~__v~3; [L2011] havoc ~__v___0~3; [L2014] FCALL call #t~ret107 := dev_get_drvdata(~dev); [L2014] ~tmp~14 := #t~ret107; [L2014] havoc #t~ret107; [L2015] ~info~4 := ~tmp~14; VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #in~enabled=0bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~enabled=0bv32, ~info~4!base=0bv32, ~info~4!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~14!base=0bv32, ~tmp~14!offset=0bv32] [L2016] CALL call #t~ret108 := tegra_rtc_wait_while_busy(~dev); VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L1873-L1908] ~dev := #in~dev; [L1875] havoc ~info~0; [L1876] havoc ~tmp~10; [L1877] havoc ~retries~0; [L1878] havoc ~tmp___0~2; [L1879] havoc ~tmp___1~0; [L1882] FCALL call #t~ret87 := dev_get_drvdata(~dev); [L1882] ~tmp~10 := #t~ret87; [L1882] havoc #t~ret87; [L1883] ~info~0 := ~tmp~10; [L1884] ~retries~0 := 500bv32; VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~info~0!base=67108865bv32, ~info~0!offset=4294967283bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~retries~0=500bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~10!base=67108865bv32, ~tmp~10!offset=4294967283bv32] [L1896] CALL call #t~ret88 := tegra_rtc_check_busy(~info~0); VAL [#in~info!base=67108865bv32, #in~info!offset=4294967283bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L1861-L1872] ~info := #in~info; [L1863] havoc ~__v~0; [L1864] havoc ~__v___0~0; [L1867] FCALL call #t~mem85 := read~$Pointer$({ base: ~info!base, offset: ~bvadd32(16bv32, ~info!offset) }, 8bv32); [L1867] FCALL call #t~mem86 := read~intINTTYPE4({ base: #t~mem85!base, offset: ~bvadd32(16bv32, #t~mem85!offset) }, 4bv32); [L1867] ~__v___0~0 := #t~mem86; [L1867] havoc #t~mem85; [L1867] havoc #t~mem86; [L1868] ~__v~0 := ~__v___0~0; [L1870] #res := ~bvand32(1bv32, ~__v~0); VAL [#in~info!base=67108865bv32, #in~info!offset=4294967283bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #res=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~__v___0~0=0bv32, ~__v~0=0bv32, ~info!base=67108865bv32, ~info!offset=4294967283bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L1896] RET call #t~ret88 := tegra_rtc_check_busy(~info~0); VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~ret88=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~info~0!base=67108865bv32, ~info~0!offset=4294967283bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~retries~0=500bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~10!base=67108865bv32, ~tmp~10!offset=4294967283bv32] [L1896] ~tmp___1~0 := #t~ret88; [L1896] havoc #t~ret88; VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~info~0!base=67108865bv32, ~info~0!offset=4294967283bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~retries~0=500bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___1~0=0bv32, ~tmp~10!base=67108865bv32, ~tmp~10!offset=4294967283bv32] [L1897] COND FALSE !(0bv32 != ~tmp___1~0) [L1903] #res := 0bv32; VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #res=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~info~0!base=67108865bv32, ~info~0!offset=4294967283bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~retries~0=500bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp___1~0=0bv32, ~tmp~10!base=67108865bv32, ~tmp~10!offset=4294967283bv32] [L2016] RET call #t~ret108 := tegra_rtc_wait_while_busy(~dev); VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #in~enabled=0bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~ret108=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~enabled=0bv32, ~info~4!base=0bv32, ~info~4!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~14!base=0bv32, ~tmp~14!offset=0bv32] [L2016] havoc #t~ret108; VAL [#in~dev!base=0bv32, #in~dev!offset=12bv32, #in~enabled=0bv32, #NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~dev!base=0bv32, ~dev!offset=12bv32, ~enabled=0bv32, ~info~4!base=0bv32, ~info~4!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32, ~tmp~14!base=0bv32, ~tmp~14!offset=0bv32] [L2017] CALL call ldv_spin_lock_check(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2962] COND FALSE !(1bv32 == ~ldv_init~0) VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L2965] CALL call ldv_error(); VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L1684] assert false; VAL [#NULL!base=0bv32, #NULL!offset=0bv32, #t~string125!base=4294963700bv32, #t~string125!offset=0bv32, #t~string134!base=4294963699bv32, #t~string134!offset=0bv32, #t~string140!base=4294963704bv32, #t~string140!offset=0bv32, #t~string148!base=4294963703bv32, #t~string148!offset=0bv32, #t~string149!base=4294963706bv32, #t~string149!offset=0bv32, #t~string193!base=4294963702bv32, #t~string193!offset=0bv32, #t~string195!base=4294965748bv32, #t~string195!offset=0bv32, #t~string198!base=4294963707bv32, #t~string198!offset=0bv32, #t~string200!base=4294963701bv32, #t~string200!offset=0bv32, #t~string222!base=4294963698bv32, #t~string222!offset=0bv32, #t~string90!base=3875469542bv32, #t~string90!offset=0bv32, old(~LDV_IN_INTERRUPT~0)=1bv32, old(~ldv_irq_1_0~0)=0bv32, old(~ldv_irq_1_1~0)=0bv32, old(~ldv_irq_1_2~0)=0bv32, old(~ldv_irq_1_3~0)=0bv32, old(~ldv_retval_0~0)=0bv32, old(~ldv_retval_1~0)=0bv32, old(~ldv_retval_2~0)=0bv32, old(~ldv_state_variable_0~0)=0bv32, old(~ldv_state_variable_1~0)=0bv32, old(~ldv_state_variable_2~0)=0bv32, old(~ldv_state_variable_3~0)=0bv32, old(~ref_cnt~0)=0bv32, old(~tegra_rtc_driver_group0~0!base)=0bv32, old(~tegra_rtc_driver_group0~0!offset)=0bv32, ~#__this_module~0!base=0bv32, ~#__this_module~0!offset=0bv32, ~#tegra_rtc_driver~0!base=2269114822bv32, ~#tegra_rtc_driver~0!offset=0bv32, ~#tegra_rtc_ops~0!base=4261409267bv32, ~#tegra_rtc_ops~0!offset=0bv32, ~LDV_IN_INTERRUPT~0=1bv32, ~ldv_init~0=0bv32, ~ldv_irq_1_0~0=0bv32, ~ldv_irq_1_1~0=0bv32, ~ldv_irq_1_2~0=0bv32, ~ldv_irq_1_3~0=0bv32, ~ldv_irq_data_1_0~0!base=0bv32, ~ldv_irq_data_1_0~0!offset=0bv32, ~ldv_irq_data_1_1~0!base=0bv32, ~ldv_irq_data_1_1~0!offset=0bv32, ~ldv_irq_data_1_2~0!base=0bv32, ~ldv_irq_data_1_2~0!offset=0bv32, ~ldv_irq_data_1_3~0!base=0bv32, ~ldv_irq_data_1_3~0!offset=0bv32, ~ldv_irq_line_1_0~0=0bv32, ~ldv_irq_line_1_1~0=0bv32, ~ldv_irq_line_1_2~0=0bv32, ~ldv_irq_line_1_3~0=0bv32, ~ldv_retval_0~0=0bv32, ~ldv_retval_1~0=0bv32, ~ldv_retval_2~0=0bv32, ~ldv_state_variable_0~0=3bv32, ~ldv_state_variable_1~0=1bv32, ~ldv_state_variable_2~0=2bv32, ~ldv_state_variable_3~0=0bv32, ~ref_cnt~0=1bv32, ~tegra_rtc_driver_group0~0!base=0bv32, ~tegra_rtc_driver_group0~0!offset=0bv32, ~tegra_rtc_ops_group0~0!base=0bv32, ~tegra_rtc_ops_group0~0!offset=0bv32, ~tegra_rtc_ops_group1~0!base=0bv32, ~tegra_rtc_ops_group1~0!offset=0bv32, ~tegra_rtc_ops_group2~0!base=0bv32, ~tegra_rtc_ops_group2~0!offset=0bv32] [L1713] int ldv_irq_1_2 = 0; [L1714] int LDV_IN_INTERRUPT = 1; [L1715] int ldv_irq_1_3 = 0; [L1717] void *ldv_irq_data_1_1 ; [L1718] int ldv_irq_1_1 = 0; [L1719] int ldv_irq_1_0 = 0; [L1720] int ldv_irq_line_1_3 ; [L1721] void *ldv_irq_data_1_0 ; [L1722] int ldv_state_variable_0 ; [L1724] int ldv_state_variable_3 ; [L1725] int ldv_irq_line_1_0 ; [L1726] int ldv_state_variable_2 ; [L1727] void *ldv_irq_data_1_3 ; [L1728] int ref_cnt ; [L1729] int ldv_irq_line_1_1 ; [L1731] void *ldv_irq_data_1_2 ; [L1732] int ldv_state_variable_1 ; [L1733] int ldv_irq_line_1_2 ; [L2342] int ldv_retval_2 ; [L2343] int ldv_retval_0 ; [L2345] int ldv_retval_1 ; [L2943] int ldv_init = 0; [L1716] struct platform_device *tegra_rtc_driver_group0 ; [L1723] struct device *tegra_rtc_ops_group1 ; [L1730] struct rtc_time *tegra_rtc_ops_group0 ; [L1734] struct rtc_wkalrm *tegra_rtc_ops_group2 ; [L2123-L2125] static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2322-L2323] static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; VAL [\old(LDV_IN_INTERRUPT)=0, \old(ldv_init)=0, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_irq_data_1_0)=null, \old(ldv_irq_data_1_0)=null, \old(ldv_irq_data_1_1)=null, \old(ldv_irq_data_1_1)=null, \old(ldv_irq_data_1_2)=null, \old(ldv_irq_data_1_2)=null, \old(ldv_irq_data_1_3)=null, \old(ldv_irq_data_1_3)=null, \old(ldv_irq_line_1_0)=0, \old(ldv_irq_line_1_1)=0, \old(ldv_irq_line_1_2)=0, \old(ldv_irq_line_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver)=null, \old(tegra_rtc_driver)=null, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_ops)=null, \old(tegra_rtc_ops)=null, \old(tegra_rtc_ops_group0)=null, \old(tegra_rtc_ops_group0)=null, \old(tegra_rtc_ops_group1)=null, \old(tegra_rtc_ops_group1)=null, \old(tegra_rtc_ops_group2)=null, \old(tegra_rtc_ops_group2)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2518] struct seq_file *ldvarg1 ; [L2519] void *tmp ; [L2520] unsigned int ldvarg0 ; [L2521] unsigned int tmp___0 ; [L2522] pm_message_t ldvarg2 ; [L2523] int tmp___1 ; [L2524] int tmp___2 ; [L2525] int tmp___3 ; [L2526] int tmp___4 ; VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg2={67108864:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2529] CALL, EXPR ldv_zalloc(136U) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(size)=136, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1635] void *p ; [L1636] void *tmp ; [L1637] int tmp___0 ; [L1640] tmp___0 = __VERIFIER_nondet_int() [L1641] COND TRUE tmp___0 != 0 [L1642] return (0); VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(size)=136, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, \result={0:0}, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, size=136, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp___0=1] [L2529] RET, EXPR ldv_zalloc(136U) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldv_zalloc(136U)={0:0}, ldvarg2={67108864:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2529] tmp = ldv_zalloc(136U) [L2530] ldvarg1 = (struct seq_file *)tmp [L2531] tmp___0 = __VERIFIER_nondet_uint() [L2532] ldvarg0 = tmp___0 [L2534] FCALL memset((void *)(& ldvarg2), 0, 4U) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, memset((void *)(& ldvarg2), 0, 4U)={67108864:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0] [L2535] ldv_state_variable_1 = 1 [L2536] ref_cnt = 0 [L2537] ldv_state_variable_0 = 1 [L2538] ldv_state_variable_3 = 0 [L2539] ldv_state_variable_2 = 0 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0] [L2541] tmp___1 = __VERIFIER_nondet_int() [L2543] case 0: [L2550] case 1: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=1] [L2551] COND TRUE ldv_state_variable_0 != 0 [L2552] tmp___2 = __VERIFIER_nondet_int() [L2554] case 0: [L2563] case 1: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=1, tmp___2=1] [L2564] COND TRUE ldv_state_variable_0 == 1 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=1, tmp___2=1] [L2565] CALL, EXPR tegra_rtc_init() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2326] int tmp ; [L2329] tmp = platform_driver_probe(& tegra_rtc_driver, & tegra_rtc_probe) [L2330] return (tmp); VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, \result=0, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp=0] [L2565] RET, EXPR tegra_rtc_init() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_init()=0, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=1, tmp___2=1] [L2565] ldv_retval_0 = tegra_rtc_init() [L2566] COND TRUE ldv_retval_0 == 0 [L2567] ldv_state_variable_0 = 3 [L2568] ldv_state_variable_2 = 1 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=1, tmp___2=1] [L2569] CALL ldv_initialize_platform_driver_2() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2476] void *tmp ; VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2479] CALL, EXPR ldv_zalloc(624U) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(size)=624, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1635] void *p ; [L1636] void *tmp ; [L1637] int tmp___0 ; [L1640] tmp___0 = __VERIFIER_nondet_int() [L1641] COND TRUE tmp___0 != 0 [L1642] return (0); VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(size)=624, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, \result={0:0}, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, size=624, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp___0=1] [L2479] RET, EXPR ldv_zalloc(624U) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldv_zalloc(624U)={0:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2479] tmp = ldv_zalloc(624U) [L2480] tegra_rtc_driver_group0 = (struct platform_device *)tmp VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}] [L2569] RET ldv_initialize_platform_driver_2() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=1, tmp___2=1] [L2573] COND FALSE !(ldv_retval_0 != 0) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=1, tmp___2=1] [L2541] tmp___1 = __VERIFIER_nondet_int() [L2543] case 0: [L2550] case 1: [L2591] case 2: [L2699] case 3: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=3, tmp___2=1] [L2700] COND TRUE ldv_state_variable_2 != 0 [L2701] tmp___4 = __VERIFIER_nondet_int() [L2703] case 0: [L2717] case 1: [L2729] case 2: [L2752] case 3: [L2764] case 4: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=3, tmp___2=1, tmp___4=4] [L2765] COND TRUE ldv_state_variable_2 == 1 [L2767] ldv_state_variable_2 = 2 [L2768] ref_cnt = ref_cnt + 1 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=3, tmp___2=1, tmp___4=4] [L2541] tmp___1 = __VERIFIER_nondet_int() [L2543] case 0: [L2550] case 1: [L2591] case 2: [L2699] case 3: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=3, tmp___2=1, tmp___4=4] [L2700] COND TRUE ldv_state_variable_2 != 0 [L2701] tmp___4 = __VERIFIER_nondet_int() [L2703] case 0: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=3, tmp___2=1, tmp___4=0] [L2704] COND FALSE !(ldv_state_variable_2 == 4) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=3, tmp___2=1, tmp___4=0] [L2710] COND TRUE ldv_state_variable_2 == 2 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=3, tmp___2=1, tmp___4=0] [L2711] CALL tegra_rtc_shutdown(tegra_rtc_driver_group0) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, pdev={0:0}, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2318] CALL tegra_rtc_alarm_irq_enable(& pdev->dev, 0U) VAL [\old(enabled)=0, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev={0:12}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2006] struct tegra_rtc_info *info ; [L2007] void *tmp ; [L2008] unsigned int status ; [L2009] unsigned long sl_irq_flags ; [L2010] u32 __v ; [L2011] u32 __v___0 ; [L2014] tmp = dev_get_drvdata((struct device const *)dev) [L2015] info = (struct tegra_rtc_info *)tmp VAL [\old(enabled)=0, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev={0:12}, dev={0:12}, enabled=0, info={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}] [L2016] CALL tegra_rtc_wait_while_busy(dev) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev={0:12}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1875] struct tegra_rtc_info *info ; [L1876] void *tmp ; [L1877] int retries ; [L1878] int tmp___0 ; [L1879] u32 tmp___1 ; [L1882] tmp = dev_get_drvdata((struct device const *)dev) [L1883] info = (struct tegra_rtc_info *)tmp [L1884] retries = 500 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev={0:12}, dev={0:12}, info={67108865:-13}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, retries=500, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={67108865:-13}] [L1896] CALL, EXPR tegra_rtc_check_busy(info) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, info={67108865:-13}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1863] u32 __v ; [L1864] u32 __v___0 ; [L1867] EXPR info->rtc_base [L1867] EXPR (unsigned int volatile *)info->rtc_base + 4U [L1867] __v___0 = *((unsigned int volatile *)info->rtc_base + 4U) [L1868] __v = __v___0 [L1870] return (__v & 1U); VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, \result=0, __this_module={0:0}, __v=0, __v___0=0, info={67108865:-13}, info={67108865:-13}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1896] RET, EXPR tegra_rtc_check_busy(info) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev={0:12}, dev={0:12}, info={67108865:-13}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, retries=500, tegra_rtc_check_busy(info)=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={67108865:-13}] [L1896] tmp___1 = tegra_rtc_check_busy(info) [L1897] COND FALSE !(tmp___1 != 0U) [L1903] return (0); VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, \result=0, __this_module={0:0}, dev={0:12}, dev={0:12}, info={67108865:-13}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, retries=500, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={67108865:-13}, tmp___1=0] [L2016] RET tegra_rtc_wait_while_busy(dev) VAL [\old(enabled)=0, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev={0:12}, dev={0:12}, enabled=0, info={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tegra_rtc_wait_while_busy(dev)=0, tmp={0:0}] [L2017] CALL ldv_spin_lock_check() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2962] COND FALSE !(ldv_init == 1) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2965] CALL ldv_error() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1684] __VERIFIER_error() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] ----- [2018-11-22 23:40:29,239 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 22.11 11:40:29 BoogieIcfgContainer [2018-11-22 23:40:29,239 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-11-22 23:40:29,240 INFO L113 PluginConnector]: ------------------------Witness Printer---------------------------- [2018-11-22 23:40:29,240 INFO L271 PluginConnector]: Initializing Witness Printer... [2018-11-22 23:40:29,240 INFO L276 PluginConnector]: Witness Printer initialized [2018-11-22 23:40:29,240 INFO L185 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 22.11 11:40:12" (3/4) ... [2018-11-22 23:40:29,243 INFO L147 WitnessPrinter]: No result that supports witness generation found [2018-11-22 23:40:29,243 INFO L132 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2018-11-22 23:40:29,244 INFO L168 Benchmark]: Toolchain (without parser) took 20598.11 ms. Allocated memory was 1.0 GB in the beginning and 1.4 GB in the end (delta: 384.3 MB). Free memory was 943.3 MB in the beginning and 1.2 GB in the end (delta: -215.2 MB). Peak memory consumption was 169.1 MB. Max. memory is 11.5 GB. [2018-11-22 23:40:29,245 INFO L168 Benchmark]: CDTParser took 0.11 ms. Allocated memory is still 1.0 GB. Free memory is still 978.7 MB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-22 23:40:29,245 INFO L168 Benchmark]: CACSL2BoogieTranslator took 828.58 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 142.6 MB). Free memory was 943.3 MB in the beginning and 1.1 GB in the end (delta: -154.0 MB). Peak memory consumption was 68.1 MB. Max. memory is 11.5 GB. [2018-11-22 23:40:29,246 INFO L168 Benchmark]: Boogie Procedure Inliner took 44.79 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.9 MB). Peak memory consumption was 6.9 MB. Max. memory is 11.5 GB. [2018-11-22 23:40:29,246 INFO L168 Benchmark]: Boogie Preprocessor took 65.97 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-22 23:40:29,246 INFO L168 Benchmark]: RCFGBuilder took 3038.47 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 967.7 MB in the end (delta: 122.7 MB). Peak memory consumption was 122.7 MB. Max. memory is 11.5 GB. [2018-11-22 23:40:29,247 INFO L168 Benchmark]: TraceAbstraction took 16612.95 ms. Allocated memory was 1.2 GB in the beginning and 1.4 GB in the end (delta: 241.7 MB). Free memory was 967.7 MB in the beginning and 1.2 GB in the end (delta: -190.8 MB). Peak memory consumption was 421.1 MB. Max. memory is 11.5 GB. [2018-11-22 23:40:29,248 INFO L168 Benchmark]: Witness Printer took 3.57 ms. Allocated memory is still 1.4 GB. Free memory is still 1.2 GB. There was no memory consumed. Max. memory is 11.5 GB. [2018-11-22 23:40:29,250 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.11 ms. Allocated memory is still 1.0 GB. Free memory is still 978.7 MB. There was no memory consumed. Max. memory is 11.5 GB. * CACSL2BoogieTranslator took 828.58 ms. Allocated memory was 1.0 GB in the beginning and 1.2 GB in the end (delta: 142.6 MB). Free memory was 943.3 MB in the beginning and 1.1 GB in the end (delta: -154.0 MB). Peak memory consumption was 68.1 MB. Max. memory is 11.5 GB. * Boogie Procedure Inliner took 44.79 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 1.1 GB in the end (delta: 6.9 MB). Peak memory consumption was 6.9 MB. Max. memory is 11.5 GB. * Boogie Preprocessor took 65.97 ms. Allocated memory is still 1.2 GB. Free memory is still 1.1 GB. There was no memory consumed. Max. memory is 11.5 GB. * RCFGBuilder took 3038.47 ms. Allocated memory is still 1.2 GB. Free memory was 1.1 GB in the beginning and 967.7 MB in the end (delta: 122.7 MB). Peak memory consumption was 122.7 MB. Max. memory is 11.5 GB. * TraceAbstraction took 16612.95 ms. Allocated memory was 1.2 GB in the beginning and 1.4 GB in the end (delta: 241.7 MB). Free memory was 967.7 MB in the beginning and 1.2 GB in the end (delta: -190.8 MB). Peak memory consumption was 421.1 MB. Max. memory is 11.5 GB. * Witness Printer took 3.57 ms. Allocated memory is still 1.4 GB. Free memory is still 1.2 GB. There was no memory consumed. Max. memory is 11.5 GB. * Results from de.uni_freiburg.informatik.ultimate.boogie.preprocessor: - GenericResult: Unfinished Backtranslation Generated EnsuresSpecification free ensures #res.base == #ptr.base && #res.offset == #ptr.offset; is not ensure(true) * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType STRUCT~~rtc_class_ops?open~*((*device ) : INT)?release~*((*device ) : VOID)?ioctl~*((*device UINT ULONG ) : INT)?read_time~*((*device *rtc_time ) : INT)?set_time~*((*device *rtc_time ) : INT)?read_alarm~*((*device *rtc_wkalrm ) : INT)?set_alarm~*((*device *rtc_wkalrm ) : INT)?proc~*((*device *seq_file ) : INT)?set_mmss~*((*device ULONG ) : INT)?read_callback~*((*device INT ) : INT)?alarm_irq_enable~*((*device UINT ) : INT)# - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType STRUCT~~platform_driver?probe~*((*platform_device ) : INT)?remove~*((*platform_device ) : INT)?shutdown~*((*platform_device ) : VOID)?suspend~*((*platform_device ~pm_message_t~0 ) : INT)?resume~*((*platform_device ) : INT)?driver~STRUCT~~device_driver?name~*CHAR?bus~*bus_type?owner~*module?mod_name~*CHAR?suppress_bind_attrs~~bool~0?of_match_table~*of_device_id?probe~*((*device ) : INT)?remove~*((*device ) : INT)?shutdown~*((*device ) : VOID)?suspend~*((*device ~pm_message_t~0 ) : INT)?resume~*((*device ) : INT)?groups~**attribute_group?pm~*dev_pm_ops?p~*driver_private#?id_table~*platform_device_id# - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *rtc_wkalrm - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType STRUCT~~rtc_class_ops?open~*((*device ) : INT)?release~*((*device ) : VOID)?ioctl~*((*device UINT ULONG ) : INT)?read_time~*((*device *rtc_time ) : INT)?set_time~*((*device *rtc_time ) : INT)?read_alarm~*((*device *rtc_wkalrm ) : INT)?set_alarm~*((*device *rtc_wkalrm ) : INT)?proc~*((*device *seq_file ) : INT)?set_mmss~*((*device ULONG ) : INT)?read_callback~*((*device INT ) : INT)?alarm_irq_enable~*((*device UINT ) : INT)# - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *rtc_time - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *rtc_time - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType STRUCT~~platform_driver?probe~*((*platform_device ) : INT)?remove~*((*platform_device ) : INT)?shutdown~*((*platform_device ) : VOID)?suspend~*((*platform_device ~pm_message_t~0 ) : INT)?resume~*((*platform_device ) : INT)?driver~STRUCT~~device_driver?name~*CHAR?bus~*bus_type?owner~*module?mod_name~*CHAR?suppress_bind_attrs~~bool~0?of_match_table~*of_device_id?probe~*((*device ) : INT)?remove~*((*device ) : INT)?shutdown~*((*device ) : VOID)?suspend~*((*device ~pm_message_t~0 ) : INT)?resume~*((*device ) : INT)?groups~**attribute_group?pm~*dev_pm_ops?p~*driver_private#?id_table~*platform_device_id# - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *rtc_wkalrm - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *VOID - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch261 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch241 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Expression #t~switch243 has a C AST node but it is no IASTExpression: class org.eclipse.cdt.internal.core.dom.parser.c.CASTSwitchStatement - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: BitvecLiteral 0bv32 could not be translated for associated CType *platform_device * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - UnprovableResult [Line: 1684]: Unable to prove that call of __VERIFIER_error() unreachable Unable to prove that call of __VERIFIER_error() unreachable Reason: overapproximation of large string literal at line 2323. Possible FailurePath: [L1713] int ldv_irq_1_2 = 0; [L1714] int LDV_IN_INTERRUPT = 1; [L1715] int ldv_irq_1_3 = 0; [L1717] void *ldv_irq_data_1_1 ; [L1718] int ldv_irq_1_1 = 0; [L1719] int ldv_irq_1_0 = 0; [L1720] int ldv_irq_line_1_3 ; [L1721] void *ldv_irq_data_1_0 ; [L1722] int ldv_state_variable_0 ; [L1724] int ldv_state_variable_3 ; [L1725] int ldv_irq_line_1_0 ; [L1726] int ldv_state_variable_2 ; [L1727] void *ldv_irq_data_1_3 ; [L1728] int ref_cnt ; [L1729] int ldv_irq_line_1_1 ; [L1731] void *ldv_irq_data_1_2 ; [L1732] int ldv_state_variable_1 ; [L1733] int ldv_irq_line_1_2 ; [L2342] int ldv_retval_2 ; [L2343] int ldv_retval_0 ; [L2345] int ldv_retval_1 ; [L2943] int ldv_init = 0; [L1716] struct platform_device *tegra_rtc_driver_group0 ; [L1723] struct device *tegra_rtc_ops_group1 ; [L1730] struct rtc_time *tegra_rtc_ops_group0 ; [L1734] struct rtc_wkalrm *tegra_rtc_ops_group2 ; [L2123-L2125] static struct rtc_class_ops tegra_rtc_ops = {0, 0, 0, & tegra_rtc_read_time, & tegra_rtc_set_time, & tegra_rtc_read_alarm, & tegra_rtc_set_alarm, & tegra_rtc_proc, 0, 0, & tegra_rtc_alarm_irq_enable}; [L2322-L2323] static struct platform_driver tegra_rtc_driver = {0, & tegra_rtc_remove, & tegra_rtc_shutdown, & tegra_rtc_suspend, & tegra_rtc_resume, {"tegra_rtc", 0, & __this_module, 0, (_Bool)0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0}; VAL [\old(LDV_IN_INTERRUPT)=0, \old(ldv_init)=0, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_irq_data_1_0)=null, \old(ldv_irq_data_1_0)=null, \old(ldv_irq_data_1_1)=null, \old(ldv_irq_data_1_1)=null, \old(ldv_irq_data_1_2)=null, \old(ldv_irq_data_1_2)=null, \old(ldv_irq_data_1_3)=null, \old(ldv_irq_data_1_3)=null, \old(ldv_irq_line_1_0)=0, \old(ldv_irq_line_1_1)=0, \old(ldv_irq_line_1_2)=0, \old(ldv_irq_line_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver)=null, \old(tegra_rtc_driver)=null, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_ops)=null, \old(tegra_rtc_ops)=null, \old(tegra_rtc_ops_group0)=null, \old(tegra_rtc_ops_group0)=null, \old(tegra_rtc_ops_group1)=null, \old(tegra_rtc_ops_group1)=null, \old(tegra_rtc_ops_group2)=null, \old(tegra_rtc_ops_group2)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2518] struct seq_file *ldvarg1 ; [L2519] void *tmp ; [L2520] unsigned int ldvarg0 ; [L2521] unsigned int tmp___0 ; [L2522] pm_message_t ldvarg2 ; [L2523] int tmp___1 ; [L2524] int tmp___2 ; [L2525] int tmp___3 ; [L2526] int tmp___4 ; VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg2={67108864:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2529] CALL, EXPR ldv_zalloc(136U) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(size)=136, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1635] void *p ; [L1636] void *tmp ; [L1637] int tmp___0 ; [L1640] tmp___0 = __VERIFIER_nondet_int() [L1641] COND TRUE tmp___0 != 0 [L1642] return (0); VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(size)=136, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, \result={0:0}, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, size=136, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp___0=1] [L2529] RET, EXPR ldv_zalloc(136U) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldv_zalloc(136U)={0:0}, ldvarg2={67108864:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2529] tmp = ldv_zalloc(136U) [L2530] ldvarg1 = (struct seq_file *)tmp [L2531] tmp___0 = __VERIFIER_nondet_uint() [L2532] ldvarg0 = tmp___0 [L2534] FCALL memset((void *)(& ldvarg2), 0, 4U) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=0, ldv_state_variable_1=0, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, memset((void *)(& ldvarg2), 0, 4U)={67108864:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0] [L2535] ldv_state_variable_1 = 1 [L2536] ref_cnt = 0 [L2537] ldv_state_variable_0 = 1 [L2538] ldv_state_variable_3 = 0 [L2539] ldv_state_variable_2 = 0 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0] [L2541] tmp___1 = __VERIFIER_nondet_int() [L2543] case 0: [L2550] case 1: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=1] [L2551] COND TRUE ldv_state_variable_0 != 0 [L2552] tmp___2 = __VERIFIER_nondet_int() [L2554] case 0: [L2563] case 1: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=1, tmp___2=1] [L2564] COND TRUE ldv_state_variable_0 == 1 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=1, tmp___2=1] [L2565] CALL, EXPR tegra_rtc_init() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2326] int tmp ; [L2329] tmp = platform_driver_probe(& tegra_rtc_driver, & tegra_rtc_probe) [L2330] return (tmp); VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, \result=0, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp=0] [L2565] RET, EXPR tegra_rtc_init() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=1, ldv_state_variable_1=1, ldv_state_variable_2=0, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_init()=0, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=1, tmp___2=1] [L2565] ldv_retval_0 = tegra_rtc_init() [L2566] COND TRUE ldv_retval_0 == 0 [L2567] ldv_state_variable_0 = 3 [L2568] ldv_state_variable_2 = 1 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=1, tmp___2=1] [L2569] CALL ldv_initialize_platform_driver_2() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2476] void *tmp ; VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2479] CALL, EXPR ldv_zalloc(624U) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(size)=624, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1635] void *p ; [L1636] void *tmp ; [L1637] int tmp___0 ; [L1640] tmp___0 = __VERIFIER_nondet_int() [L1641] COND TRUE tmp___0 != 0 [L1642] return (0); VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(size)=624, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, \result={0:0}, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, size=624, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp___0=1] [L2479] RET, EXPR ldv_zalloc(624U) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldv_zalloc(624U)={0:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2479] tmp = ldv_zalloc(624U) [L2480] tegra_rtc_driver_group0 = (struct platform_device *)tmp VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}] [L2569] RET ldv_initialize_platform_driver_2() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=1, tmp___2=1] [L2573] COND FALSE !(ldv_retval_0 != 0) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=1, tmp___2=1] [L2541] tmp___1 = __VERIFIER_nondet_int() [L2543] case 0: [L2550] case 1: [L2591] case 2: [L2699] case 3: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=3, tmp___2=1] [L2700] COND TRUE ldv_state_variable_2 != 0 [L2701] tmp___4 = __VERIFIER_nondet_int() [L2703] case 0: [L2717] case 1: [L2729] case 2: [L2752] case 3: [L2764] case 4: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=1, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=3, tmp___2=1, tmp___4=4] [L2765] COND TRUE ldv_state_variable_2 == 1 [L2767] ldv_state_variable_2 = 2 [L2768] ref_cnt = ref_cnt + 1 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=3, tmp___2=1, tmp___4=4] [L2541] tmp___1 = __VERIFIER_nondet_int() [L2543] case 0: [L2550] case 1: [L2591] case 2: [L2699] case 3: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=3, tmp___2=1, tmp___4=4] [L2700] COND TRUE ldv_state_variable_2 != 0 [L2701] tmp___4 = __VERIFIER_nondet_int() [L2703] case 0: VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=3, tmp___2=1, tmp___4=0] [L2704] COND FALSE !(ldv_state_variable_2 == 4) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=3, tmp___2=1, tmp___4=0] [L2710] COND TRUE ldv_state_variable_2 == 2 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ldvarg0=0, ldvarg1={0:0}, ldvarg2={67108864:0}, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}, tmp___0=0, tmp___1=3, tmp___2=1, tmp___4=0] [L2711] CALL tegra_rtc_shutdown(tegra_rtc_driver_group0) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, pdev={0:0}, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2318] CALL tegra_rtc_alarm_irq_enable(& pdev->dev, 0U) VAL [\old(enabled)=0, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev={0:12}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2006] struct tegra_rtc_info *info ; [L2007] void *tmp ; [L2008] unsigned int status ; [L2009] unsigned long sl_irq_flags ; [L2010] u32 __v ; [L2011] u32 __v___0 ; [L2014] tmp = dev_get_drvdata((struct device const *)dev) [L2015] info = (struct tegra_rtc_info *)tmp VAL [\old(enabled)=0, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev={0:12}, dev={0:12}, enabled=0, info={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={0:0}] [L2016] CALL tegra_rtc_wait_while_busy(dev) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev={0:12}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1875] struct tegra_rtc_info *info ; [L1876] void *tmp ; [L1877] int retries ; [L1878] int tmp___0 ; [L1879] u32 tmp___1 ; [L1882] tmp = dev_get_drvdata((struct device const *)dev) [L1883] info = (struct tegra_rtc_info *)tmp [L1884] retries = 500 VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev={0:12}, dev={0:12}, info={67108865:-13}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, retries=500, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={67108865:-13}] [L1896] CALL, EXPR tegra_rtc_check_busy(info) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, info={67108865:-13}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1863] u32 __v ; [L1864] u32 __v___0 ; [L1867] EXPR info->rtc_base [L1867] EXPR (unsigned int volatile *)info->rtc_base + 4U [L1867] __v___0 = *((unsigned int volatile *)info->rtc_base + 4U) [L1868] __v = __v___0 [L1870] return (__v & 1U); VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, \result=0, __this_module={0:0}, __v=0, __v___0=0, info={67108865:-13}, info={67108865:-13}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1896] RET, EXPR tegra_rtc_check_busy(info) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev={0:12}, dev={0:12}, info={67108865:-13}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, retries=500, tegra_rtc_check_busy(info)=0, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={67108865:-13}] [L1896] tmp___1 = tegra_rtc_check_busy(info) [L1897] COND FALSE !(tmp___1 != 0U) [L1903] return (0); VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, \result=0, __this_module={0:0}, dev={0:12}, dev={0:12}, info={67108865:-13}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, retries=500, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tmp={67108865:-13}, tmp___1=0] [L2016] RET tegra_rtc_wait_while_busy(dev) VAL [\old(enabled)=0, \old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, dev={0:12}, dev={0:12}, enabled=0, info={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}, tegra_rtc_wait_while_busy(dev)=0, tmp={0:0}] [L2017] CALL ldv_spin_lock_check() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2962] COND FALSE !(ldv_init == 1) VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L2965] CALL ldv_error() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] [L1684] __VERIFIER_error() VAL [\old(LDV_IN_INTERRUPT)=1, \old(ldv_irq_1_0)=0, \old(ldv_irq_1_1)=0, \old(ldv_irq_1_2)=0, \old(ldv_irq_1_3)=0, \old(ldv_retval_0)=0, \old(ldv_retval_1)=0, \old(ldv_retval_2)=0, \old(ldv_state_variable_0)=0, \old(ldv_state_variable_1)=0, \old(ldv_state_variable_2)=0, \old(ldv_state_variable_3)=0, \old(ref_cnt)=0, \old(tegra_rtc_driver_group0)=null, \old(tegra_rtc_driver_group0)=null, __this_module={0:0}, LDV_IN_INTERRUPT=1, ldv_init=0, ldv_irq_1_0=0, ldv_irq_1_1=0, ldv_irq_1_2=0, ldv_irq_1_3=0, ldv_irq_data_1_0={0:0}, ldv_irq_data_1_1={0:0}, ldv_irq_data_1_2={0:0}, ldv_irq_data_1_3={0:0}, ldv_irq_line_1_0=0, ldv_irq_line_1_1=0, ldv_irq_line_1_2=0, ldv_irq_line_1_3=0, ldv_retval_0=0, ldv_retval_1=0, ldv_retval_2=0, ldv_state_variable_0=3, ldv_state_variable_1=1, ldv_state_variable_2=2, ldv_state_variable_3=0, ref_cnt=1, tegra_rtc_driver={-2025852474:0}, tegra_rtc_driver_group0={0:0}, tegra_rtc_ops={-33558029:0}, tegra_rtc_ops_group0={0:0}, tegra_rtc_ops_group1={0:0}, tegra_rtc_ops_group2={0:0}] - StatisticsResult: Ultimate Automizer benchmark data CFG has 42 procedures, 363 locations, 1 error locations. UNSAFE Result, 16.5s OverallTime, 15 OverallIterations, 4 TraceHistogramMax, 7.4s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 4530 SDtfs, 4425 SDslu, 12149 SDs, 0 SdLazy, 4579 SolverSat, 402 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 5.2s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 1225 GetRequests, 1093 SyntacticMatches, 5 SemanticMatches, 127 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 306 ImplicationChecksByTransitivity, 1.3s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=1116occurred in iteration=8, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.4s AutomataMinimizationTime, 14 MinimizatonAttempts, 1437 StatesRemovedByMinimization, 10 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.4s SsaConstructionTime, 2.6s SatisfiabilityAnalysisTime, 1.4s InterpolantComputationTime, 928 NumberOfCodeBlocks, 928 NumberOfCodeBlocksAsserted, 16 NumberOfCheckSat, 1160 ConstructedInterpolants, 0 QuantifiedInterpolants, 150411 SizeOfPredicates, 41 NumberOfNonLiveVariables, 6499 ConjunctsInSsa, 95 ConjunctsInUnsatCore, 19 InterpolantComputations, 10 PerfectInterpolantSequences, 101/143 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: unable to determine feasibility of some traces Received shutdown request...